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87.
Modified Cache Line Eviction from L2 Cache May Result in Writeback
of Stale Data
Problem:
It is possible for a modified cache line to be evicted from the L2 cache just prior to
another update to the same line by software. In rare circumstances, the processor
may accrue two bus queue entries that have the same address but have different
data. If an external snoop is generated in a narrow timing window, the data from the
older eviction may be used to respond to the external snoop.
Implication: In the event that this erratum occurs, the contents of memory will be incorrect. This
may result in application, operating system, or system failure.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
88.
xAPIC May Not Report Some Illegal Vector Errors
Problem:
The local xAPIC has an Error Status Register, which records all errors. The bit 6 (the
Receive Illegal Vector bit) of this register, is set when the local xAPIC detects an
illegal vector in a received message. When an illegal vector error is received on the
same internal clock that the error status register is being written (due to a previous
error), bit 6 does not get set and illegal vector errors are not flagged.
Implication: The xAPIC may not report some Illegal Vector errors when they occur at
approximately the same time as other xAPIC errors. The other xAPIC errors will
continue to be reported.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
89.
Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation is Enabled in
a Processor Supporting Hyper-Threading Technology
Problem:
When a processor supporting Hyper-Threading Technology enables On-Demand Clock
Modulation on both logical processors, the processor is expected to select the lowest
duty cycle of the two potentially different values. When one logical processor enters
the AUTOHALT state, the duty cycle implemented should be unaffected by the halted
logical processor. Due to this erratum, the duty cycle is incorrectly chosen to be the
higher duty cycle of both logical processors.
Implication: Due to this erratum, higher duty cycle may be chosen when the On-Demand Clock
Modulation is enabled on both logical processors.
Workaround:
None identified at this time.
Status:
For the stepping affected, see the Summary Tables of Changes.
62
Errata
Specification Update
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