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5.3.2
Command descriptions
The contents of the I/O registers to be necessary for issuing a command and the example
indication of the I/O registers at command completion are shown as following in this
subsection.
Example: READ SECTOR(S)
At command issuance (I/O registers setting contents)
Bit
1F7
(CM)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(FR)
H
At command completion (I/O registers contents to be read)
Bit
1F7
(ST)
H
1F6
(DH)
H
1F5
(CH)
H
1F4
(CL)
H
1F3
(SN)
H
1F2
(SC)
H
1F1
(ER)
H
CM: Command register
DH: Device/Head register
CH: Cylinder High register
CL: Cylinder Low register
SN: Sector Number register
SC: Sector Count register
5 - 16
7
6
5
4
0
0
1
0
L
DV
Start cylinder address [MSB]
Start cylinder address [LSB] / LBA
Start sector No.
Transfer sector count
xx
7
6
5
4
Error information
L
DV
End cylinder address [MSB] / LBA
End cylinder address [LSB] / LBA
End sector No.
X'00'
Error information
FR: Features register
ST: Status register
ER: Error register
L:
LBA (logical block address) setting bit
DV: Device address. bit
x, xx: Do not care (no necessary to set)
C141-E072-01EN
3
2
1
0
0
0
0
0
Head No. / LBA [MSB]
/ LBA
/ LBA [LSB]
3
2
1
0
End Head No. / LBA [MSB]
/ LBA [LSB]
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