4.3.1.5 Drive Address Register; C156-E142-02En; 4.3.1.6 Atapi Byte Count Register; Bit Definitions Of Drive Address Register - Fujitsu MCE3064AP Product Manual

4.3.1.5 Drive Address register

This register's bits are defined as shown below.
7 6
HiZ nWTG
!
HiZ is always in the high-impedance state.
!
nWTG indicates the status of the ODD internal data write control signal (Write Gate).
!
nHS3 indicates a binary complement of bits 3 to 0 of the drive select register.
!
nDS1 is the device select bit for device 1. It is 0 when device 1 is selected.
!
nDS0 is the device select bit for device 0. It is 0 when device 0 is selected.

4.3.1.6 ATAPI Byte Count register

This register's bits are defined as shown below.
Table 4.8
7 6
!
This register is used for PIO transfer only. The ODD sets the byte count to be transferred by
the host in this register and sets DRQ to 1. The ODD does not update this register until
transfer starts.
Table 4.7

Bit definitions of Drive Address register

5 4
nHS3 nHS2

Bit definitions of ATAPI Byte Count register

5 4
Byte Count (Bits 0-7)
Byte Count (Bits 8-15)

C156-E142-02EN

3 2
nHS1 nHS0 nDS1
3 2
1 0
nDS0 Read
1 0
R/W
R/W
4 - 7