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Clock Generator
CLOCK GENERATOR
1 . 5 V S
L 3 0
H C B 1 6 0 8 K F -1 21 T 2 5 _0 6
C 2 8 7
C 2 5 1
C 29 2
C 3 10
7 , 1 1 , 15
7 , 1 1 , 15
De si gn s th at u ti li ze t he C K5 40 o r CK 61 0 cl oc k so lu ti on s ho ul d di re ct ly c on ne ct t he
BS EL 2 pi n of t he p ro ce ss or t he c lo ck c hi p an d th e In te lR S CH B SE L2 p in . Th e pr oc es so r
BS EL [1 :0 ] pi ns c an b e le ft N o Co nn ec t. I n ad di ti on , th e cl oc k FS _B s ig na l sh ou ld b e
gr ou nd ed s in ce I nt el R Ce nt ri no R At om TM w il l on ly s up po rt F SB f re qu en ci es a t 10 0 MH z
or 1 33 M Hz .
1 . 5 V S
V C C _ C LK
3 . 3V S
C 2 8 6
C 2 81
C 3 1 1
C 2 5 2
C 2 78
C 2 4 8
U 1 8
4 8
C P U T 0_ L P R
4 7
C P U C 0_ L P R
5
4 4
V D D R E F _3 . 3
C P U T 1_ L P R
8
4 3
V D D C O R E _ 1 . 5
C P U C 1_ L P R
1 4
V D D C O R E _ 1 . 5
1 5
3 9
2 2
V D D I O_ 1 . 5
C P U T 2_ L P R
3 8
V D D I O_ 1 . 5
C P U C 2_ L P R
2 3
V D D C O R E _ 1 . 5
2 9
2 7
3 0
V D D C O R E _ 1 . 5
S R C T 0_ L P R
2 6
V D D I O_ 1 . 5
S R C C 0_ L P R
4 1
V D D I O_ 1 . 5
4 2
3 2
V D D C O R E _ 1 . 5
S R C T 1_ L P R
4 6
3 1
V D D I O_ 1 . 5
S R C C 1_ L P R
XI N _ C L K _ 1 4 _R
R 23 6
3 3 _1 % _ 0 4
6
3 5
7
C L K _ R E F _ S C H
R E F
S R C T 2_ L P R
3 4
S R C C 2_ L P R
C L K _ T E S T _ MO D E
1 0
TE S T_ M OD E
C L K _ TE S T_ S E L
1 1
9
TE S T_ S E L
F S C _ L
3 7
F S B _ L
R 2 4 4
R 2 45
1
C P U _ S T O P #
*1 0 m i l _ s ho r t
* 10 m i l _s h o rt
2 1
L C D 1 0 0 T_ L P R
2 0
L C D 10 0 C _ L P R
1 2
1 7
S MB _ C L K
S C L K _ 3 . 3
D OT 9 6 T_ L P R
1 3
1 6
S MB _ D A TA
S D A T A _ 3 . 3
D O T9 6 C _ L P R
2
2 4
2 8
C L K E N #
C L K P W R GD # / P D
*C R # 0
2 8
*C R # 1
3 6
*C R # 2
4
X 1
3
X 2
I C S 9U MS 9 6 1 0
? ? ? P UL L HI GH , A ND 0 ? ?
D02 1022
R 2 4 3
*1 0 K _ 0 4
R 2 40
* 10 K _ 0 4
1 . 0 5 V S
F S L C
R 2 4 1
0_ 0 4
C P U _ B S E L 2
3 , 5
CPU Frequency Select Table
C L K _ C P U _ B C LK _R
1
4
R N 3
C L K _ C P U _ B C L K 3
C L K _ C P U _ B C LK #_ R
2
3
4P 2R X 0_ 0 4
FSLC
FSLB
CPU M HZ
C L K _ C P U _ B C L K # 3
H _ C LK _R
1
4
R N 4
C L K _ S C H _ B C L K 5
0
0
133
H _ C LK #_ R
2
3
4P 2R X 0_ 0 4
C L K _ S C H _ B C L K # 5
0
1
166
I C S _C L K 2
I C S _C L K # 2
0 827
1
0
100
C L K _ P C I E _ I N _ R
1
4
R N 7
1
1
200
C L K _ P C I E _ I N
6
C L K _ P C I E _ I N # _ R
2
3
4P 2R X 0_ 0 4
C L K _ P C I E _ I N # 6
C L K _ P C I E _ S W _ R
1
4
R N 6
C L K _ P C I E _ L A N 1 7
C L K _ P C I E _ S W # _ R
2
3
4P 2R X 0_ 0 4
C L K _ P C I E _ L A N # 1 7
3. 3V S
C L K _ P C I E _ N C _R
1
4
R N 5
C L K _ P C I E _ N C
1 5
C L K _ P C I E _ N C #_ R
2
3
4P 2R X 0_ 0 4
C L K _ P C I E _ N C # 1 5
F S L C
R 2 1 0
F S L B
R 2 22
0 _ 0 4
*4 . 7 K _ 0 4
I C S _C P U S TP #
R 2 1 7
0 _ 0 4
P M_ S T P C P U #
I C S _D R E F S S C L K
1
4
R N 9
D R E F S S C L K
7
I C S _D R E F S S C L K #
2
3
4 P 2 R X 0 _0 4
D R E F S S C L K # 7
I C S _D R E F C L K
1
4
R N 8
D R E F C L K
7
I C S _D R E F C L K #
2
3
4 P 2 R X 0 _0 4
D R E F C L K #
7
0829
I C S _C L K _ S C H _O E #
R 2 4 7
4 7 0 _0 4
C L K _ S C H _ O E # 7
I C S _P C I E _ C L K R E Q #
I C S _N C _ C LK R E Q #
R 2 4 2
X TA L_ I
X TA L_ O
4 . 7K _0 4
R 2 2 8
*1 M _1 % _ 0 4
R 2 3 8
* 47 0 _ 0 4
X 3
T P 3 6
2
1
R 3 8 2
3
4
4 . 7K _0 4
F S X 8 L_ 1 4 . 3 18 M H z
C 2 5 4
C 2 7 2
6 -2 2- 14 R3 1- 1B K
2 2 P _5 0 V _ N P O_ 0 4
22 P _ 5 0 V _ N P O _0 4
D0 2 12 08
N C _ C LK R E Q # 15
R 3 8 3
D02 1107
PL ACE CRY STAL
4 . 7K _0 4
H SX531 S_14. 318M Hz
WI THIN 50 0 MILS
OF ICS9UM S9610
D02 1 015
1 . 0 5 V S
3. . 5 , 7 , 9 , 2 5 , 26
1 . 5 V S
4, 6 , 7 , 9 , 1 4 , 15 , 2 6
3 . 3 V S
6, 7 , 9 , 1 1 . . 2 3, 2 5 , 2 6 , 2 8
Schematic Diagrams
Sheet 2 of 31
Clock Generator
7
Clock Generator B - 3
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