Processor 2/7 - Clk, Misc - Clevo W110ER Service Manual

Schematic Diagrams

Processor 2/7 - CLK, MISC

Processor Pull downs
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
Sheet 3 of 48
resistor to 1.05VS_VTT .
Processor 2/7 -
CLK, MISC
H_CPUPWRGD
C601
*0.1u_16V_Y 5V_04
Buffered reset to CPU
12,22,28 PLT_RST#
B - 4 Processor 2/7 - CLK, MISC
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
10K_04 R343 H_CPUPWRGD_R
TRACE WIDTH 10MIL, LENGTH <500MILS
H_SNB_IVB#
23 H_SNB_IVB#
H_CATERR#
H_PECI_R
R342 *10mil_short_04
34 H_PECI
R99 56_1%_04 H_PROCHOT#_R
40,42 H_PROCHOT#
H_THRMTRIP#_R
R341 *10mil_short_04
23 H_THRMTRIP#
R340 *10mil_short_04 H_PM_SYNC_R
20 H_PM_SY NC
H_CPUPWRGD_R
R98 *10mil_short_04
23 H_CPUPWRGD
PMSY S_PWRGD_BUF R173 130_1%_04 VDDPWRGOOD_R
BUF_CPU_RST#
1.05VS_VTT
3.3VS
R356
75_04
R337 R357 BUF_CPU_RST#
43_1%_04
10K_04 D
Q18B
5 G L2N7002DW1T1G
S
D
2
G Q18A
S L2N7002DW1T1G
R336
100K_04
34 H_PROCHOT#_EC
U31B
A28
BCLK
C26 A27
PROC_SELECT# BCLK#
AN34
SKTOCC#
A16
DPLL_REF_CLK
A15
DPLL_REF_CLK#
AL33
CATERR#
AN33 R8 CPU_DRAMRST#
PECI SM_DRAMRST#
AL32 AK1 SM_RCOMP_0
PROCHOT# SM_RCOMP[0]
A5
SM_RCOMP_1
SM_RCOMP[1]
A4
SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29
XDP_PRDY #
PRDY #
AP27
XDP_PREQ#
PREQ#
AR26 XDP_TCLK
TCK
AR27 XDP_TMS
TMS
AM34 AP30 XDP_TRST#
PM_SYNC TRST#
AR28
XDP_TDI_R
TDI
AP26
XDP_TDO_R
TDO
AP33
UNCOREPWRGOOD
AL35 XDP_DBR_R
V8 DBR#
SM_DRAMPWROK
AT28
XDP_BPM0_R
BPM#[0]
AR29
XDP_BPM1_R
BPM#[1]
AR30 XDP_BPM2_R
BPM#[2]
AR33 AT30 XDP_BPM3_R
RESET# BPM#[3]
AP32 XDP_BPM4_R
BPM#[4]
AR31 XDP_BPM5_R
BPM#[5] AT31
XDP_BPM6_R
BPM#[6]
AR32
XDP_BPM7_R
BPM#[7]
Iv y Bridge_rPGA_2DPC_Rev 0p61
1.05VS_VTT
Processor Pull up
R87
TRACE WIDTH 10MIL, LENGTH <500MILS
62_04
H_PROCHOT#
Q5
G
MTN7002ZHS3 C151
47p_50V_NPO_04
CAD Note: Capacitor
R79
need to be placed
100K_04
close to buffer
output pin
2,6,11,16,18,19,20,22,23,24,25,27,28,29,30,35,37,38,39,40,42
9,10,11,12,18,19,20,21,22,23,24,25,27,28,30,31,32,33,34,35,40
PU/PD for JTAG signals
XDP_TMS R361
XDP_TDI_R R354
XDP_PREQ# R355
XDP_TDO_R R362
XDP_TCLK
R363
XDP_TRST# R348
XDP_DBR_R
R339
CLK_BCLK 19
CLK_BCLK# 19
CLK_DP 19
DDR3 Compensation Signals
CLK_DP# 19
SM_RCOMP_0 R384
SM_RCOMP_1 R137
SM_RCOMP_2
R138
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R199 *0_04
R198
1K_04
Q13
MTN7002ZHS3
CPU_DRAMRST# S D
R200 1K_04
DDR3_DRAMRST# 9,10
DRAMRST_CNTRL 6,19
R449
4.99K_1%_04 C433
0.047u_10V_X7R_04
1.5VS_CPU
S3 circuit:- DRAM PWR GOOD logic
R168
200_1%_04
R174 *10mil_short_04 PMSY S_PWRGD_BUF
20 PM_DRAM_PWRGD
6,9,10,35,37,38 1.5V
6,35 1.5VS_CPU
2,5,23,24,25,37,39,40 1.05VS_VTT
3.3V
3.3VS
1.05VS_VTT
51_04
51_04
*51_04
51_04
51_04
51_04
3.3VS
1K_04
140_1%_04
25.5_1%_04
200_1%_04