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Feature
North Bridge Chipset Configuration
Channel Dependent
Sparing
Channel 0
Channel Specific
Sparing
Rank Interleaving
Channel 1
Channel Specific
Sparing
Rank Interleaving
Boots Graphic Adapter
Priority
Read Completion
Coalescing
DRAM Clock
Option
Enabled
Channel dependent rank/DIMM sparing
enabled/disabled
Disabled
Enabled
Channel 0 enabled/disabled
Disabled
Disabled
Enables rank/DIMM sparing feature
Enabled
1:1
Rank Interleaving setting
2:1
4:1
Enabled
Channel 1 enabled/disabled
Disabled
Disabled
Enables rank/DIMM sparing feature
Enabled
1:1
Rank Interleaving setting
2:1
4:1
Auto
Select which graphic controller to use
as the primary boot device.
Onboard VGA
Disabled
Read returns of > 64B
Enabled
Auto
Auto
Auto: Dram Clock running by SPD
DDR533: Force memory running at 533
MHz
DDR533
64
Description
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