Alu (Arithmetic Logic Unit) And Registers; D (Decimal) Flag And Decimal Operations - Epson S1C6200A Core Cpu Manual

2 MEMORY AND OPERATIONS

2.3 ALU (Arithmetic Logic Unit) and Registers

Table 2.3.1 shows ALU operations between the 4-bit registers, TEMPA and TEMPB.
The Z (zero) flag is set when the result of ALU operation is
The C (carry) flag is set when an add operation causes a carry or when a subtract operation causes a
borrow.

2.3.1 D (decimal) flag and decimal operations

Setting the D (decimal) flag activates the decimal mode, allowing decimal addition and subtraction. Table
2.3.1.1 shows the relations of actual (decimal) results, ALU outputs, and the values of the C and Z flags.
Actual D = 0 : Result of
result hexadecimal operation
Z C
0 1 0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
10 0 0
11 0 0
12 0 0
13 0 0
14 0 0
15 0 0
16 1 1
17 0 1
18 0 1
19 0 1
20 0 1
21 0 1
22 0 1
23 0 1
24 0 1
25 0 1
26 0 1
27 0 1
28 0 1
29 0 1
30 0 1
31 0 1
10
Table 2.3.1 ALU register operation
Operation
Add, without carry
Add, with carry
Subtract, without borrow
Subtract, with borrow
Logical-AND
Logical-OR
Exclusive-OR
Comparison
Flag bit test
Rotate right, with carry
Rotate left, with carry
Invert
C 3
X 0
Table 2.3.1.1 Results of hexadecimal and decimal operations
Addition
D = 1 : Result of
decimal operation
ALU output Z C ALU output
0 1 0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
A 1 1
B 0 1
C 0 1
D 0 1
E 0 1
F 0 1
0 0 1
1 0 1
2 0 1
3 0 1
4 0 1
5 0 1
6 0 1
7 0 1
8 0 1
9 0 1
A 1 1
B 0 1
C 0 1
D 0 1
E 0 1
F 0 1
Instruction
ADD
ADC
SUB
SBC
AND
OR
XOR
CP
FAN
RRC
RLC
NOT
2 1 0
0 0 0
Actual D = 0 : Result of
result hexadecimal operation
Z C ALU output
0 -16 1 1
1 -15 0 1
2 -14 0 1
3 -13 0 1
4 -12 0 1
5 -11 0 1
6 -10 0 1
7 -9 0 1
8 -8 0 1
9 -7 0 1
0 -6 0 1
1 -5 0 1
2 -4 0 1
3 -3 0 1
4 -2 0 1
5 -1 0 1
6 0 1 0
7 1 0 0
8 2 0 0
9 3 0 0
A 4 0 0
B 5 0 0
C 6 0 0
D 7 0 0
E 8 0 0
F 9 0 0
0 10 0 0
1 11 0 0
2 12 0 0
3 13 0 0
4 14 0 0
5 15 0 0
EPSON
X: Don't care.
Subtraction
D = 1 : Result of
decimal operation
Z C ALU output
0 0 1 A
1 0 1 B
2 0 1 C
3 0 1 D
4 0 1 E
5 0 1 F
6 1 1 0
7 0 1 1
8 0 1 2
9 0 1 3
A 0 1 4
B 0 1 5
C 0 1 6
D 0 1 7
E 0 1 8
F 0 1 9
0 1 0 0
1 0 0 1
2 0 0 2
3 0 0 3
4 0 0 4
5 0 0 5
6 0 0 6
7 0 0 7
8 0 0 8
9 0 0 9
A 0 0 A
B 0 0 B
C 0 0 C
D 0 0 D
E 0 0 E
F 0 0 F
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