Epson S1C6200A Core Cpu Manual page 25

Mne-
Classification Operand
monic
Stack POP YH
operation
YL
instructions
F
LD SPH, r
SPL, r
r, SPH
r, SPL
Arithmetic ADD r, i
instructions
r, q
ADC r, i
r, q
SUB r, q
SBC r, i
r, q
AND r, i
r, q
OR r, i
r, q
XOR r, i
r, q
CP r, i
r, q
FAN r, i
r, q
RLC r
RRC r
INC Mn
DEC Mn
ACPX MX, r
ACPY MY, r
SCPX MX, r
SCPY MY, r
NOT r
S1C6200/6200A CORE CPU MANUAL
Operation Code
B A 9 8 7 6 5 4 3 2
1 1 1 1 1 1 0 1 1 0
1 1 1 1 1 1 0 1 1 0
1 1 1 1 1 1 0 1 1 0
1 1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 0 0 1
1 1 1 1 1 1 1 1 0 1
1 1 0 0 0 0 r1 r0 i3 i2
1 0 1 0 1 0 0 0 r1 r0
1 1 0 0 0 1 r1 r0 i3 i2
1 0 1 0 1 0 0 1 r1 r0
1 0 1 0 1 0 1 0 r1 r0
1 1 0 1 0 1 r1 r0 i3 i2
1 0 1 0 1 0 1 1 r1 r0
1 1 0 0 1 0 r1 r0 i3 i2
1 0 1 0 1 1 0 0 r1 r0
1 1 0 0 1 1 r1 r0 i3 i2
1 0 1 0 1 1 0 1 r1 r0
1 1 0 1 0 0 r1 r0 i3 i2
1 0 1 0 1 1 1 0 r1 r0
1 1 0 1 1 1 r1 r0 i3 i2
1 1 1 1 0 0 0 0 r1 r0
1 1 0 1 1 0 r1 r0 i3 i2
1 1 1 1 0 0 0 1 r1 r0
1 0 1 0 1 1 1 1 r1 r0
1 1 1 0 1 0 0 0 1 1
1 1 1 1 0 1 1 0 n3 n2
1 1 1 1 0 1 1 1 n3 n2
1 1 1 1 0 0 1 0 1 0
1 1 1 1 0 0 1 0 1 1
1 1 1 1 0 0 1 1 1 0
1 1 1 1 0 0 1 1 1 1
1 1 0 1 0 0 r1 r0 1 1
Flag
Clock
1 0 I D Z C
0 0 YH M(SP), SP
5
0 1 5 YL M(SP), SP
M(SP), SP
1 0 5 F
r1 r0 5 SPH
r1 r0 5 SPL
r1 r0 5 r SPH
r1 r0 5 r SPL
i1 i0 7 r r+i3~i0
q1 q0 7 r r+q
i1 i0 7 r r+i3~i0+C
q1 q0 7 r r+q+C
q1 q0 7 r r-q
i1 i0 7 r r-i3~i0-C
q1 q0 7 r r-q-C
i1 i0 7 r r i3~i0
q1 q0 7 r r q
i1 i0 7 r rVi3~i0
q1 q0 7 r rVq
i1 i0 7 r r i3~i0
q1 q0 7 r r q
i1 i0 7 r-i3~i0
q1 q0 7 r-q
i1 i0 7 r i3~i0
q1 q0 7 r q
r1 r0 7 d3 d2, d2
r1 r0 5 d3 C, d2
n1 n0 7 M(n3~n0)
n1 n0 7 M(n3~n0)
r1 r0 7 M(X)
r1 r0 7 M(Y)
r1 r0 7 M(X)
r1 r0 7 M(Y)
1 1 7 r r
EPSON
3 INSTRUCTION SET
Operation
SP+1
SP+1
SP+1
r
r
d1, d1 d0, d0 C, C
d3, d1 d2, d0 d1, C
M(n3~n0)+1
M(n3~n0)-1
M(X)+r+C, X X+1
M(Y)+r+C, Y Y+1
M(X)-r-C, X X+1
M(Y)-r-C, Y Y+1
d3
d0
19