Fujitsu MB91401 Datasheet page 57

Prelminary
2004.11.12
(5) UART
Parameter
Serial clock
cycle time
SCLK
SOUT delay time
Valid SIN
SCLK
SCLK
valid SIN hold time
Serial clock
"H" Pulse Width
Serial clock
"L" Pulse Width
SCLK
SOUT delay time
Valid SIN
SCLK
SCLK
valid SIN hold time
Note : timcycp is operational clock period of peripheral module built-in FR70E core.
Symbol Pin
tscyc SCK1, SCK0
tslov SOUT1, SOUT0
tivsh SIN1, SIN0
tshix SIN1, SIN0
tshsl SCK1, SCK0
tslsh SCK1, SCK0
tslov SOUT1, SOUT0
tivsh SIN1, SIN0
tshix SIN1, SIN0
Value
Conditions
Min
8 timcycp
80
Internal
shift clock
mode
100
60
4 timcycp
4 timcycp
External
shift clock
mode
60
60
MB91401
Unit Remarks
Max
ns
80 ns
ns
ns
ns
ns
150 ns
ns
ns
57