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Prelminary
2004.11.12
(3) Normal memory access
Parameter
Symbol
Address delay time
tchav
CSX delay time
tchcsl
CSX delay time
tchcsh
WRX delay time
tchwrl
WRX delay time
tchwrh
Data delay time
tchdv
RDX delay time
tchrdl
RDX delay time
tchrdh
Data setup
tdsrh
Data hold
trhdx
Note : tcycp is external memory clock cycle period.
MCLKO
A23 to A0
CSX2 to CSX0
WRX3 to WRX0
D31 to D0
RDX
D31 to D0
Pin
Typical timing
A23 to A0
MCLKO
CSX2 to CSX0
MCLKO
CSX2 to CSX0
MCLKO
WRX3 to WRX0
MCLKO
WRX3 to WRX0
MCLKO
D31 to D0
MCLKO
RDX
MCLKO
RDX
MCLKO
D31 to D0
MCLKO
D31 to D0
MCLKO
tcycp
tchav
tchcsl
tchwrl
tchdv
tchrdl
Value
Min
Max
0
tcycp 2
0
tcycp 2
0
tcycp 2
1
1
0
tcycp 2
1
1
19
1
tchcsh
tchwrh
tchrdh
tdsrh
trhdx
MB91401
Unit Remarks
7
ns
7
ns
7
ns
9
ns
9
ns
7
ns
9
ns
9
ns
ns
ns
55
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