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Fujitsu MB91401 Datasheet

Lsi network security system.
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FUJITSU SEMICONDUCTOR
DATA SHEET
32-Bit Proprietary Microcontroller
LSI Network Security System
MB91401
DESCRIPTION
The MB91401 is a network security LSI incorporating a Fujitsu's 32-bit, FR-family RISC microcontroller with 10/
100Base-T MAC Controller, encryption function and authentication function. The LSI contains an encryption
authentication hardware accelerator that boosts the LSI's performance for encryption and authentication commu-
nication (IKE/IPsec/SSL) to be demanded further.
The MAC controller has a packet filtering function that reduces the load on the CPU for an increasing amount of
packet processing. In addition, the board has the External interface for high-speed data communication with
various external hosts, USB ports as general-purpose interfaces, and various card interfaces.
FEATURES
Encryption and authentication processing by hardware accelerator function
The LSI performs processing five times faster than by the conventional combination of encryption/authentication
hardware macros and software or about 400 times faster than by software only. In addition, CPU processing load
factor to be involved in the encryption and the authentication processing can be decreased to 1/5 or less.
Also, the LSI uses the embedded accelerator to execute that public-key encryption algorithm about 100 times
faster than by software processing, which generally puts an extremely heavy load microcontrollers.
PACKAGE
244-pin plastic FBGA
(BGA-240P-M01)
Prelminary
2004.11.12
(Continued)

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   Summary of Contents for Fujitsu MB91401

  • Page 1

    MB91401 DESCRIPTION The MB91401 is a network security LSI incorporating a Fujitsu’s 32-bit, FR-family RISC microcontroller with 10/ 100Base-T MAC Controller, encryption function and authentication function. The LSI contains an encryption authentication hardware accelerator that boosts the LSI’s performance for encryption and authentication commu- nication (IKE/IPsec/SSL) to be demanded further.

  • Page 2

    • For DES-ECB/DES-CBC/3DES-ECB/3DES-CBC mode* • For MD5/SHA-1/HMAC-MD5/HMAC-SHA-1 mode • DH group: for 1 (MODP 768 bit) /2 (1024 bit) For the encryption/authentication macros, a software library is available by contacting the Fujitsu sales repre- sentative as required. * : Encryption function (DES/3DES) Method to encrypt, and to decrypt plaintext in 64 bits with code and decoding key to 56 bits.

  • Page 3

    Prelminary MB91401 2004.11.12 (Continued) CARD Interface (CompactFlash) The CompactFlash interface is a memory and I/O mode correspondence. It corresponds to the I/O of data such as not only the memory card but also the communication cards. C Interface • Master/slave sending and receiving •...

  • Page 4

    Prelminary MB91401 2004.11.12 PIN ASSIGNMENT INDEX 10 11 12 13 14 15 16 17 18 19 (TOP-VIEW) (SUB240W) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 : signal (204 lines) : PLLVDD (1 line) : PLLVSS (1 line) : VDDI (12 lines) 195, 200, 203, 207, 211, 215, 1219, 223...

  • Page 5

    Prelminary MB91401 2004.11.12 PIN NUMBER TABLE Pin name Pin name Pin name Pin Number Pin name Pin Number Pin Number Pin Number EXD11 CFD15 CFWEX EXD14 USBINS ICLK CFCE1X CFCD2X ICS0 CFIORDX UCLKSEL CFRESET CFA1 CFWAITX CFREGX UCLK48 CFA5 N.C. CFA0 CFA8 CFOEX...

  • Page 6

    Prelminary MB91401 2004.11.12 PIN DESCRIPTION [SYSTEM] [ETHERNET MAC CONTROLLER] XINI TXCLK INITXI TXD3 to TXD0 NMIX TXEN INT7 to INT5 RXCLK MDI2 to MDI0 RXER [OSCILLATOR] RXD3 to RXD0 OSCEA RXDV OSCC RXCRS OSCEB MB91401 [PLL CONTROL] MDCLK PLLS MDIO PLLSET1, PLLSET0 [EXTERNAL IF] PLLBYPAS...

  • Page 7

    Prelminary MB91401 2004.11.12 SYSTEM (9 pin) Pin name Pin no. Function/application Polarity Circuit Clock input pin XINI Input pin of clock generated in clock generator. 10 MHz to 50 MHz frequency can be input. Reset input pin This pin inputs a signal to initialize the LSI. Nega- When turning on the power supply, apply “0”...

  • Page 8

    Prelminary MB91401 2004.11.12 ICE (9 pin) Pin name Pin no. Function/application Polarity Circuit Emulator break request pin BREAKI This pin inputs the emulator break request when an ICE is connected. ICS2 Emulator chip status pins ICS1 These pins output the emulator status when an ICE is ICS0 connected.

  • Page 9

    Prelminary MB91401 2004.11.12 UART (6 pin) Pin name Pin no. Function/application Polarity Circuit SIN1 Serial data input pins SIN0 Serial data input pin of UART built-in FR core. SOUT1 Serial data output pins SOUT0 Serial data output pin of UART built-in FR core. SCK1 Serial clock I/O pins SCK0...

  • Page 10

    Prelminary MB91401 2004.11.12 (Continued) Pin name Pin no. Function/application Polarity Circuit Data input/output pins 32 bits data input/output signal pin. CSX6 Chip select output pins Nega- CSX1 3-bit chip select signal pin. tive CSX0 Output the “L” level when accessing to external memory. Read strobe output pin Nega- Read strobing signal pin.

  • Page 11

    Prelminary MB91401 2004.11.12 ETHERNET MAC CONTROLLER (17 pin) Pin name Pin no. Function/application Polarity Circuit Clock input for reception pin RXCLK MII sync signal during reception. The frequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps. Receive error input pin Posi- RXER...

  • Page 12

    Prelminary MB91401 2004.11.12 EXTERNAL IF (23 pin) Pin name Pin no. Function/application Polarity Circuit Nega- External chip select input pin EXCSX tive Chip select input pin from external host. External address input pin Address input pin from external host. “0” : Register select “1”...

  • Page 13

    Prelminary MB91401 2004.11.12 USB IF (5 pin) Pin name Pin no. Function/application Polarity Circuit USB data D (differential) pin I/O signal pin on the plus side of the USB data. Use the LSI with 25 to 30 recommended) external series load resistors, 1.5 k pull-up resistors and about 100 k resistors.

  • Page 14

    Prelminary MB91401 2004.11.12 CARD IF (41 pin) Pin name Pin no. Function/application Polarity Circuit CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CF data input/output pins CFD8 I/O data/status/command signal pin to CompactFlash card CFD7 side CFD6 CFD5 CFD4 CFD3 CFD2 CFD0 CFD0 CFA10...

  • Page 15

    Prelminary MB91401 2004.11.12 (Continued) Pin name Pin no. Function/application Polarity Circuit Card connection detect input pin : CFCD1X Nega- Checking connection pin of the socket and CompactFlash CFCD1X tive card. It is shown that the CompactFlash card was connected when this signal and CFCD2X are both input by “0”. CF side GND input pin GND level detection pin from CompactFlash side.

  • Page 16

    Prelminary MB91401 2004.11.12 C IF (2 pin) Pin name Pin no. Function/application Polarity Circuit Serial data line input/output pin C bus data I/O pin Serial clock line input/output pin C bus clock I/O pin Power Supply/GND (39 pin) Pin name Pin no.

  • Page 17

    Prelminary MB91401 2004.11.12 I/O CIRCUIT TYPE Type Circuit Remarks Digital output With pull/down CMOS level output CMOS level input Digital output Value of pull-down resistance approx. 33 k (Typ) Digital input Digital output] CMOS level output CMOS level input Digital output Digital input D input D input...

  • Page 18

    Prelminary MB91401 2004.11.12 (Continued) Type Circuit Remarks CMOS level input Digital input With pull-up CMOS level input Value of pull-up resistance approx. 33 k (Typ) Digital input Digital output CMOS level output Digital output Oscillation output Control Oscillation circuit...

  • Page 19

    Prelminary MB91401 2004.11.12 HANDLING DEVICES Preventing Latch-up When a voltage that is higher than V and a voltage that is lower than V are impressed to the input terminal and the output terminal in CMOS IC or the voltage that exceeds ratings between V to V is impressed, the latch-up phenomenon might be caused.

  • Page 20

    Prelminary MB91401 2004.11.12 Figure When you share the power supply for digital and for VCO VDD (for digital PLLVDD (for VCO) Logic part APLL Power supply PLLVSS Treatment of the unused pins Leaving unused input pins open results in a malfunction, so process the pull-up or pull-down. Treatment of OPEN pins Be sure to use open pins in open state.

  • Page 21

    Prelminary MB91401 2004.11.12 CONNECTED SPECIFICATION OF MB91401 AND ICE Recommended type and circuit configuration of the emulator interface connector mounting on the user system, attention when designing and wiring regulation are shown. When the flat cable is used, the combination of the connectors with housing should be selected. Recommended connector type Attached cable Part number...

  • Page 22

    Prelminary MB91401 2004.11.12 Precaution when designing When evaluation MCU on the user system is operated in the state that the emulator is not connected, should be treated as follow each input terminal of evaluation MCU connected with the emulator interface on the user system.

  • Page 23

    Prelminary MB91401 2004.11.12 JTAG The JTAG function is installed in this LSI. Note that the terminal INITXI should be input in "L" when using JTAG. Notes when quartz vibrator is mounted The crystal oscillation circuit built into this LSI operates by the following compositions. MB91401 OSCEB OSCC...

  • Page 24

    Note : These reference values are standards. The constant changes according to the characteristic of the quartz vibrator used. Therefore, we will recommend the initial evaluation that uses the evaluation sample to the decision of the circuit constant. Please contact FUJITSU representatives about the evaluation sample. Notes when encryption/authentication accelarator is used When using the encryption/authentication installed in this LSI, it is necessary to the following notes.

  • Page 25

    Prelminary MB91401 2004.11.12 Notes as device Treatment of Unused Input Pins It causes the malfunction that the unused input terminal is made open, and do the processing such as 1 stack or 0 stacks. About Mode pins (MDI2 to MDI0) Connect these pins with the input buffer by 1 to 1 to prevent the malfunction by the noise, and connect directly to VDD or VSS outside of ASIC.

  • Page 26

    Prelminary MB91401 2004.11.12 • The instruction fetch is not done from D-bus, and does not set the code area on D-bus RAM. • Set neither stack area nor the vector table on the instruction RAM. • The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event or emulator menu: (1) The D0 and D1 flags are updated in advance.

  • Page 27

    Prelminary MB91401 2004.11.12 External bus interface • When the bus width of the area set up as little endian is 32-bit, confine to word (32-bit) access when accessing the relevant area. • When enabling prefetch to the area set to the Little endian, give the access to the corresponding area as word (32 bits) access limitation.

  • Page 28

    Prelminary MB91401 2004.11.12 NOTES OF DEBUG Step execution of RETI instruction In an environment where interrupts frequently occur during single-step execution, only the relevant interrupt processing routines are executed repeatedly during single-step execution of the RETI instruction. This will prevent the main routine and low-interrupt-level programs from being executed.

  • Page 29: Block Diagram

    Prelminary MB91401 2004.11.12 BLOCK DIAGRAM FR core Crystal Unit CLKIN D-RAM (8 KB) I-Cach (4 KB) USB CLK (48 MHz) Cont DMAC Serial IF UART Timer (2ch) DSU IF INT/NMI Authentication macro LAN controller IPsec Accelerator 10/100 Ethernet (IKE Accelerator) MAC Controller DES/3DES L3/L4 Filtering...

  • Page 30

    Prelminary MB91401 2004.11.12 MEMORY SPACE Memory space The FR family has 4 GByte of logical addresses (2 address) which can be linearly accessed by the CPU. Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction.

  • Page 31

    Prelminary MB91401 2004.11.12 GENERAL PURPOSE REGISTERS 32 bits Initial Value: XXXX XXXX XXXX XXXX 0000 0000 Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory access pointers for CPU operations. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions are enhanced.

  • Page 32

    Prelminary MB91401 2004.11.12 MODE SETTINGS The FR family uses the mode pins (MDI2 to MDI0) and the mode register (MODR) to set the operation mode. Mode Pins Three mode pins MDI[2], MDI[1], and MDI[0] are used to specify a mode vector fetch or test mode. Mode pins Reset vector Mode name...

  • Page 33

    Prelminary MB91401 2004.11.12 [bit1, bit0] WTH1, WTH0 (Bus width setting bits) These bits specify the bus width. The value of the bits is set in the DBW1 and DBW0 bits in ACR0 (CSO area). Set these bits to a value other than “11”. WTH1 WTH0 Function...

  • Page 34

    Prelminary MB91401 2004.11.12 I/O MAP This shows the location of the various peripheral resource registers in the memory space. [How to read the table] Register Address Block 0000_0000 Reserved 0000_003C EIRR [R/W] ENIR [R/W] ELVR [R/W] 0000_0040 Ext Int 00000000 00000000 00000000 00000000 Read/Write attribute...

  • Page 35

    Prelminary MB91401 2004.11.12 Register Address Block SSR0 [R/W] SIDR0 [R/W] SCR0 [R/W] SMR0 [R/W] 0000_0060 UART0 00001-00 XXXXXXXX 00000100 00--0-0- UTIM0 [R] (UTIMR0 [W]) DRCL0 [W] UTIMC0 [R/W] 0000_0064 U-TIMER0 00000000 00000000 -------- 0--00001 SSR1 [R/W] SIDR1 [R/W] SCR1 [R/W] SMR1 [R/W] 0000_0068 UART1...

  • Page 36

    Prelminary MB91401 2004.11.12 Register Address Block 0000_0308 Reserved 0000_03E0 ICHRC [R/W] Instruction 0000_03E4 0-000000 Cache 0000_03E8 Reserved 0000_03EC BSD0 0000_03F0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] 0000_03F4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Bit Search Module BSDC 0000_03F8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR 0000_03FC XXXXXXXX XXXXXXXX...

  • Page 37

    Prelminary MB91401 2004.11.12 (Continued) Register Address Block ICR44[R/W] ICR45[R/W] ICR46[R/W] ICR47[R/W] Interrupt Control 0000_046C ---11111 ---11111 ---11111 ---11111 Unit 0000_0470 Reserved 0000_047C RSRR [R/W] STCR [R/W] TBCR [R/W] CTBR [R/W] 0000_0480 10000000* 00110011* 00XXXX00* XXXXXXXX Clock Control Unit WPR [W] DIVR0 [R/W] DIVR1 [R/W] 0000_0484...

  • Page 38

    Prelminary MB91401 2004.11.12 (Continued) Register Address Block 0000_067C CSER [R/W] CHER [R/W] TCR [R/W] 0000_0680 00000001 XXXXXXX1 00000000* Memory IF 0000_0684 00XXXXXX 00XXXXXX 0000_0688 Reserved 0000_0FFC *1 : An initial value is a different register at the reset level. The display is the one at the INIT level. *2 : An initial value is a different register at the reset level.

  • Page 39

    Prelminary MB91401 2004.11.12 Register Address Block BSR[R] BCR[R/W] CCR[R/W] ADR[R/W] 010F_0000 00000000 00000000 10000000 1XXXXXXX DAR[R/W] BC2R[R/W] 010F_0004 XXXXXXXX 00XX0000 010F_0008 (Reserved) 010F_FFFF Register Address Block DLCR0* DLCR1[R, W] DLCR2* DLCR3[R/W] 0110_0000 LAN controller 0X000000 00000000 00000000 00000000 DLCR4* DLCR5* DLCR6* DLCR7* 0110_0004...

  • Page 40

    Prelminary MB91401 2004.11.12 (Continued) Register Address Block SMI_CMD[R/W] 0110_0028 00000000-00000000 SMI_CMD_ST 0110_002C [R/W] 00XXXXXX SIM IF SMI_DATA [R/W] 0110_0030 00000000-00000000 SMI_POLLINTVL [R/W] 0110_0034 00000000-00000000 SMI_PHY_ADD 0110_0038 [R/W] 00000XXX SMI_CONTROL 0110_003C [R/W] 111XXXXX SMI_STATUS[R] 0110_0040 SIM IF XXXXXXXX SMI_INTENABLE 0110_0044 [R/W] 0XXXXXXX SMI_MDCDIV 0110_0048...

  • Page 41

    Prelminary MB91401 2004.11.12 Register Address Block EXIFRXDR 0114_0000 00000000-00000000 00000000-00000000 EXIFTXDR 0114_0004 00000000-00000000 00000000-00000000 EXIFRXR[R] 0114_0008 00000000-00000000 EXIFTXR[W] 0114_000C 00000000-00000000 External IF EXIFCR[W] 0114_0010 00000000-0XXXXXXX EXIFSR[R] 0114_0014 00000000-00XXXXXX EXIFRXSR 0114_0018 00000000-00000000 00000000-00000000 EXIFTXSR 0114_001C 00000000-00000000 00000000-00000000 PIOCR[R/W] 0114_0020 00000000 GPIO PIODR[R/W] 0114_0024 Connecting...

  • Page 42

    Prelminary MB91401 2004.11.12 Register Address Block FIFO0out[R] FIFO0in[W] 0540_0000 XXXXXXXX-XXXXXXXX XXXXXXXX-XXXXXXXX FIFO1[R] FIFO2[W] 0540_0004 XXXXXXXX-XXXXXXXX XXXXXXXX-XXXXXXXX FIFO3[W] 0540_0008 XXXXXXXX-XXXXXXXX 0540_000C (Reserved) 0540_001F CONT1[R/W] 0540_0020 XXXXX0XX-XXX00000 CONT2[R/W] CONT3[R/W] 0540_0024 XXXXXXXX_XXX00000 XXXXXXXX_XXX00000 CONT4[R/W] CONT5[R/W] 0540_0028 XXXXXXXX_XXX00000 XXXXXXXX_XXXX00XX CONT6[R/W] CONT7[R/W] 0540_002C XXXXXXXX_XXXX00XX XXXXXXXX_XXX00000 CONT8[R/W] CONT9[R/W] 0540_0030...

  • Page 43

    Prelminary MB91401 2004.11.12 (Continued) Register Address Block ST2[R] ST3[R/W] 0540_0068 XXXXXXXX-X0000000 XXXXXXXX-XXX00000 ST4[R] ST5[R/W] 0540_006C XXXXX000-00000000 XXXX0XXX-XX000000 0540_0070 (Reserved) 0540_007B RESET[R/W] 0540_007C XXXXXXXX-XXXXXX00 0540_0080 (Reserved) 0540_FFFF Register Address Block MACRORR[W/R] CARDSR[R/W] 0580_0000 00000000-00000001 00000000-00000000 CARDIMR[R/W] CARDISR[R] 0580_0004 Chip Register 00000000-00000000 00000000-00000000 USBPLLRP[R/W] 0580_0008...

  • Page 44

    Prelminary MB91401 2004.11.12 INTERRUPT VECTOR Interrupt number Interrupt Address of TBR Interrupt source Offset Hexa- level default Decimal decimal Reset 000FFFFC Mode vector 000FFFF8 System reserved 000FFFF4 System reserved 000FFFF0 System reserved 000FFFEC System reserved 000FFFE8 System reserved 000FFFE4 Coprocessor absent trap 000FFFE0 Coprocessor error trap 000FFFDC...

  • Page 45

    Prelminary MB91401 2004.11.12 Interrupt number Interrupt Address of TBR Interrupt source Offset Hexa- level default Decimal decimal DMAC3 (end, error) ICR18 000FFF74 DMAC4 (end, error) ICR19 000FFF70 System reserved ICR20 000FFF6C System reserved ICR21 000FFF68 System reserved ICR22 000FFF64 System reserved ICR23 000FFF60 System reserved...

  • Page 46

    Prelminary MB91401 2004.11.12 (Continued) Interrupt number Interrupt Address of TBR Interrupt source Offset Hexa- level default Decimal decimal System reserved 000FFEEC System reserved 000FFEE8 System reserved 000FFEE4 System reserved 000FFEE0 System reserved 000FFEDC System reserved 000FFED8 System reserved 000FFED4 System reserved 000FFED0 System reserved 000FFECC...

  • Page 47

    Prelminary MB91401 2004.11.12 ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Rating Parameter Symbol Unit Remarks Power supply voltage* Internal Analog power supply voltage PLLVDD Input voltage* VDDE Output voltage* VDDE “L” level maximum output current T.B.D “L” level average output current T.B.D OLAV “L”...

  • Page 48

    No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

  • Page 49

    Prelminary MB91401 2004.11.12 3. DC Characteristics • Other than USB (VSS PLLVSS 0 V) Value Parameter Conditions Unit Symbol “H” level input VDDE voltage “L” level input voltage “H” level output 3.0 V, VDDE voltage 4.0 mA “L” level output 3.0 V, voltage 4.0 mA...

  • Page 50

    Prelminary MB91401 2004.11.12 (VSS PLLVSS 0 V) Value Parameter Conditions Unit Symbol Remarks “H” level output 100 A VDDE 0.2 VDDE voltage “L” level output 100 A voltage “H” level output 0.4 V current “L” level output 0.4 V current output short circuit mA *1 current...

  • Page 51

    Prelminary MB91401 2004.11.12 USB Specification Revision 1.1 Value Parameter Symbol Unit Remarks Input Levels High (driven) Diffential Input Sensitivity Differential Common Mode Range Output Levels High (driven) Output Signal Crossover Voltage Terminations Bus Pull-up Resistor on Upstream Port 1.425 1.575 1.5 k Termination Voltage for Upstream Port TERM...

  • Page 52

    Prelminary MB91401 2004.11.12 *4 : <Output Levels V > The cross voltage of the external differential output signals (D and D ) falls within the range from 1.3 V to 2.0 V. Max 2.0 V standard range Max 1.3 V *5 : <Terminations V >...

  • Page 53

    Prelminary MB91401 2004.11.12 4. AC Characteristics The following measurement conditions depending on the supply voltage apply to the MB91401 unless otherwise specified. AC measurement condition Input Output Load condition 55 pF (1) Clock Value Parameter Symbol Conditions Unit Remarks Fclkcyc XINI External clock 10.0...

  • Page 54

    Prelminary MB91401 2004.11.12 (2) Reset Value Parameter Conditions Unit Remarks Symbol After power At unusing of PLL 5 tcp Reset input time trstl INITXI supply & At using of PLL input clock PLL reset input time tprstl PLLS At using of PLL stabilization Note : tcp is internal CPU and clock cycle period for peripheral module.

  • Page 55

    Prelminary MB91401 2004.11.12 (3) Normal memory access Value Parameter Symbol Typical timing Unit Remarks Address delay time tchav A23 to A0 MCLKO tcycp 2 CSX delay time tchcsl CSX2 to CSX0 MCLKO tcycp 2 CSX delay time tchcsh CSX2 to CSX0 MCLKO tcycp 2 WRX delay time...

  • Page 56

    Prelminary MB91401 2004.11.12 (4) Ready input Value Parameter Symbol Typical timing Unit Remarks RDY setup trdys MCLKO RDY hold trdyh MCLKO MCLKO trdys trdys trdyh trdyh...

  • Page 57

    Prelminary MB91401 2004.11.12 (5) UART Value Parameter Symbol Conditions Unit Remarks Serial clock tscyc SCK1, SCK0 timcycp cycle time SCLK tslov SOUT1, SOUT0 Internal SOUT delay time shift clock Valid SIN mode tivsh SIN1, SIN0 SCLK SCLK tshix SIN1, SIN0 valid SIN hold time Serial clock tshsl...

  • Page 58

    Prelminary MB91401 2004.11.12 Internal shift clock mode tscyc SCK1, SCK0 tslov SOUT1, SOUT0 tshix tivsh SIN1, SIN0 External shift clock mode tslsh tshsl SCK1, SCK0 tslov SOUT1, SOUT0 tshix tivsh SIN1, SIN0...

  • Page 59

    Prelminary MB91401 2004.11.12 (6) MII interface Value Parameter Symbol Typical timing Unit Remarks TXEN delay time tdel_txen TXEN TXCLK TXD delay time tdel_txd TXD3 to TXD0 TXCLK RXDV setup time tsu_rxdv RXDV RXCLK RXSV Hold Time thd_rxdv RXDV RXCLK RXD setup time tsu_rxd RXD3 to RXD0 RXCLK...

  • Page 60

    Prelminary MB91401 2004.11.12 Reception RXCLK thd_rxdv RXDV tsu_rxdv thd_rxdv RXD3 to RXD0 tsu_rxd RXCLK thd_rxdv tsu_rxdv RXDV tsu_rxd RXD3 to RXD0 thd_rxdv RXCLK thd_rxer tsu_rxer RXER tsu_rxer thd_rxer...

  • Page 61

    Prelminary MB91401 2004.11.12 (7) MDIO interface Value Parameter Symbol typical timing Unit Remarks MDIO setup time tsu_mdio MDIO MDCLK MDIO Hold Time thd_mdio MDIO MDCLK MDIO delay time tdel_mdio MDIO MDCLK MDIO switching time tdel_turnon MDIO MDCLK OUT) MDIO switching time tdel_turnoff MDIO MDCLK...

  • Page 62

    Prelminary MB91401 2004.11.12 (8) External IF Read access Value Parameter Symbol Unit Remarks EX Read Cycle time texrc EXA, EXCSX EXA to Data Valid texadv EXA, EXD EXCSX to Data Valid texcsdv EXCSX, EXD EXRDX to Data Out Enable texdoe EXRDX, EXD EXRDX “H”...

  • Page 63

    Prelminary MB91401 2004.11.12 Write access Value Parameter Symbol Unit Remarks EX Write Cycle time texwc EXA, EXCSX EXA to Data Setup time texads EXA, EXD EXCSX to Data Setup time texcsds EXCSX, EXD EXWRX “L” Pulse width texwp EXRDX, EXD EXD Setup time texds EXRDX, EXD...

  • Page 64

    Prelminary MB91401 2004.11.12 (9) USB interface Value Parameter Symbol Unit Remarks Input clock tucyc UCLK48 MHz 2500ppm accuracy* RISE Time tutfr UDP, UDM Fall Time tutff UDP, UDM Differential Rise and Fall tutfrfm UDP, UDM 111.11 Timing Matching Driver Output Resistance tzdrv UDP, UDM tucyc...

  • Page 65

    Prelminary MB91401 2004.11.12 Full-speed Buffer to 44 Equiv. Imped 50 pF to 44 Equiv. Imped 50 pF 3-State Notes : Driver output impedance 3 to 19 Rs series resistance: 25 to 30 Add a series resistor of preferably 27...

  • Page 66

    Prelminary MB91401 2004.11.12 (10) I C interface Input timing specification Value Parameter Symbol Unit Remarks SDA input setup time ts2sdai SDA input hold time th2sdai SCL cycle time tcscli SCL input “H” pulse time twhscli SCL input “L” pulse time twlscli SCL input setup time ts2scli...

  • Page 67

    Prelminary MB91401 2004.11.12 (11) Card IF Read access Value Parameter Symbol Unit Remarks CFA10 to CFA0, CF Read Cycle time tcfrc CFCE2X, CFCE1X CFA10 to CFA0, CFA to Data Valid tcfadv CFD15 to CFD0 CFCE2X, CFCE1X, CFCEX to Data Valid tcfcedv CFD15 to CFD0 CFOEX CFIORDX to Data Out...

  • Page 68

    Prelminary MB91401 2004.11.12 Write access Value Parameter Symbol Unit Remarks CFA10 to CFA0, CF Write Cycle time tcfwc CFCE2X, CFCE1X CFA10 to CFA0, CFA to Data Setup time tcfads CFD15 to CFD0 CFCE2X, CFCE1X, CFCEX to Data Setup time tcfceds CFD15 to CFD0 CFWEX CFIOWRX “L”...

  • Page 69

    Prelminary MB91401 2004.11.12 ORDERING INFORMATION Part number Package Remarks 240-pin plastic FBGA MB91401 (BGA-240P-M01)

  • Page 70

    W V U T R P N M L K J H G F E D C B A 0.25±0.10 (.010±.004) (Stand off) 1999 FUJITSU LIMITED B240001S-2C-2 Dimensions in mm (inches). Note : The values in parentheses are reference values.

  • Page 71

    Prelminary MB91401 2004.11.12 MEMO...

  • Page 72

    Sunnyvale, CA 94088-3470, U.S.A. of the use or exercise of any intellectual property right, such as Tel: +1-408-737-5600 patent right or copyright, or any other right of Fujitsu or any third Fax: +1-408-737-5999 party or does Fujitsu warrant non-infringement of any third-party’s http://www.fma.fujitsu.com/...

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