Fujitsu MB91401 Datasheet page 66

MB91401
(10) I 2 C interface
Input timing specification
Parameter
SDA input setup time
SDA input hold time
SCL cycle time
SCL input "H" pulse time
SCL input "L" pulse time
SCL input setup time
SCL input hold time
* : Initial Value : I 2 C bus standards.
STOP START
SDA (input)
ts2scli
SCL (input)
Output timing specification
Parameter
SCL output cycle time
SCL output "H" Pulse Time
SCL output "L" Pulse Time
SCL output setup time
SCL output hold time
SDA output hold time
* : For value m, refer to Section 7.5.2.3 "Clock Control Register (CCR) in the I
indicates I 2 C interface operating clock frequency.
STOP
SDA (output)
ts2sclo
SCL (output)
66
Symbol Pin
ts2sdai SDA
th2sdai SDA
tcscli SCL
twhscli SCL
twlscli SCL
ts2scli SCL
th2scli SCL
D7 D6 D5 D4
th2scli ts2sdai th2sdai
Symbol Pin
tcsclo SCL
twhsclo SCL
twlsclo SCL
ts2sclo SCL
th2sclo SCL
th2sdao SDA
START
D7 D6 D5
th2sclo th2sdao
Value
Min Max
250
0
10
4
4.7
4
4.7
D3 D2 D1 D0
tcscli twhscli
Value
Min Max
(2 m) 2
m 2
m
m 2
m 2
5
2 C Interface Specifications." PCLK
D4 D3 D2 D1 D0
tcsclo twhsclo
Prelminary
2004.11.12
Unit Remarks
ns *
ns *
s *
s *
s *
s *
s *
RESTART
ACK
ts2scli th2scli
twlscli
Unit Remarks
PCLK *
PCLK *
PCLK *
PCLK *
PCLK *
PCLK *
RESTART
ACK
ts2sclo th2sclo
twlsclo