Fujitsu MB91401 Datasheet page 11

Prelminary
2004.11.12
ETHERNET MAC CONTROLLER (17 pin)
Pin name Pin no.
RXCLK 48
RXER 113
RXDV 172
RXCRS 115
RXD3 114
RXD2 47
RXD1 112
RXD0 45
COL 173
TXCLK 46
TXEN 43
TXD3 171
TXD2 170
TXD1 111
TXD0 44
MDCLK 222
MDIO 224
I/O
Polarity Circuit
Clock input for reception pin
IN D MII sync signal during reception. The frequency is 2.5 MHz
at 10 Mbps and 25 MHz at 100 Mbps.
Receive error input pin
Posi-
IN D It is recognized that there is an error in the reception packet
tive
when "1" is input from the PHY device at receiving.
Posi- Receive data valid input pin
IN D
tive It is recognized that receive data is effective.
Career sense input pin
Posi-
IN D The state that the reception or the transmission is done is
tive
recognized.
Receive data input pins
IN D
4-bit data input from PHY device.
Collision detection input pin
Posi- When TXEN signal is active and "1", the collision is
IN D
tive recognized. The collision is not recognized without these
conditions.
Clock input for transfer pin
IN D It becomes synchronous of MII when transmitting. The
frequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps.
Transfer enable output pin
Posi-
OUT F It is shown that effective data is on the TXD bus. It is output
tive
synchronizing with TXCLK.
Transfer data output pins
OUT F 4-bit data bus sent to the PHY device. It is output
synchronizing with TXCLK.
SMI clock output pin
OUT F SMI IF clock pin
Connect to SMI clock input pin of PHY device.
SMI data input/output pin
I/O B
Connect to SMI data of PHY device.
MB91401
Function/application
11