AMD 3200 - Athlon 64 2.0 GHz Processor Manual page 87

Rev October Revision Guide for AMD Family h Models h- Fh Processors
DRAM Scrub Request During Register Write May Cause
Unpredictable Behavior
Description
The default BIOS sequence for enabling DRAM scrubbing and performing configuration accesses to enable
DRAM phy power savings results in the possibility that a DRAM scrub event is occurring simultaneously to a
BIOS write to a register accessed through the DRAM Controller Additional Data Index Data port of
D F x dct and D F x C dct In the event that these operations occur at the same time the
processor DRAM controller may enter an invalid state
DRAM scrubbing is enabled when the value in Scrub Rate Control Register DramScrub D F x is not
equal to b or when the DRAM Scrub Address Low Register ScrubReDirEn D F x C is equal to
b BIOS does not enable DRAM scrubbing unless the DIMMs support ECC
Potential Effect on System
All future reads of the memory attached to the affected DRAM controller return unpredictable data The
processor may report but not necessarily in all circumstances an uncorrectable DRAM ECC machine check
error The system may hang or reset during the BIOS boot process or the inconsistent memory data may cause a
system crash
This failure is highly intermittent over multiple boot cycles
Suggested Workaround
BIOS should complete all writes to any register in the range of D F x C x dct through
D F x C x D F FFFF dct prior to enabling DRAM scrubbing Specifically the writes that are
BIOS and Kernel Developer's Guide BKDG for AMD Family h Models h- Fh
recommended by the
Processors order
section "DRAM Phy Power Savings" should be performed earlier in the DCT
initialization sequence so that they do not occur while scrubbing is enabled provided that they are performed
after completing DRAM data training
Fix Planned
No fix planned
Product Errata