AMD 3200 - Athlon 64 2.0 GHz Processor Manual page 7

Rev October
Conventions
Numbering
Binary numbers Binary numbers are indicated by appending a "b" at the end e g
Decimal numbers Unless specified otherwise all numbers are decimal This rule does not apply to the
register mnemonics
Hexadecimal numbers Hexadecimal numbers are indicated by appending an "h" to the end e g
Underscores in numbers Underscores are used to break up numbers to make them more readable They do
not imply any operation e g
Undefined digit An undefined digit in any radix is notated as a lower case "x"
Register References and Mnemonics
In order to define errata workarounds it is sometimes necessary to reference processor registers References to
registers in this document use a mnemonic notation consistent with that defined in the
Developer's Guide BKDG for AMD Family
a concatenation of the register-space indicator and the offset of the register The mnemonics for the various
register spaces are as follows
IOXXX x -defined input and output address space registers XXX specifies the byte address of the I O
register in hex this may be or digits This space includes the I O-Space Configuration Address Register
IOCF and the I O-Space Configuration Data Port IOCFC to access configuration registers
DZFYxXXX PCI-defined configuration space at bus
specifies the byte address of the configuration register this may be or digits in hex Y specifies the
function number For example D F x
Some registers in D F xXXX have a dct
DRAM controller DCT The DCT instance is selected by DCT Configuration Select DctCfgSel
D F x C
DZFYxXXX xZZZZZ Port access through the PCI-defined configuration space at bus
device address in hex XXX specifies the byte address of the data port configuration register this may be or
digits in hex Y specifies the function number ZZZZZ specifies the port address this may be to digits
in hex For example D F x C x C specifies the port Ch register accessed using the data port register at
bus device h function
AMD Family h Models
D F xXXX xZZZZZ have a dct
controller DCT The DCT instance is selected by DCT Configuration Select DctCfgSel D F x C
APICXXX APIC memory-mapped registers XXX is the byte address offset from the base address in hex
this may be or digits The base address for this space is specified by the APIC Base Address Register
APIC BAR at MSR
CPUID FnXXXX XXXX RRR xYYY processor capability information returned by the CPUID instruction
where the CPUID function is XXXX XXXX in hex and the ECX input is YYY if specified When a
register is specified by RRR the reference is to the data returned in that register For example CPUID
Fn EAX refers to the data in the EAX register after executing CPUID instruction function
h
MSRXXXX XXXX model specific registers XXXX XXXX is the MSR number in hex This space is
accessed through x -defined RDMSR and WRMSR instructions
PMCxXXX Y performance monitor events XXX is the hexadecimal event counter number programmed
into MSRC A
unit mask programmed into MSRC
Revision Guide for AMD Family
b
h Models
specifies the register at bus
mnemonic suffix which indicates there is one instance per
address Ch Refer to the
h- Fh Processors order
mnemonic suffix which indicates there is one instance per DRAM
B
EventSelect PERF CTL
A
Conventions
h- Fh Processors order
Z specifies the PCI device address in hex XXX
device
BIOS and Kernel Developer's Guide BKDG for
for access properties Some registers in
bits Y when specified signifies the
UnitMask PERF CTL
h Models h- Fh Processors
b
F h
BIOS and Kernel
Each mnemonic is
h function address h
Z specifies the PCI
bits