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Opteron 6200 Series
AMD Opteron 6200 Series Manuals
Manuals and User Guides for AMD Opteron 6200 Series. We have
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AMD Opteron 6200 Series manual available for free PDF download: Manual
AMD Opteron 6200 Series Manual (91 pages)
Revision Guide for AMD Family 15h Models 00h-0Fh
Brand:
AMD
| Category:
Computer Hardware
| Size: 1.01 MB
Table of Contents
List of Tables
4
Table of Contents
4
Revision History
5
Table Arithmetic and Logic Operators
8
Table CPUID Values for AMD Family
9
Processor Identification
9
Table CPUID Values for AMD Family
10
Table Supported Mixed Revision Configurations
11
Table Cross Reference of Product Revision to OSVW ID
13
Product Errata
14
Table Cross-Reference of Processor Revision to Errata
14
Table Cross-Reference of Errata to Package Type
18
Table Cross-Reference of Errata to Processor Segments
22
Breakpoint Due to an Instruction that Has an Interrupt
24
Shadow May be Lost
24
APIC Task-Priority Register May be Incorrect
25
Corrected L Errors May Lead to System Hang
26
Scrub Rate Control Register Address Depends on Dctcfgsel
27
Some Lightweight Profiling Counters Stop Counting When
28
Instruction-Based Sampling Is Enabled
28
Lightweight Profiling May Not Indicate Fused Branch
29
Performance Counter for Instruction Cache Misses Does
30
Not Increment for Sequential Prefetches
30
Performance Counter for Ineffective Software Prefetches
31
Does Not Count for L Hits
31
Performance Counter Does Not Count for some Retired Micro-Ops
32
GART Table Walk Probes May Cause System Hang
33
Latency Performance Counters Are Not Accurate
34
Incorrect Memory Controller Operation Due to a
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Wrdatgrossdly Setting of Memclks
35
A Far Control Transfer Changing Processor Operating
36
Mode May Generate a False Machine Check
36
VPEXTRQ and VPINSRQ May Not Signal Invalid-Opcode Exception
37
Last-Branch Record Enabled May Cause Machine Check
38
And Incorrect Lastbranchtoip
38
Hypertransport ™ Link Retry Due to Partial CRC Error
39
May Cause System Hang
39
Hypertransport ™ Link Frequency Changes May Cause a
40
System Hang
40
P-State Limit Changes May Not Generate Interrupts
41
Non-Posted Reads May Block Write Dependent on Probe Responses
42
Small Code Segment Limits May Cause Incorrect Limit Faults
43
SB-RMI Processor State Accesses May Persistently
44
SB-RMI Writes May Not be Observed by Processor
45
Instruction Addresses Near Canonical Address Limit May Cause GP Exception
46
Processor Does Not Report the Correct DRAM Address for MCA Errors Within the CC Save Area
47
MC STATUS Enable Bit Not Set When Logging Corrected Errors
49
CPUID Incorrectly Reports Large Page Support in L Instruction TLB
50
VMCB Interrupt Shadow Status May be Incorrect
51
APERF May Increase Unpredictably
52
P-State Limit and Stop Clock Assertion May Cause System Hang
53
Local Interrupts LINT LINT May Occur While APIC Is
54
Software Disabled
54
Processor May Generate Incorrect P-State Limit Interrupts
55
Load Operation May Receive Incorrect Data after Floating-Point Exception
56
Debug Breakpoint on Misaligned Store May Cause System Hang
57
SVM Guest Performance Counters May be Inaccurate Due to SMI
58
Misaligned Page Crossing String Operations May Cause System Hang
59
Processor May Cache Prefetched Data from Remapped Memory Region
60
Instructions Performing Read-Modify-Write May Alter
61
Architectural State before PF
61
Some Processor Cores May Have Inaccurate Instruction
62
Cache Fetch Performance Counter
62
AM R Six Core Processor May Limit P-State When Core
63
C State Is Disabled
63
Northbridge FIFO Read Write Pointer Overlap May Cause
64
Hang or Protocol Error Machine Check
64
Maximum Value
77
Documentation Support
91
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