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BH36
HSYNC/VSYNC Buffer Does Not Meet VESA Rise & Undershoot
Specification
Problem:
Both HSYNC (horizontal Sync) and VSYNC (vertical sync) signals are violating VESA
(Video Electronics Standards Association) specification due to non-monotonic slow rise
time on both signals.
HSYNC and VSYNC signals may not meet VESA specification.
Workaround: Insert a buffer in the HSYNC/VSYNC signal path before the video connector. Refer to
Platform Design Guide and Customer Reference Board (CRB) schematic for reference.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH37
Glitch on LVDS Display Interface Clocks and Data Lines May be
Observed during Power-Up Sequences
Problem:
During power up sequence (transition to S0 state from G3, S3, S4 or S5 states) when
LVDS (Low Voltage Differential Signal) power supply (1.8V source) ramps up, a glitch
on LVDS clocks (LVD_A_CLKP, LVD_A_CLKN) and data lines (LVD_A_DAPAP[2:0],
LVD_A_DATAN[2:0]) may be observed.
Due to this erratum, a glitch may be seen during power up sequence. The glitch is not seen once the
LVDS power supply is stable.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH38
Synchronous Reset of IA32_MPERF on IA32_APERF Overflow May Not
Work
Problem:
When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its
maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to
synchronously reset to 0x0 on the next clock. Due to this erratum, IA32_MPERF may
not be reset when IA32_APERF overflows. Instead, IA32_MPERF may continue to
increment without being reset.
Due to this erratum, software cannot rely on synchronous reset of the IA32_MPERF register. The typical
usage of IA32_MPERF/IA32_APERF is to initialize them with a value of 0; in this case
the overflow of the counter wouldn't happen for over 10 years.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
28
Errata
Specification Update
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