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BH32
Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
Problem:
According to the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A, "Exception and Interrupt Reference", if another exception occurs while
attempting to call the double-fault handler, the processor enters shutdown mode. Due
to this erratum, any benign faults while attempting to call double-fault handler will not
cause a shutdown. However Contributory Exceptions and Page Faults will continue to
cause a triple fault shutdown.
Implication: If a benign exception occurs while attempting to call the double-fault handler, the
processor may hang or may handle the benign exception. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH33
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check
Error Reporting Enable Correctly
Problem:
IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to indicate
whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at the time of the
last update to the IA32_MC1_STATUS MSR. Due to this erratum, IA32_MC1_STATUS
MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit.
IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the enable bit in
the IA32_MC1_CTL MSR at the time of the last update.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
26
Errata
Specification Update
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