Intel ATOM PROCESSOR N 500 - SPECIFICATION UPDATE REVISION 001 Specification

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Intel® Atom™ Processor N500
Series
Specification Update
September 2010
Revision 001
Document Number: 324341-001

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Summary of Contents for Intel ATOM PROCESSOR N 500 - SPECIFICATION UPDATE REVISION 001

  • Page 1 Intel® Atom™ Processor N500 Series Specification Update September 2010 Revision 001 Document Number: 324341-001...
  • Page 2 DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
  • Page 3: Table Of Contents

    Contents Preface ..........................5   Identification Information ......................8   Summary Tables of Changes ....................10   Errata ..........................14   Specification Changes ......................31   Specification Clarifications ....................32   Documentation Changes ...................... 33   Specification Update...
  • Page 4: Revision History

    Revision History Document Revision Description Date Number 324341 • Initial Release September 2010 § Specification Update...
  • Page 5: Preface

    Contact your Intel representative for the latest revision. RS – Pineview Processor BIOS Writer’s Guide (BWG), Volume 2 Contact your Intel representative for the latest revision. NOTES: Contact your Intel representative to receive the latest revisions of these documents. Specification Update...
  • Page 6: Related Documents

    253668 3A: System Programming Guide ® Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 253669 3B: System Programming Guide ® IA-32 Intel Architectures Optimization Reference Manual 248966 ® Intel Processor Identification and the CPUID Instruction Application Note 241618 (AP-485) ®...
  • Page 7 Preface Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification. Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request.
  • Page 8: Identification Information

    Identification Information Identification Information Intel® Atom™ Processor N500 series processor on 45-nm process stepping can be identified by the following register contents: Table 1. Component Identification via Programming Interface Reserved Extended Extended Reserved Processor Family Model Stepping Family Model Type...
  • Page 9 Identification Information Component Marking Information Intel® Atom™ Processor N500 series is identified by the following component markings. Figure 1. Intel® Atom™ Processor N500 Series (Micro-FCBGA8) Markings SAMPLE MARK EXAMPLE: GRP1LINE1 : INTEL{M}{C}’YY {e1} GRP2LINE1 : {FPO} S-Spec Processor# Table 2. Identification Table for Intel® Atom™ Processor N500 Series...
  • Page 10: Summary Tables Of Changes

    Summary Tables of Changes Summary Tables of Changes The table included in this section indicated the sightings that apply to the Intel Atom Processor N500 series. If a sighting becomes an Erratum, Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
  • Page 11 Summary Tables of Changes Stepping Number Status Description No Fix An xTPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after the Processor has Issued a Stop-Grant Special Cycle No Fix The Processor May Report a #TS Instead of a #GP Fault No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt No Fix MOV To/From Debug Registers Causes Debug Exception...
  • Page 12 Summary Tables of Changes Stepping Number Status Description No Fix Writes to IA32_DEBUGCTL MSR May Fail when FREEZE_LBRS_ON_PMI is Set BH21 No Fix Address Reported by Machine-Check Architecture (MCA) on L2 Cache Errors BH22 May be Incorrect No Fix Performance Monitoring Event for Outstanding Bus Requests Ignores BH23 AnyThread Bit No Fix Corruption of CS Segment Register During RSM While Transitioning From Real...
  • Page 13 Summary Tables of Changes Number SPECIFICATION CHANGES There are no Specification Changes in this revision of the specification Update Number SPECIFICATION CLARIFICATIONS There are no Specification Clarifications in this revision of the specification Update Number DOCUMENTATION CHANGES There are no Document Changes in this revision of the specification Update §...
  • Page 14: Errata

    Errata Errata An xTPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after the Processor has Issued a Stop-Grant Special Cycle Problem: According to the FSB (Front Side Bus) protocol specification, no FSB cycles should be issued by the processor once a Stop-Grant special cycle has been issued to the bus. If xTPR update transactions are enabled by clearing the IA32_MISC_ENABLES[bit-23] at the time of Stop-Clock assertion, an xTPR update transaction cycle may be issued to the FSB after the processor has issued a Stop Grant Acknowledge transaction.
  • Page 15 Errata Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set.
  • Page 16 Errata A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, for example CLI, is executed soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been...
  • Page 17 Errata Value for LBR/BTS/BTM will be Incorrect after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as a BTM on the system bus will also be incorrect.
  • Page 18 ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software.
  • Page 19 Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially available software, or system.
  • Page 20 #GP fault may not match the non-canonical address that caused the fault. Implication: Operating systems may observe a #GP fault being serviced before higher priority Interrupts and Exceptions. Intel has not observed this erratum on any commercially available software. Workaround: None.
  • Page 21 PML4E or PDPTE Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur.
  • Page 22 Writes to this register by software or during certain processor operations are affected. Implication: Under certain circumstances, the IA32_DEBUGCTL MSR value may not be updated properly and will retain the old value. Intel has not observed this erratum with any commercially available software.
  • Page 23 The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines the CS segment register between enabling protected mode and the first far JMP. Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode"...
  • Page 24 Errata BH26 PMI Request is Not Generated on a Counter Overflow if its OVF Bit is Already Set in IA32_PERF_GLOBAL_STATUS Problem: If a performance counter overflows and software does not clear the corresponding OVF (overflow) bit in IA32_PERF_GLOBAL_STATUS MSR (38Eh) then future overflows of that counter will not trigger PMI (Performance Monitoring Interrupt) requests.
  • Page 25 An exception to this is if the following instruction triggers a #MF. In this situation, the interrupt should be serviced before the #MF. Because of this erratum, if following STI, an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel SpeedStep Technology transitions or Thermal Monitor events occur, the pending #MF may be serviced before higher priority interrupts.
  • Page 26 Implication: If a benign exception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign exception. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 27 Due to this erratum, the processor may run unexpected code and/or generate an unexpected exception. Intel has not observed this erratum with any commercially available software. Workaround: If LINT0 is used, it is recommended to either leave the APIC enabled (IA32_APIC_BASE MSR bit [11] set to 1) or do not use MWAIT, I/O redirection, VM- entry or RSM to enter an inactive state.
  • Page 28 Errata BH36 HSYNC/VSYNC Buffer Does Not Meet VESA Rise & Undershoot Specification Problem: Both HSYNC (horizontal Sync) and VSYNC (vertical sync) signals are violating VESA (Video Electronics Standards Association) specification due to non-monotonic slow rise time on both signals. HSYNC and VSYNC signals may not meet VESA specification. Workaround: Insert a buffer in the HSYNC/VSYNC signal path before the video connector.
  • Page 29 Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit FP load around a segment boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software.
  • Page 30 Errata Problem: A subset of processors may experience circuit marginality issues when operating at high temperature. Due to this erratum a system hang may occur or the processor may proceed to reboot. Due to this erratum, the system may hang or auto reboot. Workaround: A BIOS workaround has been identified.
  • Page 31: Specification Changes

    Specification Changes Specification Changes There are no specification changes in this revision of the specification update. § Specification Update...
  • Page 32: Specification Clarifications

    Specification Clarifications Specification Clarifications There are no specification clarifications in this revision of the specification update. § Specification Update...
  • Page 33: Documentation Changes

    Documentation Changes Documentation Changes There are no document changes in this revision of the specification update. § Specification Update...

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