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Errata
BH34
LINT0 Assertion and De-assertion During an Inactive State May
Cause Unexpected Operation When APIC is Disabled
Problem:
An interrupt delivered via LINT0 pins when the APIC is hardware disabled
(IA32_APIC_BASE MSR (1BH) bit [11] is cleared) will usually keep the pin asserted
until after the interrupt is acknowledged. However, if LINT0 is asserted and then de-
asserted before the interrupt is acknowledged and both of the following are true:
• The APIC is hardware disabled (IA32_APIC_BASE MSR bit [11] is clear) and
• The processor is in an inactive state that was requested by MWAIT, I/O
redirection, VM-entry or RSM,
then the processor may operate incorrectly
Due to this erratum, the processor may run unexpected code and/or generate an unexpected
exception. Intel has not observed this erratum with any commercially available
software.
Workaround: If LINT0 is used, it is recommended to either leave the APIC enabled
(IA32_APIC_BASE MSR bit [11] set to 1) or do not use MWAIT, I/O redirection, VM-
entry or RSM to enter an inactive state.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH35
IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
Problem:
In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET
instruction even though alignment checks were disabled at the start of the IRET. This
can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs
from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the
stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e
mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.
In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment checks
are disabled at the start of the IRET. This erratum can only be observed with a
software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
27
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