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Errata
BH29
LBR/BTM/BTS Information Immediately After a Transition From
Legacy/Compatibility Mode to 64-bit Mode May be Incorrect
Problem:
If a transition from legacy/compatibility mode to 64-bit mode occurs and another
branch event occurs before the first instruction executes (for example an external
interrupt or trap) then any FROM address recorded by LBR (Last Branch Record), BTM
(Branch Trace Message) or BTS (Branch Trace Store) on that second event may
incorrectly report the upper 32-bits as zero.
Due to this erratum, bits 63:32 of the 'FROM' value for LBR/BTM/BTS may be improperly zeroed after
a transition to 64 bite mode when the RIP (Instruction Pointer Register) is greater
than 4 Gigabyte.
Workaround: None identified. This erratum may be detected by a 'FROM' address having its upper
32-bits zero but its lower 32-bits matching the previous 'TO' address recorded.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH30
During a C-state Exit due to a Pending External Interrupt the System
May Hang
Problem:
Under a precise set of conditions, a processor waking from a C-state due to a pending
external interrupt may not complete the exiting process and the system may hang.
Due to this erratum, the system may hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH31
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
Problem:
Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag)
instruction are normally serviced immediately after the instruction following the STI.
An exception to this is if the following instruction triggers a #MF. In this situation, the
interrupt should be serviced before the #MF. Because of this erratum, if following STI,
an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel
SpeedStep Technology transitions or Thermal Monitor events occur, the pending #MF
may be serviced before higher priority interrupts.
Software may observe #MF being serviced before higher priority interrupts.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
25
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