Download Print this page
Analog Devices EVAL-AD1938AZ User Manual
Analog Devices EVAL-AD1938AZ User Manual

Analog Devices EVAL-AD1938AZ User Manual

Evaluating four adc/eight dac with pll 192 khz, 24-bit codec

Advertisement

Quick Links

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the AD1938 Four ADC/Eight DAC with PLL 192 kHz, 24-Bit Codec
EVAL-AD1938AZ PACKAGE CONTENTS
AD1938 evaluation board
USBi control interface board
USB cable
OTHER SUPPORTING DOCUMENTATION
AD1938
data sheet
EVALUATION BOARD OVERVIEW
This document explains the design and setup of the evaluation
board for the AD1938. The evaluation board must be connected
to an external ±12 V dc power supply and ground. On-board
regulators derive 3.3 V supplies for the AD1938. The AD1938 is
controlled through an SPI interface. A small external interface
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
FUNCTIONAL BLOCK DIAGRAM
POWER SUPPLY
DAC 1&2
ANALOG
AUDIO
ANALOG
ADC 1&2
AUDIO
MCLK ROUTING
DAC 3&4
ANALOG
AUDIO
Evaluation Board User Guide
board, EVAL-ADUSB2EBZ (also called USBi), connects to a PC
USB port and provides SPI access to the evaluation board
through a ribbon cable. A graphical user interface (GUI)
program is provided for easy programming of the chip in a
Microsoft® Windows® PC environment. The evaluation board
allows demonstration and performance testing of most AD1938
features, including four ADCs and eight DACs, as well as the
digital audio ports.
Additional analog circuitry (ADC input filters, DAC output
filter/buffer) and digital interfaces such as S/PDIF are provided
to ease product evaluation.
All analog audio interfaces are accessible with stereo audio,
3.5 mm TRS connectors.
CONTROL
SPI
INTERFACE
LRCLK, BCLK, SDATA
AD1938
CLOCK & DATA ROUTING
Figure 1.
Rev. 0 | Page 1 of 32
S/PDIF
INTERFACE
SERIAL AUDIO
INTERFACES
UG-045

Advertisement

loading
Need help?

Need help?

Do you have a question about the EVAL-AD1938AZ and is the answer not in the manual?

Questions and answers

Summary of Contents for Analog Devices EVAL-AD1938AZ

  • Page 1 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the AD1938 Four ADC/Eight DAC with PLL 192 kHz, 24-Bit Codec board, EVAL-ADUSB2EBZ (also called USBi), connects to a PC EVAL-AD1938AZ PACKAGE CONTENTS USB port and provides SPI access to the evaluation board AD1938 evaluation board through a ribbon cable.
  • Page 2 UG-045 Evaluation Board User Guide TABLE OF CONTENTS EVAL-AD1938AZ Package Contents ..........1 Powering the Board ...............3 Other Supporting Documentation ..........1 Setting Up the Master Clock (MCLK) ........4 Evaluation Board Overview ............1 Configuring the PLL Filter ............5 Functional Block Diagram .............. 1 Connecting Audio Cables ............5...
  • Page 3 Copy the .xml file for the AD1938 from the extraction ADDR0 ADDR1 folder into the C:\Program Files\Analog Devices Inc\AutomatedRegWin folder, if it does not appear in the Figure 2. Standalone Slave Mode folder after installation.
  • Page 4 UG-045 Evaluation Board User Guide POWER SELECTION 193X_MCLKI DISABLE JP18 JP20 C147 MCLKO XTAL JP19 1938_MCLKI JP22 R160 JP5 JP6 Figure 5. AD1938 Power Jumpers C158 JP23 193X_MCLKO CPLD R167 SETTING UP THE MASTER CLOCK (MCLK) JP25 HDR2 R169 The evaluation board has a series of jumpers that give the user JP27 OSC DISABLE R172...
  • Page 5 Evaluation Board User Guide UG-045 The ADC buffer circuit is designed with a switch (S1) that 193X_MCLKI DISABLE allows the user to change the voltage reference for all of the JP20 JP18 C147 MCLKO XTAL amplifiers. GND, CM, and FILTR can be selected as a reference; JP19 1938_MCLKI it is advisable to shut down the power to the board before...
  • Page 6 UG-045 Evaluation Board User Guide In this mode, the AD1938 ADC port generates BCLK and In this default configuration, the DAC audio path routes the LRCLK when given a valid MCLK. S/PDIF audio signal to all four stereo AD1938 DSDATA inputs simultaneously.
  • Page 7 Evaluation Board User Guide UG-045 ROTARY AND DIP SWITCH SETTINGS Figure 15. Settings Chart 1 Rev. 0 | Page 7 of 32...
  • Page 8 UG-045 Evaluation Board User Guide Figure 16. Settings Chart 2 Rev. 0 | Page 8 of 32...
  • Page 9 Evaluation Board User Guide UG-045 SCHEMATICS AND ARTWORK Figure 17. Board Schematics, Page 1—ADC Buffer Circuits Rev. 0 | Page 9 of 32...
  • Page 10 UG-045 Evaluation Board User Guide Figure 18. Board Schematics, Page 2—Serial Digital Audio Interface Headers with MCLK Direction Switching Rev. 0 | Page 10 of 32...
  • Page 11 Evaluation Board User Guide UG-045 Figure 19. Board Schematics, Page 3—S/PDIF Receive and Transmit Interfaces Rev. 0 | Page 11 of 32...
  • Page 12 UG-045 Evaluation Board User Guide Figure 20. Board Schematics, Page 4—Serial Digital Audio Routing and Control CPLD Rev. 0 | Page 12 of 32...
  • Page 13 Evaluation Board User Guide UG-045 Figure 21. Board Schematic, Page 5—AD1938 with MCLK Selection Jumpers Rev. 0 | Page 13 of 32...
  • Page 14 UG-045 Evaluation Board User Guide Figure 22. Board Schematics, Page 6—Daughter Card Interface, Useful as Test Points Rev. 0 | Page 14 of 32...
  • Page 15 Evaluation Board User Guide UG-045 Figure 23. Board Schematics, Page 7—DAC Buffer Circuits Rev. 0 | Page 15 of 32...
  • Page 16 UG-045 Evaluation Board User Guide Figure 24. Board Schematics, Page 8—SPI Control Interface Rev. 0 | Page 16 of 32...
  • Page 17 Evaluation Board User Guide UG-045 Figure 25. Board Schematics, Page 9—Power Supply Rev. 0 | Page 17 of 32...
  • Page 18 UG-045 Evaluation Board User Guide Figure 26. Top Assembly Layer Rev. 0 | Page 18 of 32...
  • Page 19 Evaluation Board User Guide UG-045 Figure 27. Bottom Assembly Layer Rev. 0 | Page 19 of 32...
  • Page 20 UG-045 Evaluation Board User Guide CPLD CODE MODULE IF_Logic TITLE 'AD1938 EVB Input Interface Logic' //=================================================================================== FILE: AD1938_pld_revE.abl REVISION DATE: 04-16-09 (rev-E) REVISION: DESCRIPTION: //=================================================================================== LIBRARY 'MACH'; "INPUTS ---------------------------------------------------------------------------- // AD1938 CODEC pins DSDATA1,DSDATA2 pin 86, 87 istype 'com'; DSDATA3,DSDATA4 pin 91, 92 istype 'com';...
  • Page 21 Evaluation Board User Guide UG-045 BCLK_8416 pin 60 istype 'com'; LRCLK_8416 pin 59 istype 'com'; SOMS_RX,SFSEL1_RX,SFSEL0_RX,RMCKF_RX pin 66,67,64,65 istype 'com'; // S/PDIF Tx CS8404 pins SDATA_8406 pin 50 istype 'com'; BCLK_8406,LRCLK_8406 pin 53, 54 istype 'com'; MCLK_8406 pin 49 istype 'com';...
  • Page 22 UG-045 Evaluation Board User Guide //================================================================================ "MACROS // Switch S3, DIP POSITIONS 6 AND 7 ADC_HDR_NORMAL = ( MODE22 & MODE23); ADC_HDR_DATA2_DATA1 = ( MODE22 & !MODE23); ADC_HDR_TDM = (!MODE22 & MODE23); ADC_HDR_AUX = (!MODE22 & !MODE23); S/PDIF_OUT_MUX = MODE24; // HEX Switch S4 // S4 position 0, DAC_RX_ALL...
  • Page 23 Evaluation Board User Guide UG-045 // S4 position B, DAC_DUAL_TDM ( !MODE14 & MODE13 & !MODE12 & !MODE11); // S4 position C, DAC_HDR1_AUX ( !MODE14 & !MODE13 & MODE12 & MODE11); // S4 position D, ( !MODE14 & !MODE13 & MODE12 &...
  • Page 24 UG-045 Evaluation Board User Guide M3_8414 = 0; // CS8404 Tx interface mode select APMS_TX = 0; // Tx serial port is always slave in this application SFMT1_TX = 0; // Tx data format is I2S always SFMT0_TX = 1; M0_8404 = 0;...
  • Page 25 Evaluation Board User Guide UG-045 HDR1_DSDATA4.oe = (DAC_DUAL_TDM # ADC_HDR_AUX # DAC_HDR1_AUX); HDR1_ASDATA2.oe = (!ADC_HDR_TDM); DBCLK = I_DBCLK; DLRCLK = I_DLRCLK; ABCLK = I_ABCLK; ALRCLK = I_ALRCLK; DSDATA1 = (HDR1_DSDATA1 & (DAC_HDR1_ALL # DAC_HDR1_IND # DAC_RX_2 # DAC_RX_3 # DAC_RX_4 # DAC_HDR1_TDM # DAC_DUAL_TDM # ADC_HDR_AUX)) # (SDATA_8416 &...
  • Page 26 UG-045 Evaluation Board User Guide ORDERING INFORMATION BILL OF MATERIALS Table 1. Designator Description Manufacturer Part Number C85, C90 to C94, C101 to C103, Multilayer ceramic capacitor,16 V, X7R Panasonic EC ECJ-0EX1C104K C107, C108, C110, C115, C116, (0402) C121, C127, C132, C134 C2, C5, C8 to C10, C20, C21, C28, Multilayer ceramic capacitor, 50 V, X7R Panasonic EC...
  • Page 27 Evaluation Board User Guide UG-045 Designator Description Manufacturer Part Number R56, R57, R65, R66, R88, R89, R140, Chip resistor, 24.9 Ω, 1%, 100 mW, thick film Rohm MCR03EZPFX24R9 R154, R179, R183, R213, R216, (0603) R228 to R231 C25, C31, C45, C53, C169, C181, Multilayer ceramic capacitor, 50 V, NP0 Rohm MCH185A271JK...
  • Page 28 Description Manufacturer Part Number Crystal, 12.288 MHz, SMT, 10 pF Abracon Corp ABM3B-12.288MHZ-10- 1-U-T Four ADC/eight DAC with PLL, 192 kHz, 24- Analog Devices AD1938YSTZ bit CODEC Microprocessor voltage supervisor Analog Devices ADM811RARTZ-REEL7 Voltage regulator low dropout Analog Devices ADP3303ARZ-3.3...
  • Page 29 Evaluation Board User Guide UG-045 Designator Description Manufacturer Part Number SW2, SW3 SPDT slide switch, PC mount E-Switch EG1218 S2, S3 8-position SPST SMD switch, flush, actuated CTS Corp 219-8LPST Tact switch, 6 mm, gull wing Tyco/Alcoswitch FSM6JSMA 15 Mb/sec fiber optic receiving module Toshiba TORX147L(FT) with shutter...
  • Page 30 UG-045 Evaluation Board User Guide NOTES Rev. 0 | Page 30 of 32...
  • Page 31 Evaluation Board User Guide UG-045 NOTES Rev. 0 | Page 31 of 32...
  • Page 32 By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement.

This manual is also suitable for:

Ad1938