Advanced Chipset Features - JETWAY 615DFR1A User Manual

M/b for socket 370 pentium iii processor

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Table Of Contents

Table of Contents

The Advanced Chipset Features Setup option is used to change the values of the chipset

registers. These registers control most of the system options in the computer.

DRAM Timing Setting

System BIOS Cacheable

Video BIOS Cacheable

CPU Latency Timer

Delayed Transaction

Move Enter:Select Item +/-/PU/PD:Value F10:Save ESC:Exit

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F5:Previous Values

Note: Change these settings only if you are familiar with the chipset.

DRAM Timing Setting

Please refer to section 3-6-1

System BIOS Cacheable

Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in

better system performance. However, if any program writes to this memory area, a system

error may result. The settings are: Enabled and Disabled.

Video BIOS Cacheable

Select Enabled allows caching of the video BIOS, resulting in better system performance.

However, if any program writes to this memory area, a system error may result. The settings

are: Enabled and Disabled.

CPU Latency Timer

During Enabled, A deferrable CPU cycle will only be Deferred after it has been in a Snoop

Stall for 31 clocks and another ADS# has arrived. During Disabled, A deferrable CPU cycle

will be Deferred immediately after the GMCH receives another ADS#.

Delayed Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.

Select Enabled to support compliance with PCI specification version 2.1. The settings are:

Enabled and Disabled.

3-6-1 DRAM Timing Setting