ON Semiconductor NCP51810 User Manual

NCP51810 HB GaN Driver
Evaluation Board
User's Manual
NCP51810 High−Speed, Half−Bridge, GaN
Driver Evaluation Board for Existing or
New PCB Designs
NCP51810GAN1GEVB
INTRODUCTION
Purpose
The NCP51810 HB GaN Driver Evaluation Board (EVB) is
intended to replace the driver and power MOSFETs used in existing
half−bridge or full−bridge power supplies. This EVB highlights the
performance, simplicity and minimal number of components required
to efficiently and reliably drive two gallium nitride power switches
used in a mid−voltage, totem pole configuration. Intended applications
include off−line power converter topologies such as: phase−shifted
full−bridge, active clamp flyback and forward, dual active−bridge, and
voltage synchronous buck. This document describes mating
techniques for the NCP51810 HB GaN Driver EVB.
NCP51810 GaN Driver Description
The NCP51810 high−speed, gate driver is designed to meet the
stringent requirements of driving enhancement mode (E−mode), high
electron mobility transistor (HEMT) and gate injection transistor
(GIT) HEMT, gallium nitride (GaN) power switches in half−bridge
power topologies. The NCP51810 offers short and matched
propagation delays with advanced level shift technology providing
−3.5 V to +100 V (typical) common mode voltage range for the
high−side drive and −3.5 V to +3.5 V common mode voltage range for
the low−side drive. In addition, the device provides stable and reliable
operation when used in high dV/dt environments up to 200 V/ns. In
order to fully protect the gates of the GaN power switches against
excessive voltage, both NCP51810 drive stages employ separate,
dedicated voltage regulators to accurately maintain the gate−source
drive signal amplitude. The circuit offers active clamping of the
driver's bias rails thus protecting against potential gate−source
over−voltage under various operating conditions.
The NCP51810 offers important protection functions such as
independent under−voltage lockout (UVLO), monitoring V
voltage, VDDH and VDDL driver bias and thermal shutdown based
on die junction temperature of the device. As shown in Figure 2, the
Schmitt trigger, EN, HIN and LIN inputs are internally pulled LOW to
assure the driver is always in a default 'OFF' state during initial
application of V
by the DT pin and can be configured to prevent or allow
cross−conduction.
© Semiconductor Components Industries, LLC, 2020
October, 2020 − Rev. 0
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bias. Programmable dead−time control is available
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EVAL BOARD USER'S MANUAL
Figure 1. Evaluation Board Photo
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1 Publication Order Number:
EVBUM2762/D