ON Semiconductor NCP5106B Series User Manual

NCP5106BA36WGEVB
NCP5106B 36W Ballast
Evaluation Board User's
Manual
Introduction
This document describes how the NCP5106B driver can
be implemented in a ballast application. The scope of this
application note is to highlight the NCP5106B driver and not
to explain or detailed how to build electronic ballast.
The NCP5106B is a high voltage power MOSFET driver
providing two outputs for direct drive of 2 N−channel power
MOSFETs arranged in a half−bridge configuration with a
cross conduction protection between the 2 channels.
It uses the bootstrap technique to insure a proper drive of
the High−side power switch. The driver works with 2
independent inputs to accommodate any topology
(including half−bridge, asymmetrical half−bridge, active
clamp and full−bridge).
Evaluation Board Specification
•
Input range : 85 − 145 Vac or 184 − 265 Vac
•
Ballast Output power : 36 W (type PL−L 36W)
Pre−Heating current : 295 mA
♦
Pre−heating time : 1 second
♦
Nominal current : 414 mA
♦
BEFORE PLUGGING IN THE DEMO BOARD, MAKE
SURE THE JUMPER IS ON THE CORRECT POSITION:
IF J2 IS USED, THEN Vin MUST BE LOWER THAN
145 Vac.
© Semiconductor Components Industries, LLC, 2012
November, 2012 − Rev. 1
Detailed Operation
The lamp ballast is powered via a half bridge
configuration. The 2 power MOSFETs are driven with the
NCP5106B driver. The driver is supplied by the VCC rail,
and the high side driver is supplied by the bootstrap diode:
when the low side power MOSFET (Q2) is switched ON, the
BRIDGE pin is pulled down to the ground, thus the capacitor
connected between BRIDGE pin and VBOOT pin is
refuelled via the diode D3 and the resistor R5 connected to
V . When Q2 is switched OFF the bootstrap capacitor C6
CC
supplies the high side driver with a voltage equal to V
level minus the D3 forward voltage diode. Given the
NCP5106B architecture, it is up to the designer to generate
the right input signal polarity with the desired dead time.
Nevertheless the NCP5106B provides a cross conduction
protection with an internal fixed dead time. Thus in case of
overlap on the inputs signal, the both outputs driver will be
kept in low state, or a minimum of 100 ns dead time will be
applied between the both drivers.
The 555 timer generates only one signal for the driver, the
second one, in opposite phase is built by inserting a NPN
transistor (Q4) for inverting the signal. Afterwards the dead
time is built with R2, D2 and C13 (typically 400 ns, see
Figure 2).
Figure 1. Evaluation Board Photo
1
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EVAL BOARD USER'S MANUAL
Publication Order Number:
CC
EVBUM2154/D