ON Semiconductor NCP5181 User Manual

NCP5181BAL36WEVB
NCP5181 36 W Ballast
Evaluation Board User's
Manual
Description
This document describes how the NCP5181 driver can be
implemented in a ballast application. The scope of this
evaluation board user's manual is to highlight the NCP5181
driver and not to explain or detail how to build an electronic
ballast.
The NCP5181 is a high voltage power MOSFET driver
providing two outputs for direct drive of two N-channel
power MOSFETs arranged in a half-bridge (or any other
high-side + low-side topology) configuration.
It uses the bootstrap technique to ensure a proper drive of
the high-side power switch. The driver works with two
independent inputs to accommodate with any topology
(including half-bridge, asymmetrical half-bridge, active
clamp and full-bridge).
Evaluation Board Specification
•
Input Range: 85 − 145 Vac OR 184 − 265 Vac
•
Ballast Output Power: 36 W (type PL−L 36 W)
•
Pre-heating Current: 295 mA
•
Pre-heating Time: 1 second
•
Nominal Current: 414 mA
WARNING: BEFORE PLUGGING IN THE EVALUATION BOARD, MAKE SURE THE JUMPER IS IN THE CORRECT POSITION: IF J2
IS USED, THEN Vin MUST BE LOWER THAN 145 Vac.
© Semiconductor Components Industries, LLC, 2012
October, 2012 − Rev. 1
Detailed Operation
The lamp ballast is powered via a half bridge
configuration. The two power MOSFETs are driven with the
NCP5181 driver. The driver is supplied by the V
the high side driver is supplied by the bootstrap diode: when
the low side power MOSFET (Q2) is switched ON, the
BRIDGE pin is pulled down to the ground, thus the capacitor
connected between the BRIDGE pin and VBOOT pin is
refuelled via the diode D3 and the resistor R5 connected to
V
CC
supplies the high side driver with a voltage equal to V
level minus D3 forward voltage diode. Given the NCP5181
architecture, it is up to the designer to generate the right input
signal polarity. This includes a dead time to avoid a short
circuit between the high and low side power MOSFET.
The 555 timer generates only one signal for the driver, the
second one, in opposite phase is built by inserting an NPN
transistor (Q4) for inverting the signal. Afterwards, the dead
time is built with R2, D2 and C13 (typically 260 ns, see
Figure 2).
Figure 1. NCP5181 Evaluation Board
1
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EVAL BOARD USER'S MANUAL
. When Q2 is switched OFF, the bootstrap capacitor C6
rail, and
CC
CC
Publication Order Number:
EVBUM2141/D