Page 1 ® ® 89HPES32H8G2 ® PCI Express Switch User Manual April 2013 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2013 Integrated Device Technology, Inc.
Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
Page 3: About This Manual
About This Manual ® Introduction Notes This user manual includes hardware and software information on the 89HPES32H8G2, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard. Finding Additional Information Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.
Page 4: Signal Nomenclature
Notes Chapter 17, “Switch Control and Status Registers,” lists the switch control and status registers in the PES32H8G2 and provides a description of each bit in those registers. Chapter 18, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Page 5: Register Terminology
Notes Term Words Bytes Bits Byte Word Doubleword (Dword) Quadword (Qword) Table 1 Data Unit Terminology In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double- words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always the most significant bit and bit 0 is the least significant bit.
Page 6 Notes Type Abbreviation Description Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms such as pin strapping or serial EEPROM. (System firmware hard- ware initialization is only allowed for system integrated devices.) Bits are read-only after initialization and can only be reset (for write-once by firmware) with reset.
Page 7: Use Of Hypertext
Use of Hypertext Notes In Chapter 15, Tables 15.4, 15.5 and 15.6 contain register names and page numbers highlighted in blue under the Register Definition column. In pdf files, users can jump from this source table directly to the regis- ters by clicking on the register name in the source table.
Page 8 Notes references to LAERR bit in Table 13.2, Table 13.15, and Figure 13.8. In Chapter 15, added section Partial- Byte Access to Word and DWord Registers. In Chapter 17, added bit BDISCARD to the Switch Control register and changed bit 26 in the SMBus Status register from LAERR to Reserved. June 16, 2009: In Chapter 5, revised Table 5.1 and revised text in sections Partition Hot Reset and Port Mode Change Reset.
Page 9 Notes May 18, 2011: In Chapter 8, section Low-Swing Transmitter Voltage Mode, the reference in the first paragraph to the LSE bit being in the SerDes Control register was changed to the SerDes Configuration register. June 28, 2011: In Chapter 17, added bit 26, TX_SLEW_C, to the SerDes x Transmitter Lane Control 0 register.
Page 10 Notes PES32H8G2 User Manual April 5, 2013...
Page 11: Table Of Contents
Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................2 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................5 Reference Documents ........................5 Revision History ..........................
Page 12 IDT Table of Contents Notes End-to-End Data Path Parity Protection ................3-14 Clocking Introduction ............................. 4-1 Port Clocking Modes........................4-2 Spread Spectrum Clocking (SSC) Support ................4-2 Global Clocked Mode ......................4-4 Local Port Clocked Mode ....................... 4-5 Modification of a Port’s Clock Mode ..................4-6 Reset and Initialization Introduction .............................
Page 13 IDT Table of Contents Notes Upstream Port ........................7-10 Downstream Port........................7-10 Link States ............................ 7-11 Active State Power Management ....................7-11 L0s ASPM..........................7-12 L1 ASPM ..........................7-12 L1 ASPM Entry Rejection Timer ....................7-13 Link Status ............................ 7-14 De-emphasis Negotiation ......................
Page 14 IDT Table of Contents Notes Power Good Controlled Reset Output .................. 10-5 Hot-Plug Events..........................10-6 Legacy System Hot-Plug Support....................10-7 Hot-Swap ............................10-8 Power Management Introduction ........................... 11-1 PME Messages..........................11-3 PCI Express Power Management Fence Protocol ............... 11-3 Upstream Switch Port or Downstream Switch Port Mode ............ 11-3 Power Budgeting Capability......................
Page 15 IDT Table of Contents PCI to PCI Bridge and Proprietary Port Specific Registers Notes Type 1 Configuration Header Registers ..................16-1 PCI Express Capability Structure ....................16-11 Power Management Capability Structure ................... 16-27 Message Signaled Interrupt Capability Structure ............... 16-29 Subsystem ID and Subsystem Vendor ID ..................
Page 16 IDT Table of Contents Notes PES32H8G2 User Manual April 5, 2013...
Page 17 List of Tables ® Table 1.1 Initial Configuration Register Settings for PES32H8G2............1-4 Notes Table 1.2 PES32H8G2 Device IDs...................... 1-6 Table 1.3 PES32H8G2 Revision ID..................... 1-6 Table 1.4 PCI Express Interface Pins....................1-7 Table 1.5 Reference Clock Pins ......................1-8 Table 1.6 SMBus Interface Pins ......................
Page 18 IDT List of Tables Notes Table 9.14 Prioritization of Transaction Layer Errors ................9-14 Table 10.1 Port Hot Plug Signals ......................10-3 Table 10.2 Negated Value of Unused Hot-Plug Output Signals............10-4 Table 11.1 PES32H8G2 Power Management State Transition Diagram ..........11-2 Table 12.1 GPIO Pin Configuration .....................
Page 19: List Of Figures
List of Figures ® Figure 1.1 PES32H8G2 Block Diagram ....................1-3 Notes Figure 1.2 PES32H8G2 Logic Diagram ....................1-5 Figure 2.1 PES32H8G2 Block Diagram ....................2-1 Figure 2.2 Transparent PCIe Switch ....................2-2 Figure 2.3 Partitionable PCI Express Switch ..................2-2 Figure 3.1 Crossbar Connection to Port Ingress and Egress Buffers ..........3-3 Figure 3.2 Architectural Model of Arbitration ..................3-6 Figure 3.3...
Page 20 IDT List of Figures Notes Figure 10.6 PES32H8G2 Hot-Plug Event Signalling ................10-8 Figure 11.1 PES32H8G2 Power Management State Transition Diagram ..........11-2 Figure 13.1 Split SMBus Interface Configuration ................13-1 Figure 13.2 Single Double Word Initialization Sequence Format ............13-3 Figure 13.3 Sequential Double Word Initialization Sequence Format ..........13-3 Figure 13.4 Configuration Done Sequence Format ................13-4 Figure 13.5...
Page 21 Register List ® ACSCAP - ACS Capability Register (0x324)..................16-49 Notes ACSCTL - ACS Control Register (0x326)..................... 16-51 ACSECAPH - ACS Extended Capability Header (0x320) ..............16-49 ACSECV - ACS Egress Control Vector (0x328)................... 16-52 AERCAP - AER Capabilities (0x100) ....................16-32 AERCEM - AER Correctable Error Mask (0x114) ................
Page 22 IDT Register List Notes INTRPIN - Interrupt PIN Register (0x03D) ....................16-9 IOBASE - I/O Base Register (0x01C)......................16-5 IOBASEU - I/O Base Upper Register (0x030)..................16-8 IOEXPADDR0 - SMBus I/O Expander Address 0 (0x0AD8)..............17-23 IOEXPADDR1 - SMBus I/O Expander Address 1 (0x0ADC) ..............17-24 IOEXPADDR2 - SMBus I/O Expander Address 2 (0x0AE0) ..............17-24 IOEXPADDR3 - SMBus I/O Expander Address 3 (0x0AE4) ..............17-24 IOLIMIT - I/O Limit Register (0x01D).......................16-6...
Page 23 IDT Register List Notes PCLKMODE - Port Clocking Mode (0x0008) ..................17-3 PHYLCFG0 - Phy Link Configuration 0 (0x530)..................16-68 PHYLSTATE0 - Phy Link State 0 (0x540).....................16-69 PHYPRBS - Phy PRBS Seed (0x55C)....................16-69 PLTIMER - Primary Latency Timer (0x00D)....................16-4 PMBASE - Prefetchable Memory Base Register (0x024) ...............16-7 PMBASEU - Prefetchable Memory Base Upper Register (0x028)............16-8 PMCAP - PCI Power Management Capabilities (0x0C0)..............16-27 PMCSR - PCI Power Management Control and Status (0x0C4) ............16-28...
Page 24 IDT Register List Notes PES32H8G2 User Manual April 5, 2013...
Page 25: Pes32H8G2 Device Overview
Chapter 1 PES32H8G2 Device Overview ® Introduction Notes The 89HPES32H8G2 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES32H8G2 is a 32-lane, 8-port system interconnect switch optimized for PCI Express Gen2 packet switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows. Target applications include servers, storage, communications, embedded systems, and multi-host or intelli- gent I/O based systems with inter-domain communication.
Page 26 IDT PES32H8G2 Device Overview Notes • Receive equalization • Drive strength Switch Partitioning  – IDT proprietary feature that creates logically independent switches in the device – Supports up to 8 fully independent switch partitions – Configurable downstream port device numbering –...
Page 27 IDT PES32H8G2 Device Overview • SerDes optionally turned-off in D3hot • SerDes associated with unused ports are turned-off • SerDes associated with unused lanes are placed in a low power state 9 General Purpose I/O  Reliability, Availability and Serviceability (RAS) ...
Page 28 IDT PES32H8G2 Device Overview PCIELCAP Port MAXLNKWDTH Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Table 1.1 Initial Configuration Register Settings for PES32H8G2 PES32H8G2 User Manual 1 - 4 April 5, 2013...
Page 29: Logic Diagram
IDT PES32H8G2 Device Overview Logic Diagram Global GCLKN[2:0] Reference Clocks GCLKP[2:0] GCLKFSEL P00CLKN PCI Express PCI Express P00CLKP Switch Switch PE00TP[3:0] PE00RP[3:0] SerDes Input SerDes Output PE00TN[3:0] PE00RN[3:0] Port 0 Port 0 PCI Express P01CLKN PCI Express Switch P01CLKP PE01TP[3:0] Switch SerDes Output PE01RP[3:0]...
Page 30: System Identification
IDT PES32H8G2 Device Overview System Identification Notes Vendor ID All vendor IDs in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES32H8G2 device ID is shown in Table 1.2. PCIe Device Device ID 0x05 0x8075...
Page 31: Pin Description
IDT PES32H8G2 Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES32H8G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...
Page 32: Table 1.5 Reference Clock Pins
IDT PES32H8G2 Device Overview Notes Signal Type Name/Description PE06TP[3:0] PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans- PE06TN[3:0] mit pairs for port 6. PE07RP[3:0] PCI Express Port 7 Serial Data Receive. Differential PCI Express receive PE07RN[3:0] pairs for port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7.
Page 33: Signal Type
IDT PES32H8G2 Device Overview Notes Signal Type Name/Description GPIO[0] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PART0PERSTN Alternate function pin type: Input/Output Alternate function: Assertion of this signal initiated a partition fundamental reset in the corresponding partition.
Page 34 IDT PES32H8G2 Device Overview Notes Signal Type Name/Description GCLKFSEL Global Clock Frequency Select. These signals select the frequency of the GCLKP and GCLKN signals. 0x0 100 MHz 0x1 125 MHz P01MERGEN Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low internally.
Page 35: Table 1.9 Test Pins
IDT PES32H8G2 Device Overview Notes Signal Type Name/Description SWMODE[3:0] Switch Mode. These configuration pins determine the PES32H8G2 switch operating mode. Note: These pins should be static and not change follow- ing the negation of PERSTN. 0x0 - Single partition 0x1 - Single partition with Serial EEPROM initialization 0x2 through 0x7 - Reserved 0x8 - Single partition with port 0 selected as the upstream port (port 2 dis- abled)
Page 36: Table 1.10 Power, Ground, And Serdes Resistor Pins
IDT PES32H8G2 Device Overview Notes Signal Type Name/Description REFRES00 Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis- tor should be connected from this pin to ground. REFRES01 Port 1 External Reference Resistor.
Page 37: Pin Characteristics
IDT PES32H8G2 Device Overview Pin Characteristics Notes Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation.
Page 38: Buffer Type
IDT PES32H8G2 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor PCI Express GCLKN[1:0] HCSL Diff. Clock Refer to Table Interface (cont.) Input 9 in the GCLKP[1:0] PES32H8G2 P[2:0]CLKN Data Sheet P[2:0]CLKP SMBus MSMBCLK LVTTL pull-up on board MSMBDAT pull-up on...
Page 39: Architectural Overview
Chapter 2 Architectural Overview ® Introduction Notes This section provides a high level architectural overview of the PES32H8G2. An architectural block diagram of the PES32H8G2 is shown in Figure 2.1. PCI Express Port s PCI Express Port s SerDes SerDes SerDes SerDes SerDes...
Page 40: Switch Partitioning
IDT Architectural Overview Switch Partitioning Notes The logical view of a PCIe switch is shown in Figure 2.2. A PCI switch contains one upstream port and one or more downstream ports. Each port is associated with a PCI-to-PCI (P2P) bridge. All P2P bridges associated with a PCIe switch are interconnected by a virtual PCI bus.
Page 41: Dynamic Reconfiguration
IDT Architectural Overview Notes Each partition operates logically as a completely independent PCIe switch that implements the behavior and capabilities outlined in the PCI Express Base specification required of a switch. The PES32H8G2 supports boot-time (i.e., Fundamental Reset) and runtime configuration of ports into partitions.
Page 42 IDT Architectural Overview Notes PES32H8G2 User Manual 2 - 4 April 5, 2013...
Page 43: Switch Core
Chapter 3 Switch Core ® Introduction Notes This chapter provides an overview of the PES32H8G2’s Switch Core. As shown in Figure 2.1 in the Architectural Overview chapter, the Switch Core interconnects switch ports. The Switch Core’s main func- tion is to transfer TLPs among these ports efficiently and reliably. In order to do so, the Switch Core provides buffering, ordering, arbitration, and error detection services.
Page 44: Egress Buffer
IDT Switch Core Notes Total Size and Advertised Advertised Port Limitations Data Header Mode Queue (per-port) Credits Credits Posted 12352 Bytes and up to 127 Merged TLPs Non Posted 2048 Bytes and up to 127 TLPs Completion 12352 Bytes and up to 127 TLPs Table 3.1 IFB Buffer Sizes (Part 2 of 2) Egress Buffer...
Page 45: Crossbar Interconnect
IDT Switch Core Notes Port Replay Buffer Storage Mode Limit 32 TLPs Bifurcated 64 TLPs Merged Table 3.3 Replay Buffer Storage Limit Crossbar Interconnect The crossbar is a 8x8 matrix of pathways, capable of concurrently transferring data between a maximum of 8 port pairs.
Page 46: Packet Ordering
IDT Switch Core Notes Packets received from the port are stored in the appropriate IFB queue. After being queued in an IFB and undergoing ordering and arbitration, all data transferred through the crossbar interconnect is trans- ferred in a continuous TLP manner (i.e., the data path is never multiplexed). This choice of datapath width implies that the crossbar has 20% higher throughput than the throughput required to service all ports.
Page 47: Arbitration
IDT Switch Core Notes Posted Non-Posted Request Completion Request IO or IO or Memory Configur Row Pass Column? Configur Read Write or Read ation ation Comple- Message Request Write Write tion Request Comple- Request tion Posted Memory Request Write or Message Request Non Posted...
Page 48: Port Arbitration
IDT Switch Core Notes Switch Core Port 0 IFB VC 0 Port 0 Egress Arbitration VC 0 Arbitration Port VC 0 Port 1 IFB ( not Arbitration applicable ) VC 0 Port 7 Egress Arbitration VC 0 Arbitration Port VC 0 ( not Arbitration applicable )
Page 49: Table 3.5 Conditions For Cut-Through Transfers
IDT Switch Core Notes and egress link bandwidth is determined by the negotiated speed and width of the links. Table 3.5 shows the conditions under which cut-through and adaptive-cut-through occur. When the conditions are met, cut- through is performed across the IFB, crossbar , and EFB.
Page 50: Request Metering
IDT Switch Core Notes Ingress Ingress Egress Egress Conditions for Cut- Link Link Link Link Through Speed Width Speed Width 5.0 Gbps x8, x4, x2, x1 Always x8, x4, x2, x1 Always x8, x4, x2, x1 Always At least 50% of packet is in IFB x4, x2, x1 Always At least 50% of packet is in IFB...
Page 51 IDT Switch Core Notes If read requests are injected sporadically or at a low rate, then buffering within the switch may be used to accommodate short lived contention and allow completions to endpoints to proceed without interfering. If read requests are injected at a high rate, then no amount of buffering in the switch will prevent completions from interfering.
Page 52: Operation
IDT Switch Core Notes The request metering implementation in the PES32H8G2 makes a number of simplifying assumptions that may or may not be true in all systems. Therefore, it should be expected that some amount of parameter tuning may be required to achieve optimum performance. Note that tuning of the request metering mechanism should take into account the completion timeout value of the associated requesters (i.e., request metering should be tuned such that a requester’s comple- tion timeout value is not violated).
Page 53: Table 3.6 Request Metering Decrement Value
IDT Switch Core Notes The Decrement Value Adjustment (DVADJ) field represents a sign-magnitude fixed point 0:4:11 number (i.e., a positive fixed-point number with 4 integer bits and 11 fractional bits). – DVADJ field provides fine grain programmable adjustment of the value by which the counter is decremented.
Page 54: Completion Size Estimation
IDT Switch Core Notes tmp = RequestMeteringCounter RequestMeteringCounter (DecrementValue[LinkSpeed,LinkWidth] RMCTL.DVADJ) if (tmp < RequestMeteringCounter) { RequestMeteringCounter = 0 Figure 3.7 Request Metering Counter Decrement Operation Completion Size Estimation This section describes the value that is loaded into the request metering counter when a request is transferred into the switch core.
Page 55: Internal Errors
IDT Switch Core Notes If the number of data DWords is zero, then the completion size is estimated to be three DWords (i.e., a 0:13:3 representation value of 0x0018). – Otherwise, if the number of required data DWords is less than the Constant Limit (CNSTLIMIT) field in the RMCTL register, then the completion size is estimated as the number of required data DWords plus one.
Page 56: Switch Time-Outs
IDT Switch Core Notes To facilitate testing of software error handlers, any bit in the IERRORSTS register may be set by writing a one to the corresponding bit position in the Internal Error Test (IERRORTST) register. Once a bit is set in the ERRORSTS register, it is processed as though the actual error occurred (e.g., reported by AER).
Page 57 IDT Switch Core Notes As the TLP flows through the switch, its alignment or contents may be modified. In all such cases, parity is updated and not recomputed. Hence, any error that occurs is propagated and not masked by a parity regeneration.
Page 58 IDT Switch Core Notes PES32H8G2 User Manual 3 - 16 April 5, 2013...
Page 59: Clocking
Chapter 4 Clocking ® Introduction Notes Figure 4.1 provides a logical representation of the PES32H8G2 clocking architecture. The PES32H8G2 has a single differential global reference clock input (GCLK) as well as a differential reference clock input CLK) for ports 0, 1, and 2. [2:0] Port 0 Port 1...
Page 60: Port Clocking Modes
IDT Clocking If port reference clock inputs are associated with adjacent x4 ports, then when those two x4 ports are merged to create a x8 port, the port reference clock input used by the merged port is the one associated with the even port. The port reference clock input associated with the merged odd port is unused and and should be connected to Vss on the system board.
Page 61: Table 4.2 Gclk And Pxclk Frequencies When Pxclk Has Ssc
IDT Clocking Nominal PxCLK Effective Allowed PxCLK PxCLK GCLK Frequency Modulation Frequency Frequency 100 MHz + 300ppm +0 / - 5000ppm 100 Mhz +300 / - 100 Mhz + / - 4700ppm 300ppm 100 MHz - 300ppm +0 / - 5000ppm 100 Mhz -300 / - 100 Mhz + / - 5300ppm...
Page 62: Global Clocked Mode
IDT Clocking PES32H8G2 Switch Link Valid Port Partner Notes Port Global Config. Clocking Refclk Clock Clock Mode Local Port PxCLK with GCLK Same PxCLK as the Local port clocked with common Refclk architecture Clocked switch and SSC. Local Port PxCLK with GCLK with Same PxCLK or different Clocked...
Page 63: Local Port Clocked Mode
IDT Clocking Notes Switch GCLK Clock Generator Port Clock Link Partner Generator Figure 4.3 Clocking Connection for a Port in Global Clocked Mode, Non-Common Clocked Configuration Local Port Clocked Mode A port in local port clocked mode uses the corresponding port clock (PxCLK) input for receiving and transmitting serial data.
Page 64: Modification Of A Port's Clock Mode
IDT Clocking Notes Switch GCLK Clock Generator Port PxCLK Clock Generator Clock Link Partner Generator Figure 4.5 Clocking Connection for a Port in Local Port Clocked Mode, in a Non-Common Clocked Configuration Modification of a Port’s Clock Mode The clocking mode associated with a port may be modified at any time, with the only requirement being that the reference clock that will be used by the port after the port’s clocking mode is modified must be stable prior to the modification.
Page 65 IDT Clocking Notes PES32H8G2 User Manual 4 - 7 April 5, 2013...
Page 66 IDT Clocking Notes PES32H8G2 User Manual 4 - 8 April 5, 2013...
Page 67: Reset And Initialization
Chapter 5 Reset and Initialization ® Introduction Notes This chapter describes the PES32H8G2 resets and initialization. There are two classes of PES32H8G2 resets. The first is a switch fundamental reset which is the reset used to initialize the entire device. The second class is referred to as partition resets.
Page 68: Boot Configuration Vector
IDT Reset and Initialization Notes Registers and fields designated as Sticky (Sticky) take on their initial value as a result of the following resets. Other resets have no effect on registers and fields with this designation. – Switch Fundamental Reset –...
Page 69: Switch Fundamental Reset
IDT Reset and Initialization Notes May Be Signal Name/Description Overridden RSTHALT Reset Halt. When this pin is asserted during a switch fundamental reset sequence, the PES32H8G2 remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins.
Page 70 IDT Reset and Initialization Notes – If a one is written by the serial EEPROM to the Full Link Retrain (FLRET) bit in any Phy Link State 0 (PHYLSTATE0) register, then link retraining is initiated on the corresponding port using the current link parameters.
Page 71 IDT Reset and Initialization Notes The operation of a switch fundamental reset with serial EEPROM initialization is illustrated in Figure 5.1. Stable Stable Power GCLK GCLK* > 100ns PERSTN < 100 ms ~285 s ~2 s PLL Reset & Lock Link Ready SerDes CDR Lock...
Page 72: Switch Mode Dependent Initialization
IDT Reset and Initialization Switch Mode Dependent Initialization Notes Switch modes may be subdivided into normal switch modes and test modes. The modes listed below are normal switch modes. All other switch modes are test modes. – Single partition – Single partition with Serial EEPROM initialization –...
Page 73: Port Merging
IDT Reset and Initialization Notes Single Partition with Port 0 Upstream Port (Port 2 disabled) In single partition with port 0 upstream port, the initial values outlined in Table 5.3 result in the following configuration. – All switch ports, except port 2, are members of partition zero. –...
Page 74: Partition Resets
IDT Reset and Initialization Notes – All registers associated with the port remain accessible from the global address space. – The port remains in this state regardless of the setting of the port’s operating mode (i.e., via the port’s SWPORTxCTL register). An active port behaves as described throughout the rest of this specification and may be configured in one of several operating modes, as described in Chapter 6, Switch Partitions.
Page 75: Partition Hot Reset
IDT Reset and Initialization Partition Hot Reset Notes A partition hot reset is initiated by any of the following events: – Reception of TS1 ordered-sets on the partition’s upstream port indicating a hot reset. – Data link layer of the partition’s upstream port transitions to the DL_Down state. –...
Page 76: Partition Downstream Secondary Bus Reset
IDT Reset and Initialization Notes • If the link associated with a downstream port is in the Disabled LTSSM state, then a hot reset will not be propagated out on that port. The port will instead transition to the Detect LTSSM state. Although not a hot reset, this has the same functional effect on downstream components.
Page 77: Switch Partitions
Chapter 6 Switch Partitions ® Introduction Notes The PES32H8G2 supports up to 8 active switch partitions. Each switch partition represents an indepen- dent PCI Express hierarchy whose operation is independent of other switch partitions. A port may be configured to operate in one of four modes. –...
Page 78: Partition State
IDT Switch Partitions Notes A partition with one upstream port and no downstream ports has the following behavior. – All received requests, except configuration requests that target the upstream port, are treated as unsupported requests. – All received completions are treated as unsupported requests. –...
Page 79: Partition State Change
IDT Switch Partitions Notes The partition fundamental reset condition is considered to persist as long as the STATE field in the SWPARTxCTL register remains in the fundamental reset state. Transitioning a partition from the funda- mental reset state to the active state requires that the system meet the requirements associated with a conventional reset outlined in Section 6.6.1 in the PCIe Base specification.
Page 80: Switch Ports
IDT Switch Partitions Notes Refer to section Static Reconfiguration on page 6-15 for a sample partition and port configuration sequence programmed via the serial EEPROM. Partition State Change via Other Methods When modifying the state of a partition via methods other than EEPROM loading (i.e., via PCI Express configuration requests or using the SMBus slave), the following requirements and restrictions apply: –...
Page 81 IDT Switch Partitions Notes A port in the disabled mode has the following behavior. – All output signals associated with the port are placed in a negated state (e.g., link status and hot- plug signals). • The negated value of HPxAIN, HPxILOCKP, HPxPEP, HPxPIN, and HPxRSTN is determined as shown in Table 10.2.
Page 82 IDT Switch Partitions Notes All input signals associated with the port, except the SerDes, are ignored and have no effect on the operation of the device. – Boot configuration vector signals are sampled during a switch fundamental reset and thus their dynamic state has no effect on the operating mode of the port in any port mode.
Page 83: Port Operating Mode Change
IDT Switch Partitions Notes A port in the upstream switch port mode has the following behavior. – Has the behavior of an upstream switch port defined by the PCI express base specification. – The LTSSM is operational and behaves as an upstream port. Downstream Switch Port A port in downstream switch port mode behaves as the downstream port of a switch partition.
Page 84 IDT Switch Partitions Notes Changing the operating mode of a port is subject to the requirements and restrictions listed in the sub- sections below. Since an operating mode change may take a significant amount of time to complete, status bits are provided to indicate when the change has started and when it has completed. –...
Page 85: Common Operating Mode Change Behavior
IDT Switch Partitions Notes – The operating mode of a port in upstream switch port mode can’t be later modified to downstream switch port mode, except after a switch fundamental reset. This restriction holds even if the modi- fication from upstream switch port mode to downstream switch port mode goes through interme- diate states (e.g., unattached, disabled).
Page 86 IDT Switch Partitions Notes When a port operating mode change is initiated, the operation logically executes in the following order. 1. The OMCI bit in the SWPORTxSTS register is set. 2. The effect on the source partition, if appropriate, takes place (i.e., cleanly remove the port from the partition).
Page 87 IDT Switch Partitions Notes Upstream port removal: – A switch partition must initiate an exit from L0s on the transmitters of all downstream ports asso- ciated with the partition if it detects an exit from L0s on the receiver of its upstream port. –...
Page 88 IDT Switch Partitions Notes described in section Partition Hot Reset on page 5-9. An upstream port whose link transition to the Detect state (i.e., DL_Down) as a result of the operating mode change may trigger a hot-reset in the destination partition as described in section Partition Hot Reset on page 5-9.
Page 89 IDT Switch Partitions Notes Upstream port addition: – A switch partition must initiate an exit from L0s on the transmitters of all downstream ports asso- ciated with the partition if it detects an exit from L0s on the receiver of its upstream port. See the PCI Express Base specification for details.
Page 90: No Action Mode Change Behavior
IDT Switch Partitions Notes INTx Interrupt Signaling Adding an upstream port to a partition causes the upstream port to adopt the aggregated interrupt state of the downstream ports associated with the destination partition. This may result in the generation of Assert_INTx and Deassert_INTx messages if the new aggregated state is different from that previously reported to the root.
Page 91: Hot Reset Mode Change Behavior
IDT Switch Partitions Hot Reset Mode Change Behavior Notes Modifying the operating mode of a port when the OMA field is set to hot reset has the following behavior in addition to that specified by the common operating mode change behavior. –...
Page 92: Dynamic Reconfiguration
IDT Switch Partitions Notes – Change the port operating mode by setting the following fields in the SWPORTxCTL register. This causes the port to be added to the selected partition. • MODE field to ‘Downstream switch port’ • PART field to the appropriate partition (e.g., 0 or 1) •...
Page 93 IDT Switch Partitions Notes A system may require software notification when a partition reconfiguration occurs. If the reconfiguration results in the addition, removal, or change in operating mode of the upstream port associated with the parti- tion, then the system may be notified of the reconfiguration by a link down event detected by the component upstream of the partition (i.e., the root or switch downstream port).
Page 94 IDT Switch Partitions Notes PES32H8G2 User Manual 6 - 18 April 5, 2013...
Page 95: Link Operation
Chapter 7 Link Operation ® Introduction Notes Link operation in the PES32H8G2 adheres to the PCI Express 2.0 Base Specification, supporting speeds of 2.5 GT/s and 5.0 GT/s. The PES32H8G2 contains sixteen x4 ports which may be merged in pairs to form x8 ports.
Page 96 IDT Link Operation Notes PExRP[0] lane 0 PExRP[0] lane 3 PExRP[1] lane 1 PExRP[1] lane 2 PES32H8G2 PES32H8G2 PExRP[2] lane 2 PExRP[2] lane 1 PExRP[3] lane 3 PExRP[3] lane 0 (a) x4 Port without lane reversal (b) x4 Port with lane reversal PExRP[0] lane 0 PExRP[0]...
Page 97 IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PExRP[2] PExRP[2] PExRP[3] PExRP[3] PES32H8G2 PES32H8G2 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x2 Port with lane reversal (a) x2 Port without lane reversal PExRP[0] PExRP[0] lane 0...
Page 98 IDT Link Operation Notes PExRP[0] lane 3 PExRP[0] lane 0 PExRP[1] lane 2 PExRP[1] lane 1 PExRP[2] lane 1 PExRP[2] lane 2 PExRP[3] lane 0 PExRP[3] lane 3 PES32H8G2 PES32H8G2 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x4 Port with lane reversal (a) x4 Port without lane reversal PExRP[0] PExRP[0]...
Page 99: Link Width Negotiation
IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES32H8G2 PES32H8G2 PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5] lane 5 PExRP[6] lane 1...
Page 100: Link Width Negotiation In The Presence Of Bad Lanes
IDT Link Operation Notes The actual link width is determined dynamically during link training. Ports limited to a maximum link width of x8 are capable of negotiating to a x8, x4, x2, or x1 link width. The current negotiated width of a link may be determined from the Negotiated Link Width (NLW) field in the corresponding port’s PCI Express Link Status (PCIELSTS) register.
Page 101: Link Speed Negotiation In The Pes32H8G2
IDT Link Operation Notes A component advertises its supported speeds via the Data Rate Identifier bits in the TS1 and TS2 training sets transmitted to its link partner during link training. The PCIe spec permits a component to change its supported speeds dynamically. It is allowed for a component to advertise supported link speeds without necessarily changing the link speed, via the Recovery LTSSM state.
Page 102: Software Management Of Link Speed
IDT Link Operation Notes The current link speed of each port is reported via the Current Link Speed (CLS) field of the port’s Link Status Register (PCIELSTS). The above behavior applies after full link retrain (i.e., when the LTSSM transi- tions through the ‘Detect’...
Page 103: Link Retraining
IDT Link Operation Notes As mentioned above, the Target Link Speed (TLS) field of the port’s Link Control 2 Register (PCIELCTL2) sets the preferred link speed. By default, the Target Link Speed of each PES32H8G2 port is set to 5.0 GT/s. During normal operation, the link speed of a downstream port may be modified by setting the TLS field of the port’s PCIELCTL2 register to the desired speed and initiating link retraining by writing a one to the Link Retrain (LRET) bit in the Link Control (PCIELCTL) register.
Page 104: Link Down
IDT Link Operation Link Down Notes When an upstream port’s link goes down, it triggers a hot reset in the partition associated with the port, as described in section Partition Hot Reset on page 5-9. In addition: – All TLPs queued in the port’s ingress frame buffer (IFB) are silently discarded. –...
Page 105: Link States
IDT Link Operation Link States Notes PES32H8G2 ports support the following link states: – L0 Fully operational link state – L0s Automatically entered low power state with shortest exit latency – L1 Lower power state than L0s May be automatically entered or directed by software by placing the device in the D3 state –...
Page 106: L0S Aspm
IDT Link Operation L0s ASPM Notes L0s entry/exit operates independently for each direction of the link. On the receive side, the PES32H8G2 upstream and downstream ports always respond to L0s entry/exit requests from the link partner. On the transmit side, the L0s entry conditions must be met for 7us before the hardware transitions the transmit link to the L0s state.
Page 107: L1 Aspm Entry Rejection Timer
IDT Link Operation Notes state from its link partner. If the link partner acknowledges the transition, then the L1 state is entered. Other- wise, L0s entry is attempted A port configured in ‘Upstream Switch Port’ mode initiates L1 entry when all of the conditions listed below are met: –...
Page 108: Link Status
IDT Link Operation Notes Some endpoint devices do not meet the required 10 µs gap between consecutive L1 ASPM entry requests. A live-lock situation can develop in the following scenario: – The Endpoint sends continuous PM_Active_State_Request_L1 DLLPs to the downstream port of a switch.
Page 109: Crosslink
IDT Link Operation Notes During normal operation (i.e, not polling.compliance), de-emphasis selection is done during the Recovery state. The downstream component of the link (i.e., switch upstream port or endpoint) advertises its desired de-emphasis by transmission of training sets. The upstream component of the link (i.e., switch downstream port or root-complex port) notes its link partner desired de-emphasis, and makes a decision about the de-emphasis to be used in the link.
Page 110: Hot Reset Operation On A Crosslink
IDT Link Operation Hot Reset Operation on a Crosslink Notes When a PES32H8G2 port forms a crosslink, hot reset operates as follows. – For a port operating in downstream switch port mode: • Regardless of the physical layer’s mode of operation (i.e., upstream or downstream lanes), the physical layer responds to the reception of training sets with the hot reset bit set by transitioning to the hot reset state as specified in the PCI Express Base Specification.
Page 111: Table 7.2 Gen1 Compatibility Mode: Bits Cleared In Training Sets
IDT Link Operation Notes When a PES32H8G2 port operates in Gen1 Compatibility Mode, the PHY does not set the following bits in Table 7.2 in the training sets that it transmits. PCIe 1.1 and Training Symbol earlier PCI Express 2.0 Definition Definition Reserved 5.0 GT/s Data Rate Support...
Page 112 IDT Link Operation Notes PES32H8G2 User Manual 7 - 18 April 5, 2013...
Page 113: Serdes
Chapter 8 SerDes ® Introduction Notes This chapter describes the controllability of the Serialiazer-Deserializer (SerDes) block associated with each PES32H8G2 port. A SerDes block is composed of the serializing/deserializing logic for four PCI Express lanes (i.e., a SerDes “quad”), plus a central block that controls the quad as a whole. This central block is called CMU, and contains functionality such as a PLL to generate a high-speed clock used by each lane, initialization of the quad, etc.
Page 114: Serdes Transmitter Controls
IDT SerDes Notes Port SerDes Quad Port Lane(s) SerDes Quad Lane(s) Port 0 SerDes 0 [3:0] [0:3] Port 1 SerDes 1 [3:0] [0:3] Port 2 SerDes 2 [3:0] [3:0] Port 3 SerDes 3 [3:0] [3:0] Port 4 SerDes 4 [3:0] [0:3] Port 5 SerDes 5...
Page 115: De-Emphasis
IDT SerDes Notes page 8-4 for procedural details on modifying the default SerDes settings and to section SerDes Transmitter Control Registers on page 8-5 for details on programming the transmitter voltage level and amplitude boost controls. De-emphasis The PCI Express 2.0 specification supports three de-emphasis levels: -3.5 dB (at 2.5 GT/s or 5.0 GT/s speeds), -6.0 dB (only for 5.0 GT/s), and 0 dB (low-swing mode).
Page 116: Programming Of Serdes Controls
IDT SerDes Notes For details on programming the receiver equalizer, refer to section Receiver Equalization Controls on page 8-15. The PES32H8G2 places no restrictions on the time at which the equalizer settings may be modified (e.g., the settings can be modified during normal operation of the link or while the link is being tested).
Page 117: Serdes Transmitter Control Registers
IDT SerDes SerDes Transmitter Control Registers Notes As described above, each SerDes quad is associated with two transmitter control registers (S[x]TXLCTL0 and S[x]TXLCTL1). Together, these registers allow full programmability of the SerDes trans- mitter voltage levels and de-emphasis. These registers are segmented into fields that allow programma- bility of the transmit driver levels under the following PHY operating modes: –...
Page 118: Table 8.3 Serdes Transmit Driver Settings In Gen1 Mode
IDT SerDes Notes Modification of these settings take an immediate effect on the SerDes. Therefore, the link does not need to be retrained explicitly (i.e., by setting the link-retrain (LRET) bit in the PCIELCTL) in order for these settings to take effect. Still, the user must be careful when changing the transmit voltage margin while the port is in normal operating mode, as this may result in the link instability.
Page 119: Table 8.4 Serdes Transmit Driver Settings In Gen2 Mode With -3.5Db De-Emphasis
IDT SerDes Notes Settings of Relevant Fields in the S[x]TXLCTL0 & Transmit Levels S[x]TXLCTL1 registers Drive empha- TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW empha- Level sized FS3DBG1 3DBG1 FS3DBG1 FS3DBG1 Level -3.5 0x06 -3.5 0x05 -3.6 0x04 -3.6 0x03 -3.6 0x02 -3.6 0x01 -3.6...
Page 120: Table 8.5 Serdes Transmit Driver Settings In Gen2 Mode With -6.0Db De-Emphasis
IDT SerDes Notes Settings of Relevant Fields in the S[x]TXLCTL0 & Transmit Levels S[x]TXLCTL1 registers Drive emphas TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW emphas Level ized FS3DBG2 3DBG2 FS3DBG2 FS3DBG2 Level -3.6 0x0F -3.5 0x0E -3.4 0x0D -3.4 0x0C -3.4 0x0B -3.4 0x0A -3.4...
Page 121 IDT SerDes Notes Settings of Relevant Fields in the Transmit Levels S[x]TXLCTL0 & S[x]TXLCTL1 registers Drive empha- TDVL_ TX_EQ_ CDC_ FDC_ TX_SLEW empha- Level sized FS6DBG2 6DBG2 FS6DBG2 FS6DBG2 Level -5.8 0x19 -5.8 0x18 -5.9 0x17 -6.0 0x16 -6.1 0x15 -6.2 0x14 -6.2...
Page 122 IDT SerDes Notes In addition to the SerDes settings described above, the user may apply an amplitude boost to the drive swing by setting the TX_AMPBOOST field in the S[x]TXLCTL0 register. Amplitude boost may be applied on a per-lane basis. Amplitude boost may be applied to increase the drive swings above the values shown in Tables 8.3, 8.4, and 8.5.
Page 123 IDT SerDes Notes Figure 8.1 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -3.5 dB Nominal de-emphasis Figure 8.2 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit Drive Level Controls, when the PHY Operates in Gen2 Data Rate with -3.5 dB Nominal de-emphasis PES32H8G2 User Manual 8 - 11...
Page 124: Table 8.6 Transmitter Slew Rate Settings
IDT SerDes Notes Figure 8.3 De-emphasis Applied on Link as a Function of the Fine de-emphasis and Transmit Drive Level Controls, when the PHY Operates in Gen1 Data Rate with -6.0 dB Nominal de-emphasis Finally, note that it is possible to turn off de-emphasis (i.e., 0 dB de-emphasis) for a given PHY operating mode by setting the corresponding transmitter equalization control to 0x0, the coarse de-emphasis control to a value of 0x3, and the fine de-emphasis control to a value of 0x7.
Page 125: Transmit Margining Using The Pci Express Link Control 2 Register
IDT SerDes Notes Table 8.6 Transmitter Slew Rate Settings (Part 2 of 2) Transmit Margining using the PCI Express Link Control 2 Register When the Transmit Margin (TM) field in the port’s PCIELCTL2 register is set to a value other than ‘Normal Operating Range’, the transmitter voltage levels are controlled by hardware based on the setting of the TM field, and not by the S[x]TXLCTL0 and S[x]TXLCTL1 registers.
Page 126: Low-Swing Transmitter Voltage Mode
IDT SerDes Notes Finally, when the TM field is modified, the newly selected value is not applied until the PHY LTSSM tran- sitions through the states in which it is allowed to modify the transmit margin setting on the line (e.g., Recovery.RcvrLock).
Page 127: Receiver Equalization Controls
IDT SerDes Notes Drive Level TDVL_LSG2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Table 8.9 SerDes Transmit Drive Swing in Low Swing Mode at Gen2 Speed When the PHY enters the Polling.Compliance state and low-swing mode is enabled, the following occurs: –...
Page 128: Serdes Power Management
IDT SerDes SerDes Power Management Notes In order to maximize power savings in the SerDes, the PES32H8G2 adheres to the following guidelines. For SerDes quads that are used, their power state depends on the state of the port(s) associated with the SerDes, as described below.
Page 129: Theory Of Operation
Chapter 9 Theory of Operation ® Introduction Notes Each PES32H8G2 partition operates logically as a completely independent PCI Express switch that implements the behavior and capabilities required of a switch by the PCI Express Base 2.0 specification. This chapter describes the PES32H8G2-specific architectural behavior for the PCI Express switch associ- ated with each partition.
Page 130: Downstream Port Interrupts
IDT Theory of Operation Notes It follows that MSIs generated by the switch’s ports can’t fall within the multicast BAR aperture in the partition. When this occurs, the behavior is undefined. EN bit in INTXD bit Unmasked MSICAP in PCICMD Action Interrupt Register...
Page 131: Access Control Services
IDT Theory of Operation Notes Upstream Port Interrupt (Port 0) INTA INTB INTC INTD Device (N mod 4) = Device (N mod 4) = Device (N mod 4) = Device (N mod 4) = 0 INTA 0 INTB 0 INTC 0 INTD Device (N mod 4) = Device (N mod 4) =...
Page 132 IDT Theory of Operation Notes Upstream Port TLP route Completion with Bridge completer-abort status Partition 1 – Virtual PCI Bus ACS Source Validation (TLP is dropped at this point) Bridge Bridge Downstream Ports Figure 9.1 ACS Source Validation Example Figure 9.2 shows an example of ACS peer-to-peer request re-direct at a downstream port. In this case, the offending TLP received by the downstream port is re-directed towards the root-complex.
Page 133: Table 9.4 Prioritization Of Acs Checks For Request Tlps
IDT Theory of Operation Notes Upstream Port Intended TLP Route ACS Re-directed Route Bridge Partition 1 – Virtual PCI Bus ACS Upstream Forwarding Bridge Bridge Downstream Ports Figure 9.3 ACS Upstream Forwarding Example When multiple ACS checks are enabled, they are prioritized as described below. Table 9.4 shows the prioritization for ACS checks associated with the reception of request TLPs.
Page 134: Error Detection And Handling
IDT Theory of Operation Notes ACS Check Priority Comment ACS Upstream For- 2 (Highest) Applicable to request or completion TLPs warding received by the downstream port on its ingress link that target the port’s egress link. This is not considered a peer-to-peer transfer. ACS Peer-to-Peer 1 (Lowest) Applicable to non-relaxed-ordered peer-to-peer...
Page 135: Physical Layer Errors
IDT Theory of Operation Notes A PCI-to-PCI Bridge function claims a TLP in the following cases: – Address Routed TLPs: If received on the primary side of the bridge, the TLPs address falls within the address space range(s) programmed in the base/limit registers. If received on the secondary side of the bridge, always.
Page 136: Transaction Layer Errors
IDT Theory of Operation Notes A DL protocol error occurs when an ACK or NAK DLLP is received and the sequence number specified by AckNak_Seq does not correspond to an unacknowledged TLP or to the value in ACKD_SEQ Transaction Layer Errors Table 9.9 lists non-ACS error checks associated with a PCI-to-PCI bridge function and the action taken when an error is detected.
Page 137: Table 9.9 Transaction Layer Errors Associated With The Pci-To-Pci Bridge Function
IDT Theory of Operation Notes Role Func- Based Express Error tion- (Advisory) Specifica- Action Taken Condition Specific Error tion Error Reporting Section Condition Poisoned TLP 2.7.2.2 Advisory when Detected Parity Error (DPE) bit in the received the correspond- PCISTS or SECSTS register set appro- ing error is con- priately.
Page 138 IDT Theory of Operation Notes Role Func- Based Express Error tion- (Advisory) Specifica- Action Taken Condition Specific Error tion Error Reporting Section Condition Unexpected com- 2.3.2 Yes if a func- Advisory when Non-advisory cases: uncorrectable pletion received tion claims the correspond- error processing.
Page 139: Table 9.10 Conditions Handled As Unsupported Requests (Ur) By The Pci-To-Pci Bridge Function
IDT Theory of Operation Notes PCIe Specifica- Conditions handled as UR Description tion Section Routing Errors Refer to section Routing Errors on page 9-16. Numerous Vendor Defined Type 0 message recep- Vendor Defined Type 0 message which targets the 2.2.8.6 tion PCI-to-PCI bridge function.
Page 140: Table 9.12 Egress Malformed Tlp Error Checks
IDT Theory of Operation Notes TLP Type Error Check Message Requests TC = 0 interrupt message Power management message Error signalling message Unlock message Set power limit message TLPs with Route to Root Complex routing. May only be received on downstream ports TLPs with Broadcast from Root Complex rout- May only be received on upstream ports ing.
Page 141: Table 9.13 Acs Violations For Ports Operating In Downstream Switch Port Mode
IDT Theory of Operation Notes Role Based Express (Advisory) ACS Check Specifica- Error Action Taken tion Reporting Section Condition ACS Source Validation 6.12.1.1 Advisory when If TLP is a non-posted request, a completion the correspond- with ‘completer abort’ status is generated. Note ing error is con- that this is not considered a completer abort figured as non-...
Page 142 IDT Theory of Operation Notes In addition, the Detected Parity Error bit (DPE) in the PCISTS and SECSTS registers is not subject to error pollution rules and is therefore set when the PCI-to-PCI bridge receives a poisoned TLP on its primary or secondary side respectively, even if error pollution rules indicate that the poisoned TLP received error is superseded by a higher priority error.
Page 143: Table 9.14 Table
IDT Theory of Operation Notes TLP Received by Done Function Handle per Table 12.9 Receiver Overflow Error? Handle per Table 12.9 ECRC TLP Dropped? Error? If ECRC error detected, handle per Table 12.9 but do not log Malformed error; Else, Malformed TLP? handle per Table 12.9 If ECRC detected, handle per Table 12.13...
Page 144: Routing Errors
IDT Theory of Operation Notes Note the following: – Except for ECRC and Poisoned TLP errors, all other errors detected on the received TLP cause the detecting function to consume, drop, or nullify the TLP. – Receiver overflow errors are only checked and logged. –...
Page 145: Bus Locking
IDT Theory of Operation Notes Address Routed TLPs TLPs received by an upstream port that match the upstream port’s address range but which do not match a downstream port’s address range within the partition (i.e., TLPs that do not route through the parti- tion).
Page 146 IDT Theory of Operation Notes A locked transaction sequence is requested by the root complex by issuing a Memory Read Request - Locked (MRdLk) transaction. A lock is established when a lock request is successfully completed with a Completion with Data - Locked (CplDLk). A lock is released with an Unlock message (Msg) sent by the root complex.
Page 147 IDT Theory of Operation Notes Note that when a TLP received by port is blocked from being forwarded due to a bus-locked partition, the TLP is delayed until the partition is unlocked. If the partition is locked for an extended period, this may cause TLPs to be discarded due to switch time-outs.
Page 148 IDT Theory of Operation Notes PES32H8G2 User Manual 9 - 20 April 5, 2013...
Page 149: Hot-Plug And Hot-Swap
Chapter 10 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 10.1 through 10.3, a PCIe switch may be used in one of three hot-plug configu- rations. Figure 10.1 illustrates the use of PES32H8G2 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.
Page 150 IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES32H8G2 Port x Port y PCI Express PCI Express Device Device Figure 10.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES32H8G2 Master SMBus Port x Port y SMBus I/O...
Page 151: Hot-Plug Signals
IDT Hot-Plug and Hot-Swap Notes Associated with all PES32H8G2 ports is a hot-plug controller. However, hot-plug is only supported when a port is configured to operate in downstream switch port mode. Hot-plug is supported within switch parti- tions. When hot-plug is enabled in a downstream port of a switch partition, the behavior is identical do that expected if the switch partition were a stand-alone PCIe switch.
Page 152: Table 10.2 Negated Value Of Unused Hot-Plug Output Signals
IDT Hot-Plug and Hot-Swap Notes Negated Output Negated Output Value with Non- Value with Signal Inverted Polarity Inverted Polarity (IPXxxx = 0) (IPXxxx = 1) PxAIN 1 (high) 0 (low) PxILOCKP 0 (low) 1 (high) PxPEP 0 (low) 1 (high) PxPIN 1 (high) 0 (low)
Page 153: Port Reset Outputs
IDT Hot-Plug and Hot-Swap Port Reset Outputs Notes Individual port reset outputs PxRSTN are provided as I/O expander outputs. Port reset outputs may be configured to operate in one of two modes. These modes are power enable controlled reset output and power good controlled reset output. The port reset output mode for all ports is determined by the Reset Mode (RSTMODE) field in the Hot-Plug Configuration Control (HPCFGCTL) register.
Page 154: Hot-Plug Events
IDT Hot-Plug and Hot-Swap Notes PWR2RST RST2PWR PxPEP PxPWRGDN PxRSTN Figure 10.5 Power Good Controlled Reset Output Mode Operation The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that when power is enabled, the negation of the corresponding port reset output occurs as a result of and after assertion of the slot’s Power Good (PxPWRGDN) signal is observed.
Page 155: Legacy System Hot-Plug Support
IDT Hot-Plug and Hot-Swap Notes If a hot-plug event occurs while a downstream port is in D3hot and the corresponding interrupt is enabled, the port will generate an interrupt if the corresponding event’s status bit is set in the PCIESCTL is set and the state of the port is transitioned from D3 to D0 without a reset.
Page 156: Hot-Swap
IDT Hot-Plug and Hot-Swap Notes General Purpose Event Enable General Purpose Event Mechanism Interrupt Slot Control Disable Register Activate INTx Hot-Plug Interrupt Mechanism Enable Slot Status Register Activate MSI Mechanism Command Completed Enable Command Completed MSI Enable RW1C RW1C Attention Button Pressed Enable Attention Button Pressed...
Page 157: Power Management
Chapter 11 Power Management ® Introduction Notes Located in configuration space of each Function in the PES32H8G2 (i.e., PCI-to-PCI Bridge Function) is a power management capability structure. PES32H8G2 Functions support the following device power management states: – D0 (D0 and D0 uninitialized active –...
Page 158: Table 11.1 Pes32H8G2 Power Management State Transition Diagram
IDT Power Management Notes Reset Uninitialized Active cold Figure 11.1 PES32H8G2 Power Management State Transition Diagram From State To State Description D0 Uninitialized Switch reset (any type). D0 Uninitialized D0 Active Function configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the D3 state.
Page 159: Pme Messages
IDT Power Management Notes • This requires transitioning the link to the L0 state when the completion needs to be transmitted on the link by the bridge Function and the link is not in L0. – All request TLPs received on the secondary interface are treated as unsupported requests (UR). PME Messages PES32H8G2 does not support generation of PME messages from the D3 state.
Page 160: Power Budgeting Capability
IDT Power Management Power Budgeting Capability Notes PES32H8G2 contains the mechanisms necessary to implement the PCI-Express power budgeting enhanced capability. However, by default, these mechanisms are not enabled. To enable the power budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in one of the other enhanced capabilities should be initialized to point to the power budgeting capability.
Page 161: General Purpose I/O
Chapter 12 General Purpose I/O ® Introduction Notes The PES32H8G2 has 9 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function [1:0] (GPIOFUNCx), General Purpose I/O Configuration [1:0] (GPIOCFGx), General Purpose I/O Data [1:0] (GPIODx), and General Purpose I/O Alternate Function Select [1:0] (GPIO- AFSELx) registers.
Page 162: Table 12.2 General Purpose I/O Pin Alternate Function
IDT General Purpose I/O Notes GPIO Pin Alternate Function 0 Alternate Function 1 PART0PERSTN — PART1PERSTN — PART2PERSTN — PART3PERSTN — — P0LINKUPN GPEN P0ACTIVEN IOEXPINTN — Table 12.2 General Purpose I/O Pin Alternate Function Alternate function signals are described in Table 12.3. Signal Type Name/Description...
Page 163: Smbus Interfaces
Chapter 13 SMBus Interfaces ® Introduction Notes PES32H8G2 has two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers, allowing every register in the device to be read or written by an external SMBus master. The slave SMBus may also be used to program the serial EEPROM used for initialization.
Page 164: Initialization From Serial Eeprom
IDT SMBus Interfaces Initialization from Serial EEPROM Notes During initialization from the optional serial EEPROM, the master SMBus interface reads configuration blocks from the serial EEPROM and updates corresponding registers in PES32H8G2. Any software visible register in the device may be initialized with values stored in the serial EEPROM. All software visible registers have a system address.
Page 165: Figure 13.2 Single Double Word Initialization Sequence Format
IDT SMBus Interfaces Notes TYPE Reserved Byte 0 (must be zero) Byte 1 SYSADDR[9:2] Byte 2 SYSADDR[18:10] Byte 3 DATA[7:0] Byte 4 DATA[15:8] Byte 5 DATA[23:16] Byte 6 DATA[31:24] Figure 13.2 Single Double Word Initialization Sequence Format The second type of configuration block is the sequential double word initialization sequence. It is similar to a single double word initialization sequence except that it contains a double word count that allows multiple sequential double words to be initialized in one configuration block.
Page 166: Figure 13.4 Configuration Done Sequence Format
IDT SMBus Interfaces Notes The final type of configuration block is the configuration done sequence which is used to signify the end of a serial EEPROM initialization sequence. If during serial EEPROM initialization, an attempt is made to initialize a register that is not defined in a configuration space (i.e., not defined in Chapter 14), then the Unmapped Register Initialization Attempt (URIA) bit is set in the SMBUSSTS register and the write is ignored.
Page 167: Programming The Serial Eeprom
IDT SMBus Interfaces Notes Error Action Taken Configuration Done Sequence checksum mis- - Set RSTHALT bit in SWCTL register match with that computed - ICSERR bit is set in the SMBUSSTS register - Abort initialization, set DONE bit in the SMBUSSTS register Invalid configuration block type - Set RSTHALT bit in SWCTL register (only invalid type is 0x2)
Page 168: Table 13.3 I/O Expander Function Allocation
IDT SMBus Interfaces Notes PES32H8G2 supports up to 14 external I/O expanders. Table 13.3 summarizes the allocation of func- tions to I/O expanders. I/O expander signals associated with LED control (i.e., link status and activity) are active low (i.e., driven low when an LED should be turned on). I/O expander signals associated with hot- plug signals are not inverted.
Page 169: Table 13.4 I/O Expander Default Output Signal Value
IDT SMBus Interfaces Notes Default Hot-Plug Signal Description Value PxAIN Attention indicator output (off) PxPIN Power indicator output (on) PxPEP Power enable output (on) PxILOCKP Electromechanical interlock (negated - off) Table 13.4 I/O Expander Default Output Signal Value The following I/O expander configuration sequence is issued by PES32H8G2 to I/O expanders 0 through 7, 9 and 10 (i.e., the ones that contain general port hot-plug signals and electromechanical interlock signals).
Page 170 IDT SMBus Interfaces Notes While the I/O expander is enabled, PES32H8G2 maintains the I/O bus expander signals and the PES32H8G2 internal view of the hot-plug signals in a consistent state. This means that whenever that I/O bus expander state and the internal view of the signal state differs, an SMBus transaction is initiated to resolve the state conflict.
Page 171: Table 13.6 Pin Mapping I/O Expander 8
IDT SMBus Interfaces Notes Hot-Plug I/O Expanders 0 through 7 SMBus I/O Expander Type Signal Description Port x attention push button input 0 (I/O-0.0) PxAPN 1 (I/O-0.1) PxPDN Port x presence detect input 2 (I/O-0.2) PxPFN Port x power fault input 3 (I/O-0.3) PxPWRGDN Port x power good input...
Page 172 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 6 (I/O-0.6) P6MRLN Port 6 manually operated retention latch (MRL) input 7 (I/O-0.7) P7MRLN Port 7 manually operated retention latch (MRL) input 8 (I/O-1.0) Unused Unused 9 (I/O-1.1) 10 (I/O-1.2) 11 (I/O-1.3) 12 (I/O-1.4) 13 (I/O-1.5)
Page 173: Table 13.8 I/O Expander 11 - Fundamental Reset Inputs
IDT SMBus Interfaces Notes I/O Expander 11 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) PART0PERSTN Partition 0 Fundamental Reset Input 1 (I/O-0.1) PART1PERSTN Partition 1 Fundamental Reset Input 2 (I/O-0.2) PART2PERSTN Partition 2 Fundamental Reset Input 3 (I/O-0.3) PART3PERSTN Partition 3 Fundamental Reset Input 4 (I/O-0.4) PART4PERSTN...
Page 174: Slave Smbus Interface
IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 8 (I/O-1.0) Unused Unused 9 (I/O-1.1) 10 (I/O-1.2) 11 (I/O-1.3) 12 (I/O-1.4) 13 (I/O-1.5) 14 (I/O-1.6) 15 (I/O-1.7) Table 13.9 I/O Expander 12 - Link Up Status (Part 2 of 2) I/O-x.y corresponds to the notation used for PCA9555 port x I/O pin y.
Page 175: Initialization
IDT SMBus Interfaces Initialization Notes Slave SMBus initialization occurs during a switch fundamental reset. During the switch fundamental reset initialization sequence, the slave SMBus address is initialized. The address is specified by the SSMBADDR[2,1] signals as shown in Table 13.11. Address Address Bit Value SSMBADDR[1]...
Page 176: Table 13.12 Slave Smbus Command Code Fields
IDT SMBus Interfaces Notes Name Description Field End of transaction indicator. Setting both START and END signi- fies a single transaction sequence 0 - Current transaction is not the last read or write sequence. 1 - Current transaction is the last read or write sequence. START Start of transaction indicator.
Page 177: Table 13.14 Csr Register Read Or Write Cmd Field Description
IDT SMBus Interfaces Notes Byte Field Description Position Name ADDRL Address Low. Lower 8-bits of the doubleword system address of register to access. ADDRU Address Upper. Upper 8-bits of the doubleword system address of register to access. DATALL Data Lower. Bits [7:0] of data doubleword. DATALM Data Lower Middle.
Page 178: Table 13.15 Serial Eeprom Read Or Write Operation Byte Sequence
IDT SMBus Interfaces Notes Name Type Description Field Reserved. Must be zero RERR Read-Only Read Error. This bit is set if the last CSR read SMBus transaction and Clear was not claimed by the device. Success indicates that the transaction was claimed, not necessarily that the operation completed without error.
Page 179: Table 13.16 Serial Eeprom Read Or Write Cmd Field Description
IDT SMBus Interfaces Notes OTHERERR NAERR Figure 13.7 Serial EEPROM Read or Write CMD Field Format Name Type Description Field Serial EEPROM Operation. This field encodes the serial EEPROM operation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address.
Page 180: Figure 13.9 Serial Eeprom Read Using Smbus Block Write/Read Transactions With Pec
IDT SMBus Interfaces Notes PES32H8G2 Slave CCODE BYTCNT=4 CMD=read EEADDR ADDRL SMBus Address START,END ADDRU PES32H8G2 Slave CCODE (PES32H8G2 not ready with data) SMBus Address START,END PES32H8G2 Slave CCODE PES32H8G2 Slave BYTCNT=5 CMD (status) EEADDR SMBus Address START,END SMBus Address ADDRL ADDRU DATA...
Page 181: Figure 13.13 Csr Register Read Using Smbus Read And Write Transactions With Pec Disabled
IDT SMBus Interfaces Notes PES32H8G2 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES32H8G2 Slave CCODE ADDRU SMBus Address END, Byte PES32H8G2 Slave CCODE (PES32H8G2 not ready with data) SMBus Address START,Word PES32H8G2 Slave CCODE SMBus Address START,Word PES32H8G2 Slave CMD (status) ADDRL SMBus Address...
Page 182 IDT SMBus Interfaces Notes PES32H8G2 User Manual 13 - 20 April 5, 2013...
Page 183: Multicast
Chapter 14 Multicast ® Introduction Notes The PES32H8G2 implements multicast within switch partitions as defined by the PCI-SIG Multicast ECN. The multicast capability enables a single TLP to be forwarded to multiple destinations. The destina- tions to which a multicast TLP is forwarded are referred to as a multicast group. –...
Page 184: Figure 14.1 Multicast Group Address Ranges
IDT Multicast Notes Only posted memory write TLPs and address routed message TLPs can be multicast TLPs. The primary determinant of whether or not a memory write or address routed message TLP is a multicast TLP is its address and the address associated with multicast address regions. A multicast address region may overlap a non-multicast address region.
Page 185: Figure 14.2 Multicast Group Address Region Determination
IDT Multicast Notes The starting address of the region associated multicast group zero is equal to the multicast base address defined by the Multicast Base Address Low (MCBARL) field in the MCBARL register and the Multi- cast Base Address High (MCBARH) field in the Multicast Base Address High (MCBARH) register. –...
Page 186: Multicast Tlp Routing
IDT Multicast Notes Note that the “block all” and “block untranslated” functions are performed at the ingress port on which the multicast TLP was received. A received multicast TLP without errors is forwarded to egress ports as described in the next section. Multicast TLP Routing A multicast TLP received without error by a function is forwarded as described in this section.
Page 187 IDT Multicast Notes A side-effect of modifying the address due to multicast overlay processing is that the ECRC associated with the original TLP may not be correct for the new modified TLP. Therefore, functions perform the following ECRC processing: – If multicast overlay processing is disabled, then no ECRC processing is performed as part of multi- cast egress processing.
Page 188 IDT Multicast Notes PES32H8G2 User Manual 14 - 6 April 5, 2013...
Page 189: Register Organization
Chapter 15 Register Organization ® Introduction Notes All software visible registers in the PES32H8G2 are contained in a 256 KB global address space. The address of a register in this address range is referred to as the system address of the register. –...
Page 190: Partial-Byte Access To Word And Dword Registers
IDT Register Organization Notes The entire PES32H8G2 global address space may be accessed using PCI configuration requests from any PES32H8G2 PCI function. – Located in each PCI function is a Global Address Space Access Address (GASAADDR) and Global Address Space Access Data (GASADATA) register. –...
Page 191: Pci-To-Pci Bridge Registers
IDT Register Organization PCI-to-PCI Bridge Registers Notes This section outlines the configuration space associated with PCI-to-PCI bridges. These registers are accessible as function 0 when the port is configured in the following modes. – Upstream switch port – Downstream switch port These registers are always accessible regardless of the port mode using global address space access registers (i.e., GASAADDR and GASADATA), SMBus, or serial EEPROM.
Page 192: Table 15.2 Default Pci Capability List Linkage
IDT Register Organization Notes Default Value of PCI Capability Structure Next Pointer Field (NXTPTR) Offset in Name Configuration Space PCI Express Capability (PCIECAP) 0x040 0x0C0 0x0C0 PCI Power Management Capability (PMCAP) 0x0C0 0x0D0 Message Signaled Interrupt Capability (MSICAP) 0x0D0 Subsystem ID and Subsystem Vendor Capability 0x0F0 (SSIDSSVIDCAP) Table 15.2 Default PCI Capability List Linkage...
Page 193: Figure 15.1 Pci-To-Pci Bridge Configuration Space Organization
IDT Register Organization Notes 0x000 PCI Configuration Space (64 Dwords) 0x000 0x100 Advanced Error Reporting Enhanced Capability 0x180 Device Serial Number Enhanced Capability Type 1 Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 Power Budgeting Enhanced Capability 0x040 0x320 PCI Express Capability Structure ACS Enhanced Capability...
Page 194: Register Definition
IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x000 Word VID - Vendor Identification Register (0x000) on page 16-1 0x002 Word DID - Device Identification Register (0x002) on page 16-1 0x004 Word PCICMD PCICMD - PCI Command Register (0x004) on page 16-1 0x006 Word PCISTS...
Page 195 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x044 DWord PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 16-11 0x048 Word PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 16-13 0x04A Word PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 16-14 0x04C DWord PCIELCAP...
Page 196 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x10C Dword AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page 16-36 0x110 Dword AERCES AERCES - AER Correctable Error Status (0x110) on page 16-37 0x114 Dword AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 16-38 0x118 Dword AERCTL...
Page 197 IDT Register Organization Cfg. Register Size Register Definition Offset Mnemonic 0x30C Dword PWRBDV3 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on page 16-48 0x310 Dword PWRBDV4 PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0x31C) on page 16-48 0x314 Dword...
Page 198: Idt Proprietary Port Specific Registers
IDT Register Organization IDT Proprietary Port Specific Registers Notes This section outlines the address range 0x400 through 0xFFF in the PCI-to-PCI bridge address space. This address range contains IDT proprietary registers that are port specific. Registers in this address range may be accessed using PCI configuration requests to the corresponding PCI-to-PCI bridge function 0 header, global address space access registers, SMBus, or serial EEPROM.
Page 199: Table 15.5 Proprietary Port Specific Registers
IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x420 Dword PCIESCTLIV PCIESCTLIV - PCI Express Slot Control Initial Value (0x420) on page 16-57 0x480 DWord IERRORCTL IERRORCTL - Internal Error Reporting Control (0x480) on page 16- 0x484 DWord IERRORSTS IERRORSTS - Internal Error Reporting Status (0x484) on page 16-...
Page 200: Switch Configuration And Status Registers
IDT Register Organization Switch Configuration and Status Registers Notes This section outlines switch configuration and status registers. These registers are accessible using global address space access registers (i.e., GASAADDR and GASADATA), SMBus, or serial EEPROM. Figure 15.3 shows the organization of the address space. Registers in this address range are referenced as REGNAME where REGNAME represents the register name in Table 15.6.
Page 201: Table 15.6 Switch Configuration And Status
IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0000 DWord SWCTL SWCTL - Switch Control (0x0000) on page 17-1 0x0004 DWord BCVSTS BCVSTS - Boot Configuration Vector Status (0x0004) on page 17-2 0x0008 DWord PCLKMODE PCLKMODE - Port Clocking Mode (0x0008) on page 17-3 USSBRDELAY - Upstream Secondary Bus Reset Delay (0x008C) 0x008C DWord...
Page 202 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x03C4 DWord SWPORT6STS SWPORT[7:0]STS - Switch Port x Status on page 17-6 0x03E0 DWord SWPORT7CTL SWPORT[7:0]CTL - Switch Port x Control on page 17-5 0x03E4 DWord SWPORT7STS SWPORT[7:0]STS - Switch Port x Status on page 17-6 0x0400 —...
Page 203 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x08B0 DWord S5RXEQLCTL S[7:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control on page 17-15 0x08C0 DWord S6CTL S[7:0]CTL - SerDes x Control on page 17-8 0x08C4 DWord S6TXLCTL0 S[7:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 on page 17-9 0x08C8 DWord S6TXLCTL1...
Page 204 IDT Register Organization Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0AE8 DWord GPECTL GPECTL - General Purpose Event Control (0x0AE8) on page 17-25 0x0AEC DWord GPESTS GPESTS - General Purpose Event Status (0x0AEC) on page 17-25 0x0AF0 — 0x0F10 Reserved Table 15.6 Switch Configuration and Status (Part 4 of 4) PES32H8G2 User Manual...
Page 205: Pci To Pci Bridge And Proprietary Port Specific Registers
Chapter 16 PCI to PCI Bridge and Proprie- tary Port Specific Registers ® Type 1 Configuration Header Registers VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT.
Page 206 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value VGAS VGA Palette Snoop. Not applicable. PERRE Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit (MDPED) in the PCI Status (PCISTS) register.
Page 207 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MDPED RW1C Master Data Parity Error Detected. This bit is set by the bridge function if the PERRE bit in the PCI Command register (PCICMD) is set to 0x1 and either of the following two conditions occurs: the function receives a Poisoned Completion going Downstream, or the function transmits a Poisoned Request Upstream.
Page 208 IDT PCI to PCI Bridge and Proprietary Port Specific Registers CLS - Cache Line Size Register (0x00C) Field Default Type Description Field Name Value 0x00 Cache Line Size. This field has no effect on the bridge’s function- ality but may be read and written by software. This field is implemented for compatibility with legacy software.
Page 209 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PBUSN - Primary Bus Number Register (0x018) Field Default Type Description Field Name Value PBUSN Primary Bus Number. This field is used to record the bus number of the PCI bus segment to which the primary interface of the bridge is connected.
Page 210 IDT PCI to PCI Bridge and Proprietary Port Specific Registers IOLIMIT - I/O Limit Register (0x01D) Field Default Type Description Field Name Value IOCAP I/O Capability. Indicates if the bridge supports 16-bit or 32-bit I/O addressing. This bit always reflects the value of the IOCAP field in the IOBASE register.
Page 211 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MBASE - Memory Base Register (0x020) Field Default Type Description Field Name Value Reserved Reserved field. 15:4 MBASE 0xFFF Memory Address Base. The MBASE and MLIMIT registers are used to control the forwarding of non-prefetchable transactions between the primary and secondary interfaces of the bridge.
Page 212 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. 15:4 PMLIMIT Prefetchable Memory Address Limit. The PMBASE, PMBASEU, PMLIMIT and PMLIMITU registers are used to control the forward- ing of prefetchable transactions between the primary and second- ary interfaces of the bridge.
Page 213 IDT PCI to PCI Bridge and Proprietary Port Specific Registers CAPPTR - Capabilities Pointer Register (0x034) Field Default Type Description Field Name Value CAPPTR 0x40 Capabilities Pointer. This field specifies a pointer to the head of the capabilities structure. EROMBASE - Expansion ROM Base Address Register (0x038) Field Default Type...
Page 214 IDT PCI to PCI Bridge and Proprietary Port Specific Registers BCTL - Bridge Control Register (0x03E) Field Default Type Description Field Name Value PERRE Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit (MDPED) in the Secondary Status (SECSTS) register.
Page 215: Pci Express Capability Structure
IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCI Express Capability Structure PCIECAP - PCI Express Capability (0x040) Field Default Type Description Field Name Value CAPID 0x10 Capability ID. The value of 0x10 identifies this capability as a PCI Express capability structure.
Page 216 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value E0AL Endpoint L0s Acceptable Latency. This field indicates the acceptable total latency that an endpoint can withstand due to tran- sition from the L0s state to the L0 state. The value is hardwired to 0x0 as this field is only applicable to end- point functions.
Page 217 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDCTL - PCI Express Device Control (0x048) Field Default Type Description Field Name Value CEREN Correctable Error Reporting Enable. This bit controls reporting of correctable errors. NFEREN Non-Fatal Error Reporting Enable. This bit controls reporting of non-fatal errors.
Page 218 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDSTS - PCI Express Device Status (0x04A) Field Default Type Description Field Name Value RW1C Correctable Error Detected. This bit indicates the status of cor- rectable errors. Errors are logged in this register regardless of whether error reporting is enabled or not.
Page 219 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MAXLNK- HWINIT Maximum Link Width. This field indicates the maximum link width WDTH of the given PCI Express link. This field may be overridden to allow the link width to be forced to a smaller value.
Page 220 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Upstream: Link Bandwidth Notification Capability. When set, this bit indi- cates support for the link bandwidth notification status and interrupt mechanisms. The switch downstream ports support the capability. Downstream: This field is not applicable for the upstream port and must be zero.
Page 221 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value CCLK Common Clock Configuration. When set, this bit indicates that this port and the port at the opposite end of the link are operating with a distributed common reference clock.
Page 222 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value HWINIT Negotiated Link Width. This field indicates the negotiated width of the link. 00 0001b - x1 00 0010b - x2 00 0100b - x4 00 1000b - x8 00 1100b - x12 01 0000b - x16...
Page 223 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value LABWSTS RW1C Link Autonomous Bandwidth Status. This bit is set to indicate that either that the PHY has autonomously changed link speed or width for reasons other than to attempt to correct unreliable link operation.
Page 224 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 14:7 SPLV Slot Power Limit Value. In combination with the Slot Power Limit Scale, this field specifies the upper limit on power supplied by the slot.
Page 225 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value PFDE HWINIT Power Fault Detected Enable. This bit when set enables the gen- eration of a Hot-Plug interrupt or wake-up event on a power fault event.
Page 226 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value HWINIT Power Indicator Control. When read, this register returns the cur- rent state of the Power Indicator. Writing to this register sets the indicator.
Page 227 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value MRLSC RW1C MRL Sensor Changed. Set when an MRL Sensor state change is detected. RW1C Presence Detected Changed. Set when a Presence Detected change is detected.
Page 228 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) Field Default Type Description Field Name Value Reserved Reserved field. ARIFS ARI Forwarding Supported. This bit is set to indicate that the switch supports ARI Forwarding.
Page 229 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIELCTL2 - PCI Express Link Control 2 (0x070) Field Default Type Description Field Name Value Target Link Speed. For downstream ports, this field sets an upper Sticky limit on the link operational speed by restricting the values adver- tised by the upstream component in its training sequences.
Page 230 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Transmit Margin. This field controls the value of the non de- Sticky emphasized voltage level at the transmitter pins. This field is reset to 0x0 on entry to the LTSSM Polling.Configuration substate.
Page 231: Power Management Capability Structure
IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCIELSTS2 - PCI Express Link Status 2 (0x072) Field Default Type Description Field Name Value Current De-emphasis. The value of this bit indicates the current de-emphasis level when the link operates in 5.0 Gbps. 0x0 - De-emphasis level = -6.0 dB 0x1 - De-emphasis level = -3.5 dB The value of this bit in undefined when the link operates at...
Page 232 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 18:16 Power Management Capability Version. This field indicates compliance with version two of the specification. Complies with version the PCI Bus Power Management Interface Specification, Revision 1.2.
Page 233: Message Signaled Interrupt Capability Structure
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value PMEE PME Enable. When this bit is set, PME message generation is Sticky enabled for the port. If a hot plug wake-up event is desired when exiting the D3 cold state, then this bit should be set during serial EEPROM initializa- tion.
Page 234 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MSIADDR - Message Signaled Interrupt Address (0x0D4) Field Default Type Description Field Name Value Reserved Reserved field. 31:2 ADDR Message Address. This field specifies the lower portion of the DWORD address of the MSI memory write transaction. The switch assumes that all downstream port generated MSIs are targeted to the root and routes these transactions to the upstream port.
Page 235: Subsystem Id And Subsystem Vendor Id
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Subsystem ID and Subsystem Vendor ID SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) Field Default Type Description Field Name Value CAPID Capability ID. The value of 0xD identifies this capability as a SSID/ SSVID capability structure.
Page 236: Advanced Error Reporting (Aer) Enhanced Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 11:8 EREG Extended Register Number. This field selects the extended con- figuration register number as defined by Section 7.2.2 of the PCI Express Base Specification, Rev. 2.0. The value of this register must not be programmed to point to the address offset of this register (i.e., 0xF8) or the ECFGDATA regis- ter (i.e., 0xFC).
Page 237 IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERUES - AER Uncorrectable Error Status (0x104) Field Default Type Description Field Name Value UDEF RW1C Undefined. This bit is no longer used in this version of the specifi- Sticky cation.
Page 238 IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERUEM - AER Uncorrectable Error Mask (0x108) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the specifi- Sticky cation. Reserved Reserved field.
Page 239 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value UECOMP Unexpected Completion Mask. When this bit is set, the corre- Sticky sponding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error...
Page 240 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Uncorrectable Internal Error Mask. When this bit is set, the cor- Sticky responding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure, the First Error Pointer field (FEPTR) in the AERCTL register is not updated, and an error...
Page 241 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value COMPTO Completion Timeout Severity. A switch port does not initiate non- posted requests on its own behalf. Therefore, this field is hardwired to zero. CABORT Completer Abort Severity.
Page 242 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value BADTLP RW1C Bad TLP Status. This bit is set when a bad TLP is detected. Sticky BADDLLP RW1C Bad DLLP Status. This bit is set when a bad DLLP is detected. Sticky RPLYROVR RW1C...
Page 243 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value BADDLLP Bad DLLP Mask. When this bit is set, the corresponding bit in the Sticky AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root com- plex.
Page 244 IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERCTL - AER Control (0x118) Field Default Type Description Field Name Value FEPTR First Error Pointer. This field contains a pointer to the bit in the Sticky AERUES register that resulted in the first reported error. This field is valid only when the bit in the AERUES register pointed to by this field is set.
Page 245: Device Serial Number Enhanced Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers AERHL4DW - AER Header Log 4th Doubleword (0x128) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 4th doubleword of the TLP Sticky header that resulted in the first reported uncorrectable error. Device Serial Number Enhanced Capability SNUMCAP - Serial Number Capabilities (0x180) Field...
Page 246: Pci Express Virtual Channel Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers PCI Express Virtual Channel Capability PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2 indicates a virtual channel capabil- ity structure.
Page 247 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 31:24 VCATBLOFF VC Arbitration Table Offset. Not applicable (only the default VC 0 is implemented). PVCCTL - Port VC Control (0x20C) Field Default Type Description Field...
Page 248 IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0CTL- VC Resource 0 Control (0x214) Field Default Type Description Field Name Value TCVCMAP bit 0: 0xFF TC/VC Map. This field indicates the TCs that are mapped to the VC resource. Each bit corresponds to a TC.
Page 249 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value VCNEG VC Negotiation Pending. This bit is not applicable for VC0 and is therefore hardwired to 0x0. 31:18 Reserved Reserved field. VCR0TBL0 - VC Resource 0 Port Arbitration Table Entry 0 (0x240) Field Default Type...
Page 250 IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0TBL1 - VC Resource 0 Port Arbitration Table Entry 1 (0x244) Field Default Type Description Field Name Value PHASE8 Phase 8. This field contains the port ID for the corresponding port arbitration period.
Page 251: Power Budgeting Enhanced Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers VCR0TBL3 - VC Resource 0 Port Arbitration Table Entry 3 (0x24C) Field Default Type Description Field Name Value PHASE24 Phase 24. This field contains the port ID for the corresponding port arbitration period.
Page 252 IDT PCI to PCI Bridge and Proprietary Port Specific Registers PWRBDSEL - Power Budgeting Data Select (0x284) Field Default Type Description Field Name Value DVSEL Data Value Select. This field selects the Power Budgeting Data Value (PWRBDVx) register whose contents are reported in the Data (DATA) field of the Power Budgeting Data (PWRBD) register.
Page 253: Acs Extended Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers ACS Extended Capability ACSECAPH - ACS Extended Capability Header (0x320) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0xD indicates an ACS extended capa- bility structure.
Page 254 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Upstre Upstream ACS Upstream Forwarding. If set, indicates the port implements Port: ACS Upstream Forwarding. Port: Downstream Down- Port: stream Port: Upstre Upstream ACS P2P Egress Control.
Page 255 IDT PCI to PCI Bridge and Proprietary Port Specific Registers ACSCTL - ACS Control Register (0x326) Field Default Type Description Field Name Value Upstream Port: ACS Source Validation Enable. When set, the port performs ACS Source Validation. Downstream NOTE: This field remains read-write (RW) for downstream ports, Port: even if the corresponding bit in the ACSCAP register is cleared.
Page 256: Multicast Extended Capability
IDT PCI to PCI Bridge and Proprietary Port Specific Registers ACSECV - ACS Egress Control Vector (0x328) Field Default Type Description Field Name Value 15:0 See Description Egress Control Vector. This field is used to configure ACS peer- to-peer egress control. The value in this field is only valid when ACS peer-to-peer egress control is enabled in the ACSCTL regis- ter.
Page 257 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCCAP - Multicast Capability (0x334) Field Default Type Description Field Name Value MAXGROUP 0x1F Max Multicast Groups. This field indicates the default number of multicast groups supported by the switch partition, which is 32. The maximum number of supported groups is 64, and this field may be re-programmed during initial switch configuration (e.g., via EEPROM) to 0x3F to enable support for 64 multicast groups.
Page 258 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCBARH- Multicast Base Address High (0x33C) Field Default Type Description Field Name Value 31:0 MCBARH Multicast BAR High. This field specifies the upper 32-bits (i.e., bits 32 through 63) of the multicast BAR. The behavior is undefined if bits in this field corresponding to address bits that contain the multicast group number or those less than the multicast index position (i.e., INDEXPOS) are non-zero.
Page 259 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCBLKALLL- Multicast Block All Low (0x348) Field Default Type Description Field Name Value 31:0 MCBLKALL Multicast Block All. Each bit in this field corresponds to one of the lower 32 multicast groups (e.g., bit 0 corresponds to multicast group 0, bit 1 corresponds to multicast group 1, and so on).
Page 260 IDT PCI to PCI Bridge and Proprietary Port Specific Registers MCBLKUTH - Multicast Block Untranslated High (0x354) Field Default Type Description Field Name Value 31:0 MCBLKUT Multicast Block Untranslated. Each bit in this field corresponds to one of the upper 32 multicast groups (e.g., bit 0 corresponds to multicast group 32, bit 1 corresponds to multicast group 33, and so on).
Page 261: Proprietary Port Specific Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Proprietary Port Specific Registers Port Control and Status Registers PCIESCTLIV - PCI Express Slot Control Initial Value (0x420) Field Default Type Description Field Name Value ABPE Attention Button Pressed Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corre-...
Page 262 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value CCIE Command Complete Interrupt Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corre- sponding slot or hot-plug capability is enabled.
Page 263: Internal Error Control And Status Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. DLLLASCE Data Link Layer Link Active State Change Enable. SWSticky This field contains the initial value of the corresponding field in the PCI Express Slot Control (PCIESCTL) register when the corre- sponding slot or hot-plug capability is enabled.
Page 264 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value IFBDATDBE RW1C IFB Data Double Bit Error. This bit is set when a double bit ECC SWSticky error is detected in the IFB data RAM. IFBCTLSBE RW1C IFB Control Single Bit Error.
Page 265 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value EFBPTLPTO EFB Posted TLP Time-Out. When this bit is set, the correspond- SWSticky ing error bit in the IERRORSTS register is masked from reporting an internal error to the AER Capability Structure.
Page 266 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value EFBCTLDBE EFB Control Double Bit Error. When this bit is set, the corre- SWSticky sponding error bit in the IERRORSTS register is masked from reporting an internal error to the AER Capability Structure.
Page 267 IDT PCI to PCI Bridge and Proprietary Port Specific Registers IERRORSEV - Internal Error Reporting Severity (0x48C) Field Default Type Description Field Name Value IFBPTLPTO IFB Posted TLP Time-Out. This bit controls how an unmasked SWSticky error of the corresponding type is reported. When this bit is set and the corresponding status bit is set and unmasked, then the error is reported as an uncorrectable internal error.
Page 268 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value IFBDATDBE IFB Data Double Bit Error. This bit controls how an unmasked SWSticky error of the corresponding type is reported. When this bit is set and the corresponding status bit is set and unmasked, then the error is reported as an uncorrectable internal error.
Page 269 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Unreliable Link Detected. This bit controls how an unmasked SWSticky error of the corresponding type is reported. When this bit is set and the corresponding status bit is set and unmasked, then the error is reported as an uncorrectable internal error.
Page 270 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value IFBDATDBE IFB Data Double Bit Error. Writing a one to this bit sets the corre- sponding bit in the IERRORSTS register. This bit always returns a value of zero when read.
Page 271: Physical Layer Control And Status Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Physical Layer Control and Status Registers SERDESCFG - SerDes Configuration (0x510) Field Default Type Description Field Name Value RCVD_OVRD Receiver Detect Override. Each bit in this register corresponds to SWSticky a SerDes lane.
Page 272 IDT PCI to PCI Bridge and Proprietary Port Specific Registers LANESTS1 - Lane Status 1 (0x520) Field Default Type Description Field Name Value RW1C Receiver Underflow Detected. Each bit in this field corresponds Sticky to a SerDes lane associated with the port. A bit is set when the corresponding link receiver is unable to com- pensate for clock variance between link partners and has inserted one or more zero bytes into the stream.
Page 273 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value 13:12 Reserved Reserved field. ILSCC Downstream: Initial Link Speed Change Control. This field determines whether a port automatically initiates a speed change to Gen2 speed, if Gen2 speed is permissible, after initial entry to L0 from Detect.
Page 274: Power Management Control And Status Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Power Management Control and Status Registers L1ASPMRTC - L1 ASPM Rejection Timer Control (0x710) Field Default Type Description Field Name Value 13:0 MTL1ER 0x947 Minimum Time between L1 Entry Requests. This field indicates SWSticky the minimum time (in 250Mhz cycles) that the port waits between detecting consecutive L1 ASPM entry requests.
Page 275 IDT PCI to PCI Bridge and Proprietary Port Specific Registers Field Default Type Description Field Name Value Reserved Reserved field. 15:6 CNSTLIMIT 0x10 Constant Limit. This field is used to control the algorithm used to SWSticky compute the completion size estimate for non-posted read requests when request metering is enabled.
Page 276: Global Address Space Access Registers
IDT PCI to PCI Bridge and Proprietary Port Specific Registers Global Address Space Access Registers GASAADDR - Global Address Space Access Address (0xFF8) Field Default Type Description Field Name Value Reserved Reserved field. 18:2 GADDR Global Address. This field selects the system address of the reg- ister to be accessed via the GASADATA register.
Page 277: Switch Configuration And Status Registers
Chapter 17 Switch Configuration and Status Registers ® Switch Control and Status Registers SWCTL - Switch Control (0x0000) Field Default Type Description Field Name Value Reserved Reserved field. RSTHALT HWINIT Reset Halt. When this bit is set, all of the switch logic except the SWSticky SMBus interface remains in a quasi-reset state.
Page 278 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 10:9 DDDNC Disable Downstream Device Number Checking. This field con- SWSticky trols the extent to which device numbers are checked by down- stream ports. This field is present for backwards compatibility with earlier IDT switches that implement a proprietary version of ARI forwarding.
Page 279 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value P01MERGEN HWINIT Port 0 and 1 Merge. Boot configuration vector value sampled dur- ing a switch fundamental reset. P23MERGEN HWINIT Port 2 and 3 Merge. Boot configuration vector value sampled dur- ing a switch fundamental reset.
Page 280: Internal Switch Timer
IDT Switch Configuration and Status Registers Internal Switch Timer USSBRDELAY - Upstream Secondary Bus Reset Delay (0x008C) Field Default Type Description Field Name Value 15:0 USSBR Side Effect Delay.This field specifies the delay in microseconds SWSticky from when a configuration request that initiates a secondary bus reset is processed to the start of the secondary bus reset action.
Page 281 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value RW1C Switch Partition State Change Completed. This bit is set when a SWSticky switch partition state change is completed. Reserved RW1C This field is unused in the switch and serves as a place holder for SWSticky the future.
Page 282 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value Reserved Reserved field. 17:16 Operating Mode Change Action. This field specifies the action SWSticky taken when a modification is made to the operating mode of a port. 0x0 - (noaction) No action - preserve state 0x1 - (reset) Port reset - behavior associated with fundamental reset...
Page 283: Protection
IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value MODE HWINIT Port Mode. This field contains the current operating mode of the switch port. Due to the time it takes for a partition state change to complete, this value may be different than that in the MODE field in the SWPORTxCTL register.
Page 284: Serdes Control And Status Registers
IDT Switch Configuration and Status Registers SerDes Control and Status Registers Refer to Chapter 8, SerDes, for a details on programming SerDes controls. Note that in order to program the SerDes controls for a given port, it is necessary to identify which SerDes block is associated with the port. Refer to section SerDes Numbering and Port Association on page 8-1 for details.
Page 285 IDT Switch Configuration and Status Registers S[7:0]TXLCTL0 - SerDes x Transmitter Lane Control 0 Field Default Type Description Field Name Value CDC_FS3DBG1 Transmit Driver Coarse De-Emphasis Control for Full Swing SWSticky mode in Gen1. This field provides coarse level control of the trans- mit driver de-emphasis level in full-swing mode and Gen1 data rate (i.e., 2.5 Gbps).
Page 286 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 11:10 TX_EQ_3DBG2 Transmit Equalization for Full Swing Mode with -3.5dB in SWSticky Gen2. This field controls the transmit equalization in Gen2 data rate when the SDE field in the associated port’s PCIELCTL2 regis- ter is set to -3.5 dB de-emphasis.
Page 287 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 25:23 TX_FSLEW_G2 Transmit Driver Fine Slew Adjustment in Gen2. This field allows SWSticky fine adjustment of the output driver’s slew rate at Gen2 data-rate, for the lane(s) selected by the Lane Select (LANESEL[3:0]) field in the SerDes Control (S[x]CTL) register.
Page 288 IDT Switch Configuration and Status Registers S[7:0]TXLCTL1 - SerDes x Transmitter Lane Control 1 Field Default Type Description Field Name Value TDVL_FS3DBG1 0x11 Transmit Driver Voltage Level for Full-Swing Mode with -3.5dB SWSticky De-emphasis in Gen1. This field controls the SerDes transmit driver voltage level in full- swing mode and Gen 1 data rate (i.e., 2.5 GT/s).
Page 289 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 15:13 FDC_FS3DBG2 Transmit Driver Fine De-emphasis Control for Full Swing SWSticky Mode with -3.5dB in Gen 2. This field provides fine level control of the transmit driver de- emphasis level in Gen 2 mode, when the SDE field in the associ- ated port’s PCIELCTL2 register is set to -3.5dB de-emphasis.
Page 290 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 23:21 FDC_FS6DBG2 Transmit Driver Fine De-emphasis Control for Full Swing SWSticky Mode with -6.0dB in Gen 2. This field provides fine level control of the transmit driver de- emphasis level in Gen 2 mode, when the SDE field in the associ- ated port’s PCIELCTL2 register is set to -6.0dB de-emphasis.
Page 291: General Purpose I/O Registers
IDT Switch Configuration and Status Registers S[7:0]RXEQLCTL - SerDes x Receiver Equalization Lane Control Field Default Type Description Field Name Value RXEQZ Receiver Equalization Zero. Amplifies the high-frequency gain of SWSticky the equalizer. A value of 0x0 results in the smallest amount of high frequency gain.
Page 292 IDT Switch Configuration and Status Registers GPIOFUNC1 - General Purpose I/O Function 1 (0x0A94) Field Default Type Description Field Name Value 21:0 GPIOFUNC GPIO Function. Each bit in this field controls the corresponding SWSticky GPIO pin. When set, the corresponding GPIO pin operates as the selected alternate function.
Page 293 IDT Switch Configuration and Status Registers GPIOCFG0 - General Purpose I/O Configuration 0 (0x0AA8) Field Default Type Description Field Name Value 31:0 GPIOCFG GPIO Configuration. Each bit in this field controls the correspond- SWSticky ing GPIO pin. When a bit is configured as a general purpose I/O pin and the corresponding bit in this field is set, then the pin is con- figured as a GPIO output.
Page 294: Hot-Plug And Smbus Interface Registers
IDT Switch Configuration and Status Registers GPIOD1 - General Purpose I/O Data 1 (0x0AB4) Field Default Type Description Field Name Value 21:0 GPIOD HWINIT GPIO Data. Each bit in this field controls the corresponding GPIO SWSticky pin. Reading this field returns the current value of each GPIO pin regardless of GPIO pin mode (i.e., alternate function or GPIO pin).
Page 295 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value 24:20 HP4GPIOPRT 0x1F Hot-Plug GPIO 4 Port Map. This field selects the PES32H8G2 SWSticky port whose hot-plug signals are mapped to GPIO alternate function HP4 signals. A value of all ones (i.e., 0x1F) indicates that no port is mapped to HPx GPIO alternate function signals.
Page 296 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value MRLPWROFF MRL Automatic Power Off. When this bit is set and the Manual SWSticky Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register, then power to the slot is automat- ically turned off when the MRL sensor indicates that the MRL is open.
Page 297 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value BLANK RW1C Blank Serial EEPROM. When the switch is configured to operate in a mode in which serial EEPROM initialization occurs during a Switch Fundamental Reset, this bit is set when a blank serial EEPROM is detected.
Page 298 IDT Switch Configuration and Status Registers SMBUSCTL - SMBus Control (0x0ACC) Field Default Type Description Field Name Value 15:0 MSMBCP HWINIT Master SMBus Clock Prescalar. This field contains a clock pres- SWSticky calar value used during master SMBus transactions. The prescalar clock period is equal to 32 ns multiplied by the value in this field.
Page 299 IDT Switch Configuration and Status Registers EEPROMINTF - Serial EEPROM Interface (0x0AD0) Field Default Type Description Field Name Value 15:0 ADDR EEPROM Address. This field contains the byte address in the Serial EEPROM to be read or written. 23:16 DATA EEPROM Data.
Page 300 IDT Switch Configuration and Status Registers IOEXPADDR1 - SMBus I/O Expander Address 1 (0x0ADC) Field Default Type Description Field Name Value Reserved Reserved field. IOE4ADDR I/O Expander 4 Address. This field contains the SMBus address SWSticky assigned to I/O expander 4 on the master SMBus interface. Reserved Reserved field.
Page 301 IDT Switch Configuration and Status Registers Field Default Type Description Field Name Value Reserved Reserved field. 15:9 IOE13ADDR I/O Expander 13 Address. This field contains the SMBus address SWSticky assigned to I/O expander 13 on the master SMBus interface. 31:16 Reserved Reserved field.
Page 302 IDT Switch Configuration and Status Registers Notes PES32H8G2 User Manual 17 - 26 April 5, 2013...
Page 303: Jtag Boundary Scan
Chapter 18 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the switch: AC-coupled and DC-coupled (also called AC and DC pins).
Page 304: Table 18.1 Jtag Pin Descriptions
IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. JTAG_TMS Input JTAG Mode Select.
Page 305: Boundary Scan Chain
IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Interface PE00RN[3:0] PE00RP[3:0] PE00TN[3:0] PE00TP[3:0] PE01RN[3:0] PE01RP[3:0] PE01TN[3:0] PE01TP[3:0] PE02RN[3:0] PE02RP[3:0] PE02TN[3:0] PE02TP[3:0] PE03RN[3:0] PE03RP[3:0] PE03TN[3:0] PE03TP[3:0] PE04RN[3:0] PE04RP[3:0] PE04TN[3:0] PE04TP[3:0] PE05RN[3:0] PE05RP[3:0] PE05TN[3:0] PE05TP[3:0] PE06RN[3:0] PE06RP[3:0]...
Page 306: Test Data Register (Dr)
IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell General Purpose I/O GPIO[8:0] System Pins CLKMODE[2:0] GCLKFSEL P01MERGEN P23MERGEN P45MERGEN P67MERGEN PERSTN RSTHALT SWMODE[3:0] — EJTAG / JTAG JTAG_TCK — JTAG_TDI — JTAG_TDO — JTAG_TMS — JTAG_TRST_N — SerDes Reference Resis- REFRES00 —...
Page 307: Figure 18.3 Diagram Of Observe-Only Input Cell
IDT JTAG Boundary Scan Notes Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values are not driven out onto the system pins. All of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incor- rect data to be latched into a cell.
Page 308: Instruction Register (Ir)
IDT JTAG Boundary Scan Notes shift_dr EXTEST Output enable from core Data from previous cell OEN to pad clock_dr update_dr I/O pin shift_dr Data from core EXTEST To next cell Figure 18.5 Diagram of Bidirectional Cell The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains only one register.
Page 309: Extest
IDT JTAG Boundary Scan Notes Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec- 000000 tions. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed.
Page 310: Clamp
IDT JTAG Boundary Scan Notes Therefore, instead of having to shift many times to get a value through the device, the user only needs to shift one time to get the value from JTAG_TDI to JTAG_TDO. When the TAP controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
Page 311: Extest_Pulse
IDT JTAG Boundary Scan Notes If the Run-Test/Idle state is not entered, the output of the AC pins is not distinguishable from the output of the DC EXTEST instruction. EXTEST_PULSE EXTEST_PULSE is an instruction listed in IEEE 1149.6 JTAG specification and is used to test AC pins during boundary scan by shifting data from TDI to TDO within the Shift-DR-TAP controller State.
Page 312 IDT JTAG Boundary Scan Notes PES32H8G2 User Manual 18 - 10 April 5, 2013...
Page 313: Corporate Headquarters
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