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Renesas IDT 89HPES16T4 User Manual
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Renesas IDT 89HPES16T4 User Manual

Renesas IDT 89HPES16T4 User Manual

Pci express switch
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®
IDT
89HPES16T4
™
PCI Express® Switch
User Manual
April 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.

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Summary of Contents for Renesas IDT 89HPES16T4

  • Page 1 ® 89HPES16T4 ™ PCI Express® Switch User Manual April 2008 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2008 Integrated Device Technology, Inc.
  • Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
  • Page 3 About This Manual ® Introduction Notes This user manual includes hardware and software information on the 89HPES16T4, a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan- dard. Finding Additional Information Information not included in this manual such as mechanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com) as well as through your local IDT sales representative.
  • Page 4 Notes To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter- preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
  • Page 5 Notes The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte zero as the least significant (rightmost) byte of a word. See Figure 2. bit 31 bit 0 Address of Bytes within Words: Big Endian...
  • Page 6 Notes Type Abbreviation Description Read and Write Clear RW1C Software can read and write to registers/bits with this attribute. However, writing a value of zero to a bit with this attribute has no effect. A RW1C bit can only be set to a value of 1 by a hardware event.
  • Page 7 Table of Contents ® About This Manual Notes Introduction ............................ 1 Content Summary .......................... 1 Signal Nomenclature ........................1 Numeric Representations ......................2 Data Units ............................2 Register Terminology ........................3 Use of Hypertext ..........................4 Reference Documents ........................4 Revision History ..........................
  • Page 8 IDT Table of Contents Notes Peer-to-Peer Transactions......................3-8 Bus Locking ............................ 3-9 Port Interrupts ..........................3-10 Legacy Interrupt Emulation......................3-11 Standard PCIe Error Detection and Handling................3-11 Physical Layer Errors ......................3-11 Data Link Layer Errors......................3-12 Transaction Layer Errors ...................... 3-12 Routing Errors ........................
  • Page 9 IDT Table of Contents Hot-Plug and Hot-Swap Notes Introduction ............................. 8-1 Hot-Plug I/O Expander ......................8-4 Hot-Plug Interrupts and Wake-up ................... 8-4 Legacy System Hot-Plug Support ..................8-4 Hot-Swap ............................8-6 Configuration Registers Introduction ............................. 9-1 Upstream Port (Port 0) ......................9-3 Downstream Ports (Ports 1, 6, 7) ...................
  • Page 10 IDT Table of Contents Notes PES16T4 User Manual April 10, 2008...
  • Page 11 List of Tables ® Table 1.1 PES16T4 Device ID......................1-5 Notes Table 1.2 PES16T4 Revision ID ......................1-5 Table 1.3 PCI Express Interface Pins....................1-6 Table 1.4 SMBus Interface Pins ......................1-7 Table 1.5 General Purpose I/O Pins....................1-7 Table 1.6 System Pins.........................1-8 Table 1.7 Test Pins..........................
  • Page 12 IDT List of Tables Notes PES16T4 User Manual April 10, 2008...
  • Page 13 List of Figures ® Figure 1.1 PES16T4 Architectural Block Diagram ................1-3 Notes Figure 1.2 I/O Expansion Application ....................1-3 Figure 1.3 PES16T4 Logic Diagram ....................1-4 Figure 1.4 All Ports Unmerged Configuration ...................1-12 Figure 1.5 Two Ports Merged Configuration ..................1-12 Figure 1.6 All Ports Merged Configuration ..................1-13 Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread...
  • Page 14 IDT List of Figures Notes Figure 10.2 State Diagram of PES16T4’s TAP Controller ..............10-2 Figure 10.3 Diagram of Observe-only Input Cell .................10-4 Figure 10.4 Diagram of Output Cell ....................10-5 Figure 10.5 Diagram of Bidirectional Cell ....................10-5 Figure 10.6 Device ID Register Format ....................10-7 PES16T4 User Manual viii April 10, 2008...
  • Page 15 Register List ® AERCAP - AER Capabilities (0x100) ..................... 9-37 Notes AERCEM - AER Correctable Error Mask (0x114) .................. 9-41 AERCES - AER Correctable Error Status (0x110) ................. 9-41 AERCTL - AER Control (0x118)......................9-42 AERHL1DW - AER Header Log 1st Doubleword (0x11C) ..............9-42 AERHL2DW - AER Header Log 2nd Doubleword (0x120)..............
  • Page 16 IDT Register List Notes PCICMD - PCI Command Register (0x004)....................9-12 PCIECAP - PCI Express Capability (0x040) ...................9-21 PCIEDCAP - PCI Express Device Capabilities (0x044) ................9-22 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) ..............9-32 PCIEDCTL - PCI Express Device Control (0x048)..................9-23 PCIEDCTL2 - PCI Express Device Control 2 (0x068)................9-32 PCIEDSTS - PCI Express Device Status (0x04A) ..................9-24 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) ................9-32...
  • Page 17 IDT Register List Notes SWPESTS - Switch Parity Error Status (0x744) ..................9-62 SWSTS - Switch Status (0x400) ......................9-50 SWTOCNT - Switch Time-Out Count (0x75C) ..................9-65 SWTOCTL - Switch Time-Out Control (0x750) ..................9-63 SWTORCTL - Switch Time-Out Reporting Control (0x758) ..............9-64 SWTOSTS - Switch Time-Out Status (0x754) ..................9-63 SWTOTSCTL - Switch Time-Out Time-Stamp Control (0x760) ..............9-65 SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8) .............9-61...
  • Page 18 IDT Register List Notes PES16T4 User Manual April 10, 2008...
  • Page 19 Chapter 1 PES16T4 Device Overview ® Introduction Notes The 89HPES16T4 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES16T4 is a 16-lane, 4-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking.
  • Page 20 IDT PES16T4 Device Overview Notes Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O –...
  • Page 21 IDT PES16T4 Device Overview System Diagrams Switch Core D-Bus Bus Decoupler D-Bus U-Bus U-Bus Arbiter Queue Arbiter GPIO Controller Master SMBus Interface Slave Input Input Input Input SMBus Frame Frame Frame Frame Interface Buffer Buffer Buffer Buffer Reset Controller TDM Demux TDM Demux Application Layer Application Layer...
  • Page 22 IDT PES16T4 Device Overview Logic Diagram PEREFCLKP PE0TP[0] Reference PCI Express PEREFCLKN PE0TN[0] Clocks Switch REFCLKM SerDes Output PE0TP[3] PE0RP[0] Port 0 PE0TN[3] PCI Express PE0RN[0] Switch PE1TP[0] PCI Express SerDes Input PE1TN[0] PE0RP[3] Switch Port 0 PE0RN[3] SerDes Output PE1TP[3] Port 1 PE1RP[0]...
  • Page 23 IDT PES16T4 Device Overview System Identification Notes Vendor ID All vendor ID fields in the device are hardwired to 0x111D which corresponds to Integrated Device Tech- nology, Inc. Device ID The PES16T4 device ID is shown in Table 1.1. PCIe Device Device ID 0x802C Table 1.1 PES16T4 Device ID...
  • Page 24 IDT PES16T4 Device Overview Pin Description Notes The following tables list the functions of the pins provided on the PES16T4. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N”...
  • Page 25 IDT PES16T4 Device Overview Notes Signal Type Name/Description MSMBADDR[4:1] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed.
  • Page 26 IDT PES16T4 Device Overview Notes Signal Type Name/Description GPIO[8] General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 GPIO[11] General Purpose I/O.
  • Page 27 IDT PES16T4 Device Overview Notes Signal Type Name/Description JTAG_TCK JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI JTAG Data Input.
  • Page 28 IDT PES16T4 Device Overview Pin Characteristics Notes Note: Some input pads of the PES16T4 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
  • Page 29 IDT PES16T4 Device Overview Notes Internal Function Pin Name Type Buffer Notes Type Resistor EJTAG / JTAG JTAG_TCK LVTTL pull-up JTAG_TDI pull-up JTAG_TDO JTAG_TMS pull-up JTAG_TRST_N pull-up External pull- down Table 1.9 Pin Characteristics (Part 2 of 2) Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. Schmitt Trigger Input (STI).
  • Page 30 IDT PES16T4 Device Overview Notes Port 0 Dev. 0 PES16T4 PCI to PCI Bridge Virtual PCI Bus Dev. 1 Dev. 2 Dev. 3 PCI to PCI PCI to PCI PCI to PCI Bridge Bridge Bridge Port 1 Port 6 Port 7 Figure 1.4 All Ports Unmerged Configuration Port 0 Dev.
  • Page 31 IDT PES16T4 Device Overview Notes Port 0 Dev. 0 PES16T4 PCI to PCI Bridge Virtual PCI Bus Dev. 2 PCI to PCI Bridge Port 7 Figure 1.6 All Ports Merged Configuration PES16T4 User Manual 1 - 13 April 10, 2008...
  • Page 32 IDT PES16T4 Device Overview Notes PES16T4 User Manual 1 - 14 April 10, 2008...
  • Page 33 Chapter 2 Clocking, Reset, and Initialization ® Introduction Notes The PES16T4 has two differential reference clock inputs that are used internally to generate all of the clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both reference clock input pairs be driven from a common clock source.
  • Page 34 IDT Clocking, Reset, and Initialization Clock Operation Notes Port 1 PES16T4 Port 6 Port 0 Root Complex Port 7 CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable Spread Spectrum Clock) Port 1 PES16T4...
  • Page 35 IDT Clocking, Reset, and Initialization Clock Operation Notes Port 1 PES16T4 Port 6 Port 0 Root Complex Port 7 CCLKUS CCLKDS REFCLK0 REFCLK1 Clock Generator Clock Generator Clock Generator Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock) Initialization A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES16T4 during a fundamental reset when PERSTN is negated.
  • Page 36 IDT Clocking, Reset, and Initialization Clock Operation Notes Signal Type Name/Description P67MERGEN Port 6 and 7 Merge. When this pin is asserted, port 7 is merged with port 6 to form a single x8 port. The SerDes lanes associated with port 3 become lanes 4 through 7 of port 6.
  • Page 37 IDT Clocking, Reset, and Initialization Clock Operation Notes The following reset sequence is executed. 1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN). 2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.2. If PERSTN was not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental reset is the result of a one being written to the FRST bit in the SWCTL register).
  • Page 38 IDT Clocking, Reset, and Initialization Clock Operation Notes The PES16T4 provides a reset output signal for each downstream port implemented as a GPIO alter- nate function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port resets are tri-stated.
  • Page 39 IDT Clocking, Reset, and Initialization Clock Operation Notes 6. If the selected switch operating mode is one that requires initialization from the serial EEPROM and the Disable Hot Reset Serial EEPROM Initialization (DHRSTSEI) bit is not set in the Switch Control (SWCTL) register, then the contents of the serial EEPROM are read and the appropriate PES16T4 registers are updated.
  • Page 40 IDT Clocking, Reset, and Initialization Clock Operation Notes When a downstream secondary bus reset occurs, the following sequence is executed. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are transmitted 2. All TLPs received from corresponding downstream port and queued in the PES16T4 are discarded. 3.
  • Page 41 IDT Clocking, Reset, and Initialization Clock Operation Power Good Controlled Reset Output Notes As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on the power good state of the slot’s power supply.
  • Page 42 IDT Clocking, Reset, and Initialization Clock Operation Notes PES16T4 User Manual 2 - 10 April 10, 2008...
  • Page 43 Chapter 3 Theory of Operation ® Introduction Notes An architectural block diagram of the PES16T4 is shown in Figure 1.1 in Chapter 1. The PES16T4 contains four x4 ports labeled ports 0, 1, 6, and 7. Port 0 is always the upstream port and the remaining three are always downstream ports.
  • Page 44 IDT Theory of Operation Notes Associated with each port in the data link layer is a shared output and replay buffer. That is, the buffer is partitioned into two sections with a section dedicated to each x4 port in bifurcated mode. This buffer contains TLPs that have been transmitted but have not been acknowledged by the link partner.
  • Page 45 IDT Theory of Operation Notes continuous TLP manner (i.e. the data is not TDMed) regardless of the operating mode of the stack. If the stack is in bifurcated mode, data is read from the output and replay buffer by the data link layer in a TDM manner.
  • Page 46 IDT Theory of Operation Notes Bus Decoupler Queue U-Bus D-Bus Upstream Downstream Downstream Downstream Port Port Port Port Figure 3.1 Simplified Switch Core U-Bus and D-Bus Datapath In addition to transactions between the upstream port and downstream port and peer-to-peer transac- tions, the switch core is responsible for routing of transactions which are destined to the same stack on which the TLP was received.
  • Page 47 IDT Theory of Operation Notes The only Gathered and Routed to Root message supported is a PME_TO_Ack message received on a downstream port. Transaction Reordering Each IFB has a free-running timer which is clocked at the 250 MHz core clock frequency. When a TLP is enters the IFB, a time-stamp of when the TLP arrived is stored in a descriptor associated with the TLP.
  • Page 48 IDT Theory of Operation Scheduling and Port Arbitration Notes Associated with each port is an Egress Selection Picker (ESP) and associated with each bus (i.e., U- Bus or D-Bus) is a bus arbiter. The function of the ESP is to provide a candidate vector with one bit per port indicating which ports have a TLP in their input frame buffer or insertion buffer that can be transferred to that output port.
  • Page 49 IDT Theory of Operation Notes There are two 8-bit fields in these registers associated with each transfer class. The first field is a transfer count field that indicates how many transfers of that class can occur in an arbitration period. The second field is a current transfer count field that indicates how many transfers from that class are remaining in the current arbitration period.
  • Page 50 IDT Theory of Operation Notes There are two D-Bus transfer classes. They are upstream-to-downstream and bus decoupler queue transfers. Upstream-to-downstream transfers proceed from the upstream port, through the D-Bus multi- plexor, and to a downstream port. The requests for this transfer comes from the upstream portion of the candidate vector produced by the downstream ports.
  • Page 51 IDT Theory of Operation Bus Locking Notes The PES16T4 supports locked transactions, allowing legacy software to run without modification on PCIe. Only one locked transaction sequence may be in progress at a time. – A locked transaction sequence is requested by the root by issuing a Memory Read Request - Locked (MRdLk) transaction.
  • Page 52 IDT Theory of Operation Notes When an Unlock message is received on the upstream port, the switch is unlocked. This causes the Unlock message to be forwarded to the locked downstream port and the unblocking of transactions destined to the upstream and previously locked downstream port. The unlock message obeys PCI ordering rules, meaning that all queued posted requests from the upstream port are completed prior to the switch becoming unlocked.
  • Page 53 IDT Theory of Operation Legacy Interrupt Emulation Notes The PES16T4 supports legacy PCI INTx emulation. Rather than use sideband INTx signals, PCIe defines two messages that indicate the assertion and negation of an interrupt signal. An Assert_INTx message is used to signal the assertion of an interrupt signal and an Deassert_INTx message is used to signal its negation.
  • Page 54 IDT Theory of Operation Notes PCIe Base 1.1 Error Condition Specification Action Taken Section Invalid symbol or running disparity error 4.2.1.3 Correctable error processing detected. Any TLP or DLLP framing rule violation. 4.2.2.1 Correctable error processing 8b/10b decode error 4.2.4.4 Correctable error processing Any violation of the link initialization or training 4.2.4...
  • Page 55 IDT Theory of Operation Notes PCIe Base 1.1 Error Condition Specification Action Taken Section Poisoned TLP received 2.7.2.2 For the non-advisory cases: non- fatal error processing. Advisory cases: correctable error processing. TLP header logged in AER. ECRC check failure 2.7.1 For the non-advisory cases: non- fatal error processing.
  • Page 56 IDT Theory of Operation Notes Table 3.12 lists the error checks performed by the ingress transaction layer for malformed TLPs. These TLP error checks are performed when a TLP is received by the switch (i.e., by the stack associated with the port on which the switch receives the TLP).
  • Page 57 IDT Theory of Operation Notes TLP Type Error Check TLP traffic class (TC) must be mapped to VC0. TC to VC mapping is controlled by the TC/VC Map (TCVC- MAP) field in the egress port’s VC Resource 0 Con- trol (VCR0CTL) register Table 3.13 Egress Malformed TLP Error Checks Routing Errors This section lists TLP routing errors that are detected by the PES16T4.
  • Page 58 IDT Theory of Operation Notes ID Routed Messages – Messages that attempt to route back onto the link on which they were received. – Messages that do not have a valid route through the PES16T4. – Messages that target a downstream port device number that does not exist. –...
  • Page 59 IDT Theory of Operation Notes Since deep sub-micron devices are known to be susceptible to single-event-upsets, a mechanism is desired that detects errors that occur within a PCI express switch. The PES16T4 parity protects all TLPs in the switch, thus enabling corruption that may occur inside of the device to be detected and reported even in systems that do not implement ECRC.
  • Page 60 IDT Theory of Operation Notes TLP Processing Control (TLPPCTL) register, the value of the relaxed ordering attribute is set to the value dictated by the Relaxed Ordering Modification (ROM) field in the TLPPCTL register. This transformation is only performed on TLPs in which the relaxed ordering attribute is applicable. The relaxed ordering attribute is applicable to all TLPs except: configuration requests, I/O requests, memory requests that are Message Signaled Interrupts (MSIs), and Message requests (except where specifically permitted).
  • Page 61 Chapter 4 Link Operation ® Introduction Notes The PES16T4 contains four x4 ports which may be merged in pairs to form x8 ports. The default link width of each port is x4 and the SerDes lanes are statically assigned to a port. Polarity Inversion Each port of the PES16T4 supports automatic polarity inversion as required by the PCIe specification.
  • Page 62 IDT Link Operation Notes PExRP[0] lane 0 PExRP[0] lane 3 PExRP[1] lane 1 PExRP[1] lane 2 PES16T4 PES16T4 PExRP[2] lane 2 PExRP[2] lane 1 PExRP[3] lane 3 PExRP[3] lane 0 (a) x4 Port without lane reversal (b) x4 Port with lane reversal PExRP[0] lane 0 PExRP[0]...
  • Page 63 IDT Link Operation Notes PExRP[0] lane 1 PExRP[0] lane 0 PExRP[1] lane 0 PExRP[1] lane 1 PExRP[2] PExRP[2] PExRP[3] PExRP[3] PES16T4 PES16T4 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x2 Port with lane reversal (a) x2 Port without lane reversal PExRP[0] PExRP[0] lane 0...
  • Page 64 IDT Link Operation Notes PExRP[0] lane 3 PExRP[0] lane 0 PExRP[1] lane 2 PExRP[1] lane 1 PExRP[2] lane 1 PExRP[2] lane 2 PExRP[3] lane 0 PExRP[3] lane 3 PES16T4 PES16T4 PExRP[4] PExRP[4] PExRP[5] PExRP[5] PExRP[6] PExRP[6] PExRP[7] PExRP[7] (b) x4 Port with lane reversal (a) x4 Port without lane reversal PExRP[0] PExRP[0]...
  • Page 65 IDT Link Operation Notes PExRP[0] lane 7 PExRP[0] lane 0 PExRP[1] lane 6 PExRP[1] lane 1 PExRP[2] lane 5 PExRP[2] lane 2 PExRP[3] lane 4 PExRP[3] lane 3 PES16T4 PES16T4 PExRP[4] lane 3 PExRP[4] lane 4 PExRP[5] lane 2 PExRP[5] lane 5 PExRP[6] lane 1...
  • Page 66 IDT Link Operation Link Down Notes When a link goes down, all TLPs received by that port and queued in the switch are discarded and all TLPs received by other ports and destined to the port whose link is down are treated as Unsupported Requests (UR).
  • Page 67 IDT Link Operation Notes Fundamental Reset Hot Reset Etc. Link Down L2/L3 Ready Figure 4.6 PES16T4 ASPM Link Sate Transitions Active State Power Management The operation of Active State Power Management (ASPM) is independent of power management. Once enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi- tions are initiated by hardware without software involvement.
  • Page 68 IDT Link Operation Link Status Notes Associated with each port is a Port Link Up (PxLINKUP) status output and a Port Activity (PxACTIVE) status output. These outputs are provided on I/O Expander 4. See section I/O Expanders on page 6-6 for the operation of the I/O expander and the mapping of these status outputs to I/O expander pins.
  • Page 69 Chapter 5 General Purpose I/O ® Introduction Notes The PES16T4 has 11 General Purpose I/O (GPIO) pins that may be individually configured as: general purpose inputs, general purpose outputs, or alternate functions. GPIO pins are controlled by the General Purpose I/O Function (GPIOFUNC), General Purpose I/O Configuration (GPIOCFG), and General Purpose I/O Data (GPIOD) registers in the upstream port’s PCI configuration space.
  • Page 70 IDT General Purpose I/O GPIO Pin Configured as an Input Notes When configured as an input in the GPIOCFG register and as a GPIO function in the GPIOFUNC register, the GPIO pin is sampled and registered in the GPIOD register. The value of the input pin can be determined at any time by reading the GPIOD register.
  • Page 71 IDT General Purpose I/O Notes PES16T4 User Manual 5 - 3 April 10, 2008...
  • Page 72 IDT General Purpose I/O PES16T4 User Manual 5 - 4 April 10, 2008...
  • Page 73 Chapter 6 SMBus Interfaces ® Introduction Notes The PES16T4 contains two SMBus interfaces. The slave SMBus interface provides full access to all software visible registers in the PES16T4, allowing every register in the device to be read or written by an external SMBus master.
  • Page 74 IDT SMBus Interfaces Notes In the split configuration, the master and slave SMBuses operate as two independent buses. Thus, multi-master arbitration is not required. Master SMBus Interface The master SMBus interface is used during a fundamental reset to load configuration values from an optional serial EEPROM.
  • Page 75 IDT SMBus Interfaces Notes Serial EEPROM Size 24C32 4 KB 24C64 8 KB 24C128 16 KB 24C256 32 KB 24C512 64 KB Table 6.2 PES16T4 Compatible Serial EEPROMs During serial EEPROM initialization, the master SMBus interface begins reading bytes starting at serial EEPROM address zero.
  • Page 76 IDT SMBus Interfaces Notes Byte 0 CSR_SYSADDR[7:0] TYPE Byte 1 CSR_SYSADDR[13:8] Byte 2 NUMDW[7:0] Byte 3 NUMDW[15:8] Byte 4 DATA0[7:0] Byte 5 DATA0[15:8] Byte 6 DATA0[23:16] Byte 7 DATA0[31:24] Byte 4n+4 DATAn[7:0] Byte 4n+ 5 DATAn[15:8] Byte 4n+6 DATAn[23:16] Byte 4n+7 DATAn[31:24] Figure 6.3 Sequential Double Word Initialization Sequence Format The final type of configuration block is the configuration done sequence which is used to signify the end...
  • Page 77 IDT SMBus Interfaces Notes An 8-bit counter is cleared and the 8-bit sum is computed over the bytes read from the serial EEPROM, including the entire contents of the configuration done sequence . The correct result should always be 0xFF (i.e., all ones). Checksum checking may be disabled by setting the Ignore Checksum Errors (ICHECKSUM) bit in the SMBus Control (SMBUSCTL) register.
  • Page 78 IDT SMBus Interfaces Notes Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results. SMBus errors may occur when accessing the serial EEPROM. If an error occurs, it is reported in the SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial EEPROM access.
  • Page 79 IDT SMBus Interfaces Notes The following I/O expander configuration sequence is issued by the PES16T4 to I/O expander three (i.e., the one that contains hot-plug signals). – Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through I/O-0.7) to I/O expander register 2.
  • Page 80 IDT SMBus Interfaces Notes An example of an event that may lead to a state conflict is a hot reset. When a hot reset occurs, one or more hot-plug register control fields may be re-initialized to its default value. When this occurs, the internal PES16T4 state of the hot-plug signals is in conflict with the state of I/O expander hot-plug output signals.
  • Page 81 IDT SMBus Interfaces Notes System Design Recommendations 1. I/O expander addresses and default output values may be configured during serial EEPROM initial- ization. If I/O expander addresses are configured via the serial EEPROM, then the PES16T4 will initialize the I/O expanders when normal device operation begins following the completion of the fundamental reset sequence.
  • Page 82 IDT SMBus Interfaces Notes I/O Expander 3 SMBus I/O Expander Type Signal Description 0 (I/O-0.0) P7APN Port 7 attention push button input 1 (I/O-0.1) P7PDN Port 7 presence detect input 2 (I/O-0.2) P7PFN Port 7 power fault input 3 (I/O-0.3) P7MRLN Port 7 manually-operated retention latch (MRL) input...
  • Page 83 IDT SMBus Interfaces Notes SMBus I/O Expander Type Signal Description 9 (I/O-1.1) P1ACTIVE Port 1 activity output 10 (I/O-1.2) Reserved Tie high or low 11 (I/O-1.3) Reserved Tie high or low 12 (I/O-1.4) Reserved Tie high or low 13 (I/O-1.5) Reserved Tie high or low 14 (I/O-1.6)
  • Page 84 IDT SMBus Interfaces Notes SIZE FUNCTION START Figure 6.5 Slave SMBus Command Code Format Name Description End of transaction indicator. Setting both START and END signifies a single transaction sequence. 0 - Current transaction is not the last read or write sequence.
  • Page 85 IDT SMBus Interfaces Notes Byte Field Name Description Position CCODE Command Code. Slave Command Code field described in Table 6.9. BYTCNT Byte Count. The byte count field is only transmitted for block type SMBus transactions. SMBus word and byte accesses do not contain this field. The byte count field indi- cates the number of bytes following the byte count field when performing a write or setting up for a read.
  • Page 86 IDT SMBus Interfaces Notes Bit Field Name Type Description Read/Write CSR Operation. This field encodes the CSR operation to be performed. 0 - CSR write 1 - CSR read Reserved. Must be zero RERR Read-Only Read Error. This bit is set if the last CSR read SMBus and Clear transaction was not claimed by a device.
  • Page 87 IDT SMBus Interfaces Notes LAERR NAERR OTHERERR Figure 6.7 Serial EEPROM Read or Write CMD Field Format Bit Field Name Type Description Serial EEPROM Operation. This field encodes the serial EEPROM operation to be performed. 0 - Serial EEPROM write 1 - Serial EEPROM read Use Specified Address.
  • Page 88 IDT SMBus Interfaces Notes PES16T4 Slave CCODE BYTCNT=3 CMD=read ADDRL ADDRU SMBus Address START,END PES16T4 Slave CCODE (PES16T4 not ready with data) SMBus Address START,END PES16T4 Slave CCODE PES16T4 Slave BYTCNT=7 CMD (status) ADDRL SMBus Address START,END SMBus Address ADDRU DATALL DATALM DATAUM...
  • Page 89 IDT SMBus Interfaces Notes PES16T4 Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled PES16T4 Slave CCODE BYTCNT=5 CMD=write EEADDR ADDRL SMBus Address START,END ADDRU DATA Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled PES16T4 User Manual...
  • Page 90 IDT SMBus Interfaces Notes PES16T4 Slave CCODE CMD=read ADDRL SMBus Address START, Word PES16T4 Slave CCODE ADDRU SMBus Address END, Byte CCODE PES16T4 Slave (PES16T4 not ready with data) START,Word SMBus Address PES16T4 Slave CCODE SMBus Address START,Word PES16T4 Slave CMD (status) ADDRL SMBus Address...
  • Page 91 Chapter 7 Power Management ® Introduction Notes Located in configuration space of each PCI-PCI bridge in the PES16T4 is a power management capa- bility structure. The power management capability structure associated with a PCI-PCI bridge of a down- stream port only affects that port. Entering the D3 state allows the link associated with the bridge to enter the L1 state.
  • Page 92 IDT Power Management Notes From State To State Description D0 Uninitialized Power-on fundamental reset. D0 Uninitialized D0 Active PCI-PCI bridge configured by software D0 Active The Power Management State (PMSTATE) field in the PCI Power Management Control and Status (PMCSR) register is written with the value that corresponds to the state.
  • Page 93 IDT Power Management Notes The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any power management state. When the PES16T4 receives a PME_Turn_Off message, it broadcasts the PME_Turn_Off message on all active downstream ports. The PES16T4 transmits a PME_TO_Ack message on its upstream port and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its active downstream ports.
  • Page 94 IDT Power Management Notes PES16T4 User Manual 7 - 4 April 10, 2008...
  • Page 95 Chapter 8 Hot-Plug and Hot-Swap ® Introduction Notes As illustrated in Figures 8.1 through 8.3, a PCIe switch may be used in one of three hot-plug configura- tions. Figure 8.1 illustrates the use of the PES16T4 in an application in which two downstream ports are connected to slots into which add-in cards may be hot-plugged.
  • Page 96 IDT Hot-Plug and Hot-Swap Notes Upstream Link Add-In Card Port 0 PES16T4 Port 6 Port 7 PCI Express PCI Express Device Device Figure 8.2 Hot-Plug with Switch on Add-In Card Application Upstream Link Carrier Card Port 0 PES16T4 Master SMBus Port 6 Port 7 SMBus I/O...
  • Page 97 IDT Hot-Plug and Hot-Swap Notes The remainder of this section discusses the use of the PES16T4 in an application involving an add-in card hot-plugged into a downstream slot. Associated with each downstream port in the PES16T4 is a hot- plug controller. The hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capa- bilities (PCIESCAP) register associated with that port during configuration (e.g., via serial EEPROM).
  • Page 98 IDT Hot-Plug and Hot-Swap Notes The default value of hot-plug registers following a hot or fundamental reset may be configured via serial EEPROM initialization. Since hot-plug I/O expander initialization occurs after serial EEPROM initialization, the Command Completed (CC) bit is not set in the PCI Express Slot Status (PCIESSTS) register as a result of serial EEPROM initialization.
  • Page 99 IDT Hot-Plug and Hot-Swap Notes The hot-plug event signalling mechanism is the only thing that is affected when a port is configured to use general purpose events instead of the PCIe defined hot-plug signalling mechanisms (i.e., INTx, MSI and PME). Thus, the PCIe defined capability, status and mask bits defined in the PCIe slot capabilities, status and control registers operate as normal and all other hot-plug functionality associated with the port remains unchanged.
  • Page 100 IDT Hot-Plug and Hot-Swap Hot-Swap Notes The PES16T4 is hot-swap capable and meets the following requirements: – All of the I/Os are tri-stated on reset (i.e., SerDes, GPIO, SMBuses, etc.). – All I/O cells function predictably from early power. This means that the device is able to tolerate a non-monotonic ramp-up as well as a rapid ramp-up of the DC power.
  • Page 101 Chapter 9 Configuration Registers ® Introduction Notes Each software-visible register in the PES16T4 is contained in the PCI configuration space of one of the ports. Thus, there are no registers in the PES16T4 that cannot be accessed by the root. Each software- visible register in the PES16T4 has a system address.
  • Page 102 IDT Configuration Registers Notes 0x000 Configuration Space (64 DWords) 0x100 Advanced Error Reporting 0x000 Enhanced Capability 0x180 Device Serial Number Type 1 Enhanced Capability Configuration Header 0x200 PCIe Virtual Channel Enhanced Capability 0x280 0x040 PCI Express Capability Structure Power Budgeting Enhanced Capability Switch Control 0x400...
  • Page 103 IDT Configuration Registers Upstream Port (Port 0) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 104 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on page 9-19 0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-20 0x03E Word...
  • Page 105 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x11C Dword P0_AERHL1DW AERHL1DW - AER Header Log 1st Doubleword (0x11C) on page 9-42 0x120 Dword P0_AERHL2DW AERHL2DW - AER Header Log 2nd Doubleword (0x120) on page 9-42 0x124 Dword P0_AERHL3DW AERHL3DW - AER Header Log 3rd Doubleword (0x124) on page...
  • Page 106 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x30C Dword P0_PWRBDV3 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x310 Dword P0_PWRBDV4 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x314 Dword P0_PWRBDV5 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on...
  • Page 107 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x748 Dword P0_SWPERCTL SWPERCTL - Switch Parity Error Reporting Control (0x748) on page 9-62 0x74C Dword P0_SWPECNT SWPECNT - Switch Parity Error Count (0x74C) on page 9-63 0x750 Dword P0_SWTOCTL SWTOCTL - Switch Time-Out Control (0x750) on page 9-63 0x754...
  • Page 108 IDT Configuration Registers Downstream Ports (Ports 1, 6, 7) Notes Note: In pdf format, clicking on a register name in the Register Definition column creates a jump to the appropriate register. To return to the starting place in this table, click on the same register name (in blue) in the register section.
  • Page 109 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x038 DWord Px_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038) on page 9-19 0x03C Byte Px_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19 0x03D Byte Px_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-20 0x03E Word...
  • Page 110 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x0F0 Dword Px_SSIDSSVIDCAP SSIDSSVIDCAP - Subsystem ID and Subsystem Vendor ID Capability (0x0F0) on page 9-36 0x0F4 Dword Px_SSIDSSVID SSIDSSVID - Subsystem ID and Subsystem Vendor ID (0x0F4) on page 9-36 0x0F8 Word Px_ECFGADDR...
  • Page 111 IDT Configuration Registers Notes Cfg. Register Size Register Definition Offset Mnemonic 0x288 Dword Px_PWRBD PWRBD - Power Budgeting Data (0x288) on page 9-49 0x28C Dword Px_PWRBPBC PWRBPBC - Power Budgeting Power Budget Capability (0x28C) on page 9-50 0x300 Dword Px_PWRBDV0 PWRBDV[0..7] - Power Budgeting Data Value [0..7] (0x300) on page 9-50 0x304...
  • Page 112 IDT Configuration Registers Register Definitions Notes Type 1 Configuration Header Registers VID - Vendor Identification Register (0x000) Field Default Type Description Field Name Value 15:0 0x111D Vendor Identification. This field contains the 16-bit vendor ID value assigned to IDT. See section Vendor ID on page 1-5. DID - Device Identification Register (0x002) Field Default...
  • Page 113 IDT Configuration Registers Notes Field Default Type Description Field Name Value ADSTEP Address Data Stepping. Not applicable. SERRE SERR Enable. Non-fatal and fatal errors detected by the bridge are reported to the Root Complex when this bit is set or the bits in the PCI Express Device Control register are set (see PCIEDCTL - PCI Express Device Control (0x048) on page 9-23).
  • Page 114 IDT Configuration Registers Notes Field Default Type Description Field Name Value RTAS Received Target Abort. Not applicable. RMAS Received Master Abort. Not applicable. RW1C Signalled System Error. This bit is set when the bridge sends a ERR_FATAL or ERR_NONFATAL message and the SERR Enable (SERRE) bit is set in the PCICMD regis- ter.
  • Page 115 IDT Configuration Registers Notes HDR - Header Type Register (0x00E) Field Default Type Description Field Name Value 0x01 Header Type. This value indicates a type 1 header with a single function bridge layout. BIST - Built-in Self Test Register (0x00F) Field Default Type...
  • Page 116 IDT Configuration Registers Notes SUBUSN - Subordinate Bus Number Register (0x01A) Field Default Type Description Field Name Value SUBUSN Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge.
  • Page 117 IDT Configuration Registers Notes Field Default Type Description Field Name Value MDPED RW1C Master Data Parity Error. This bit is controlled by the Parity Error Response Enable bit in the Bridge Control register. If the Parity Response Enable bit is cleared, then this bit is never set.
  • Page 118 IDT Configuration Registers Notes PMBASE - Prefetchable Memory Base Register (0x024) Field Default Type Description Field Name Value PMCAP Prefetchable Memory Capability. Indicates if the bridge supports 32-bit or 64-bit prefetchable memory addressing. 0x0 -(prefmem32) 32-bit prefetchable memory addressing. 0x1 - (prefmem64) 64-bit prefetchable memory addressing. Reserved Reserved field.
  • Page 119 IDT Configuration Registers Notes IOBASEU - I/O Base Upper Register (0x030) Field Default Type Description Field Name Value 15:0 IOBASEU 0xFFFF I/O Address Base Upper. This field specifies the upper 16- bits of IOBASE. When the IOCAP field in the IOBASE register is cleared, this field becomes read-only with a value of zero.
  • Page 120 IDT Configuration Registers Notes INTRPIN - Interrupt PIN Register (0x03D) Field Default Type Description Field Name Value INTRPIN Interrupt Pin. Interrupt pin or legacy interrupt messages are not used by the bridge by default. However, they can be used for hot-plug by the downstream ports. This field should only be configured with values of 0x0 through 0x4.
  • Page 121 IDT Configuration Registers Notes Field Default Type Description Field Name Value VGA16EN VGA 16-bit Enable. This bit only has an effect when the VGAEN bit is set in this register. This read/write bit enables system configuration software to select between 10-bit and 16-bit I/O space decoding for VGA transactions.
  • Page 122 IDT Configuration Registers Notes PCIEDCAP - PCI Express Device Capabilities (0x044) Field Default Type Description Field Name Value MPAYLOAD Maximum Payload Size Supported. This field indicates the maximum payload size that the device can support for TLPs. The default value corresponds to 2048 bytes. Phantom Functions Supported.
  • Page 123 IDT Configuration Registers Notes Field Default Type Description Field Name Value 27:26 CSPLS Captured Slot Power Limit Scale. This field specifies the scale used for the Slot Power Limit Value. The value of this field is set by a Set_Slot_Power_Limit Message and is only applicable for the upstream port.
  • Page 124 IDT Configuration Registers Notes Field Default Type Description Field Name Value 14:12 MRRS Maximum Read Request Size. The bridge does not gener- ate transactions larger than 128 bytes and passes transac- tions through the bridge with the size unmodified. Therefore, this field has no functional effect on the behavior of the bridge.
  • Page 125 IDT Configuration Registers Notes Field Default Type Description Field Name Value MAXLNK- HWINIT Maximum Link Width. This field indicates the maximum WDTH link width of the given PCI Express link. This field may be overridden to allow the link width to be forced to a smaller value.
  • Page 126 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 PORTNUM Port 0: 0x0 Port Number. This field indicates the PCI express port num- Port 1: 0x1 ber for the corresponding link. Resvd: 0x2 Resvd: 0x3 Resvd: 0x4 Resvd: 0x5 Port 6: 0x6 Port 7: 0x7...
  • Page 127 IDT Configuration Registers Notes Field Default Type Description Field Name Value HWAWDTH- Hardware Autonomous Width Disable. When set, this bit disables hardware from changing the link width for reasons other than attempting to correct for unreliable link operation by reducing the link width. This field is read-only zero in PCIe 1.1 mode.
  • Page 128 IDT Configuration Registers Notes Field Default Type Description Field Name Value LBWSTS RW1C Link Bandwidth Management Status. This bit is set to indicate that either of the following have occurred without the link transitioning through the DL_Down state. A link retraining initiated by setting the LRET bit in the PCIELCTL register has completed.
  • Page 129 IDT Configuration Registers Notes Field Default Type Description Field Name Value Hot-Plug Capable. This bit is set if the slot corresponding to the port is capable of supporting hot-plug operations. This bit is read-only and has a value of zero when the SLOT bit in the PCIECAP register is cleared.
  • Page 130 IDT Configuration Registers Notes Field Default Type Description Field Name Value MRLSCE MRL Sensor Change Enable. This bit when set enables the generation of a Hot-Plug interrupt or wake-up event on a MRL sensor change event. This bit is read-only and has a value of zero when the corre- sponding capability is not enabled in the PCIESCAP regis- ter.
  • Page 131 IDT Configuration Registers Notes Field Default Type Description Field Name Value Electromechanical Interlock Control. This field always returns a value of zero when read. If an electromechanical interlock is implemented, a write of a one to this field causes the state of the interlock to toggle and a write of a zero has no effect.
  • Page 132 IDT Configuration Registers Notes PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) Field Default Type Description Field Name Value 31:0 Reserved Reserved field. PCIEDCTL2 - PCI Express Device Control 2 (0x068) Field Default Type Description Field Name Value 15:0 Reserved Reserved field.
  • Page 133 IDT Configuration Registers Notes Field Default Type Description Field Name Value 15:6 Reserved Reserved field. PCIELSTS2 - PCI Express Link Status 2 (0x072) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PCIESCAP2 - PCI Express Slot Capabilities 2 (0x074) Field Default Type...
  • Page 134 IDT Configuration Registers Notes Field Default Type Description Field Name Value DEVSP Device Specific Initialization. The value of zero indicates that no device specific initialization is required. 24:22 AUXI AUX Current. not used D1 Support. This field indicates that the PES16T4 does not support D1.
  • Page 135 IDT Configuration Registers Notes Field Default Type Description Field Name Value 21:16 Reserved Reserved field. B2B3 B2/B3 Support. Does not apply to PCI Express. BPCCE Bus Power/Clock Control Enable. Does not apply to PCI Express. 31:24 DATA Data. This optional field is not implemented. Message Signaled Interrupt Capability Structure MSICAP - Message Signaled Interrupt Capability and Control (0x0D0) Field...
  • Page 136 IDT Configuration Registers Notes MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8) Field Default Type Description Field Name Value 31:0 UADDR Upper Message Address. This field specifies the upper portion of the DWORD address of the MSI memory write transaction. If the contents of this field are non-zero, then 64-bit address is used in the MSI memory write transaction.
  • Page 137 IDT Configuration Registers Notes Extended Configuration Space Access Registers ECFGADDR - Extended Configuration Space Access Address (0x0F8) Field Default Type Description Field Name Value Reserved Reserved field. Register Number. This field selects the configuration regis- ter number as defined by Section 7.2.2 of the PCI Express Base Specification, Rev.
  • Page 138 IDT Configuration Registers Notes AERUES - AER Uncorrectable Error Status (0x104) Field Default Type Description Field Name Value UDEF RW1C Undefined. This bit is no longer used in this version of the Sticky specification. Reserved Reserved field. DLPERR RW1C Data Link Protocol Error Status. This bit is set when a Sticky data link layer protocol error is detected.
  • Page 139 IDT Configuration Registers Notes Field Default Type Description Field Name Value SDOENERR Surprise Down Error Status. When this bit is set, the cor- Sticky responding bit in the AERUES register is masked. When a bit is masked in the AERUES register, the corresponding event is not logged in the advanced capability structure and an error is not reported to the root complex.
  • Page 140 IDT Configuration Registers Notes AERUESV - AER Uncorrectable Error Severity (0x10C) Field Default Type Description Field Name Value UDEF Undefined. This bit is no longer used in this version of the Sticky specification. Reserved Reserved field. DLPERR Data Link Protocol Error Severity. If the corresponding Sticky event is not masked in the AERUEM register, then when the event occurs, this bit controls the severity of the reported...
  • Page 141 IDT Configuration Registers Notes Field Default Type Description Field Name Value ECRC ECRC Severity. If the corresponding event is not masked in Sticky the AERUEM register, then when the event occurs, this bit controls the severity of the reported error. If this bit is set, the event is reported as a fatal error.
  • Page 142 IDT Configuration Registers Notes Field Default Type Description Field Name Value BADDLLP Bad DLLP Mask. When this bit is set, the corresponding bit Sticky in the AERCES register is masked. When a bit is masked in the AERCES register, the corresponding event is not reported to the root complex.
  • Page 143 IDT Configuration Registers Notes AERHL3DW - AER Header Log 3rd Doubleword (0x124) Field Default Type Description Field Name Value 31:0 Header Log. This field contains the 3rd doubleword of the Sticky TLP header that resulted in the first reported uncorrectable error.
  • Page 144 IDT Configuration Registers PCI Express Virtual Channel Capability Notes PCIEVCECAP - PCI Express VC Enhanced Capability Header (0x200) Field Default Type Description Field Name Value 15:0 CAPID Capability ID. The value of 0x2. indicates a virtual channel capability structure. 19:16 CAPVER Capability Version.
  • Page 145 IDT Configuration Registers Notes Field Default Type Description Field Name Value 31:24 VCATBLOFF VC Arbitration Table Offset. This field contains the offset of the VC arbitration table from the base address of the Vir- tual Channel Capability structure in double quad words (16 bytes).
  • Page 146 IDT Configuration Registers Notes Field Default Type Description Field Name Value Advanced Packet Switching. Not supported. RJST Reject Snoop Transactions. No supported for switch ports. 22:16 MAXTS Maximum Time Slots. Since this VC does not support time- based WRR, this field is not valid. Reserved Reserved field.
  • Page 147 IDT Configuration Registers Notes VCR0STS - VC Resource 0 Status (0x218) Field Default Type Description Field Name Value 15:0 Reserved Reserved field. PATS Port Arbitration Table Status. This bit indicates the coher- ency status of the port arbitration table associated with the VC resource and is valid only when the port arbitration table is used by the selected arbitration algorithm.
  • Page 148 IDT Configuration Registers Notes Field Default Type Description Field Name Value PHASE9 Phase 9. This field contains the port ID for the correspond- ing port arbitration period. 11:8 PHASE10 Phase 10. This field contains the port ID for the correspond- ing port arbitration period.
  • Page 149 IDT Configuration Registers Notes Field Default Type Description Field Name Value 19:16 PHASE28 Phase 28. This field contains the port ID for the correspond- ing port arbitration period. 23:20 PHASE29 Phase 29. This field contains the port ID for the correspond- ing port arbitration period.
  • Page 150 IDT Configuration Registers Notes PWRBPBC - Power Budgeting Power Budget Capability (0x28C) Field Default Type Description Field Name Value System Allocated. When this bit is set, it indicates that the power budget for the device is included within the system power budget and that reported power data for this device should be ignored.
  • Page 151 IDT Configuration Registers Notes Field Default Type Description Field Name Value 10:11 PEMODE HWINIT PCI Express Base Specification Mode. This field selects the PCIe base specification operating mode for the PES16T4. 0x0 - reserved 0x1 - (pebase1p1) PCIe 1.1 base specification compliant mode.
  • Page 152 IDT Configuration Registers Notes Field Default Type Description Field Name Value REGUN- Register Unlock. When this bit is set, the contents of regis- LOCK Sticky ters and fields of type Read and Write when Unlocked (RWL) are modified when written to. When this bit is cleared, all registers and fields denoted as RWL become read-only.
  • Page 153 IDT Configuration Registers Notes Field Default Type Description Field Name Value IPXPFN Invert Polarity of PxPFN. When this bit is set, the polarity Sticky of the PxPFN input is inverted in all ports. IPXMRLN Invert Polarity of PxMRLN. When this bit is set, the polarity Sticky of the PxMRLN input is inverted in all ports.
  • Page 154 IDT Configuration Registers Notes GPR - General Purpose Register (0x40C) Field Default Type Description Field Name Value 31:0 DATA Data. General purpose register available for software use. GPIOFUNC - General Purpose I/O Control Function (0x418) Field Default Type Description Field Name Value 15:0...
  • Page 155 IDT Configuration Registers Notes SMBUSSTS - SMBus Status (0x424) Field Default Type Description Field Name Value Reserved Reserved field. SSMBADDR HWINIT Slave SMBus Address. This field contains the SMBus address assigned to the slave SMBus interface. Reserved Reserved field. 15:9 MSMBADDR HWINIT Master SMBus Address.
  • Page 156 IDT Configuration Registers Notes Field Default Type Description Field Name Value MSMBIOM Master SMBus Ignore Other Masters. When this bit is set, Sticky the master SMBus proceeds with transactions regardless of whether it won or lost arbitration. ICHECKSUM Ignore Checksum Errors. When this bit is set, serial Sticky EEPROM initialization checksum errors are ignored (i.e., the checksum always passes).
  • Page 157 IDT Configuration Registers Notes Field Default Type Description Field Name Value BUSY EEPROM Busy. This bit is set when a serial EEPROM read or write operation is in progress. 0x0 -(idle) serial EEPROM interface idle 0x1 -(busy) serial EEPROM interface operation in progress DONE RW1C EEPROM Operation Completed.
  • Page 158 IDT Configuration Registers Notes Field Default Type Description Field Name Value DONE RW1C I/O Expander Operation Done. This bit is set when any of the following conditions occurs: - RELOADIOEX bit in this register is written, the corre- sponding I/O expander is selected by the SELECT field in this register, and the corresponding IO expander SMBus transaction completes.
  • Page 159 IDT Configuration Registers Notes GPECTL - General Purpose Event Control (0x450) Field Default Type Description Field Name Value IGPE Invert General Purpose Event Enable Signal Polarity. Sticky When this bit is set, the polarity of all General Purpose Event (GPEN) signals is inverted. 0x0 - (normal) GPEN signals are active low 0x1 -...
  • Page 160 IDT Configuration Registers Notes Field Default Type Description Field Name Value P7GPES Port 7 General Purpose Event Status. When this bit is set, the corresponding port is signalling a general purpose event by asserting the GPEN signal. This bit is never set if the cor- responding general purpose event is not enabled in the GPECTL register.
  • Page 161 IDT Configuration Registers Notes DARBTC - D-Bus Arbiter Transfer Count (0x460) Field Default Type Description Field Name Value U2DTC 0x01 Upstream to Downstream Transfer Count. This field con- Sticky tains the upstream to downstream transfer count. The U2DCTC field in the DARBCTC register is set to this value after each arbitration period.
  • Page 162 IDT Configuration Registers Internal Switch Error Control and Status Registers Notes SWPECTL - Switch Parity Error Control (0x740) Field Default Type Description Field Name Value DEEPC Disable End-to-End Parity Checking. When this bit is set, Sticky end-to-end parity is not checked by the port and errors are never generated.
  • Page 163 IDT Configuration Registers Notes SWPECNT - Switch Parity Error Count (0x74C) Field Default Type Description Field Name Value EEPEC End-to-End Parity Error Count. This field is incremented Sticky each time an end-to-end parity error is detected at the port until it saturates at its maximum count value (i.e., it does not roll over from 0xFF to 0x00).
  • Page 164 IDT Configuration Registers Notes SWTORCTL - Switch Time-Out Reporting Control (0x758) Field Default Type Description Field Name Value PTLPTO Posted TLP Time-Out Reporting. This field controls the Sticky manner in which posted TLP time-outs are reported. A time- out is reported as specified in this field whenever the corre- sponding bit in the Switch Time-Out Status (SWTOSTS) register transitions from a zero to a one.
  • Page 165 IDT Configuration Registers Notes SWTOCNT - Switch Time-Out Count (0x75C) Field Default Type Description Field Name Value PTLPTOC Posted TLP Time-Out Count. This field is incremented Sticky each time a TLP is discarded from the port’s IFB posted queue because of a time-out. This counter saturates at its maximum value.
  • Page 166 IDT Configuration Registers Notes PES16T4 User Manual 9 - 66 April 10, 2008...
  • Page 167 Chapter 10 JTAG Boundary Scan ® Introduction Notes The JTAG Boundary Scan interface provides a way to test the interconnections between integrated circuit pins after they have been assembled onto a circuit board. There are two pin types present in the PES16T4: AC-coupled and DC-coupled (also called AC and DC pins).
  • Page 168 IDT JTAG Boundary Scan Notes Pin Name Type Description JTAG_TRST_N Input JTAG RESET (active low) Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG_TCK Input JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. JTAG_TMS Input JTAG Mode Select.
  • Page 169 IDT JTAG Boundary Scan Boundary Scan Chain Notes Function Pin Name Type Boundary Cell PCI Express Inter- PE0RN[3:0] face PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE1RN[3:0] PE1RP[3:0] PE1TN[3:0] PE1TP[3:0] PE6RN[3:0] PE6RP[3:0] PE6TN[3:0] PE6TP[3:0] PE7RN[3:0] PE7RP[3:0] PE7TN[3:0] PE7TP[3:0] PEREFCLKN[2:1] — PEREFCLKP[2:1] — REFCLKM SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT...
  • Page 170 IDT JTAG Boundary Scan Notes Function Pin Name Type Boundary Cell EJTAG / JTAG JTAG_TCK — JTAG_TDI — JTAG_TDO — JTAG_TMS — JTAG_TRST_N — Table 10.2 Boundary Scan Chain (Part 2 of 2) I = Input, O = Output O = Observe, C = Control Test Data Register (DR) The Test Data register contains the following: Bypass register...
  • Page 171 IDT JTAG Boundary Scan Notes EXTEST To Next Cell Data from Core To Output Pad Data from Previous Cell shift_dr clock_dr update_dr Figure 10.4 Diagram of Output Cell The output enable cells are also output cells. The simplified logic is shown in Figure 10.5. shift_dr EXTEST Output enable from core...
  • Page 172 IDT JTAG Boundary Scan Instruction Register (IR) Notes The Instruction register allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK. The instruction is then used to select the test to be performed or the test register to be accessed, or both.
  • Page 173 IDT JTAG Boundary Scan SAMPLE/PRELOAD Notes The sample/preload instruction has a dual use. The primary use of this instruction is for preloading the boundary scan register prior to enabling the EXTEST instruction. Failure to preload will result in unknown random data being driven onto the output pins when EXTEST is selected. The secondary function of SAMPLE/PRELOAD is for sampling the system state at a particular moment.
  • Page 174 IDT JTAG Boundary Scan VALIDATE Notes The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std. 1149.1 specification. RESERVED Reserved instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions.
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