Renesas 9SQ440 User Manual
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Renesas 9SQ440 User Manual

Renesas 9SQ440 User Manual

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1.
Introduction
The 9SQ440 Evaluation Board (EVB) is designed to help users evaluate the 9SQ440 PCIe Gen5 clock synthesizer. When the EVB is
connected via USB to the user's computer running the Renesas 9SQ440
control frequencies with best-in-class performance. The 9SQ440 offers features of 7 pairs of 100MHz differential LP-HCSL outputs, 9 MXCLK
pairs of differential outputs multiplexable between 100MHz/25MHz, and 3 pairs of 25MHz outputs. 9 selectable SMBus addresses available.
Board Overview
Figure 1.
9SQ440 EVB – Top View
© 2020 Renesas Electronics Corporation
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Evaluation Board User Manual
Timing Commander™
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EVB 9SQ440
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Software, the 9SQ440 can be configured to
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9SQ440
May 19, 2020

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Summary of Contents for Renesas 9SQ440

  • Page 1 9SQ440 Evaluation Board User Manual Introduction The 9SQ440 Evaluation Board (EVB) is designed to help users evaluate the 9SQ440 PCIe Gen5 clock synthesizer. When the EVB is connected via USB to the user’s computer running the Renesas 9SQ440 Timing Commander™...
  • Page 2 Active low on OE# pins for enabling 100M outputs. OE# Pins Control 1 = disable output; 0 = enable output. DIP switch device is used to setup 9SQ440 device condition. See DIP Switch Figure in below for detail. SMBus Connector SMBus connector for SCLK and SDATA pins.

  • Page 3: Board Power Supply

    Software Connection Renesas Timing Commander Software can control the 9SQ440 on the board. Timing Commander is compatible using the USB connector or an Aardvark adapter as optional. Timing Commander displays a block diagram for entering the configuration and allows control features into the 9QS440 on the board.

  • Page 4: On-Board Crystal

    Platform Time Connectors The 9SQ440 offers 25MHz differential outputs for platform time clock. The 25MHz frequency can be used to communicate to another 9SQ440 device, keeping the 25MHz frequency the same on all devices. This feature ensures the CPU time stamp counter (TSC) is the same on all devices with the frequency lock.
  • Page 5 Output OE Pin Control The 9SQ440 has two methods for enabling and disabling outputs. The evaluation board offers 7 OE# pins for 9SQ440 in hardware control. There are 3 positions using a jumper to apply either 3-2 on OE# pin to pull-low as output enable, or 2-1 on OE# pin to pull-high as output disable.

  • Page 6: Dip Switch Control

    DIP Switch Control The DIP switch (SW1) connects to pins on the 9SQ440 devices. The middle position leaves the pin open. This is the default for each switch. Move to the “+” side to pull the pin high and move to the “-” side to pull the pin low.
  • Page 7 Switch 6 = No Connect.  Switch 7 = PWRGDR: Connects to the PWRGD pin. The main purpose of this switch is to set 9SQ440 operated in a normal operational  mode as this switch to set High or in power-down mode as this switch to set Low. Set as High to be default on evaluation board.

  • Page 8: Board Schematics

    9SQ440 Evaluation Board User Manual Board Schematics Figure 10. 9SQ440 Evaluation Board Schematics – Page 1 Dual layout for crystal or 3.3 V XO with LVCMOS output Socket\IC 85 OHM DIFFERENTIAL J120 VDDXTAL VDD_440_1 VDDXTAL VDD100M1 VDDA25 R105 4 CLOCK PAIRS...
  • Page 9 9SQ440 Evaluation Board User Manual Figure 11. 9SQ440 Evaluation Board Schematics – Page 2 J115 RJ11 Cat3 4pin 25M_[2..0] PURPOSE OF CONNECTORS 25M_[2..0] 25M#[2..0] 3 21 1 23 IS FOR VNA CONNECTORS 25M#[2..0] FOR TESTING RJ11 CABLE. 25M_0 25M#0 25M_1...
  • Page 10 9SQ440 Evaluation Board User Manual Figure 12. 9SQ440 Evaluation Board Schematics – Page 3 FID1 VPHY VPLL 3V3_FTDI 3V3_FTDI 3V3_FTDI Standof f 20mm Fiducial FID2 VDD3P3 Standof f 20mm 10.0K Fiducial 10uF 0.1uF 10uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF near pins 39 , 12 , 24 , 46...
  • Page 11 9SQ440 Evaluation Board User Manual Figure 13. 9SQ440 Evaluation Board Schematics – Page 4 SBI_CLKE SBI_CLK SBI_OUT SBI_OUT SBI_IN SHFT_LDE# SHFT_LD# 0.1uF VDD3P3 J125 SBI_CLK SBI_CLK CLKIN R125 EN_CLK SBI_CLKIR 10.0K VDD3P3 SBI_CLKI SBI_CLKE DNI_R0402 Headerstrip 1X1 RES_SHORT Male J101...
  • Page 12 9SQ440 Evaluation Board User Manual Figure 14. 9SQ440 Evaluation Board Schematics – Page 5 MXCK_[8..0] MXCK_[8..0] MXCK#[8..0] MXCK#[8..0] CK_0 MK_0 MK_5 CK_EXT0 MXCK_0 MXCK_5 CK_EXC0 MXCK#0 MXCK#5 DNI Headerstrip 2X2 DNI Headerstrip 2X2 DNI Headerstrip 2X2 CK#0 MK#0 MK#5 Vertical_c120h60...

  • Page 13: Ordering Information

    9SQ440 Evaluation Board User Manual Ordering Information Orderable Part Number Description 9SQ440-EVB 9SQ440 Evaluation Board. Revision History Revision Date Description of Change Rebranded document.  May 19, 2020 Minor formatting/edits performed.  April 09, 2020 Updated schematic to RevB. February 09, 2020 Initial release.

  • Page 14: Corporate Headquarters

    Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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