NXP Semiconductors i.MX 8M Nano Developer's Manual

NXP Semiconductors
User's Guide
i.MX 8M Nano Hardware Developer's Guide

1. Overview

This document aims to help hardware engineers design
and test the i.MX 8M Nano series processors. It provides
examples on board layout and design checklists to ensure
first-pass success, and solutions to avoid board bring-up
problems.
Engineers should understand board layouts and board
hardware terminology.
This guide is released with relevant device-specific
hardware documentation, such as datasheets, reference
manuals, and application notes. All these documents are
available on www.nxp.com/imx8mnanoevk.

1.1. Device supported

This document supports the i.MX 8M Nano (14 x 14 mm
package).
© 2019 NXP B.V.
Document Number: IMX8MNHDG
Contents
1. Overview ............................................................................ 1
1.1. Device supported ..................................................... 1
1.2. Essential references ................................................. 2
1.3. Supplementary references ....................................... 2
1.4. Related documentation ............................................ 3
1.5. Conventions ............................................................ 3
1.6. Acronyms and abbreviations ................................... 4
2. i.MX 8M Nano design checklist ......................................... 5
2.1. Design checklist table.............................................. 5
2.2. JTAG signal termination ....................................... 13
2.3. Signal termination for Boundary-scan ................... 13
3. i.MX 8M Nano layout/routing recommendations ............. 13
3.1. Introduction ........................................................... 13
3.2. Basic design recommendations ............................. 13
3.3. Stack-up and manufacturing recommendations ..... 14
3.4. DDR design recommendations .............................. 17
3.5. Trace impedance recommendations ...................... 27
3.6. Power connectivity/routing ................................... 28
3.7. USB connectivity .................................................. 30
3.8. Unused input/output terminations ......................... 31
4. Avoiding board bring-up problems .................................. 31
4.1. Introduction ........................................................... 31
4.2. Avoiding power pitfalls -Current .......................... 32
4.3. Avoiding power pitfalls -Voltage .......................... 32
4.4. Checking for clock pitfalls .................................... 33
4.5. Avoiding reset pitfalls ........................................... 33
4.6. Sample board bring-up checklist ........................... 33
5. Using BSDL for Board-level Testing ............................... 35
5.1. BSDL overview ..................................................... 35
5.2. How BSDL functions ............................................ 35
5.3. Downloading the BSDL file .................................. 35
5.4. Pin coverage of BSDL........................................... 36
5.5. Boundary scan operation ....................................... 36
5.6. I/O pin power considerations ................................ 38
6. Thermal Considerations ................................................... 38
6.1. Introduction ........................................................... 38
6.2. PCB Dimensions ................................................... 39
6.3. Copper Volume ..................................................... 39
6.4. Thermal Resistance ............................................... 40
6.5. Power Net Design ................................................. 40
6.6. Component Placement........................................... 41
6.7. PCB Surroundings ................................................. 41
6.8. Thermal Simulations ............................................. 42
6.9. Software optimization ........................................... 42
6.10. The Thermal Checklist .......................................... 42
7. Revision history ............................................................... 43
Rev. 0 , 12/2019