NXP Semiconductors i.MX 8M Nano Developer's Manual
NXP Semiconductors i.MX 8M Nano Developer's Manual

NXP Semiconductors i.MX 8M Nano Developer's Manual

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NXP Semiconductors
User's Guide
i.MX 8M Nano Hardware Developer's Guide

1. Overview

This document aims to help hardware engineers design
and test the i.MX 8M Nano series processors. It provides
examples on board layout and design checklists to ensure
first-pass success, and solutions to avoid board bring-up
problems.
Engineers should understand board layouts and board
hardware terminology.
This guide is released with relevant device-specific
hardware documentation, such as datasheets, reference
manuals, and application notes. All these documents are
available on www.nxp.com/imx8mnanoevk.

1.1. Device supported

This document supports the i.MX 8M Nano (14 x 14 mm
package).
© 2019 NXP B.V.
Document Number: IMX8MNHDG
Contents
1.
Overview ............................................................................ 1
1.1.
Device supported ..................................................... 1
1.2.
Essential references ................................................. 2
1.3.
Supplementary references ....................................... 2
1.4.
Related documentation ............................................ 3
1.5.
Conventions ............................................................ 3
1.6.
Acronyms and abbreviations ................................... 4
2.
i.MX 8M Nano design checklist ......................................... 5
2.1.
Design checklist table.............................................. 5
2.2.
JTAG signal termination ....................................... 13
2.3.
3.
3.1.
Introduction ........................................................... 13
3.2.
Basic design recommendations ............................. 13
3.3.
3.4.
DDR design recommendations .............................. 17
3.5.
Trace impedance recommendations ...................... 27
3.6.
Power connectivity/routing ................................... 28
3.7.
USB connectivity .................................................. 30
3.8.
Unused input/output terminations ......................... 31
4.
Avoiding board bring-up problems .................................. 31
4.1.
Introduction ........................................................... 31
4.2.
Avoiding power pitfalls -Current .......................... 32
4.3.
Avoiding power pitfalls -Voltage .......................... 32
4.4.
Checking for clock pitfalls .................................... 33
4.5.
Avoiding reset pitfalls ........................................... 33
4.6.
Sample board bring-up checklist ........................... 33
5.
Using BSDL for Board-level Testing ............................... 35
5.1.
BSDL overview ..................................................... 35
5.2.
How BSDL functions ............................................ 35
5.3.
Downloading the BSDL file .................................. 35
5.4.
Pin coverage of BSDL........................................... 36
5.5.
Boundary scan operation ....................................... 36
5.6.
I/O pin power considerations ................................ 38
6.
Thermal Considerations ................................................... 38
6.1.
Introduction ........................................................... 38
6.2.
PCB Dimensions ................................................... 39
6.3.
Copper Volume ..................................................... 39
6.4.
Thermal Resistance ............................................... 40
6.5.
Power Net Design ................................................. 40
6.6.
Component Placement........................................... 41
6.7.
PCB Surroundings ................................................. 41
6.8.
Thermal Simulations ............................................. 42
6.9.
Software optimization ........................................... 42
6.10.
The Thermal Checklist .......................................... 42
7.
Revision history ............................................................... 43
Rev. 0 , 12/2019

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Summary of Contents for NXP Semiconductors i.MX 8M Nano

  • Page 1: Table Of Contents

    1.1. Device supported 4.3. Avoiding power pitfalls -Voltage ......32 4.4. Checking for clock pitfalls ........33 This document supports the i.MX 8M Nano (14 x 14 mm 4.5. Avoiding reset pitfalls ........... 33 4.6. Sample board bring-up checklist ......33 package).
  • Page 2: Essential References

    Overview 1.2. Essential references This guide is supplementary to the i.MX 8M Nano series chip reference manuals and data sheets. For reflow profile and thermal limits during soldering, see General Soldering Temperature Process Guidelines (document AN3300). These documents are available on www.nxp.com/i.MX8MNANO.
  • Page 3: Related Documentation

    An italicized x indicates an alphanumeric variable. n, m An italicized n indicates a numeric variable. In this guide, notation for all logical, bit-wise, arithmetic, comparison, and assignment operations follow C Language conventions. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 4: Acronyms And Abbreviations

    Power Management Integrated Circuit Power-On Reset Plated Through Hole PCB (i.e. no microvias) RGMII Reduced Gigabit Media Independent Interface (Ethernet) RMII Reduced Media Independent Interface (Ethernet) Read-Only Memory i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 5: I.mx 8M Nano Design Checklist

    8M Nano design checklist 2. i.MX 8M Nano design checklist This document provides a design checklist for the i.MX 8M Nano (14 x 14 mm package) processor. The design checklist tables recommend optimal design and provide explanations to help users understand better.
  • Page 6 POR_B pin of the CPU. When working voltage. This functionality is controlled by POR_B is asserted (low) on the i.MX 8M Nano, the PMIC on EVK. the output PMIC_ON_REQ remains asserted (high). i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 7 4. ESD protection should be implemented at the This will prevent potential damages to board connector pins. Choose a low capacitance device components from ESD. recommended for high-speed interfaces. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 8 This external resistor is used for temperature connected with a 100K Ω, 1% resistor to GND. calibration, the wrong resistor value will result in erroneous behavior for the temperature sensor. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 9 VDD_DRAM_PLL_0P8 NVCC_DRAM VDD_ARM VDD_SNVS_0P8 NVCC_SNVS_1P8 VDD_24M_XTAL_1P8 VDD_DRAM_PLL_1P8 PVCC_1P8 VDD_ARM_PLL_1P8, VDD_ANA0_1P8, VDD_ANA1_1P8, VDD_USB_1P8, VDD_MIPI_1P8 NVCC_SAI3, NVCC_SAI5, NVCC_ECSPI, VDD_USB_3P3 NVCC_JTAG, NVCC_NAND, NVCC_SAI2, NVCC_GPIO1, NVCC_I2C, NVCC_UART, NVCC_SD1, NVCC_CLK NVCC_SD2 NVCC_ENET i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 10 4.7 uF --- CL05A475KP5NRNC • 10 uF --- GRM188R61A106KE69D • 22 uF --- C1608X5R1A226M080AC Table 15. Bulk/Bypass capacitors recommendations (PCA9450B PMIC) Checkbox Supply 1 µF 2.2 µF 22 µF Notes i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 11 DDR interface that runs at 3200 MT/s to ensure stable working. If this is not feasible, just copy the EVK DDR layout design as well as the board stack-up. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 12 Decoupling capacitors are placed as close to IC Tight routing to both power and ground is power pins and GND pins as possible. needed to provide optimum decoupling effectiveness. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 13: Jtag Signal Termination

    Pull up 3. i.MX 8M Nano layout/routing recommendations 3.1. Introduction This chapter describes how to assist design engineers with the layout of an i.MX 8M Nano-based system. 3.2. Basic design recommendations When using the Allegro design tool, the schematic symbol & PCB footprint created by NXP is recommended.
  • Page 14: Stack-Up And Manufacturing Recommendations

    3.3.1. Stack-up recommendation (i.MX 8M Nano) Due to the number of balls on the i.MX 8M Nano processor in the 14 mm x 14 mm package, a minimum 6-layer PCB stack-up is recommended. For the 6-layers on the PCB, a sufficient number of layers need to be dedicated to power on routing to meet the IR drop target of 2% for the i.MX 8M Nano CPU power...
  • Page 15 • Minimum via size: 8mil-diameter hole, 16mil-diameter pad • Minimum via pad to pad spacing: 4mil Figure 1 shows the reference routing of the i.MX 8M Nano, PTH is ok for the fanout, HDI is not needed.. Figure 1. i.MX 8M Nano fanout routing on EVK 3.3.3.
  • Page 16 11.085 mil Power Dielectric 14.170 mil Power Dielectric 11.415 mil Signal Dielectric 4.33 mil Dielectric 2.717 mil Signal 0.5+Plating Total thickness: 62.992(6.299/-6.299) mil 1.6(+0.16/-0.16) MM Material: TU768 TU768 i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 17: Ddr Design Recommendations

    3.4. DDR design recommendations 3.4.1. DDR connection information The i.MX 8M Nano processor can be used with LPDDR4, DDR4 or DDR3L memory. Since these memory types have different I/O signals, there are 38 generically-named functional balls, depending on the type of memory used. See...
  • Page 18 TBD. 3.4.3. i.MX 8M Nano DDR4-2400 design recommendations The following list provides some generic guidelines for implementing an i.MX 8M Nano design using DDR4. 1. It is expected that the layout engineer and design team already has experience and training with DDR designs at speeds of 1.2 GHz / 2400 MT/s.
  • Page 19 This can be realized in Allegro tool by enabling the Z Axis Delay in Setup -> Constraints -> Modes. An example of the delay match calculation has been shown for the i.MX 8M Nano DDR4 EVK board design in...
  • Page 20 Total Net Delay DRAM_A13 193.5 31.9 Routed on top layer, no via U1.W6:U2.T8 225.4 Total Net Delay 188.4 34.4 Vias are L1-> L3->L1 DRAM_BA0 U1.V6:U2.N2 222.8 Total Net Delay i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 21 DRAM_DQ07 194.8 Total Net Delay 106.3 58.6 Routed on top layer, no via DRAM_DMI1 164.9 Total Net Delay DRAM_DQS1_N 115.9 47.2 Routed on top layer, no via i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 22 Addr/Cmd/Ctrl signals are routed on the top layer, layer 3 and bottom layer since they have more tolerance for crosstalk. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 23 8M Nano layout/routing recommendations Figure 3. i.MX 8M Nano DDR4 EVK board DDR4 routing (Top Layer) Figure 4. i.MX 8M Nano DDR4 EVK board DDR4 routing (Layer 3) i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019...
  • Page 24 The simulation architecture includes the DDR controller (i.e., the i.MX 8M Nano processor), the PCB and the DRAM device. The IBIS model for the i.MX 8M Nano processor is available from NXP. The DRAM device IBIS model must be obtained from the memory vendor.
  • Page 25 — DQ Write: Eye width at threshold should be over TBD. — DQ Read: Eye width @641.5 ±70mV should be over TBD. — Cmd/Addr/Ctrl: Eye width at threshold should be over TBD. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 26 Figure 6. Example of simulated eye width 3.4.6. i.MX 8M Nano DDR package delay When performing the required delay matching for LPDDR4/DDR4 routing, the bond wires within the i.MX 8M Nano package need to be accounted for and included in the match calculation. Table 25 lists the propagation/fly time from the die I/O to the package ball.
  • Page 27: Trace Impedance Recommendations

    3.5. Trace impedance recommendations Table 26 is a reference when you are updating or creating constraints in the PCB design tool to set up the impedances/trace widths. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 28: Power Connectivity/Routing

    ONE PMIC part for all kinds of DDR memories. Figure 7 shows a block diagram of the power tree of the NXP i.MX 8M Nano EVK board. It uses a single BD71850MWV PMIC to power ON rails of the processor.
  • Page 29 8M Nano layout/routing recommendations Figure 7. i.MX 8M Nano development platform power distribution block diagram 3.6.2. Power routing/distribution requirements The designing for a good Power Delivery Network (PDN) is complicated. It includes: 1. Choose a good PCB stack-up (adequate Cu thicknesses, and layer assignments/utilization).
  • Page 30: Usb Connectivity

    VDD_SOC&DRAM&GPU NVCC_DRAM 3.7. USB connectivity The i.MX 8M Nano provides one complete USB2.0 interface and the following configurations (or any subset) are supported: • Dedicated host or device using Type-A connector or Type-B connector; • Dual role using Type-C connector.
  • Page 31: Unused Input/Output Terminations

    Avoiding board bring-up problems 3.8. Unused input/output terminations 3.8.1. i.MX 8M Nano unused input/output guidance For the i.MX 8M Nano, the I/Os and power rails of an unused function can be terminated to reduce overall board power. Table 30 lists connectivity examples for unused power supply rails and Table 31 list connectivity examples for unused signal contacts/interfaces.
  • Page 32: Avoiding Power Pitfalls -Current

    • Make two measurements: the first after initial board power-up and the second while running a heavy use-case that stresses the i.MX 8M Nano processor. Ensure that the i.MX 8M Nano power supply meets the DC electrical specifications as listed in the chip- specific data sheet. See Table 32 for a sample voltage report table.
  • Page 33: Checking For Clock Pitfalls

    CLK1_P/N can be an advantage if low jitter or special frequency clock sources are required by modules driven by CLKIN_1/2. See the CCM chapter in the i.MX 8M Nano chip reference manual for details. When checking crystal frequencies, using an active probe is recommended to avoid excessive loading. A passive probe might inhibit the 24 MHz oscillators from starting up.
  • Page 34 Confirm that the voltages match the data sheet’s requirements. Be sure to check voltages as close to the i.MX 8M Nano as possible (like on a bypass capacitor). This reveals any IR drops on the board that could cause issues later.
  • Page 35: Using Bsdl For Board-Level Testing

    The BSDL file for each i.MX processor is stored on the NXP website upon product release. Contact your local sales office or fields applications engineer to check the availability of information prior to product releases. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 36: Pin Coverage Of Bsdl

    TAP controller, the serial instructions and data are received by the test logic at TDI. The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 37 WDOG_B pin can’t be connected to GPIO1_IO02 and should be pulled up to 100Kohm resistor during boundary scan test. Or use the WDOG timer buffer circuit as below. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 38: I/O Pin Power Considerations

    This chapter introduces basic thermal considerations that need to be considered, when designing an i.MX 8M Nano processor-based system. PCBs should be designed with the thermal requirements factored in early as only remedial actions are possible after. Factoring thermal management at the end of the design cycle will increase the cost of the overall design and delay productization.
  • Page 39: Pcb Dimensions

    If the CTE is closely matched to copper, expansion of the PCB material and copper will be more uniform and the plated via holes will be more robust during thermal cycling. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 40: Thermal Resistance

    Using over- sized power transistors is a way to cut total power and subsequent heat dissipation. i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 41: Component Placement

    • Avoid routing circuitry in an area where mounting holes would need to go • Plan to make space for the thermal management solution early in the system design phase and consider the complete board and packaging form factor (enclosure) i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 42: Thermal Simulations

    6.10. The Thermal Checklist NXP recommends using the checklist below as a high-level guide for designing an optimal thermal management solution for your end product: i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 43: Revision History

    Consider lower power memory and other system components, or retarget use case 7. Revision history Table 35. Revision history Revision number Date Substantive changes 12/2019 Initial release i.MX 8M Nano Hardware Developer’s Guide, User's Guide, Rev. 0, 12/2019 NXP Semiconductors...
  • Page 44 Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP How to Reach Us: reserves the right to make changes without further notice to any products herein.

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