NXP Semiconductors Contents Chapter 1 Introduction................... 7 1.1 Introduction..........................7 1.2 References..........................7 Chapter 2 Porting Kernel..................9 2.1 Introduction..........................9 2.1.1 How to build and load Kernel in standalone environment............9 2.1.2 How to build and load Kernel in Yocto Project................11 Chapter 3 Porting U-Boot..................12...
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12.2 Enabling an LVDS channel with LDB..................39 12.3 LDB ports on i.MX 6......................40 12.3.1 LDB on i.MX 6 for input parallel display ports................. 40 12.3.2 LDB on i.MX 6 Output LVDS ports..................41 Chapter 13 Connecting MIPI-DSI Panel.............. 42 13.1 Introduction..........................42...
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NXP Semiconductors Contents 16.1.1 Porting the reference BSP to a custom board (audio codec is the same as in the reference design)............................56 16.1.2 Porting the reference BSP to a custom board (audio codec is different from the reference design)............................56 Chapter 17 Porting HiFi 4..................
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NXP Semiconductors Figures Figure 1. Booting flow on i.MX 6 and i.MX 7..........................21 Figure 2. Booting flow on i.MX 8..............................22 Figure 3. Example of TZASC configuration for i.MX 6UL......................25 Figure 4. i.MX 6 LVDS Display Bridge (LDB) block........................40 Figure 5.
Release Notes describes which SoC is supported in the current release. Some previously released SoCs might be buildable in the current release but not validated if they are at the previous validated level. • i.MX 6 Family: 6QuadPlus, 6Quad, 6DualLite, 6SoloX, 6SLL, 6UltraLite, 6ULL, 6ULZ • i.MX 7 Family: 7Dual, 7ULP •...
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8M Plus Evaluation Kit Quick Start Guide (IMX8MPLUSQSG) • i.MX 8DXL Multisensory Enablement Kit Quick Start Guide (IMX8DXLUSQSG) Documentation is available online at nxp.com. • i.MX 6 information is at nxp.com/iMX6series • i.MX SABRE information is at nxp.com/imxSABRE • i.MX 6UltraLite information is at nxp.com/iMX6UL...
SDK. The default location is but can be placed anywhere on the host /opt machine. Arm-v7A (32-bit) and Arm-v8A (64-bit) toolchain script and environment are as follows: • i.MX 6 Toolchain : environment-setup-cortexa9hf-vfp-neon-poky-linux-gnueabi Linux_Config: imx_v7_defconfig ARCH=arm CROSS_COMPILE=arm-poky-linux-gnueabi- •...
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The environment variables are created in the terminal window after running the script. environment-setup-<toolchain> See the information above for i.MX 6, i.MX 7, and i.MX 8 toolchains. $ source <toolchain install directory>/environment-setup-<toolchain script> Example for i.MX 8: $ source /opt/fsl-imx-wayland/environment-setup-aarch64-poky-linux...
NXP Semiconductors Porting Kernel To flash the device trees generated from the build, execute the following commands: $ sudo dd if=<DevicetreeName>.dtb of=/dev/sd<partition> bs=512 seek=20480 conv=fsync NOTE For i.MX 8QuadMax and i.MX 8QuadXPlus, the kernel image and DTB need to be flashed after the first 6 MB of the SD card.
On the host machine, set the environment with the following command before building for i.MX 8 SoC. $ source/opt/fsl-imx-xwayland/5.4.47/environment-setup-aarch64-poky-linux $ export ARCH=arm64 b. On the host machine, set the environment with the following command before building for i.MX 6 or i.MX 7 SoC. $ export CROSS_COMPILE=/opt/fsl-imx-fb/5.4.47/environment-setup-cortexa9hf-vfp-neon-poky- linux-gnueabi $ export ARCH=arm c.
Before initializing the memory interface, configure the relevant I/O pins with the right mode and impedance, and then initialize the MMDC module. For how to generate calibration parameters for DDR, see i.MX 6 Series DDR Calibration (AN4467). Users can also use the DDR script Aid and DDR stress tools in i.MX Design and Tool Lists...
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NXP Semiconductors Porting U-Boot Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 NAND: 0 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 No panel detected: default to Hannstar-XGA Display: Hannstar-XGA (1024x768) serial Out: serial Err: serial...
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NXP Semiconductors Porting U-Boot The following message should be displayed on the console if the custom board is based on the i.MX 8M Quad EVK board: U-Boot SPL 2017.03-imx_v2017.03_4.9.51_imx8m_ga+gb026428 (Mar 01 2018 - 03:15:20) PMIC: PFUZE100 ID=0x10 start to config phy: p0=3200mts, p1=667mts with 1D2D training...
NXP Semiconductors Porting U-Boot 3.2.3 Adding new driver initialization code to board files The following steps describe how to add a new driver and how to initialize the code. 1. Find mx<customer_board>.c board/freescale/mx<customer_board>/ 2. Edit and add new driver initialization code, including clock, IOMUX, and GPIO.
1. Make sure that the JTAG tool supports Arm Cortex -A9 cores on i.MX 6, Arm Cortex-A7 cores on i.MX 7Dual and 6UltraLite, Arm Cortex-A53/A72 on i.MX 8QuadMax, and Arm Cortex-A35 on i.MX 8QuadXPlus. It is recommended to use TRACE32.
NXP Semiconductors Chapter 4 Porting System Controller Firmware 4.1 Introduction The System Controller is supported through a firmware also known as SCFW flashed into the boot image on SoC in the i.MX 8 and i.MX 8X families. Each release provides a System Controller Firmware porting kit, which includes a porting guide document.
TEE GlobalPlatform specifications can be found at https://globalplatform.org/specs-library/. 5.2 Boards supported All the i.MX 6, 7, and 8 boards support OP-TEE. Some support the same OP-TEE flavor for multiple boards like the i.MX 6ULL EVK and i.MX 6ULZ EVK. 5.3 OP-TEE booting flow Booting flow on i.MX 6 and i.MX 7 (Arm V7):...
NXP Semiconductors Configuring OP-TEE Figure 1. Booting flow on i.MX 6 and i.MX 7 Booting flow on i.MX 8 (Arm V8) Files and binaries required in the boot partition: • flash.bin: Fit image containing U-Boot and the ATF • zImage: Kernel image •...
= "linaro, optee-tz"; method = "smc"; This node is added by OP-TEE OS for i.MX 6, i.MX 7, and i.MX 7ULP, and added by U-Boot on i.MX 8M Mini, i.MX 8M Nano, and i.MX 8M Plus. 5.5 Memory protection OCRAM protection OCRAM stands for On-Chip RAM.
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NXP Semiconductors Configuring OP-TEE power management features, such as suspending or CPU idle. Therefore, OP-TEE needs to allocate a secure area in the OCRAM to execute its own power management code. This can be done by configuring the IOMUXC_GPR registers. The lower part is set to non-secure and the upper part is set to secure.
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NXP Semiconductors Configuring OP-TEE hardcoded: CFG_TZDRAM_START and CFG_TZDRAM_SIZE. These values are added in the device tree by OP-TEE OS after its initialization: /sys/firmware/devicetree/base/reserved-memory/ optee_core@<some_address> optee@<some address> The optee_core address belongs to the OP-TEE firmware. Any reading or writing from the normal world will result in a crash. The OP-TEE address is the shared memory between Linux OS and OP-TEE.
• On i.MX 8M Quad, i.MX 8M Mini, i.MX 8M Nano, and i.MX 8M Plus Similarly to i.MX 6 and i.MX 7 families, the TZASC enablement is done by setting a TZASC_EN bit in IOMUXC_GPR10. In mscale family, this bit is not a "one time write" type and TZASC_EN_LOCK must be programmed to avoid unintended disable operation.
NXP Semiconductors Configuring OP-TEE Flash the SD card: $ cd tmp/deploy/images/<platform>/ $ bzip2 -d tmp/deploy/images/<platform>/imx-image-multimedia*.wic.bz2 $ sudo dd if=imx-image-multimedia*.wic of=/dev/sd<partition> bs=1M && sync Run the test suite to check if optee is operational: $ root@imx: xtest Another way to compile OP-TEE is to use .
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NXP Semiconductors Configuring OP-TEE Specify the Linux entry address, the device tree address, and the DDR size. ifneq (,$(filter $(PLATFORM_FLAVOR),mx*)) CFG_DT ?= y CFG_NS_ENTRY_ADDR ?= CFG_DT_ADDR ?= CFG_DDR_SIZE ?= CFG_PSCI_ARM32 ?= y CFG_BOOT_SYNC_CPU = * CFG_BOOT_SECONDARY_REQUEST = * endif In plat-imx/sub.mk, define the Arm processor (Cortex A7 or A9) if the SoC is an Arm V7.
NXP Semiconductors Chapter 6 Configuring Arm Trusted Firmware 6.1 Introduction Arm Trusted Firmware (ATF) is required for all i.MX 8 boards. ATF might need some customization on new boards. ATF currently partitions non-secure resources for the OS partition before launching. When porting to a new board, ATF must be modified for the intended partitioning of system resources with System Controller Firmware.
NXP Semiconductors Chapter 7 Memory Assignment 7.1 Introduction On i.MX 8QuadMax, i.MX 8QuadXPlus, and i.MX 8DXL, SCFW provides partition concept to divide resources. The memory is divided into several regions and can only be accessed by particular software modules with corresponding security mode.
NXP Semiconductors Chapter 8 Configuring IOMUX 8.1 Introduction Before using the i.MX pins (or pads), select the desired function and correct values for characteristics such as voltage level, drive strength, and hysteresis. You can configure a set of registers from the IOMUX controller.
NXP Semiconductors Configuring IOMUX 8.1.2 Using IOMUX in the Device Tree - example The following example shows how to use IOMUX in the Device Tree. usdhc@0219c000 { /* uSDHC4 */ fsl,card-wired; vmmc-supply = <®_3p3v>; status = "okay"; pinctrl-names = "default";...
NXP Semiconductors Chapter 10 Adding SDHC 10.1 Introduction uSDHC has 14 associated I/O signals.The following list describes the associated I/O signals. Signal overview • The SD_CLK is an internally generated clock used to drive the MMC, SD, and SDIO cards.
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NXP Semiconductors Adding SDHC status = "disabled"; For more information, see: The binding document at linux/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt arch/arm/boot/dts/imx6ul.dtsi arch/arm/boot/dts/imx6ul-14x14-evk.dts arch/arm/boot/dts/imx6qdl.dtsi arch/arm/boot/dts/imx6qdl-sabresd.dtsi Support of SD3.0 SD3.0 requires 3.3 V and 1.8 V for signal voltage. Voltage selection needs to be implemented on your platform.
11.1.2 Changing the SPI interface configuration The i.MX 6 SoC has five ECSPI interfaces. The i.MX 7Dual SoC has four ECSPI interfaces. The i.MX 8QuadMax/8QuadXPlus has four LPSPI interfaces. By default, the BSP configures ECSPI-1 interface in master mode to connect to the SPI NOR Flash.
NXP Semiconductors Configuring SPI NOR 11.1.3 Hardware operation SPI NOR Flash is SPI compatible with frequencies up to 66 MHz. The memory is organized in pages of 512 bytes or 528 bytes. SPI NOR Flash also contains two SRAM buffers of 512/528 bytes each, which allows data reception while a page in the main memory is being reprogrammed.
6 with IPU and i.MX 8QuadMax, i.MX 8QuadXPlus, and i.MX 8M Plus support the LVDS display interfaces. The implementationn of the LVDS is a DRM driver for i.MX 8 and framebuffer driver for i.MX 6. The LVDS connects to a LVDS Display bridge (LBB), which is configured as a DRM LDB driver for i.MX 8 and a framebuffer driver for i.MX 6.
• Control signals to configure LDB parameters and operations • Clocks from the SoC PLLs 12.3.1 LDB on i.MX 6 for input parallel display ports The LDB is configurable to support either one or two (DI0, DI1) parallel RGB input ports. The LDB only supports synchronous access mode.
• For single-channel output: up to 85 MHz per interface (such as WXGA-1366 x 768 at 60 Hz + 35% blanking). 12.3.2 LDB on i.MX 6 Output LVDS ports The LDB has two LVDS channels, which are used to communicate RGB data and controls to external LCD displays either through the LVDS interface or through LVDS receivers.
NXP Semiconductors Chapter 13 Connecting MIPI-DSI Panel 13.1 Introduction The MIPI DSI support on i.MX 8 is enabled through the device trees located in the kernel source in arch/arm64/boot/dts/ . For more information about MIPI-DSI, see the MIPI-DSI section in the Video chapter in Display Interfaces. MIPI-DSI freescale on i.MX with IPU is supported with Synopsys hardware while i.MX 8 uses the Mixel and the Advantec panel.
The camera sensor is support on all i.MX but configured using different capture controllers. For more information, see the "Capture i.MX Linux Reference Manual (IMXLXRM). For i.MX 6 with IPU, the CSI interface Overview" section in the ‘Video“ chapter in the is through the IPU, but on other parts, the Parallel CSI driver is available to support the CSI interface.
NXP Semiconductors Supporting Cameras with CSI CSI0 is used as a parallel sensor input interface. CSI1 is used as a MIPI sensor input interface. 14.1.3 Configuring the CSI unit in test mode This section uses the test mode for its example scenario of a new camera driver that generates a chess board.
NXP Semiconductors Supporting Cameras with CSI 14.2.1 Adding a camera sensor entry in Kconfig Select specific camera drivers in the following location (as shown in the following figure): Device Drivers > Multimedia support > Video capture adapters V4L platform devices > MXC Video For Linux Camera >...
NXP Semiconductors Supporting Cameras with CSI NOTE Before connecting a camera sensor to the i.MX 6Dual/6Quad/6Solo/6DualLite board, check whether the sensor is powered with the proper supply voltages and whether the sensor data interface has the correct VIO value. Power supply mismatches can damage either the CMOS or the i.MX 6Dual/6Quad/6Solo/6DualLite.
NXP Semiconductors Supporting Cameras with CSI 14.3 Using the I C interface Many camera sensor modules require a synchronous serial interface for initialization and configuration. This section uses the file as its example code. This file contains a driver linux/drivers/media/video/mxc/capture/ov5642.c that uses the I C interface for sensor configuration.
NXP Semiconductors Supporting Cameras with CSI To test the video0 input (camera), an mxc_v4l2_overlay test is included in the BSP. If the imx-test package has also been included, open the unit test folder and execute the test. root@ ~$ cd /unit_tests/ root@ /unit_tests$ ./mxc_v4l2_overlay.out...
NXP Semiconductors Supporting Cameras with CSI Figure 7. IPU block diagram Several sensors can be connected to each of the CSIs. Simultaneous functionality (for sending data) is supported as follows: • Two sensors can send data independently, each through a different port.
NXP Semiconductors Supporting Cameras with CSI Figure 8. Parallel interface layout In parallel interface, a single value arrives in each clock, except in BT.1120 mode when two values arrive per cycle. Each value can be 8-16 bits wide according to the configuration of DATA_WIDTH. If DATA_WIDTH is configured to N, then 20-N LSB bits are ignored.
NXP Semiconductors Supporting Cameras with CSI Table 5. CSI0 parallel interface signals (continued) Signal IPU Pin Description HSYNC CSI0_HSYNC Horizontal synchronization signal DATA_EN CSI0_DATA_EN Data enable or data ready DATA[19:10] CSI0_DAT [19:10] Pixel data bus, optional to [19:4] The following section explains how the timing data mode protocols use these signals. Not all signals are used in each timing data mode protocol.
NXP Semiconductors Chapter 15 Supporting Cameras with MIPI-CSI 15.1 Introduction This chapter describes how to configure the MIPI-CSI cameras on the i.MX 7 and i.MX8. For more information on MIPI-CSI, see i.MX Linux Reference Manual (IMXLXRM). the "Capture Overview" section in the "Video" chapter in the A variety of capture controllers are used and included to support different cameras.
CODEC DAI driver, and DAI LINK driver machine driver) should be registered in the device tree, and accordingly there must be three nodes in the board specified dts file. Device trees are located in for i.MX 6 and i.MX 7 and arch/arm/boot/dts arch/ for all i.MX 8.
NXP Semiconductors Porting Audio Codecs "MICBIAS", "AMIC", "IN3R", "MICBIAS", "DMIC", "MICBIAS", "DMICDAT", "DMIC"; mux-int-port = <2>; mux-ext-port = <3>; hp-det-gpios = <&gpio7 8 1>; /*active low*/ mic-det-gpios = <&gpio1 9 1>; /*active low*/ NOTE For the specific meaning of the device tree binding, see the document located in Documentation/devicetree/ bindings/sound/.
NXP Semiconductors Porting Audio Codecs The source code for the ALSA driver is located in the Linux kernel source tree at . The following table shows linux/sound/soc the files used for the wm8962 codec support. Table 7. Files for wm8962 codec support...
NXP Semiconductors Chapter 17 Porting HiFi 4 17.1 Porting HiFi 4 DSP framework The HiFi 4 DSP framework is provided on specific i.MX 8QuadXPlus, i.MX 8QuadMax, and i.MX 8M Plus SoC. Supporting the HiFi 4 on a custom board is documented in the i.MX DSP Porting Guide inlcuded in the i.MX DSP Redistribution package available to customers who have a HiFi 4 license with Cadence.
Porting Ethernet 18.1 Introduction This chapter explains how to port the Ethernet controller driver to the i.MX 6 or i.MX 7 processor. Using i.MX FEC standard driver makes porting simple. Porting needs to address the following three areas: • Pin configuration •...
Data in, bit 3K Because i.MX 6 has more functionality than it has physical I/O pins, it uses I/O pin multiplexing. Every module requires specific pad settings. For each pad, there are up to eight muxing options called ALT modes. For further explanation, see IOMUX chapter in the SoC Application Processor Reference Manual.
19.1 Introduction The USB supports USB 2.0 on i.MX 6 and i.MX 7 families using the Chip IDEA hardware. On all i.MX 8 families, the USB supports USB 2.0 and USB 3.0. This chapter describes how to configure USB ports.
To secure HSIC connection, the USB HSIC port must be powered up before the USB HSIC device. 19.2 USB overview for i.MX 6SLL and 6SoloX There are up to three USB ports on i.MX 6 6SLL and 6SoloX serial application processors: • USB OTG1 port •...
NXP Semiconductors Porting USB NOTE For the USBOTG_ID pin, a pin that has an alternate USBOTG_ID function must be used. • USBOTG_ID • USBOTG_OC_B • One pin used to control the USB_OTG_VBUS signal. For USB OTG2 port, the following signals are used: •...
NXP Semiconductors Chapter 20 Revision History 20.1 Revision History This table provides the revision history. Table 9. Revision history Revision number Date Substantive changes L4.9.51_imx8qxp-alpha 11/2017 Initial release L4.9.51_imx8qm-beta1 12/2017 Added i.MX 8QuadMax L4.9.51_imx8mq-beta 12/2017 Added i.MX 8M Quad L4.9.51_8qm-beta2/8qxp-beta 02/2018 Added i.MX 8QuadMax Beta2 and i.MX...
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Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
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