NXP Semiconductors IMXRT500HDG Hardware Design Manual
  1. Manuals
  2. Brands
  3. NXP Semiconductors Manuals
  4. Computer Hardware
  5. IMXRT500HDG
  6. Hardware design manual

NXP Semiconductors IMXRT500HDG Hardware Design Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
IMXRT500HDG
i.MX RT500 Hardware Design Guide
Rev. 0 — 15 November 2022
Document information
Information
Content
Keywords
IMXRT500HDG, i.MX RT500, MIMXRT595-EVK
Abstract
This user guide provides details about the system hardware design to help
the users to develop their i.MX RT500 based designs
User guide

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the IMXRT500HDG and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for NXP Semiconductors IMXRT500HDG

Summary of Contents for NXP Semiconductors IMXRT500HDG

  • Page 1 RT500 Hardware Design Guide Rev. 0 — 15 November 2022 User guide Document information Information Content Keywords IMXRT500HDG, i.MX RT500, MIMXRT595-EVK Abstract This user guide provides details about the system hardware design to help the users to develop their i.MX RT500 based designs...

  • Page 2: Introduction

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Introduction This user guide provides details about the system hardware design to help the users to develop their i.MX RT500 based designs. Recommendations and examples from the NXP MIMXRT595-EVK board are also included in the following section to illustrate the concepts.

  • Page 3: Acronyms And Abbreviations

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Operating characteristics: • Power supply: – VDDCORE: 0.6 V to 1.155 V – VDDIO_0/1/2/4: 1.71 V to 1.89 V – VDDIO_3: 1.71 V to 3.6 V • Temperature range (ambient): -20 C° to +70 C°...

  • Page 4: Power Domains

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Power domains This section provides details about the power domains on the chip and in the system. 3.1 i.MX RT500 power domains always-on, GPIO, and analog The i.MX RT500 has several digital and analog supplies to power internal circuits and the GPIO ports that interface to the system.
  • Page 5 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide The minimum voltage is 0.7 V in active mode to save power, but the level can be reduced in retention mode. This supply requires quite a bit of decoupling capacitance. Refer the following steps on how to apply the minimum quantity of capacitors across the 12 of VDDCORE pins.

  • Page 6: I.mx Rt500 Power Domains, Internal Regulator

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide 3.3 i.MX RT500 power domains, internal regulator The LDO_ENABLE input signal is listed in this power domain section because it is the control signal that enables the internal VDDCORE LDO regulator when an external VDDCORE supply is not used.

  • Page 7: Power-On Sequence Using Pmic (Internal Ldo Disabled)

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Table 5. Domains ...continued VDDIO rail GPIO pins VDDIO_1 PIO0_14 to PIO0_19 PIO0_21 to PIO0_25 PIO0_28 to PIO0_31 PIO1_0 PIO1_3 to PIO1_7 PIO1_9 to PIO1_10 PIO2_24 to PIO2_31 PIO3_1 to PIO3_3 PIO4_11 to PIO4_17...
  • Page 8 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide 2. PMIC mode pins are the outputs that are controlled by an always-on supply. These pins must have external pullups to VDD_AO1V8 and get validated after several microseconds once VDD_AO1V8 is stable.

  • Page 9: Nxp Pca9420 Pmic

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide VDD_AO1V8 ERR050716: VDDIO_x should be powered at same time as VDD1V8 PMIC_MODE0/1 VDD1V8, VVD1V8_1 VDDA_ADC1V8, VREFP VDDIO_0, 1, 2, 3, 4 VDDA_BIAS VDDIO_3(3.3V) VDDCORE RESETN Figure 2. Power-on sequence The power-on sequences are shown in the...

  • Page 10: Mimxrt595-Evk Pmic Supply Assignments

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide • BGA-style wafer level chip scale package WLCSP • 24-pin quad flat pack, no leads QFN The block diagram shown in Figure 3 has taken from the PCA9420 data sheet. If VIN is greater than 6 V, the voltage rating on the capacitor of 2.2 µF/10 V...

  • Page 11: I.mx Rt500 Power Domains, Other Power Rails

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Always-on 1.8 V 2.2 µH Default: 1.0 V VDDCORE VDD_AO1V8 LDO1_OUT 1 µF 10 µF 6.3 V 6.3 V SW1_OUT i.MXRT RT5xx RT6xx PCA9420 Default 3.3 V VDDIO_1,2,3, PSYS2 ASYS LDO2_OUT 2.2 µF and/or 4 2.2 µF...

  • Page 12: External Clocks

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide • USB 3.3 V supply • 1.1 V MIPI_DSI_VDD11 supply for the MIPI_DSI digital core (which we recommend tying to the VDDCORE supply) • 1.8 V MIPI_DSI_VDD18 supply for the MIPI_DSI PHY •...

  • Page 13: External Clocks

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide 5.1 External clocks The main crystal oscillator (XTALIN / XTALOUT) can drive crystals from 4 MHz to 32 MHz. The main crystal oscillator can operate in low-power or high gain modes, while the possible frequency range is 4 MHz to 32 MHz, the practical range is 5 MHz to 26 MHz due to limitations of the on-chip PLLs.

  • Page 14: Main Crystal Oscillator (Xtalin/Xtalout), At High Gain Mode

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide OSC Module OSC Module XTALIN XTALOUT XTALIN XTALOUT crystal crystal High gain mode Low power mode Figure 5. High gain and low-power modes Table 8. PLL frequency PLL frequency (MHz) based on multiplier Crystal (MHz) VCO range is from 80 MHz to 572 MHz.

  • Page 15: Main Crystal Oscillator (Xtalin/Xtalout) At Low-Power Mode

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide OSC Module XTALIN XTALOUT crystal High gain mode Figure 6. High gain mode Note: The series resistor is in the XTALOUT leg. A small value resistance may be used for low frequency (<8 MHz) crystals, but it is normally not needed.

  • Page 16: Main Crystal Oscillator (Xtalin/Xtalout) Bypass Mode

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide OSC Module XTALIN XTALOUT crystal Low power mode Figure 7. Low-power mode 5.5 Main crystal oscillator (XTALIN/XTALOUT) bypass mode The main crystal oscillator can be bypassed with an external oscillator. It is recommended to: 1.

  • Page 17: Clkin Input Clock

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide • The RTC oscillator frequency can be tuned using the CLKOUT or 32KHZ_CLKOUT output to measure the frequency. RTxxx RTCXIN RTCXOUT XTAL Figure 8. RTC oscillator 5.7 CLKIN input clock The CLKIN input is available as a shared function on one of four GPIO pins on the i.MX...

  • Page 18: Oscillator Load Capacitance

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Note: Higher frequency clocks may show wave deformation due to loading and drive strength. Full drive strength can be enabled to resolve it. CLKOUT Port PIO0_24 PIO1_10 osc_clk PIO1_19 1m_lposc PIO2_29 FRO_DIV2...
  • Page 19 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide There are many methods to calculate load capacitance, but none are accurate. At best, they are approximations. We recommend using a simple calculation to determine the initial values of the external load capacitors. Then, after placing these values on the crystal, measure the frequency with a CLKOUT pin.
  • Page 20 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Refer to Load capacitance expression 1: Let C and C be the same value. Multiply the crystal load capacitance C by 2, subtract the pad capacitance, and then subtract 2 x stray capacitance.

  • Page 21: Debug, Trace, Jtag Scan, And Programming

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide ≈ 2(18 pF – 0 pF) – 3 pF = 33 pF Example 4: Small 24 MHz crystal: = 10 pF = 3 pF = 0 (ignore for first pass calculation) Stray ≈...

  • Page 22: Jtag Boundary Scan

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Table 10. Trace signals Signal GPIO Description TRACECLK PIO0_21 or PIO4_23 Trace Clock TRACEDATA0 PIO0_22 or PIO4_24 Trace Data 0 TRACEDATA1 PIO0_23 or PIO4_25 Trace Data 1 TRACEDATA2 PIO0_24 or PIO4_26 Trace Data 2...

  • Page 23: Boot Source From Isp_Pin [2:0]

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide If the boot source field is not programmed, the bootloader checks the status of three GPIO pins to determine where to boot from. Table 12. Boot session Boot mode Field Primary boot source. (a.k.a. master boot source)

  • Page 24: Physical Isp Pins Configuration On Evk Board

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Table 13. Boot source ...continued Boot mode ISP2 pin ISP1 pin ISP0 pin Description PIO3_29 PIO3_28 PIO1_15 USB HID ISP high Boot to ISP mode, using USB-HID class FlexSPI Boot high high Boot from QSPI/Octal Flash devices connected to the FlexSPI interface 0.

  • Page 25: Reset Pin

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Figure 13. MIMXRT595-EVK board 6.7 Reset pin The external reset pin is an active low input. A low resets the device, causing I/O ports and peripherals to take on their default states, and the boot code to execute. RESETN...

  • Page 26: Layout Recommendations

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Table 14. Reset pin Signal Description Recommendations RESETN External reset input: A When used with a PMIC, tie low on this pin resets the this pin to the SYSRSTb or device, causing I/O ports and...

  • Page 27: Evk Stack-Up Comments, Top 3 Layers

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide The total thickness: 1.6 mm +/- 10 % Loss Dielectric Layers stackup Layer Material Thickness Layer type tangent constant Copper 1 Oz Routing Prepreg Prepreg TU-768 2.7 MIL Thin dielectric 0.02 L2 GND_1...

  • Page 28: Evk Stack-Up Comments, Bottom 3 Layers

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide • L1 - Contains signals and components, high-speed signal routing, and routed power traces. • L2 - It is a solid ground plane that is a reference that provides the return paths for L1 and L3 signals.

  • Page 29: Trace Impedance Requirements

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide 7.5 Trace impedance requirements The trace impedance requirements for the MIMXRT595-EVK PCB were developed with the board vendor who provided guidance based on the signal impedance requirements. • Except for critical impedance traces, we specified minimum trace widths of 4.0 mils and minimum spaces of 5.0 mils.

  • Page 30: Hdi Recommendations

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Avoid creating slots, voids, and splits into reference planes. It creates discontinuities that can degrade signal integrity and generate emissions. Review the via voids to ensure they do not create splits. Provide ground return vias adjacent to signal vias when transitioning between different reference ground planes.

  • Page 31: Hdi Escape Routing

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Layers stackup Layer Material Thickness Layer type Copper 1 Oz Routing Prepreg Prepreg TU-768 2.7 MIL L2 GND_1 L2 Inner Copper 1 Oz Plane Prepreg Prepreg TU-768 4 MIL L3 INT_1 L3 Inner...

  • Page 32: Hdi Recommendations, Layers - 6

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide The 12 VDDCORE balls routed to 4 microvias are highlighted on the left figure. Microvias are used to connect layers 1-2, 2-3, 3-4, 4-5, and 5-6. Skip vias are used to connect layers 1-3 and layers 4-6, as shown in the right figure.

  • Page 33: Bulk And Decoupling Capacitor Placement

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide • Image A shows all the MCU ball pads on the top layer. • Image B shows the corresponding via-in-pad microvias for the MCU on the top layer. • Image C shows that many fewer microviases are connected to the decoupling capacitors on the bottom layer.
  • Page 34 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Traces should be as short as possible and must not cross or couple with other signal lines. The crystal signal loop area must be made as small as possible to minimize the noise coupled through the PCB and to keep the parasitics as small as possible.

  • Page 35: Evk Memories Octal Flash (U38)

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide We recommend placing load capacitors for the RTC oscillator even when using internal capacitors, in case the internal capacitors do not have enough tuning resolution. It is important to maintain the RTC frequency accurately.

  • Page 36: Evk Memories Qspi Flash (U37)

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Figure 25. EVK external memory layouts • Octal flash: Most data and control lines are routed on L1, it is good because all the HS signals between MCU and memory must be on the same layer. The MCU and memory can be on different layers, but all the HS signals should be on one layer.
  • Page 37 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide QSPI flash MEM_1V8 MEM_1V8 MEM_1V8 C212 C213 1.0 F 0.1 F 10 V 16 V R358 R359 R360 33 k 33 k 10 k SI_IO0 R427 FLEXSPI0_DATA0 SO_IO1 R429 R430 FLEXSPI0_SSO_B FLEXSPI0_DATA1...

  • Page 38: Evk Memories Psram (U108)

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide 7.17 EVK memories PSRAM (U108) Continuing to look at good and poor design practices as fallows, for more details, see Figure 28 Figure pSRAM MEM_1V8 C218 C217 C219 0.1 F 1.0 F 4.7 F...
  • Page 39 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Figure 29. EVK external PSRAM layout For the PSRAM footprint, a few lines are completely on the top layer. • Addr/Data lines are routed across several layers: It is poor since all HS signals between MCU and memory should be on the same layer and have matched lengths for signal integrity.

  • Page 40: Evk Memories Emmc (U111) And Sd Card

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide • L2 ground reference: All HS signals should have a ground plane for return currents. L6 signals do not have the same reference as L1 signals. The MCU and memory can be on different layers, but all HS signals must be on one layer.
  • Page 41 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Many signals on multiple layers. HS signals shared among multiple devices. Shorting resistors for shared components and signals. MCU_1V8 SDC_3V3 SD CARD R500 C285 R483 R482 4.7 k 100 k 100 k...

  • Page 42: I.mx Rt500 Power Domains

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Due to the removal of 3.3 V support on the high-speed pads, the SD card interface is no longer supported. This considerably reduced the current leakage on VDD1V8. An erratum is issued to describe this further describe. We are evaluating the use of using an external level shifter to enable this.

  • Page 43: Mlcc Capacitor Dc Bias Effect

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Jumpers and 0 esistors are used on the EVK to enable current measurements. JUMPER (DEFAULT) = 1-2 These should not be used in an end application because they require additional components and routing, which contribute to EMC HDR 1x2 emissions and susceptibility.

  • Page 44: Mlcc Capacitor Dc Bias Effect Recommendations

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide GRM152R60J225ME05 2.2 µF, 20 %, 0402, 6.3 V, X5R 1.32 µF @ 1.8 V 0.75 µF @ 3.3 V 0.47 µF @ 5.0 V DC Bias [V] GRM152R60J225ME05 C-DC bias capacitance, 25. 0degC, ACO. 5Vrms MLCC DC bias effect - Capacitance is measured at low AC voltage.
  • Page 45 IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide GRM188R61C106MA73 10 µF, 20 %, 0603, 16 V, X5R 8.30 µF @ 1.8 V 6.06 µF @ 3.3 V 4.03 µF @ 5.0 V L = 1.6 mm W = 0.8 mm T = 1.0 mm...

  • Page 46: Conclusion

    IMXRT500HDG NXP Semiconductors i.MX RT500 Hardware Design Guide Conclusion Reviewed the multiple power domains on the chip, how to filter them, the power sequencing for these domains, and the implementation of the recommended PMIC for i.MX RT500 system power. Examined the crystal oscillators that feed the internal clock systems, as well as the features of these oscillators.

  • Page 47: Legal Information

    NXP Semiconductors. In the event that customer uses the product for design-in and use in In no event shall NXP Semiconductors be liable for any indirect, incidental, automotive applications to automotive specifications and standards, punitive, special or consequential damages (including - without limitation - customer (a) shall use the product without NXP Semiconductors’...

  • Page 48: Table Of Contents

    Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2022 NXP B.V. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 15 November 2022 Document identifier: IMXRT500HDG...

This manual is also suitable for:

I.mx rt500Mimxrt595-evk

Table of Contents