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RC38208A (Revision A)
The RC38208A Evaluation Board (Revision A,
RC38208A-EVK) allows users to evaluate the
board's high-performance synthesizer and jitter
attenuator applications. This document describes the
following:
Basic hardware and GUI setup using Renesas IC
■
Toolbox (RICBox™) software
■
Board power-up instructions
Instructions to get active output signals using a
■
provided configuration file
■
Hardware modifications required for different
conditions
Board Contents
RC38208A evaluation board
■
■
EVB manual
Configuration software (installable plugin for
■
RICBox)
Configuration example file for four built-in device
■
settings
■
Board schematic and BOM
OSCI
OSCO
DPLL feedbacks from:
APLL/FOD0, FOD1
CLKIN0
CLKIN2
Time Sync
DPLL feedbacks from:
APLL/FOD0, FOD1
Time Clock Div
SPI / I
SPI/I
C
2
I
C Master
2
R31UH0033EU0100 Rev.1.00
Aug 20, 2024
Oscillator
ref
Time Clock Div
fb
Monitors
from APLL
or FOD0
Div
ref
Div
fb
Div
from FOD1
Div
TDC
Time Sync
OTP
C
2
Registers
GPIO
Figure 1. RC38208A Block Diagram
Features
Four differential clock inputs
■
■
Twelve differential clock outputs
■
On-board EEPROM stores startup-configuration
data
XIN terminal can use laboratory signal generator
■
or OCXO/TCXO/XO components and board
■
Laboratory power supply connectors
USB-C power supply
■
■
Serial port for configuration and register read out
Computer Requirements
■
USB 2.0 or USB 3.0 interface
■
Processor: minimum 1GHz
Memory: minimum 512MB; recommended 1GB
■
■
Available disk space: minimum 600MB (1.5GB
64-bit); recommended 1GB (2GB 64-bit)
Combo Bus
APLL
DPLL0
APLL
DPLL1
FOD1
APLL
FOD2
APLL
TS DCO
FOD0
FOD[2:0]
TOD and Synthesis
Time Sync
Time Clock
Time Clock Div
Evaluation Board Manual
SYSREF
IOD1
Div
IOD2
IOD4
IOD5
SYSREF
Controller
IOD6
IOD7
IOD8
IOD10
© 2024 Renesas Electronics
OUT1
OUT2
OUT4
OUT5
OUT6
OUT7
OUT8
OUT10
Page 1
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Related Manuals for Renesas RC38208A
Summary of Contents for Renesas RC38208A
- Page 1 Twelve differential clock outputs attenuator applications. This document describes the ■ On-board EEPROM stores startup-configuration following: data Basic hardware and GUI setup using Renesas IC ■ XIN terminal can use laboratory signal generator ■ Toolbox (RICBox™) software or OCXO/TCXO/XO components and board ■...
- Page 2 C Mode ...................... 12 Figure 17. EEPROM in Socket ..........................13 Figure 18. EEPROM Pin Description ........................13 Figure 19. EEPROM Schematic ..........................13 Figure 20. EEPROM Connection Jumpers for RC38208A SCL_SCLK and SDA_SDIO ........14 R31UH0033EU0100 Rev.1.00 Page 2 Aug 20, 2024...
- Page 3 RC38208A (Revision A) Evaluation Board Manual Figure 21. EEPROM Connection Jumpers for RC38208A GPIO ................15 Figure 22. GPIO Schematic and EVB DIP Switches ....................15 Figure 23. Create New Project in RICBox ......................16 Figure 24. Selecting RC38208A Device GUI in RICBox ..................16 Figure 25.
- Page 4 1kHz to 1GHz. The RC38208A consists of a single APLL and three DPLLs design that allows for multiple separate frequency domains. The APLL can be used independently of the DPLL to generate synthesized clocks at the outputs that track the frequency of the input at the XIN pin.
- Page 5 3.3V and 1.8V voltages to the entire EVB. These voltages can be set by various jumpers found around the RC38208A. The RC38208A voltage source can be derived from the on-board voltage regulators for 3.3V, 1.8V, or directly from the J90 banana connector with an external supply. The J90 connection can be used to measure total supply current into pins as reference.
- Page 6 RC38208A (Revision A) Evaluation Board Manual ■ Power connection ● Set the power supply voltage to 5V and the current limit to 2A ● +5V (J123) = +5V ● GND (J125) = GND Expected current draw: ~0.5A ■ ● After programming the device ~0.4A to ~1A during normal operation (device configuration dependent) 1.2.1.1.
- Page 7 The following steps and Figure 8 describe how to overdrive XIN with an external signal: 1. Populate C1 with a 0.1µF capacitor to ensure that J2 has a connected path to the RC38208A device. 2. Depopulate R570 and R569 (near DUT XOUT pin) to ensure that excess trace is not used.
- Page 8 RC38208A (Revision A) Evaluation Board Manual Figure 8. XIN Pin Overdrive Schematic 1.2.3. On-board Crystal Mount The crystal mounting position can only be used if there is no other signal present on the XIN path (see Figure 9). To set up the evaluation board for crystal input: 1.
- Page 9 RC38208A (Revision A) Evaluation Board Manual Figure 9. Crystal Mount Schematic 1.2.4. On-board XO Mount The evaluation board contains an independent XO circuit with an SMA connector output. The U27 XO footprint located at the bottom of the board can be either 4-pin or 6-pin. The footprints are in parallel and should only be used one at a time.
- Page 10 RC38208A (Revision A) Evaluation Board Manual Figure 11. XO Schematic 4. Set the DIP switch SW1 S7 and S8 to pull the XO output enable pin high or low depending on the XO datasheet. 5. If the XO is a differential output driver, check the termination requirement of the XO. The spare footprint can be used for LVPECL, LVDS, HCSL drivers.
- Page 11 RC38208A (Revision A) Evaluation Board Manual 1.2.5. Clock Inputs The RC38208A can accept two differential clock inputs to be used as a jitter attenuator source. To enable proper connection, make sure the input termination resistor setup corresponds to the input signal that is connected. By default, the Sense SMA connectors need 50Ω...
- Page 12 1.2.8. On-board EEPROM The EVB also supports an external EEPROM IC for loading of an RC38208A configuration programmed into the EEPROM as an option. To load the configurations from EEPROM, the EEPROM load enable bit must be set in device OTP.
- Page 13 RC38208A (Revision A) Evaluation Board Manual Figure 18. EEPROM Pin Description Figure 17. EEPROM in Socket Figure 19. EEPROM Schematic The A0 (Pin 1), A1 (Pin2), and A2 (Pin 3) are the EEPROM address inputs that can be pull either high or low using jumpers at J74 and J1 to define the device address.
- Page 14 SCL_SCLK/SDA_SDIO or GPIO0 and GPIO1 pins communication path through setting J279 and J280, as shown in Figure 20. Figure 20. EEPROM Connection Jumpers for RC38208A SCL_SCLK and SDA_SDIO For the EEPROM connected to the RC38208 GPIO0 and GPIO1 pins communication path through setting J279 and J280 as shown in Figure 21.
- Page 15 1.2.9. GPIO DIP Switch Selectors The EVB has one DIP switch set (SW1) to support GPIO pins on the RC38208A device. GPIOs 0–1 can support a two-level input (low/high). The middle position of the DIP switches leaves the pin open so GPIOs can be controlled with internal pull-up and pull-down resistors.
- Page 16 Renesas IC Toolbox Software Manual. 2.1.2. Launch the GUI After installing the Renesas IC Toolbox software, launch the software from the Windows Start menu. 1. Click Start > RICBox to open the initial RICBox window. 2. Click Create new project.
- Page 17 RC38208A (Revision A) Evaluation Board Manual 5. Follow the on-screen wizard (see Figure 25) to configure the device for general evaluation starting from “Inputs”, then “DPLL”, and finally ”Outputs”. Figure 25. RICBox Wizard Navigation 6. Click on the Finish button after the settings are decided and to review the control panel page.
- Page 18 RC38208A (Revision A) Evaluation Board Manual 2.1.3. Configure the Evaluation Board 1. To establish communication between the EVB and the GUI, click the Not Connected button (1) in the lower right corner, then click Connect (2). Figure 27. Connect to the Device in RICBox 2.
- Page 19 RC38208A (Revision A) Evaluation Board Manual 3. Board Design The RC38208A EVB schematic and BOM is available upon request. Figure 30. RC38208A Evaluation Board (Top) Figure 31. RC38208A Evaluation Board (Bottom) R31UH0033EU0100 Rev.1.00 Page 19 Aug 20, 2024...
- Page 20 RC38208A (Revision A) Evaluation Board Manual 4. Typical Performance Graphs Figure 32. Phase Noise 491.52MHz Output Synthesizer Mode 5. Ordering Information Part Number Description RC38208A-EVK RC38208A Evaluation Board 6. Revision History Revision Date Description 1.00 Aug 20, 2024 Initial release.
- Page 21 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
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