Renesas RC38312A Manual

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RC38312A

The RC38312A Evaluation Board (EVB) is designed

to support users evaluating high performance

synthesizer and jitter attenuator applications. This

document describes the following:

■

Basic hardware and GUI setup using Renesas IC

Toolbox (RICBox™) software

■

Board power-up instructions

■

Instructions to get active output signals using a

provided configuration file

■

Hardware modifications required for different

conditions

Board Contents

■

RC38312A evaluation board

■

EVB manual

■

Configuration software (installable plugin for

RICBox)

■

Configuration example file for four built-in device

settings

■

Board schematic and BOM

OSCI

OSCO

DPLL feedbacks from:

APLL/FOD0, FOD[2:1]

CLKIN0

CLKIN1

CLKIN2

CLKIN3

Time Sync

DPLL feedbacks from:

APLL/FOD0, FOD[2:1]

SPI / I

SPI/I

C Master

R31UH0025EU0100 Rev.1.00

Sep 12, 2023

Oscillator

ref

Time Clock Div

Monitors

from APLL

or FOD0

Div

ref

Div

ref

TDC

Time Clock Div

Time Sync

OTP

Registers

GPIO

Figure 1. RC38312A Block Diagram

Features

■

Four differential clock inputs

■

Twelve differential clock outputs

■

On-board EEPROM stores startup-configuration

data

■

XIN terminal can use laboratory signal generator

or OCXO/TCXO/XO components and board

■

Laboratory power supply connectors

■

USB-C power supply

■

Serial port for configuration and register read out

Computer Requirements

■

USB 2.0 or USB 3.0 interface

■

Processor: minimum 1GHz

■

Memory: minimum 512MB; recommended 1GB

■

Available disk space: minimum 600MB (1.5GB 64-

bit); recommended 1GB (2GB 64-bit)

Combo Bus

DPLL0

APLL

DPLL1

FOD1

from FOD1

APLL

DPLL2

FOD2

from FOD2

APLL

FOD0

TOD and

FOD[2:0]

Synthesis

Time Sync

Time Clock

Time Clock Div

Evaluation Board Manual

SYSREF

IOD0

IOD1

IOD2

Div

IOD3

IOD4

IOD5

SYSREF

Controller

IOD6

IOD7

IOD8

IOD9

IOD10

IOD11

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

Page 1

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Summary of Contents for Renesas RC38312A

Page 1 Evaluation Board Manual RC38312A Features The RC38312A Evaluation Board (EVB) is designed to support users evaluating high performance ■ Four differential clock inputs synthesizer and jitter attenuator applications. This ■ Twelve differential clock outputs document describes the following: ■ On-board EEPROM stores startup-configuration ■...
Page 2 Typical Performance Graphs ........................21 Ordering Information ..........................21 Revision History ............................21 Figures Figure 1. RC38312A Block Diagram........................1 Figure 2. Evaluation Board – General Setup ......................5 Figure 3. USB Power Jumpers ..........................6 Figure 4. External 5V Board Input .......................... 6 Figure 5.
Page 3 RC38312A Evaluation Board Manual Figure 21. EEPROM Schematic ........................... 14 Figure 22. EEPROM Connection Jumpers for RC38312A SCL_SCLK and SDA_SDIO ........14 Figure 23. EEPROM Connection Jumpers for RC38312A GPIO ................. 15 Figure 24. GPIO Schematic and EVB DIP Switches .................... 15 Figure 25.
Page 4 1kHz to 1GHz. The RC38312A consists of a single APLL and three DPLLs design that allows for multiple separate frequency domains. The APLL can be used independently of the DPLL to generate synthesized clocks at the outputs that track the frequency of the input at the XIN pin.
Page 5 3.3V and 1.8V voltages to the entire EVB. These voltages can be set by various jumpers found around the RC38312A. The RC38312A voltage source can be derived from the on-board voltage regulators for 3.3V, 1.8V, or directly from the J90 banana connector with an external supply. The J90 connection can be used to measure total supply current into pins as reference.
Page 6 RC38312A Evaluation Board Manual ■ Power Connection ● Set the power supply voltage to 5V and the current limit to 1A ● +5V (J123) = +5V ● GND (J125) = GND ■ Expected Current Draw: ~ 0.7A ● After programming the device ~0.6A to ~1A during normal operation (device configuration dependent) 1.2.1.1.
Page 7 The following steps and Figure 8 describe how to overdrive XIN with an external signal: 1. Populate C1 with 0.1µF capacitor to ensure that J2 has a connected path to the RC38312A device. 2. Depopulate R570 and R569 (near DUT XOUT pin) to ensure that excess trace is not used.
Page 8 RC38312A Evaluation Board Manual Figure 8. XIN Pin Overdrive Schematic 1.2.3. On-board Crystal Mount The crystal mounting position can only be used if there is no other signal present on the XIN path (see Figure 9). To setup the evaluation board for crystal input: 1.
Page 9 RC38312A Evaluation Board Manual Figure 9. Crystal Mount Schematic 1.2.4. On-board XO Mount The evaluation board contains an independent XO circuit with an SMA connector output. The U27 XO footprint located at the bottom of the board can be either 4-pin or 6-pin. The footprints are in parallel and should only be used one at a time.
Page 10 RC38312A Evaluation Board Manual 3. Set to Overdrive XIN. Figure 11. LDO Power Supply for XO and OCXO Connection Schematic 4. If the XO is a single-ended LVCMOS driver, ensure that the XO output is below the ~1.3V amplitude signal in order to support proper XIN pin characteristics.
Page 11 Figure 13. XO_OE and XO_FS Pins DIP Switch Schematic 1.2.5. Clock Inputs The RC38312A can accept four differential clock inputs to be used as a jitter attenuator source. To enable proper connection, make sure the input termination resistor setup corresponds to the input signal that is connected.
Page 12 RC38312A Evaluation Board Manual 1.2.6. Clock Outputs Each of the 12 differential output pairs can be programmed to LVDS, HCSL or CML logic type. The OUT8 to OUT11 can also be programmed to CMOS logic type. ■ The HCSL mode supports HCSL by default and can be modified to support other modes by changing the amplitude and enabling/disabling the internal termination.
Page 13 1.2.8. On-board EEPROM The EVB also supports an external EEPROM IC for loading of an RC38312A configuration programmed into the EEPROM as an option. To load the configurations from EEPROM, the EEPROM load enable bit must be set in device OTP.
Page 14 SCL_SCLK/SDA_SDIO or GPIO0 and GPIO1 pins communication path through setting J279 and J280 as shown in Figure 22. Figure 22. EEPROM Connection Jumpers for RC38312A SCL_SCLK and SDA_SDIO For the EEPROM connected to the RC38312 GPIO0 and GPIO1 pins communication path through setting J279 and J280 as shown in Figure 23.
Page 15 1.2.9. GPIO DIP Switch Selectors The EVB has one DIP switch set (SW1) to support GPIO pins on RC38312A device. GPIOs 0–6 can support a two-level input (low/high). The middle position of the DIP switches leaves the pin open so GPIOs can be controlled with internal pull-up and pull-down resistors.
Page 16 1 and 11. 2.1.2. Launch the GUI After installing the Renesas IC Toolbox software, launch the software from the Windows Start menu at the bottom-left corner of the screen. 1. Click Start > RICBox to open the initial RICBox window.
Page 17 RC38312A Evaluation Board Manual Figure 27. RICBox Wizard Navigation 6. Click on the Finish button after the settings are decided and to review the control panel page. 7. Use the side panel menu buttons (see Figure 28) to navigate through the GUI for all five separate pages.
Page 18 RC38312A Evaluation Board Manual 2.1.3. Configure the Evaluation Board 1. To establish communication between the EVB and the GUI, click the Not Connected button (1) in the lower right corner, then click Connect (2). Figure 29. Connect to the Device in RICBox 2.
Page 19 RC38312A Evaluation Board Manual 3. Board Design The RC38312A EVB schematic and BOM is available upon request. Figure 32. RC38312A Evaluation Board (top) R31UH0025EU0100 Rev.1.00 Page 19 Sep 12, 2023...
Page 20 RC38312A Evaluation Board Manual Figure 33. RC38312A Evaluation Board (bottom) R31UH0025EU0100 Rev.1.00 Page 20 Sep 12, 2023...
Page 21 RC38312A Evaluation Board Manual 4. Typical Performance Graphs Figure 34. Phase Noise 491.52MHz Output Synthesizer Mode 5. Ordering Information Part Number Description RC38312A-EVK RC38312A Evaluation Board 6. Revision History Revision Date Description 1.00 Sep 12, 2023 Initial release. R31UH0025EU0100 Rev.1.00...
Page 22 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

Renesas RC38312A Manual

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