Infineon AURIX TC375DP96F300SAAKXUMA1 Manuals

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Infineon AURIX TC375DP96F300SAAKXUMA1 Manual (864 pages)

Brand: Infineon | Category: Microcontrollers | Size: 5 MB

Table of Contents
2
Introduction
9
Memory Maps (MEMMAP)
10
Overview
10
Functional Description
10
Segments
10
Bus Fabric SRI
11
Bus Instance SPB
17
Revision History
21
Tc37X Firmware
22
Checker Software Exit Information for ALL CHECKS PASSED
22
Additional Conditions
22
Revision History
22
On-Chip System Connectivity {And Bridges
23
Tc37X Specific IP Configuration
23
Tc37X Specific Register Set
24
Tc37X Specific Registers
26
Sri Slave Interface
26
Connectivity
26
Interconnection Matrices
26
Domain 0 Interconnection Matrix
26
Revision History
27
FPI Bus Control Units (SBCU)
28
Tc37X Specific IP Configuration
28
SBCU Control Unit Registers
29
SBCU Control Registers Descriptions
32
SBCU OCDS Registers Descriptions
34
Connectivity
41
SBCU Connectivity
42
Revision History
42
CPU Subsystem (CPU)
43
Tc37X Specific Configuration
43
Tc37X Specific Register Set
43
Tc37X Specific Registers
67
SRI Slave Interface for SFR+CSFR
67
Connectivity
68
Revision History
68
Non Volatile Memory (NVM) Subsystem
69
Overview
69
Revision History
72
Data Memory Unit (DMU)
73
Tc37X Specific Register Set
74
Tc37X Specific Registers
81
SRI Slave Interface - Register Address Space
81
Revision History
86
Non Volatile Memory (NVM)
87
Tc37X Specific Register Set
88
Connectivity
89
Revision History
90
Local Memory Unit (LMU)
91
Default Application Memory (DAM)
92
Tc37X Specific IP Configuration
92
Tc37X Specific Register Set
92
Tc37X Specific Registers
93
Connectivity
93
Revision History
93
System Control Unit (SCU)
94
Tc37X Specific IP Configuration
94
LBIST Considerations for Tc37X
94
Tc37X AA
94
Tc37X Specific Register Set
95
Tc37X Specific Registers
103
SCU: Connections to FPI/BPI Bus
103
Type Description
103
Connectivity
120
Revision History
123
Clocking System
125
Power Management System (PMS)
126
Tc37X Specific IP Configuration
126
Tc37X Specific Register Set
127
Tc37X Specific Registers
131
Connectivity
132
Revision History
132
Power Management System for Low-End (PMSLE)
134
Memory Test Unit (MTU)
135
Tc37X Specific IP Configuration
135
Handling of Large DSPR Srams
135
Tc37X Specific Register Set
136
Tc37X Specific Registers
137
MEMTEST Implementation
137
MEMMAP Implementation
143
MEMSTAT Implementation
146
MEMDONE Implementation
150
MEMFDA Implementation
154
SSH Instances
159
Ganging for SRAM Test and Initialization
162
Connectivity
163
Revision History
164
General Purpose I/O Ports and Peripheral I/O Lines (Ports)
166
Tc37X Specific IP Configuration
166
Tc37X Specific Register Set
166
SPB Bus Slave Interface
166
Type Description
221
Type Description
247
Connectivity
282
Revision History
283
Safety Management Unit (SMU)
284
Tc37X Specific IP Configuration
284
Tc37X Specific Register Set
285
Tc37X Specific Registers
287
Tc37X Specific Registers
288
15.3.1.1 FPI Slave Interface
288
Tc37X Specific Alarm Mapping
307
Tc37X Specific Pre-Alarms
307
Tc37X Specific Alarms
311
Connectivity
329
Revision History
329
Interrupt Router (IR)
331
Tc37X Specific Interrupt Router Configuration
331
Tc37X Specific Control Registers
332
Tc37X Specific Registers
335
IR Status and Control Registers
335
Tc37X Specific Service Request Control (SRC) Registers
336
Tc37X Specific Registers
342
IR Service Request Control Registers (SRC)
342
Revision History
364
Flexible CRC Engine (FCE)
365
Tc37X Specific IP Configuration
365
Tc37X Specific Register Set
366
Tc37X Specific Registers
367
Connectivity
367
Revision History
367
Direct Memory Access (DMA)
368
Tc37X Specific IP Configuration
368
Tc37X Specific Register Set
368
Tc37X Specific Registers
371
Connectivity
371
Revision History
371
Signal Processing Unit (SPU)
373
SPU Lockstep Comparator (SPULCKSTP)
374
Extension Memory (EMEM)
375
Radar Interface (RIF)
376
High Speed Pulse Density Modulation Module (HSPDM)
377
Camera and ADC Interface (CIF)
378
System Timer (STM)
379
Tc37X Specific IP Configuration
379
Tc37X Specific Register Set
379
Tc37X Specific Registers
379
Connectivity
379
Revision History
380
Generic Timer Module (GTM)
381
Tc37X Specific IP Configuration
381
Tc37X Registers Register Set
385
Tc37X Specific Registers
416
GTM IP Registers Specific Settings
416
Port to GTM TIM Connections
439
Timeout Control
470
GTM to Port Connections
471
GTM DTMAUXINSEL Connections
581
GTM to MSC (Micro Second Channel) Connections
584
EDSADC to GTM TIM Connections
614
GTM to EDSADC Connections
634
EVADC to GTM Connections
639
GTM to EVADC Connections
640
GTM to CAN/TTCAN Connections
660
GTM to PSI5(S) Connections
666
Type Description
668
GTM to LC DC/DC Connection
671
ARU Parameters
673
ARU Write Address Overview
673
ARU Port Partitioning
674
ARU Read ID
674
Revision History
677
Capture/Compare Unit 6 (CCU6)
679
Tc37X Specific Register Set
679
Tc37X Specific Registers
685
Connectivity
685
Revision History
691
General Purpose Timer Unit (GPT12)
692
Tc37X Specific Register Set
692
Tc37X Specific Registers
692
Connectivity
693
Revision History
694
Converter Control Block (CONVCTRL)
695
Tc37X-Specific IP Configuration
695
Tc37X Specific Register Set
695
Tc37X Specific Registers
695
Connectivity
696
Revision History
696
Enhanced Versatile Analog-To-Digital Converter (EVADC)
697
Tc37X-Specific IP Configuration
697
Tc37X Specific Register Set
698
Connectivity
699
Analog Module Connections
699
Revision History
708
Enhanced Delta-Sigma Analog-To-Digital Converter (EDSADC)
709
Tc37X-Specific IP Configuration
709
Tc37X Specific Register Set
709
Revision History
717
Inter-Integrated Circuit (I2C)
719
Tc37X Specific IP Configuration
719
Tc37X Specific Register Set
719
Tc37X Specific Registers
719
Connectivity
719
Revision History
720
High Speed Serial Link (HSSL)
721
Tc37X Specific IP Configuration
721
Tc37X Specific Register Set
721
Address Map
721
Tc37X Specific Registers
721
Connectivity
721
Revision History
722
High Speed Communication Tunnel (HSCT)
723
Tc37X Specific IP Configuration
723
Tc37X Specific Register Set
723
33.6.2.1 Address Map
723
Tc37X Specific Registers
723
Connectivity
723
Revision History
724
Asynchronous Serial Interface (ASCLIN)
725
Tc37X Specific IP Configuration
725
Tc37X Specific Register Set
726
Tc37X Specific Registers
749
Connectivity
749
Revision History
758
Queued Synchronous Peripheral Interface (QSPI)
759
Tc37X Specific IP Configuration
759
Tc37X Specific Register Set
760
Tc37X Specific Registers
770
Register Block QSPI
770
Connectivity
776
Revision History
782
Micro Second Channel (MSC)
783
Tc37X Specific IP Configuration
783
Tc37X Specific Register Set
783
Tc37X Specific Registers
783
Connectivity
783
Revision History
785
Interrupt and DMA Controller Service Requests
787
Trigger Inputs
787
Connections of SENT
787
Revision History
789
CAN Interface (MCMCAN)
790
Tc37X Specific IP Configuration
790
Tc37X Specific Register Set
791
Tc37X Specific Registers
803
Bus Interface
803
Connectivity
804
Revision History
809
Flexray™ Protocol Controller (E-Ray)
810
Tc37X Specific IP Configuration
810
Tc37X Specific Register Set
811
Tc37X Specific Registers
818
Connectivity
818
Revision History
819
Peripheral Sensor Interface (PSI5)
821
Tc37X Specific IP Configuration
821
Tc37X Specific Register Set
821
Tc37X Specific Registers
827
Connectivity
827
Revision History
827
Peripheral Sensor Interface with Serial PHY Connection (PSI5-S)
829
Tc37X Specific IP Configuration
829
Tc37X Specific Register Set
829
Tc37X Specific Registers
829
Connectivity
829
Revision History
830
Gigabit Ethernet MAC (GETH)
831
Tc37X Specific IP Configuration
831
Tc37X Specific Register Set
831
Tc37X Specific Registers
848
Connectivity
848
DMA Burst Lengths Limitations by the System
849
Buffer and Descriptor Alignment
850
Embedded Fifos
850
Master TAG ID
850
Interrupt Service Requests
850
Clocks
851
Revision History
852
External Bus Unit (EBU)
853
SD- and Emmc Interface (SDMMC)
854
Hardware Security Module (HSM)
855
Input Output Monitor (IOM)
856
Tc37X Specific IP Configuration
856
Tc37X Specific Register Set
856

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Infineon AURIX TC375DP96F300SAAKXUMA1 Manual (864 pages)

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