Texas Instruments ADS848 EVM Series User Manual page 2

EVM Overview
1 EVM Overview
1.1 Features
• Full-featured evaluation board for the high-speed, 18-bit ADS8482 and ADS8484 1-MSPS/1.25-MSPS,
single-channel, parallel interface, SAR-type analog-to-digital converters
• Onboard signal conditioning
• Onboard reference
• Input and output digital buffers
• Onboard decoding for stacking multiple EVMs
2 Introduction
The ADS8482 is an 18-bit, 1-MSPS analog-to-digital converter (ADC) with an internal 4.096-V reference
and a pseudo-bipolar, fully differential input. The
core design. These devices are capacitor-based, successive approximation register (SAR) converters with
an inherent sample-and-hold stage. The ADS848x has 8-bit, 16-bit, and 18-bit parallel interface bus
options, allowing a variety of processors to interface easily.
The ADS848xEVM is an evaluation and demonstration platform for the ADS848x ADC. The EVM board is
a flexible design that allows the user to choose among many different analog signal conditioning,
reference, and interface modes.
3 Analog Interface
The ADC accepts a pseudo-bipolar differential input. A pseudo-bipolar differential signal is a fully
differential signal that has a common-mode voltage such that the voltage on each input is always equal to
or greater than 0 V. The common-mode voltage should be half the reference voltage. The peak-to-peak
amplitude on each input leg can be as large as the reference voltage.
The positive leg of the input signal can be applied at connector P1, pin 2 (shown in
center pin of SMA connector J1. Likewise, the negative input signal can be applied at P1, pin 1 or via the
center pin of SMA connector J2.
Description
Not connected
Reserved
Reserved
Reserved
Reserved
Pin tied to ground
Pin tied to ground
Reserved
Pin tied to ground
Pin tied to ground
2 ADS848xEVM
ADS8484
Table 1. Analog Input Connector
Signal Name Connector Pin No.
– P1.1
N/A P1.3
N/A P1.5
N/A P1.7
N/A P1.9
AGND P1.11
AGND P1.13
N/A P1.15
AGND P1.17
AGND P1.19
is an 18-bit, 1.25-MSPS version of the same
Signal Name
P1.2 +
P1.4 N/A
P1.6 N/A
P1.8 N/A
P1.10 N/A
P1.12 N/A
P1.14 N/A
P1.16 N/A
P1.18 N/A
P1.20 REF+
SLAU186A – August 2006 – Revised September 2008
Submit Documentation Feedback
www.ti.com
Table 1) or via the
Description
Noninverting input channel
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
External reference input