Icom IC-211 Instruction Manual page 37

= аб
voltage changes in steps to give 100Hz step variation to the УХО frequency. This
frequency is adjusted coarsely by R17 and finely by R18. R20 is for temperature
compensation.
TRANSMIT MUTING CIRCUIT
When the PLL is unlocked, pulses with a width proportional to the phase difference
appear at Pin 40 of IC1. These pulses are fed to the gate of Q2, and the output from
the source is rectified by D5 and D6. The rectified DC voltage from D5 and D6 is
applied to the base of ОЗ, turning it ON. Since the collector of ОЗ is connected to the
base of Q35 іп the main unit, the base voltage of 035 falls and O35 is turned OFF, thus
the transmit 9V of the main unit goes to zero and inhibits transmitting when the PLL is
unlocked.
Therefore, if unlock occurs during transmitting, Q52 in the squelch circuit on the main
unit is turned OFF and Q51 is turned ON, and the receive indicator lights up even if the
set is in the transmit mode, to give warning.
LOGIC CIRCUITS
The PLL unit has logic circuits which consist of ІС2 and ІСЗ for controlling IC1, the
PLL LSI.
SL CONTROL CIRCUIT
This circuit controls the SL signal to select either "А" or "B" set of up/down counters.
The SL line is connected to Pin 14 of IC1. When this line is LOW, the set is controlled
with "A" VFO, and when HIGH, with "B" VFO.
The R9V line is connected to the power line which is supplied in the RECEIVE mode,
resulting in a HIGH level in the RECEIVE mode and LOW level in the TRANSMIT
mode.
The DUP and INV lines are connected to the VFO switch. The DUP line is HIGH in the
"N-DUP" and "R-DUP" positions, and the INV line is HIGH in the "A", "SIM" and
^R-DUP'"' positions.
SL CONTROL CIRCUIT SCHEMATIC DIAGRAM `