Icom IC-211 Instruction Manual page 35

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PLL (PHASE LOCKED LOOP) UNIT
1.
LOCAL OSCILLATOR CIRCUIT
MIXER AND AMPLIFIER CIRCUIT
The local oscillator output and VCO output are mixed by ІС4 and the mixed signal
(1MHz ~ 3MHz) taken from Pin З and 5 is filtered by a low-pass filter and amplified by
IC8 up to a level of more than 1.6Vp-p.
PLL LSI CIRCUIT
The output from ІС5 is the input to the LSI, Pin 2. The LSI contains PLL and control
circuits. To drive the reference frequency of the PLL, a 5MHz crystal oscillator is
connected to Pins 3 and 4. This frequency is divided into 1/500 by the fixed frequency
divider in the LSI and becomes the accurate frequency of 10KHz.
The input from Pin 2
is divided by the Programmable divider in the LSI from 1/100 — 1/299 which is decided
by the controller, fed into the phase frequency detector with the reference frequency of
10KHz. The output is taken from Pin 40 in the form of a pulse from the phase detector
according to these two input's difference of phase. The controller circuit consists of
two sets of a 4-1/2 digit BCD up-down counter for the A and B VFOs, the digit selector
to control the up-down counters by a parallel data, A/B counter selector, etc.
The CLOCK (CK) and UP/DOWN (UD) signals, which are the output from the tuning
knob/chopper circuit, are fed to Pins 12 and 19 respectively. The clock signal is in
proportion to the rotation of the tuning knob, and the up/down signal is dependant on
the direction of rotation of the tuning knob. When the UD signal is HIGH, the up/down
counter increases the frequency in proportion to the number of CK pulses, and when
the UD is LOW, the frequency is decreased in the same way.
,
If you push the Tuning Speed button on the front panel, аге set in the FM mode, or in