Icom IC-211 Instruction Manual page 36

the range between 146MHz and 148MHz, the signal is locked in the driver unit and fed
to Pin 16 as the X signal. In this case the Kilohertz and Hundred Hertz digits are cleared
to 0, the CK signal is fed to the 5KHz digit counter, which results in high speed or 5KHz
steps tuning.
The FCL KO ~ К8 pins of ІС1 are connected to the ACC socket on the rear panel.
When a HIGH level signal is supplied to FCL Pin 11 and KO ~ K8 at the same time, the
MHz digit figure can be reset according to the input data at KO ~ K8, any figure can be
set according to the data from the higher digit to the lower.
For use with an external controller, such as the IC-RM2, resetting of the frequency can
be accomplished in the same manner through the ACC socket.
By the input of CK and UD signals, or by resetting the up/down counter, the output
signals appear at AO ~ B4 and are supplied to the driver unit for frequency display.
The output signals of A2 — A4 are supplied to the PLL programmable divider for
determination of the divider ratio in accordance with the up/down signal. Also, the
output signals of AO — D1 are supplied to the D/A converter for 100Hz steps tuning.
151 BLOCK DIAGRAM B, A, 0,0, В.А; D C; B; A, D C, B, A; Dy C, B, До to Frequency Display
Programmable Divider
UP/DOWN Control
B ALD; Ay Phase
UP/DOWN Counter A CK UP/DOWN Counter B Detector
Е YZ CL Ak | ћ і KK К. К, | у {| а я! I fo KK, KK,
ipn
е Ер | =
GANG Control
Divider
Eu
Frequency control Pulse input 4 фи
CLOCK Oscillator Crystal
XYZ CL Ail фи
STEP Switch
4. LOOP FILTER CIRCUIT
The phase-detected signal from Pin 40 of IC1 is fed to the loop filter circuit of Q4 and
Q6. This circuit changes the output of the phase detector, which is a pulse, into a DC
voltage, and also decides the response time of the whole loop. The output is fed to the
secondary low-pass filter Q7 to reduce noise components contained in the output signal.
This output is fed to the VCO unit and is used as the voltage to control the VCO
frequency.
5. D/A (DIGITAL TO ANALOG) CONVERTER CIRCUIT
The PLL unit has a D/A converter for the VXO (local oscillator) circuit. The signals
from А0 ~ 01 of IC1 are supplied to R1 ~ R9 for D/A conversion. This D/A converted