Silicon Laboratories C8051F996-DK User Manual page 11

7. Target Board
The C8051F996 Development Kit includes a target board with a C8051F996 device pre-installed for evaluation and
preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping
using the target board. Refer to Figure 7 for the locations of the various I/O connectors. Figure 9 on page 13 shows
the factory default shorting block positions.
P1
P2
P3
J1
J2, J3, J18 Port I/O headers (provide access to Port I/O pins)
J5
J6
J7
J8
J9
J10, J11
J12
J13
J14
J15
J16
J17
TB1
H2
SW5
P1
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Expansion connector (96-pin)
Power connector (accepts input from 7 to 15 VDC unregulated power adapter)
USB connector (connects to PC for serial communication)
Enable/Disable VBAT Power LED
Enable/Disable VDD Power LED
Provides an easily accessible ground clip
Connects pin P0.7 (IREF0 Output) to resistor R14 and capacitor C19
Connects P0.2 and P0.3 to switches and P1.5 and P1.3 to LEDs
DEBUG connector for Debug Adapter interface
Selects the power supply source (Wall Power, AAA Battery, or Coin Cell)
Connects Port I/O to UART0 interface
Connects external VREF capacitor to the P0.0/VREF
Connects the PCB ground plane to P0.1/AGND
Connects negative potentiometer (R15) terminal to pin P1.4 or to GND
Connects the potentiometer (R15) wiper to P0.6/CNVSTR
Creates an open in the power supply path to allow supply current measurement
Analog I/O terminal block
Provides terminal block access to the input and output nodes of J17
Turns power to the MCU on or off
R15
J16
P1.4
J15
TOUCH SENSE SWITCH
GND
P1.0
SILICON LABS
PORT2 www.silabs.com
J18
J7
PORT1
J3
J6 VDD/DC+
J5
H1
Pin 1
Figure 7. C8051F996 Target Board
P1.3 P0.2
SW2
P1.5
USB POWER
TOUCH SENSE SWITCH
P1.1
J8
F912
U1
COIN_CELL
AAA_BAT
J13
WALL_PWR
SW1
J14 +3VD
RESET
IMEASURE
PORT0
`
J2
J17
H2
OFF
ON
SW5
Rev. 0.1
C8051F996-DK
P0.3
SW3
P3
CP
2103
U3
J9
J12
J11
VBAT
Pin 1
Pin 2
VBAT
J1
P2
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