Analog Devices SCP-ADP7142-EVALZ Demo Manual page 3

CONFIGURATION SETTINGS
Demonstration circuit SCP-ADP7142-EVALZ is a 40V,
200mA Low Dropout (LDO) regulator designed to allow
low noise operation in noise sensitive circuits. It is easily
configured for a wide output range and can provide ex-
tremely quiet operation with its high PSRR.
The output of the SCP-ADP7142-EVALZ is resistor-pro-
grammable from 1.2V to 39.5V.
OUTPUT VOLTAGE PROGRAMMING
⎛ R1 ⎞
V = 1 .2 V 1 +
⎝ ⎜ ⎠ ⎟
OUT
R2
Table 2. Resistor Selection Guide for Common Output Voltages
V (V)
OUT
1.2
1.25
1.5
1.8
2.0
2.5
2.7
3.0
3.3
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10
11
12
13
14
15
20
25
30
35
39.5
DEMO MANUAL SCP-ADP7142-EVALZ
R1 (Ω) R2 (Ω)
0 Open
1.07k 25.5k
2.55k 10.2k
5.90k 11.8k
10.0k 15.0k
16.2k 15.0k
18.7k 15.0k
15.0k 10.0k
18.7k 10.7k
41.2k 21.5k
24.9k 10.7k
31.6k 11.5k
47.5k 15.0k
41.2k 11.5k
102k 25.5k
280k 63.4k
107k 22.1k
105k 20.0k
113k 20.0k
69.8k 11.5k
71.5k 11.0k
102k 14.7k
110k 15.0k
133k 16.2k
102k 11.3k
113k 11.5k
200k 18.7k
115k 10.0k
215k 13.7k
102k 5.11k
255k 10.7k
324k 11.5k
340k 10.7k
ENABLE PIN CONFIGURATION
The EN pin is tied to the optional SCP Run/Sequence
header P1. To create a harness for this function, use Molex
part 0510650300 with crimp pin 50212-8000.
To use an active run signal, use a 1.00MΩ resistor for ei-
ther pull-up or pull-down resistors R4 and R6, short R5
with 0W, and use the drive signal from connector P1.
If precision undervoltage lockout (UVLO) operation is de-
sired, program enable divider R4 and R6 such that:
R6 in the 10k–100k (nominal) range.
− 1 .2 V
⎛ V ⎞
IN
R4 = R6
⎝ ⎜ ⎠ ⎟
1 .2 V
The hysteresis threshold is 100mV typical, and scales by
the factor:
R4 + R6
V = 100mV
HYST
R6
SOFT-START CONFIGURATION
The SS pin can be used to limit inrush current to the load
by retarding the output voltage slew. With the pin left
open, the startup time defaults to approximately 380µs.
This can be modified with additional capacitance C
increase the soft-start time t
0 .6
⎛ ⎞
( )
t s = 3 8 0 + C
⎝ ⎜ ⎠ ⎟
SS SS
1 .1 5
Table 3. Soft Start Capacitance Configuration
C
SS
180pF
1.5nF
10nF
22nF
47nF
100nF
180nF
470nF
1µF
SS
:
SS
t (approx.)
SS
500ns
1ms
5ms
10ms
25ms
50ms
100ms
250ms
500ms
to
Rev. 0
3