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Cmsemicon BAT32A237 User Manual

Ultra-low power 32-bit microcontrollers based on arm cortex-m0+

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BAT32A237 User Manual | Documentation Instructions

BAT32A237 User Manual

®

®

Ultra-low power 32-bit microcontrollers based on ARM

Cortex

-M0+

Rev 1.0.4

Please note the following CMS IP policy

＊China Micro Semicon Co., Ltd. (hereinafter referred to as the Company) has applied for patents and holds absolute legal rights

and interests. The patent rights associated with the Company's MCUs or other products have not been authorized for use, and

any company, organization, or individual who infringes the Company's patent rights through improper means will be subject to all

possible legal actions taken by the Company to curb the infringement and to recover any damages suffered by the Company as

a result of the infringement or any illegal benefits obtained by the infringer.

＊The name and logo of Cmsemicon are registered trademarks of the Company.

＊The Company reserves the right to further explain the reliability, functionality and design improvements of the products in the

data sheet. However, the Company is not responsible for the use of the Specification Contents. The applications mentioned herein

are for illustrative purposes only and the Company does not warrant and does not represent that these applications can be applied

without further modification, nor does it recommend that its products be used in places that may cause harm to persons due to

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Page 1 ＊The name and logo of Cmsemicon are registered trademarks of the Company. ＊The Company reserves the right to further explain the reliability, functionality and design improvements of the products in the data sheet.
Page 2: Documentation Instructions
BAT32A237 User Manual | Documentation Instructions Documentation Instructions This manual is the technical reference manual for the BAT32A237 microcontroller product. The technical reference manual is the application instruction material on how to use this series of products, including the structure, function description, working mode and register configuration of each functional module.
Page 3: Table Of Contents
BAT32A237 User Manual | Table of Contents Table of Contents Documentation Instructions ......................2 Chapter 1 CPU ........................22 Overview ............................22 Cortex-M0+ core features ......................... 22 Debug features ..........................22 SWD interface pins ........................... 24 ARM reference documents ....................... 25 Chapter 2 Pin Function ......................
Page 4 BAT32A237 User Manual | Table of Contents 4.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) ..........76 4.3.9 High-speed on-chip oscillator trimming register (HIOTRM) ............. 77 System clock oscillation circuit......................78 4.4.1 X1 oscillation circuit .......................... 78 4.4.2 XT1 oscillation circuit ........................78 4.4.3...
Page 5 BAT32A237 User Manual | Table of Contents 6.3.5 Timer channel enable status register m (TEm) ................125 6.3.6 Timer channel start register m (TSm) ..................... 126 6.3.7 Timer channel stop register m (TTm)..................... 127 6.3.8 Timer input-output selection register (TIOS0, TIOS1) ..............128 6.3.9...
Page 6 BAT32A237 User Manual | Table of Contents 6.10.1 Cautions on using timer output ....................... 200 Chapter 7 Timer A ....................... 201 Function of timer A .......................... 201 Structure of timer A ......................... 202 Registers for controlling timer A ...................... 203 7.3.1...
Page 7 BAT32A237 User Manual | Table of Contents 8.3.2 Timer B mode register (TBMR) ...................... 226 8.3.3 Timer B count control register (TBCNTC) ..................227 8.3.4 Timer B control register (TBCR) ..................... 228 8.3.5 Timer B interrupt enable register (TBIER) ..................229 8.3.6...
Page 8 BAT32A237 User Manual | Table of Contents 9.4.3.1 Setting and action when selecting comparator 1 as the trigger ............ 272 9.4.3.2 Setting and action for software triggering ..................272 9.4.4 Input capture action ........................273 9.4.5 Timer C count reset action ......................274 9.4.6...
Page 9 BAT32A237 User Manual | Table of Contents 10.4.6 Events output to event link controller (EVENTC)/direct memory access (DMA) ......333 10.5 Operation of timer M ........................334 10.5.1 Input capture function ........................334 10.5.2 Output compare function ........................ 339 10.5.3 PWM function ..........................346 10.5.4 Reset synchronous PWM mode .....................
Page 10 BAT32A237 User Manual | Table of Contents 11.3.8 Hour count register (HOUR) ......................411 11.3.9 Day count register (DAY) ........................ 413 11.3.10 Week count register (WEEK) ......................414 11.3.11 Month count register (MONTH) ...................... 415 11.3.12 Year count register (YEAR) ......................415 11.3.13 Alarm minute register (ALARMWM) ....................
Page 11 BAT32A237 User Manual | Table of Contents 14.3.2 LOCKUP control register (LOCKCTL) and its protection register (PRCR) ........440 14.3.3 WDTCFG configuration register (WDTCFG0/1/2/3) ..............441 14.4 Operation of watchdog timer ......................442 14.4.1 Operation control of watchdog timer ....................442 14.4.2 Setting overflow time of watchdog timer ..................
Page 12 BAT32A237 User Manual | Table of Contents 15.4.12 Hardware trigger wait mode (scan mode, single conversion mode) ..........482 15.5 A/D converter setup flowchart ......................483 15.5.1 Setting up software trigger mode ....................483 15.5.2 Setting up hardware trigger no-wait mode ..................484 15.5.3 Setting up hardware trigger wait mode ..................
Page 13 BAT32A237 User Manual | Table of Contents Chapter 18 Programmable Gain Amplifier (PGA) ..............517 18.1 Function of programmable gain amplifier ..................517 18.2 Structure of programmable gain amplifier ..................518 18.3 Registers for controlling programmable gain amplifier ..............519 18.3.1 Peripheral enable register 1 (PER1) ....................
Page 14 BAT32A237 User Manual | Table of Contents 19.5.2 Master reception ..........................567 19.5.3 Master transmission/reception ....................... 576 19.5.4 Slave transmission.......................... 584 19.5.5 Slave reception ..........................592 19.5.6 Slave transmission/reception......................598 19.5.7 Calculation of transmission clock frequency .................. 607 19.5.8 Procedure for handling errors during 3-wire I/O communication (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) ............................
Page 15 BAT32A237 User Manual | Table of Contents 20.2.7 Serial clock control circuit ....................... 693 20.2.8 Serial clock waiting control circuit ....................693 20.2.9 Ack generation circuit, stop condition detection circuit, start condition detection circuit, Ack detection circuit ................................ 694 20.2.10 Data hold time correction circuit ..................... 694 20.2.11 Start condition generation circuit ....................
Page 16 BAT32A237 User Manual | Table of Contents 21.1 Overview ............................778 21.1.1 Features ............................778 21.1.2 Overview of functions ........................779 21.1.3 Configuration ..........................780 21.2 CAN protocol ........................... 781 21.2.1 Frame format ..........................781 21.2.2 Frame types ............................ 782 21.2.3 Data frame and remote frame ......................
Page 17 BAT32A237 User Manual | Table of Contents 21.7.16 CAN module receive history list register (C0RGPT) ..............842 21.7.17 CAN module last out-pointer register (C0LOPT)................844 21.7.18 CAN module transmit history list register (C0TGPT) ..............845 21.7.19 CAN module time stamp register (C0TS) ..................847 21.7.20 CAN message data byte register (C0MDBxm) (x = 0 to 7), (C0MDBzm) (z = 01, 23, 45, 67) ..
Page 18 BAT32A237 User Manual | Table of Contents 21.14 Time stamp function ........................887 21.14.1 Time stamp function ........................887 21.15 Baud rate setting ..........................889 21.15.1 Baud rate setting..........................889 21.15.2 Representative examples of baud rate settings ................893 21.16 Operation of CAN controller ......................897 Chapter 22 IrDA ........................
Page 19 BAT32A237 User Manual | Table of Contents 23.5.2 Assignment of DMA control data area and DMA vector table area..........957 23.5.3 Number of execution clocks for DMA ..................... 958 23.5.4 Response time for DMA ......................... 959 23.5.5 Start source for DMA ........................959 23.5.6 Operation in standby mode ......................
Page 20 BAT32A237 User Manual | Table of Contents 29.2 Structure of power-on reset circuit ....................1005 29.3 Operation of power-on reset circuit ....................1006 Chapter 30 Voltage Detection Circuit ................... 1009 30.1 Function of voltage detection circuit ..................... 1009 30.2 Structure of voltage detection circuit ..................... 1010 30.3...
Page 21 BAT32A237 User Manual | Table of Contents 32.3 Instructions for using the temperature sensor ................1045 32.3.1 How temperature sensors are used ..................... 1045 32.3.2 How to use temperature sensor ....................1046 Chapter 33 Option Bytes ..................... 1047 33.1 Function of option bytes ........................ 1047 33.1.1 User option bytes (000C0H~000C2H/010C0H~010C2H)............
Page 22: Chapter 1 Cpu
BAT32A237 User Manual | Chapter 1 CPU Chapter 1 CPU 1.1 Overview This chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+ core. For details, please refer to the ARM related documentation. 1.2 Cortex-M0+ core features ⚫...
Page 23 BAT32A237 User Manual | Chapter 1 CPU Debug block diagram of Cortex-M0+ Figure 1-1 MCU debug support Cortex - M0+ debug support Cortex - M0+ System bus core bus matrix Bridge DBGMCU SWDIO SW - DP AHB - AP SWCLK NVIC Note: SWD does not work in Deep Sleep mode, please debug in active and sleep mode.
Page 24: Swd Interface Pins
BAT32A237 User Manual | Chapter 1 CPU 1.4 SWD interface pins The 2 GPIOs of this product can be used as SWD interface pins, which exist in all packages. Table 1-1 SWD debug port pins SWD port name Debug function...
Page 25: Arm Reference Documents
BAT32A237 User Manual | Chapter 1 CPU 1.5 ARM reference documents The built-in debugging features in the Cortex®-M0+ kernel are part of the ARM® CoreSight design suite. For documentation, refer to: ® Cortex -M0+ Technical Reference Manual (TRM) ⚫ ®...
Page 26: Chapter 2 Pin Function
BAT32A237 User Manual | Chapter 2 Pin Function Chapter 2 Pin Function 2.1 Port function Please refer to the datasheet of respective product series for more information. 2.2 Port multiplexing feature Please refer to the datasheet of respective product series for more information.
Page 27: Registers For Controlling Port Functions
BAT32A237 User Manual | Chapter 2 Pin Function 2.3 Registers for controlling port functions The port functions are controlled through the following registers. • Port Mode Register (PMxx) • Port Register (Pxx) • Pull-Up Resistor Selection Register (PUxx) • Port Input Mode Register (PIMx) •...
Page 28 BAT32A237 User Manual | Chapter 2 Pin Function Table 2-2: PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and their bits assigned to each product (2/2) Bit name Ports PMxx PUxx PIMxx POMxx PMCxx pins pins pins pins pins pins register...
Page 29: Port Mode Register (Pmxx)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.1 Port mode register (PMxx) This is a register that sets the port input/output in 1-bit units. After a reset signal is generated, the value of the register changes to “FFH”. When using a port pin as a pin for a multiplexing function, refer to 2.5 Register settings when using multiplexing function.
Page 30: Port Register (Pxx)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.2 Port register (Pxx) This is a register that sets the value of the port output latch in 1-bit units. The pin level is read in the input mode and the output latch value of the port is read in the output mode. After a reset signal is generated, the value of the register changes to “00H”.
Page 31: Pull-Up Resistor Selection Register (Puxx)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.3 Pull-up resistor selection register (PUxx) This is a selection register for the internal pull-up resistor. The internal pull-up resistor can only be used in 1-bit units if the POMmn bit is “0” and set to the input mode (PMmn=1). For the bit set to the output mode, the internal pull-up resistor is not connected regardless of the setting of the pull-up resistor selection register.
Page 32: Port Input Mode Register (Pimxx)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.4 Port input mode register (PIMxx) This is a register that sets the input buffer in 1-bit units. The TTL input buffer can be selected in serial communication with external devices of different potentials. After a reset signal is generated, the value of the register changes to “00H”.
Page 33: Port Output Mode Register (Pomxx)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.5 Port output mode register (POMxx) This is a register that sets the output mode in 1-bit units. When serial communication is performed with external devices of different potentials and simplified I C communication is performed with external devices of same potential, N channel drain open output mode is selected for SDAxx pin.
Page 34: Port Mode Control Register (Pmcxx)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.6 Port mode control register (PMCxx) A digital input/output or analog input that is set in 1-bit units by the PMC register. After a reset signal is generated, the value of the register changes to “FFH”.
Page 35: Peripheral I/O Redirection Register 0 (Pior0)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.7 Peripheral I/O redirection register 0 (PIOR0) This register 0 is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned.
Page 36 BAT32A237 User Manual | Chapter 2 Pin Function INTP3 INTP4 INTP8 INTP9 www.mcu.com.cn 36 / 1066 V1.0.4...
Page 37: Peripheral I/O Redirection Register 1 (Pior1)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.8 Peripheral I/O redirection register 1 (PIOR1) This register 1 is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned.
Page 38: Peripheral I/O Redirection Register 2 (Pior2)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.9 Peripheral I/O redirection register 2 (PIOR2) This register 2 is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. After a reset signal is generated, the value of this register changes to “00H”.
Page 39: Peripheral I/O Redirection Register 3 (Pior3)
BAT32A237 User Manual | Chapter 2 Pin Function 2.3.10 Peripheral I/O redirection register 3 (PIOR3) This register 3 is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. After a reset signal is generated, the value of this register changes to “00H”.
Page 40: Handling Of Unused Pins
BAT32A237 User Manual | Chapter 2 Pin Function 2.4 Handling of unused pins The handling of each unused pin is shown in Table 2-3. Table 2-3 Handling of each unused pin Pin name Input/Output Recommended connection method when not in use...
Page 41: Register Settings When Using Multiplexing Function
BAT32A237 User Manual | Chapter 2 Pin Function 2.5 Register settings when using multiplexing function 2.5.1 Basic concept when using multiplexing function In the beginning, or a pin also assigned to be used for analog input, use the ADPC register or port mode control register (PMCxx) to specify whether to use the pin for analog input or digital input/output.
Page 42: Examples Of Register Settings For Used Port Functions And Multiplexing Functions
BAT32A237 User Manual | Chapter 2 Pin Function 2.5.2 Examples of register settings for used port functions and multiplexing functions Examples of register settings (64-pin products) using port functions and multiplexing functions are shown in Table 2-5 to Table 2-10.
Page 43 BAT32A237 User Manual | Chapter 2 Pin Function — — — — — Input × — — — — — Output — — — — Input × (INTP10) PIOR01=1 — — — — — Input × — — — Output ×...
Page 44 BAT32A237 User Manual | Chapter 2 Pin Function — — — — Output — — × — — (INTP5) Input PIOR04=1 Table 2-6: Example of register setting when using P10~P17 pin functions (2/3) Functions used Output of multiplexing functions Pin name...
Page 45 BAT32A237 User Manual | Chapter 2 Pin Function Table 2-6: Example of register setting when using P10~P17 pin functions (3/3) Functions used Output of multiplexing functions Pin name PIORx POMxx PMCxx PMxx Function Input/Output SCI output function Other than SCI name —...
Page 46 BAT32A237 User Manual | Chapter 2 Pin Function Table 2-7: Example of register setting when using P20~P27 pin functions Functions used Pin name PIORx PMCxx PMxx Function name Input/Output — × Input — Output — × ANI0 Analog input Reference voltage —...
Page 47 BAT32A237 User Manual | Chapter 2 Pin Function Table 2-8: Example of register setting when using P30~P43 pin functions Functions used Output of multiplexing functions Pin name PIORx POMxx PMCxx PMxx Function Input/Output SCI output function Other than SCI name —...
Page 48 BAT32A237 User Manual | Chapter 2 Pin Function Table 2-9: Example of register setting when using P50~P55 pin functions Functions used Output of multiplexing functions Pin name PIORx POMxx PMCxx PMxx Function SCI/CAN output Other than SCI/ Input/Output name function —...
Page 49 BAT32A237 User Manual | Chapter 2 Pin Function Table 2-10: Example of register setting when using P60~P63 pin functions Functions used Output of multiplexing functions Pin name PIORx POMxx PMCxx PMxx Function Input/Output SCI output function Other than SCI name —...
Page 50 BAT32A237 User Manual | Chapter 2 Pin Function Table 2-11: Example of register setting when using P70~P77 pin functions Functions used Output of multiplexing functions Pin name PIORx POMxx PMCxx PMxx Function Input/Output SCI output function Other than SCI name —...
Page 51 BAT32A237 User Manual | Chapter 2 Pin Function — — — — (TxD2) Output PIOR01=1 Figure 2-12: Example of register setting when using P120 pin functions Functions used Output of multiplexing functions PIORx POMxx PMCxx PMxx Function name Input/Output SCI output function...
Page 52: Chapter 3 System Architecture
BAT32A237 User Manual | Chapter 3 System Architecture Chapter 3 System Architecture 3.1 Overview This product system consists of the following components: 2 AHB buses Master: ⚫ - Cortex-M0+ - Enhanced DMA 4 AHB buses Slaves: ⚫ - FLASH Memory...
Page 53: System Address Partitioning
BAT32A237 User Manual | Chapter 3 System Architecture 3.2 System address partitioning Figure3-2 Map of address area FFFF_FFFFH Reserved E00F_FFFFH Cortex-M0+ dedicated peripheral area E000_0000H Reserved 4005_FFFFH Peripheral resource area 4000_0000H Reserved 2000_2FFFH SRAM (up to 12KB) 2000_0000H Reserved 0050_05FFH Data flash 1.5KB...
Page 54 BAT32A237 User Manual | Chapter 3 System Architecture Peripheral address assignment Table 3-1 Register group start address for peripheral Start address Peripheral Remark 0x4000_000 - 0x4000_4FFF Reserved 0x4000_5000 - 0x4000_5FFF 0x4000_6000 - 0x4000_6FFF Interrupt control 0x4000_7000 - 0x4001_8FFF Reserved 0x4001_A000 - 0x4001_FFFF...
Page 55: Chapter 4 Clock Generator
BAT32A237 User Manual | Chapter 4 Clock Generator Chapter 4 Clock Generator The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the product.
Page 56 BAT32A237 User Manual | Chapter 4 Clock Generator Sub-system clock · XT1 oscillation circuit The XT1 pin and XT2 pin are connected to a 32.768KHz resonator to oscillate the clock with =32.768kHz and to stop the oscillation by setting the XTSTOP bit (bit6 of clock operation status control register (CSC)).
Page 57: Configuration Of Clock Generation Circuit
BAT32A237 User Manual | Chapter 4 Clock Generator 4.2 Configuration of clock generation circuit The clock generation circuit is composed of the following hardware. Table 4-1 Structure of clock generation circuit Item Configuration Clock operation mode control register (CMC) System clock control register (CKC)
Page 58 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-1 Block diagram of clock generation circuit www.mcu.com.cn 58 / 1066 V1.0.4...
Page 59 BAT32A237 User Manual | Chapter 4 Clock Generator Remark: F : X1 clock oscillation frequency : High-speed on-chip oscillator clock frequency (up to 64MHz) HOCO Note : High-speed on-chip oscillator clock frequency (up to 48MHz) : External main system clock frequency...
Page 60: Registers For Controlling Clock Generation Circuit
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3 Registers for controlling clock generation circuit The clock generation circuit is controlled by the following registers. • Clock operation mode xontrol register (CMC) • System clock xontrol register (CKC) • Clock operation status control register (CSC) •...
Page 61: Clock Operation Mode Control Register (Cmc)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.1 Clock operation mode control register (CMC) This is a register that sets the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, XT2/EXCLKS/P124 pin and selects the gain of the oscillating circuit. The CMC register can only be written 1 time by the 8-bit memory manipulation instruction after reset. The register can be read by an 8-bit memory manipulation instruction.
Page 62 BAT32A237 User Manual | Chapter 4 Clock Generator selected as the F (the state before switching the F to F or F 5. The oscillation stabilization time of the F must be counted by software. 6. The maximum frequency of the system clock is 48MHz, but the maximum frequency of the X1 oscillator circuit is 20MHz.
Page 63: System Clock Control Register (Ckc)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.2 System clock control register (CKC) This is a register that selects the CPU/peripheral hardware clock and the main system clock. The CKC register is set by an 8-bit memory manipulation instruction.
Page 64 BAT32A237 User Manual | Chapter 4 Clock Generator datasheet for each peripheral hardware. 4. To select F as the counting source for Timer M, F must be set to F before bit4 (TMMEN) of peripheral enable HOCO register 1 (PER1) is set If F...
Page 65: Clock Operation Status Control Register (Csc)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.3 Clock operation status control register (CSC) This is a register that controls the operation of a high speed system clock, a high-speed on-chip oscillator clock, and a subsystem clock (except for a low-speed on-chip oscillator clock). The CSC register is set by an 8-bit memory manipulation instruction.
Page 66: Oscillation Stabilization Time Counter Status Register (Ostc)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.4 Oscillation stabilization time counter status register (OSTC) This is a register that represents the count state of the oscillating steady-time counter of the X1 clock. The X1 clock oscillation stabilization time can be checked in the following cases: •...
Page 67 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-5 Format of oscillation stabilization time counter status register (OSTC) Address: 40020402H After reset: 00H Symbol OSTC MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 Oscillator stabilization time state MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18...
Page 68: Oscillation Stabilization Time Select Register (Osts)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time. If the X1 clock is made to oscillate, it automatically waits for the time set in the OSTS register after the X1 oscillation circuit runs (MSTOP=0).
Page 69 BAT32A237 User Manual | Chapter 4 Clock Generator Deep sleep mode release X1 pin voltage waveform Remark: F : X1 clock oscillation frequency www.mcu.com.cn 69 / 1066 V1.0.4...
Page 70: Peripheral Enable Registers 0, 1 (Per0, Per1)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.6 Peripheral enable registers 0, 1 (PER0, PER1) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise.
Page 71 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-7 Format of peripheral enable register 0 (PER0) (2/3) Address: 40020420H After reset: 00H Symbol PER0 ICAHN RTCEN IRDEN ADCEN SCI1EN SCI0EN CAN0 TM40EN Control of serial interface IICA1 input clock supply IRDEN Stop to supply the input clock.
Page 72 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-7 Format of peripheral enable register 0 (PER0) (3/3) Address: 40020420H After reset: 00H Symbol PER0 ICAHN RTCEN IRDEN ADCEN SCI1EN SCI0EN CAN0 TM40EN Control of CAN module input clock supply CAN0 Stop to supply the input clock.
Page 73 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-8 Format of peripheral enable register 1 (PER1) (1/2) Address: 4002081AH After reset: 00H Symbol PER1 Note 1 DACEN TMBEN PGACMPEN TMMEN DMAEN PWMPEN TMCEN TMAEN Note2 DACEN Control of D/A converter input clock supply Stop to supply the input clock.
Page 74 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-8 Format of peripheral enable register 1 (PER1) (2/2) Address: 4002081AH After reset: 00H Symbol PER1 PGACMPEN TMMEN DACEN TMBEN DMAEN PWMPEN TMCEN TMAEN Note 1 Note 2 Control of DMA input clock supply DMAEN Stop to supply the input clock.
Page 75: Subsystem Clock Supply Mode Control Register (Osmc)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.7 Subsystem clock supply mode control register (OSMC) This register is used to reduce power consumption by stopping unnecessary clock functions. Setting the RTCLPC bit to “1” stops clocking peripheral functions other than the real-time clock and the 15-bit interval timer in the deep sleep mode or in the sleep mode in which the CPU operates with the subsystem clock, and thus reduces power consumption.
Page 76: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) This is a register that changes the high-speed on-chip oscillator frequency set by the option byte (000C2H). However, the frequency that can be selected varies depending on the values of the FRQSEL4 bit and FRQSEL3 bit of the option byte (000C2H).
Page 77: High-Speed On-Chip Oscillator Trimming Register (Hiotrm)
BAT32A237 User Manual | Chapter 4 Clock Generator 4.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. It can be used for self- measurement and accuracy correction of the high-speed on-chip oscillator frequency using a timer with high- precision external clock input, etc.
Page 78: System Clock Oscillation Circuit
BAT32A237 User Manual | Chapter 4 Clock Generator 4.4 System clock oscillation circuit 4.4.1 X1 oscillation circuit The X1 oscillation circuit oscillates by a crystal resonator or a ceramic resonator (1 to 20MHz) connecting the X1 pin. An external clock can also be input, at which time a clock signal must be input to the EXCLK pin.
Page 79 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-13 Example of an external circuit for XT1 oscillation circuit (b) External clock (a) Crystal oscillation 32.768 External clock EXCLKS Caution: When using the X1 oscillator circuit and the XT1 oscillator circuit, the dashed portions of Figure 4-12 and Figure 4-13 must be routed in order to avoid the effects of wiring capacitance, etc., by the following method:...
Page 80 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-14 shows examples of incorrect resonator connection. Figure 4-14 Examples of incorrect resonator connections (1/2) (a) Too long wiring (b) Crossed signal line PORT A power supply/GND pattern exists (c) The X1 and X2 signal line wires cross under the X1 and X2 wires.
Page 81 BAT32A237 User Manual | Chapter 4 Clock Generator Figure4-14 Examples of incorrect resonator connections (2/2) Current flowing through ground line of oscillator Wiring near high alternating current (potential at points A, B, and C fluctuates) high current Signals are fetched Note: When X2 and XT1 are in parallel, the crosstalk noise of X2 will be superimposed to XT1 and cause misoperation.
Page 82: High-Speed On-Chip Oscillator
BAT32A237 User Manual | Chapter 4 Clock Generator 4.4.3 High-speed on-chip oscillator The BAT32A237 has a built-in high speed on-chip oscillator. Frequency can be selected from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, 2MHz, 1MHz and via option bytes (000C2H). The CPU clock is divided by 2 when 64MHz is selected.
Page 83: Operation Of Clock Generation Circuit
CPU/peripheral hardware clock: F After the BAT32A237 is released from reset, the CPU begins operation through the output of the high-speed on-chip oscillator. The operation of the clock generation circuit when the power is turned on is shown in Figure 4-15.
Page 84 BAT32A237 User Manual | Chapter 4 Clock Generator Figure 4-15 Operation of the clock generation circuit when the power is turned on at least 10us Low limit of working voltage range Power voltage (V Power on reset signal RESETB pin...
Page 85: Clock Control
BAT32A237 User Manual | Chapter 4 Clock Generator 4.6 Clock control 4.6.1 Example of setting up a high-speed on-chip oscillator The CPU/peripheral hardware clock (F ) must run at high internal oscillator clock. High-speed on-chip oscillator frequencies can be selected from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, 2MHz and 1MHz by FRQSEL0~FRQSEL4 bits of option bytes (000C2H).
Page 86 BAT32A237 User Manual | Chapter 4 Clock Generator [Setting of HOCODIV for high-speed on-chip oscillator] Address: 0x40021C20 Symbol HOCODIV HOCODIV2 HOCODIV1 HOCODIV0 Selection of clock frequency for high-speed on-chip oscillator FRQSEL4=0 FRQSEL4=1 HOCODIV2 HOCODIV1 HOCODIV0 FRQSEL3=0 FRQSEL3=1 FRQSEL3=0 FRQSEL3=1 =32MHz...
Page 87: Example Of Setting X1 Oscillation Circuit
BAT32A237 User Manual | Chapter 4 Clock Generator 4.6.2 Example of setting X1 oscillation circuit After a reset release, the CPU/peripheral hardware clock (F ) always starts operating with the high- speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator...
Page 88: Example Of Setting Xt1 Oscillation Circuit
BAT32A237 User Manual | Chapter 4 Clock Generator 4.6.3 Example of setting XT1 oscillation circuit After a reset release, the CPU/peripheral hardware clock (F ) always starts operating with the high- speed on-chip oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the...
Page 89: Cpu Clock Status Transition Diagram
BAT32A237 User Manual | Chapter 4 Clock Generator 4.6.4 CPU clock status transition diagram Figure 4-16 shows the CPU clock status transition diagram of this product. Figure 4-16 CPU clock status transition diagram Power on X1 oscillation / EXCLK input: stop (input port mode)
Page 90 BAT32A237 User Manual | Chapter 4 Clock Generator Examples of CPU clock transfer and SFR register setting are in Table 4-3. Table 4-3 CPU clock transition and SFR register setting examples (1/5) (1). CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Page 91 BAT32A237 User Manual | Chapter 4 Clock Generator Table 4-3 CPU clock transition and SFR register setting examples (2/5) (4). CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Settings flag of SFR register...
Page 92 BAT32A237 User Manual | Chapter 4 Clock Generator Table 4-3 CPU clock transition and SFR register setting examples (3/5) (6). The CPU is transferred from a high-speed system clock operation (C) to a high-speed on-chip oscillator clock operation (B). (Order in which SFR registers are set)
Page 93 BAT32A237 User Manual | Chapter 4 Clock Generator Table 4-3 CPU clock transition and SFR register setting examples (4/5) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Settings flag of SFR register...
Page 94 BAT32A237 User Manual | Chapter 4 Clock Generator Table 4-3 CPU clock transition and SFR register setting examples (5/5) (11) CPU changing from high-speed on-chip oscillator clock operation (B) to deep sleep mode (H). CPU changing from high-speed system clock operation (C) to deep sleep mode (I).
Page 95: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
BAT32A237 User Manual | Chapter 4 Clock Generator 4.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 4-4 Changing CPU clock (1/2)
Page 96 BAT32A237 User Manual | Chapter 4 Clock Generator Table 4-4 Changing CPU clock (2/2) CPU clock Conditions before change Processing after change Before change After change Oscillation of high-speed on-chip oscillator High-speed on- and selection of high-speed on-chip chip oscillator oscillator clock as main system clock.
Page 97: Time Required To Switch Cpu Clock And Main System Clock
BAT32A237 User Manual | Chapter 4 Clock Generator 4.6.6 Time required to switch CPU clock and main system clock It can switch CPU clock (main system clock↔sub system clock) and main system clock (high-speed on-chip oscillator clock↔high speed system clock) by setting bit6 and bit4 (CSS, MCM0) of system clock control register.
Page 98: Conditions Before Clock Oscillation Is Stopped
BAT32A237 User Manual | Chapter 4 Clock Generator 4.6.7 Conditions before clock oscillation is stopped The register flag settings for stopping clock oscillations (invalid external clock input) and the conditions before stopping are as follows. Table 4-8 Condition and flag setting before clock oscillation stops...
Page 99: Chapter 5 Hardware Divider
BAT32A237 User Manual | Chapter 5 Hardware Divider Chapter 5 Hardware Divider Hardware divider is a 32-bit signed integer divider, which is specialized hardware carried to support high- performance computing, and outputs 32-bit signed quotient and remainder results. 5.1 Features ⚫...
Page 100: Dividend Register (Dividend)
BAT32A237 User Manual | Chapter 5 Hardware Divider 5.3.1 Dividend register (DIVIDEND) The dividend register is a register that holds the value of the dividend, which is a 32-bit signed integer participating in the division calculation. DIVIDEN [31:24] DIVIDEN [23:16]...
Page 101: Status Register (Status)
BAT32A237 User Manual | Chapter 5 Hardware Divider 5.3.5 Status register (STATUS) The status register allows querying the state of the hardware divider, including the flags for division by zero and the BUSY flag. Reserve Reserve Reserve DIVBYZE BUSY Reserve DIVBYZERO Used to indicate the case of a division, updated each time the division register is written.
Page 102: Universal Timer Unit (Timer4)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Chapter 6 Universal Timer Unit (Timer4) The product is carried with a universal timer unit with four channels. The number of channels of the universal timer unit varies depending on the product. See table below:...
Page 103 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) The universal timer unit has four 16-bit timers. Each 16-bit timer is referred to as a “channel” and can be used individually as a stand-alone timer or in combination with multiple channels for advanced timer functions.
Page 104: Function Of Universal Timer Unit
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.1 Function of universal timer unit The universal timer unit has the following functions: 6.1.1 Independent channel operation The independent channel operation function is a function that enables independent use of any channel without being affected by other channel operation modes.
Page 105 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) (6) Measurement of the high-/low-level width of the input signal The high- and low-level width of the input signal is measured by starting the count on one edge of the input signal at the timer input pin (TImn) and capturing the count value on the other edge.
Page 106: Multi-Channel Linkage Operation Functions
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.1.2 Multi-channel linkage operation functions The multi-channel linked operation function is a combination of a master channel (the reference timer for the master control cycle) and a slave channel (a timer that operates in compliance with the master channel).
Page 107: 8-Bit Timer Operation Function (Channels 1 And 3 Of Unit 0 Only)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.1.3 8-bit timer operation function (channels 1 and 3 of unit 0 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels.
Page 108: Structure Of Universal Timer Unit
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.2 Structure of universal timer unit The universal timer unit consists of the following hardware. Table 6-2 Structure of universal timer unit Item Structure Counter Timer count register mn (TCRmn)
Page 109 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Whether the timer input/output pins of each channel of the universal timer unit are different depends on the product. Table 6-3 Timer input/output pins for each product Availability of input/output pins for each product...
Page 110 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) The block diagram of the universal timer unit is shown in Figure 6-1. Figure 6-1 Overall block diagram of universal timer unit 0 Timer clock select register 0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000...
Page 111: List Of Universal Timer Unit Register
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.2.1 List of universal timer unit register Register base address: 0x40041C00 Offset address Register name Bit width Reset value 0x180 TCR00 FFFFFH 0x182 TCR01 FFFFFH 0x184 TCR02 FFFFFH 0x186 TCR03...
Page 112: Timer Count Register Mn (Tcrmn)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.2.2 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register that counts the count clock. The count is incremented or decremented synchronously with the rising edge of the count clock.
Page 113 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) As shown below, the read values of the TCRmn register vary depending on the operating mode and operating state. Table 6-4: Read value of timer count register mn (TCRmn) in each running mode...
Page 114: Timer Data Register Mn (Tdrmn)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.2.3 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).
Page 115: Register For Controlling Universal Timer Unit
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3 Register for controlling universal timer unit The registers that control the universal timer units are as follows: • Peripheral enable register 0 (PER0) • Timer clock select register m (TPSm) •...
Page 116: Peripheral Enable Register 0 (Per0)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.1 Peripheral enable register 0 (PER0) The PER0 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 117: Timer Clock Select Register M (Tpsm)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that selects the two or four common operating clocks (CKm0, CKm1, CKm2, CKm3) provided to each channel. CKm0 is selected via bits 3~0 of the TPSm register, and CKm1 is selected via bits 7~4 of the TPSm register.
Page 118 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-6 Table of timer clock select register m (TPSm) (1/2) Symbol TPSm Note Selection of operation clock(CKmk) (k=0,1) =2MHz =4MHz =8MHz F =20MHz F =32MHz 2MHz 4MHz 8MHz 20MHz...
Page 119 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-7 Table of timer clock select register m (TPSm) (2/2) Symbol TPSm Note Selection of operation clock (CKm2) PRSm21 PRSm20 =2MHz =4MHz =8MHz F =20MHz F =32MHz 1MHz 2MHz...
Page 120: Timer Mode Register Mn (Tmrmn)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.3 Timer mode register mn (TMRmn) The TMRmn register is a register that sets the operation mode of channel n. It performs the selection of the operation clock (F ), the selection of the count clock, the selection of master/slave, the selection of the 16-bit/8-bit...
Page 121 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Note: 1. Bit11 is a read-only bit, fixed to “0”, ignoring write operations. Caution: 1. Bits 13, 5 and 4 must be set to 0. 2. To change the clock selected as F...
Page 122 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-10: Table of timer mode register mn (TMRmn) (3/4) Symbol TMRmn CKSm CKSm CCSm MASTE STSm CISm CISm (n=2) Symbol TMRmn CKSm CKSm CCSm SPLITm STSm CISm CISm (n=1,3)
Page 123 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-11 Table of timer mode register mn (TMRmn) (4/4) Symbol TMRmn CKSmn CKSmn MASTER STSm STSm STSm CISm CISm CCSmn (n=2) Symbol TMRmn CKSmn CKSmn STSm STSm STSm CISm...
Page 124: Timer Status Register Mn (Tsrmn)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.4 Timer status register mn (TSRmn) The TSRmn register is a register that indicates the overflow status of the channel n counter. The TSRmn register is valid only in capture mode (MDmn3~MDmn1=010B) and capture & single count mode (MDmn3~MDmn1=110B).
Page 125: Timer Channel Enable Status Register M (Tem)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.5 Timer channel enable status register m (TEm) The TEm register is a register that indicates the enable or stop status of each channel timer operation. Each of the TEm register corresponds to each of the timer channel start register m (TSm) and timer channel stop register m (TTm).
Page 126: Timer Channel Start Register M (Tsm)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that initializes the timer counter register mn (TCRmn) and sets the start of counting operation for each channel. If each bit is set to “1”, the corresponding bit of the timer channel enable status register m (TEm) is set to “1”.
Page 127: Timer Channel Stop Register M (Ttm)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.7 Timer channel stop register m (TTm). The TTm register is a trigger register to set the count stop of each channel. If each bit is set to “1”, the corresponding bit in the timer channel enable status register m (TEm) is cleared to "0".
Page 128: Timer Input-Output Selection Register (Tios0, Tios1)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.8 Timer input-output selection register (TIOS0, TIOS1) The TIOS0 register is used to make selections for the inputs and outputs of unit 0. The timer inputs for channel 0 and channel 1 and the timer output for channel 2 of unit 0 are selected. The TIOS0 register is set by an 8-bit memory manipulation instruction.
Page 129 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) The TIOS1 register selects the timer input for channel 2 of unit 0. The TIOS1 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of the TIOS1 register changes to "00H".
Page 130: Timer Output Enable Register M (Toem)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.9 Timer output enable register m (TOEm) The TOEm register is a register that sets to enable or disable the timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
Page 131: Timer Output Register M (Tom)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.10 Timer output register m (TOm) The TOm register is a buffer register for each channel timer output. The bit value of this register is output from the output pin (TOmn) of each channel timer.
Page 132: Timer Output Level Register M (Tolm)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.11 Timer output level register m (TOLm) The TOLm register is a register that controls the output level of each channel timer. When timer output (TOEmn=1) is enabled and the multi-channel linkage operation function (TOMmn=1) is used, the set and reset timing of the timer output signal reflects the inverse setting of each channel n performed by this register.
Page 133: Timer Output Mode Register M (Tomm)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.12 Timer output mode register m (TOMm) The TOMm register is a register that controls the output mode of each channel timer. When used as an independent channel operation function, the corresponding bit of the using channel should be set to “0”.
Page 134: Input Switch Control Register (Isc)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.13 Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using channel 3 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data input pin (RxD0) is selected as a timer input signal.
Page 135: Noise Filter Enable Register (Nfen1)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.14 Noise filter enable register (NFEN1) The NFEN1 register sets whether the noise filter is used for the input signals of the timer input pins of each channel of Unit 0. For pins that require noise removal, the corresponding bit must be set to “1” to make the noise filter effective.
Page 136: Registers For Controlling Port Functions Of Timer Input/Output Pins
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.3.15 Registers for controlling port functions of timer input/output pins When using the Universal Timer Unit, you must set the control registers (Port Mode Register (PMxx), Port Register (Pxx), and Port Mode Control Register (PMCxx)) for the port function that is multiplexed with the target channel.
Page 137: Basic Rules Of Universal Timer Unit
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.4 Basic rules of universal timer unit 6.4.1 Basic rules of multi-channel linkage operation function The multi-channel linkage function is a function that combines a master channel (a reference timer that counts cycles) and a slave channel (a timer that operates in compliance with the master channel), and several rules need to be observed when using it.
Page 138 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Example 1 Timer4 Channel group 1 (Multi-channel linkage function) CK00 Channel 0: Master Channel 1: Slave Channel group 2 (Multi-channel linkage function) CK01 Channel 2: Master Channel 3: Slave The operating clock of channel group 1 may be different from that of channel group 2.
Page 139: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels.
Page 140: Operation Of Counter
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.5 Operation of counter 6.5.1 Count clock (F TCLK The count clock of the general-purpose timer unit (F ) can be selected by the CCSmn bit of the timer TCLK mode register mn (TMRmn) for any of the following clocks: •...
Page 141 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (F ) is a signal that detects an active edge of the TImn pin input signal and is synchronized...
Page 142: Start Timing Of Counter
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.5.2 Start timing of counter The timer count register mn (TCRmn) enters the operation enable state by setting TSmn bit of the timer channel start register m (TSm). Execution from the counting enable state to the start of the timer count register mn (TCRmn) is shown in Table 6-7.
Page 143: Operation Of Counter
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.5.3 Operation of counter The following describes the counter operation for each mode. Operation of interval timer mode ① The operation enable state is entered by writing “1” to the TSmn bit (TEmn=1). The timer count register mn (TCRmn) remains at its initial value until a count clock is generated.
Page 144 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) (2) Operation of event counter mode ① The timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn=0). ② The operation enable state is enabled by writing “1” to the TSmn bit (TEmn=1).
Page 145 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Operation of capture mode (interval measurement of input pulses) ① The operation enable state is entered by writing “1” to the TSmn bit (TEmn=1). ② The timer count register mn (TCRmn) remains at its initial value until a count clock is generated.
Page 146 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) the count timing, set MDmn0 to “1” so that an interrupt can be generated at the start of the count. Remark: This is a timing without the noise filter. If the noise filter is used, the edge detection is delayed by 2 more F cycles (3~4 cycles in total) from the TImn input.
Page 147 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Operation of capture & single count mode (measurement of high-level width) ① The operation enable state is entered by writing "1" to the TSmn bit of the timer channel start register m (TSm)(TEmn=1).
Page 148: Control Of Channel Output (Tomn Pin)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.6 Control of channel output (TOmn pin) 6.6.1 Configuration of TOmn pin output circuit Figure 6-31 Configuration of output circuit TOmn register Interrupt signal of master channel （INTTMmn） interrupt singal of slave...
Page 149: Output Settings For Tomn Pins
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.6.2 Output settings for TOmn pins The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-32 State change from setting timer output to start of operation TCRmn Random value ( "FFFFH"...
Page 150: Cautions For Channel Output Operation
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.6.3 Cautions for channel output operation (1) Changes of setting values for TOm, TOEm, TOLm, TOMm registers in timer operation The operation of the timer (timer count register mn (TCRmn) and timer data register mn (TDRmn)) and the Tomn output circuit are independent.
Page 151 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) (b) When operation starts with slave channel output mode (TOMmn = 1) setting (PWM output)) In slave channel output mode (TOMmn=1), the active level depends on the setting of timer output level register m (TOLmn).
Page 152 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition.
Page 153 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-36 Set/reset timing operation status Basic operation timing TCLK INTTMmn Master channel Internal reset signal Tomn Pin/TOmn Toggle Toggle internal reset signal delay 1 clock cycle INTTMmp Slave channel...
Page 154: One-Time Operation Of Tomn Bit
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.6.4 One-time operation of TOmn bit Like the timer channel start register m (TSm), the timer output register m (TOm) has the set bits (TOmn) for all channels and can therefore operate the TOmn bits for all channels at once.
Page 155: Timer Interrupt And Tomn Pin Output When Counting Starts
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.6.5 Timer interrupt and TOmn pin output when counting starts In interval timer mode or capture mode, the MDmn0 bit of timer mode register mn (TMRmn) is the bit that sets whether to generate a timer interrupt when counting starts.
Page 156: Control Of Timer Input (Timn)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.7 Control of timer input (TImn) 6.7.1 Structure of TImn pin input circuit The signal of the timer input pin is input to the timer control circuit through the noise filter and the edge detection circuit.
Page 157: Cautions On Channel Input Operation
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.7.3 Cautions on channel input operation When set to not use the timer input pin, no operating clock is provided to the noise filter circuit. Therefore, the following wait time is required from the time set to use the timer input pin to the time the channel corresponding to the timer input pin is set to operate the enable trigger.
Page 158: Independent Channel Operation Function Of Universal Timer Unit
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.8 Independent channel operation function of universal timer unit 6.8.1 Operation as interval timer/square wave output Interval timer It can be used as a reference timer to generate INTTMmn (timer interrupt) at fixed intervals. The interrupt...
Page 159 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-42 Example of basic timing operating as an interval timer/square wave output (MDmn0=1) CKm1 Operation Output Note Timer counter register mn clock TOmn pin control (TCRmn) CKm0 circuit Interrupt...
Page 160 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-44 Example of register setting contents for interval timer/square wave output Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 note...
Page 161 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-45 Procedure for interval timer/square wave output function Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register) Set the TM4mEN bit of peripheral enable register 0(PER0) The input clock of timer unit m is in the providing state.
Page 162: Operation As External Event Counter
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.8.2 Operation as external event counter It can be used as an event counter to count the active edges (external events) detected on the TImn pin input and generate an interrupt if the specified count value is reached. The specified count value can be calculated using...
Page 163 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-47 Example of register setting content in external event counter mode Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 note...
Page 164 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-48 Procedure for external event counter function Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 165: Operation As Frequency Divider (Only For Channel 0 Of Unit 0)
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.8.3 Operation as frequency divider (only for channel 0 of unit 0) The clock input from the TI00 pin can be divided and used as a divider for the output of the TO00 pin.
Page 166 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) TI00: TI00 pin input signal TCR00: Timer count register 00 (TCR00) TDR00: Timer data register 00 (TDR00) TO00: TO00 pin output signal www.mcu.com.cn 166 / 1066 V1.0.4...
Page 167 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-50 Example of register contents setting when operating as a frequency divider (a) Timer mode register 00 (TMR00). CKS001 CKS000 CCS00 STS002 STS001 STS000 CIS001 CIS000 MD003 MD002 MD001...
Page 168 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-51: Procedure for frequency divider function Software operation Hardware status The input clock of timer unit 0 is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 169: Operation As Input Pulse Interval Measurement
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.8.4 Operation as input pulse interval measurement The count value can be captured at the active edge of TImn and the interval between TImn input pulses can be measured. The software operation (TSmn=1) can also be set to capture the count value during the period when the TEmn bit is “1”.
Page 170 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer count register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) OVF: Bit 0 of timer state register mn (TSRmn).
Page 171 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-54: Procedure for input pulse interval measurement function Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 172: Operation As Voltage High And Low Level Width Measurement Of Input Signal
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.8.5 Operation as voltage high and low level width measurement of input signal Caution: When used as a LIN-bus support function, bit1 (ISC1) of the Input Switching Control Register (ISC) must be set to “1”...
Page 173 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-55: Example of basic timing operating as high-/low-level width measurement of input signal TSmn TEmn TImn TCRmn TDRmn 0000H INTTMmn Remark: m: unit number (m= 0) n: channel number (n=0 ~ 3)
Page 174 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-56: Example of register contents setting in measuring high-/low-level width of input signal Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn Note STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
Page 175: Operation
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-57: Procedure for high-/low-level width measurement function of input signal Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 176: Operation As Delay Counter
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.8.6 Operation as delay counter The count can be decremented by the active edge detection (external event) of the TImn pin input and INTTTMmn (timer interrupt) is generated at any set interval.
Page 177 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-59: Example of register setting content when delaying counter function (a) Timer mode register mn (TMRmn) CKSmn1 Note CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2 MDmn1...
Page 178 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-60: Procedure when delaying counter function Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 179: Multi-Channel Coordinated Operation Function For Universal Timer Unit
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.9 Multi-channel coordinated operation function for universal timer unit 6.9.1 Operation as single trigger pulse output function Using the 2 channels in pairs, a single trigger pulse with any delay pulse width can be generated from the input of the TImn pin.
Page 180 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-61: Block diagram of operation as single trigger pulse output function Master channel (Single count mode) CKm1 Operation Timer count register mn clock CKm0 (TCRmn) TNFENxx TSmn Interrupt signal...
Page 181 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-62: Example of basic timing operating as a single trigger pulse output function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Save...
Page 182 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-63: Example of register contents setting for single trigger pulse output function (master channel) (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3...
Page 183 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-64: Example of register setting content for single trigger pulse output function (slave channel) (a) Timer mode register mp (TMRmp) CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp0...
Page 184 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-65: Procedure for single trigger pulse output function (1/2) Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 185 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-66: Procedure for single trigger pulse output function (2/2) Software operation Hardware status Set the TOEmp bit (slave) to "1" (restart operation only). The TEmn and TEmp bits are set to 1 and the master...
Page 186: Operation As Pwm Function
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.9.2 Operation as PWM function By using the 2 channels in pairs, pulses of any period and duty cycle can be generated. The period and duty cycle of the output pulses can be calculated using the following equations: Pulse period = {TDRmn (master) set value +1} ...
Page 187 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-67: Block diagram of operation as PWM function Master channel (Interval timer mode) CKm1 Operation clock Timer counter CKm0 register mn (TCRmn) interrupt Timer data Interrupt signal control TSmn...
Page 188 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-68: Example of basic timing operating as PWM function TSmn TEmn FFFFH TCRmn 0000H Master channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp...
Page 189 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-69: Example of register contents setting for PWM function (master channel) (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2 MDmn1...
Page 190 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-70: Example of register contents setting for PWM function (slave channel) (a) Timer mode register mp (TMRmp) CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp0 Note MDmp3 MDmp2...
Page 191 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-71: Operating steps for PWM functions Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register)
Page 192: Operation As Multiple Pwm Output Function
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.9.3 Operation as multiple PWM output function This is a function that extends the PWM function and uses multiple slave channels for multiple PWM outputs with different duty cycles. For example, when using 2 slave channels in pairs, the period and duty cycle of the output pulse can be calculated by using the following equation: Pulse period = {TDRmn(master) set value +1} ...
Page 193 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-72 Block diagram of operation as multiple PWM output function (output two types of PWMs) Master channel (Interval timer mode) CKm1 Operation clock Timer count register mn CKm0 (TCRmn)
Page 194 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-73 Example of basic timing operating as multiple PWM output function (output two types of PWMs) TSmn TEmn FFFFH TCRmn 0000H Master channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH...
Page 195 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Remark: m: unit number (m= 0) n: master channel number (n=0) p: slave channel number q: slave channel number n < p < q ≤ 3 (p and q are integers greater than n)
Page 196 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-74 Example of register contents setting for multiple PWM output function (master channel) (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
Page 197 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-75 Example of register contents setting for multiple PWM output function (slave channel) (output two types of PWMs) (a) Timer mode registers mp, mq (TMRmp, TMRmq) CKSmp1 CKSmp0 CCSmp...
Page 198 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-76 Procedure for the multiple PWM output function (output two types of PWMs) (1/2) Software operation Hardware status The input clock of timer unit m is in the stop-providing state.
Page 199 BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) Figure 6-76 Procedure for the multiple PWM output function (output two types of PWMs) (2/2) Software operation Hardware status (Sets the TOEmp and TOEmq (slave) bits to 1 only when resuming operation.)
Page 200: Cautions When Using A Universal Timer Unit
BAT32A237 User Manual | Chapter 6 Universal Timer Unit (Timer4) 6.10 Cautions when using a universal timer unit 6.10.1 Cautions on using timer output According to the product, the pins to which the timer output function is assigned may also be assigned the output of other multiplexing functions.
Page 201: Chapter 7 Timer A
BAT32A237 User Manual | Chapter 7 Timer A Chapter 7 Timer A 7.1 Function of timer A The timer A is a 16-bit timer capable of pulse output, pulse width and period measurement of external inputs, and counting of external events.
Page 202: Structure Of Timer A
BAT32A237 User Manual | Chapter 7 Timer A 7.2 Structure of timer A The block diagram and the pin structure of the timer A are shown in Figure 7-1 and Table 7-2 respectively. Figure 7-1 Block diagram of timer A...
Page 203: Registers For Controlling Timer A
BAT32A237 User Manual | Chapter 7 Timer A 7.3 Registers for controlling timer A The registers for controlling timer A are shown in Table 7-3. Table 7-3 Registers for controlling timer A Register name Symbol Peripheral I/O redirection register 1...
Page 204: Subsystem Clock Supply Mode Control Register (Osmc)
BAT32A237 User Manual | Chapter 7 Timer A 7.3.2 Subsystem clock supply mode control register (OSMC) The operating clock of timer A can be selected by the WUTMMCK0 bit. The RTCLPC bit is a bit that reduces power consumption by stopping the unwanted clock function. For the setting of RTCLPC bit, please refer to “Chapter 4 Clock Generation Circuit”.
Page 205: Timer A Count Register 0 (Ta0)
BAT32A237 User Manual | Chapter 7 Timer A 7.3.3 Timer A count register 0 (TA0) This is a 16-bit register. If this register is written, the data is written to the reload register. If this register is read, the count value is read. The status of the reload register and counter changes depending on the value of the TSTART bit of the TACR0 register.
Page 206: Timer A Control Register 0 (Tacr0)
BAT32A237 User Manual | Chapter 7 Timer A 7.3.4 Timer A control register 0 (TACR0). The TACR0 register is a register that controls the count and stop of register A and indicates the status of timer The TACR0 register is set by an 8-bit memory manipulation instruction.
Page 207: Timer Ai/O Control Register 0 (Taioc0)
BAT32A237 User Manual | Chapter 7 Timer A 7.3.5 Timer AI/O control register 0 (TAIOC0) The TAIOC0 register is a register that sets the input/output of the timer A. The TAIOC0 register is set by an 8- bit memory manipulation instruction.
Page 208 BAT32A237 User Manual | Chapter 7 Timer A Table 7-4 Edge and polarity switching of TAIO input/output Operation mode Function Timer mode Not used (input/output ports). 0: Output from “H” level (initial level: “H”) Pulse output mode 1: Output from “L” level (initial level: “L”)
Page 209: Timer A Control Register 0 (Tamr0)
BAT32A237 User Manual | Chapter 7 Timer A 7.3.6 Timer A control register 0 (TAMR0). The TAMR0 register is a register that sets the operating mode of register A. The TAMR0 register is set by an 8-bit memory manipulation instruction.
Page 210: Timer A Event Pin Selection Register 0 (Taisr0)
BAT32A237 User Manual | Chapter 7 Timer A 7.3.7 Timer A event pin selection register 0 (TAISR0) The TAISR0 register is a register that selects a timer that controls the period of the event count in the event counter mode and sets the polarity. The TAISR0 register is set by an 8-bit memory manipulation instruction.
Page 211: Port Mode Register X (Pmx)
BAT32A237 User Manual | Chapter 7 Timer A 7.3.8 Port mode register x (PMx) This is a register that sets the port input/output. When the multiplexed ports (TAIO, TAO, etc.) of the timer output pin are used as the output of the timer, the corresponding bits of the port mode register (PMxx) and port register (Pxx) must be set to “0”.
Page 212: Operation Of Timer A
BAT32A237 User Manual | Chapter 7 Timer A 7.4 Operation of timer A 7.4.1 Rewriting the reload register and counter Independent of the operation mode, the rewrite timing of the reload registers and counters varies depending on the value of the TSTART bit in the TACR0 register. When the TSTART bit is “0” (stop counting), the reload register and counter are written directly.
Page 213: Timer Mode
BAT32A237 User Manual | Chapter 7 Timer A 7.4.2 Timer mode This is a mode of decreasing count by the count source selected by the TCK0~TCK2 bits of TAMR0 register. In the timer mode, the count value is decremented by 1 whenever the count source is input, and if the count value becomes “0000H”...
Page 214: Pulse Output Mode
BAT32A237 User Manual | Chapter 7 Timer A 7.4.3 Pulse output mode In this mode, the count source selected by bits TCK0 to TCK2 of the TAMR0 register is decremented to count, and the output levels of the TAIO pin and TAO pin are inverted and output whenever an underflow occurs.
Page 215: Event Counter Mode
BAT32A237 User Manual | Chapter 7 Timer A 7.4.4 Event counter mode This is a mode of decrementing counting via an external event signal (count source) input from the TAIO pin. Various settings during event counting can be made via the TIOGT0~TIOGT1 bits of TAIOC0 register and TAISR0 register, and the filter function of TAIO input can be specified via the TIPF0~TIPF1 bits of TAIOC0 register.
Page 216: Pulse Width Measurement Mode
BAT32A237 User Manual | Chapter 7 Timer A 7.4.5 Pulse width measurement mode This is a mode to measure the pulse width of the external signal input to the TAIO pin. In the pulse width measurement mode, if the level specified by the TEDGSEL bit of the TAIOC0 register is input to the TAIO pin, counting starts decreasingly by the selected counting source.
Page 217: Pulse Period Measurement Mode
BAT32A237 User Manual | Chapter 7 Timer A 7.4.6 Pulse period measurement mode This is a mode to measure the pulse period of the external signal input to the TAIO pin. The counter counts decreasingly by the count source selected by bits TCK0 to TCK2 of the TAMR0 register. If...
Page 218: Collaboration With Eventc
BAT32A237 User Manual | Chapter 7 Timer A 7.4.7 Collaboration with EVENTC By working with EVENTC, events entered by EVENTC can be set as the count source. Counting is performed on the rising edge of the event of the ELC input via bits TCK0 to TCK2 of the TAMR0 register.
Page 219: Cautions When Using Timer A
BAT32A237 User Manual | Chapter 7 Timer A 7.5 Cautions when using timer A 7.5.1 Start and stop control of counting • Event counting mode or when the counting source is set to non-EVENTC If “1” is written to the TSTART bit of the TACR0 register during the counting stop, the TCSTF bit of the TACR0 register will be “0”...
Page 220: Setting Procedure For Tao Pin And Taio Pin
BAT32A237 User Manual | Chapter 7 Timer A changed during the count. When the operation mode related registers of Timer A are changed, the values of the TEDGF and TUNDF bits are indefinite. Counting must start after writing “0” to the TEDGF bit (no valid edge) and “0” to the TUNDF bit (no underflow occurs).
Page 221: Setting Steps For Deep Sleep Mode (Event Counter Mode)
BAT32A237 User Manual | Chapter 7 Timer A 7.5.8 Setting steps for deep sleep mode (event counter mode) To make the event counter mode run in deep sleep mode, you must transfer to deep sleep mode after providing the clock for timer A by following these steps Setting steps (1) Set the operation mode.
Page 222: Chapter 8 Timer B
BAT32A237 User Manual | Chapter 8 Timer B Chapter 8 Timer B 8.1 Function of timer B Timer B has the following three modes: ⚫ Timer mode: Input capture function: Counts are made along the rising edge, the falling edge, or the double edges of the rising edge/falling edge.
Page 223: Structure Of Timer B
BAT32A237 User Manual | Chapter 8 Timer B 8.2 Structure of timer B The block diagram and pin structure of Timer B are shown in Figure 8-1 and Table 8-1, respectively. Figure 8-1: Block diagram of timer B /2, F...
Page 224: Registers For Controlling Timer B
BAT32A237 User Manual | Chapter 8 Timer B 8.3 Registers for controlling timer B The registers that control Timer B are shown in Table 8-2. Table 8-2 Registers for controlling timer B Register name Symbol Peripheral enable register 1 PER1 Timer B mode register TBMR.
Page 225: Peripheral Enable Register 1 (Per1)
BAT32A237 User Manual | Chapter 8 Timer B 8.3.1 Peripheral enable register 1 (PER1) The PER1 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 226: Timer B Mode Register (Tbmr)
BAT32A237 User Manual | Chapter 8 Timer B 8.3.2 Timer B mode register (TBMR) Figure 8-3 Format of timer B mode register (TBMR) Address: 40042650H After reset: 00H Symbol TBMR. TBDFB TBDFA TBMDF TBPWM TBSTART Start of TB count The count is stopped and the PWM output signal (TBIO0 pin) is initialized (PWM mode).
Page 227: Timer B Count Control Register (Tbcntc)
BAT32A237 User Manual | Chapter 8 Timer B 8.3.3 Timer B count control register (TBCNTC) The TBCNTC register is used in the phase count mode to set the count condition of the phase count mode. Figure 8-4 Format of timer B count control register (TBCNTC) Address: 40042651H.
Page 228: Timer B Control Register (Tbcr)
BAT32A237 User Manual | Chapter 8 Timer B 8.3.4 Timer B control register (TBCR) The TBCR register must be written with the TBSTART bit of the TBMR register at “0” (stop counting). Figure 8-5 Format of Timer B control register (TBCR)
Page 229: Timer B Interrupt Enable Register (Tbier)
BAT32A237 User Manual | Chapter 8 Timer B 8.3.5 Timer B interrupt enable register (TBIER) Figure 8-6 Format of Timer B interrupt enable register (TBIER) Address: 400426 53H. After reset: 00H Symbol TBIER TBUDIE TBIMIEB TBIMIEA Overflow interrupt enable TBOVIE Disables interrupts generated by the TBOVF bit.
Page 230: Timer B Status Register (Tbsr)
BAT32A237 User Manual | Chapter 8 Timer B 8.3.6 Timer B status register (TBSR) Figure 8-7 Format of timer B status register (TBSR) Address: 40042654H After reset: 00H Symbol TBSR TBDIRF TBOVF TBUDF TBIMFB TBIMFA Count direction flag TBDIRF The TB register performs decrement counting.
Page 231 BAT32A237 User Manual | Chapter 8 Timer B After setting the Timer B Interrupt Enable Register (TBIER) to “00H” (all interrupts are disabled), you must set the target status flag to “0”. When the timer B interrupt enable register (TBIER) is “1” (enabled) and the interrupt source status flag is “0”, the target flag bit should be set to “0”.
Page 232: Timer Bi/O Control Register (Tbior)
BAT32A237 User Manual | Chapter 8 Timer B 8.3.7 Timer BI/O control register (TBIOR) Figure 8-8 Format of timer BI/O control register (TBIOR) Address: 40042655H After reset: 00H R/W After reset: 00H R Symbol TBIOR TBBUFB TBIOB2 TBIOB1 TBIOB0 TBBUFA...
Page 233 BAT32A237 User Manual | Chapter 8 Timer B TBGRA control TBIOA1 TBIOA0 Comparison of matched pin outputs is disabled. Output “L” level. Output “H” level. Toggle output. The output comparison function is used to compare the output of the TB register and the TBGRA register.
Page 234: Timer B Counter (Tb)
BAT32A237 User Manual | Chapter 8 Timer B 8.3.8 Timer B counter (TB) The TB register is connected to the CPU by a 16-bit internal bus, so it must be accessed in 16-bit units. The TB register may be capable of incremental count, free run, periodic count, or external event count. The TB register can be cleared to “0000H”...
Page 235: Timer B General Registers A, B, C, D
BAT32A237 User Manual | Chapter 8 Timer B 8.3.9 Timer B general registers A, B, C, D (TBGRA, TBGRB, TBGRC, TBGRD) The TBGRA register and the TBGRB register are 16-bit readable and writable registers, which have the functions of output comparison register and input capture register. Function conversion is performed through the TBIOR register.
Page 236 BAT32A237 User Manual | Chapter 8 Timer B Table 8-4 TBGRA, TBGRB, TBGRC, TBGRD register functions Mode and Register Configuration Function function TBIOR (TBIOA2=1) TBGRA Input capture register (saves the value of the TB register) TBMR. (TBPWM=0) Input capture TBIOR (TBIOB2=1)
Page 237: Port Register And Port Mode Register
BAT32A237 User Manual | Chapter 8 Timer B 8.3.10 Port register and port mode register When using the multiplexed ports of the timer output pins as timer outputs, the bit of the port mode register (PMxx) and the bit of the port register (Pxx) corresponding to each port must be set to “0”.
Page 238: Operation Of Timer B
BAT32A237 User Manual | Chapter 8 Timer B Operation of timer B 8.4.1 Common matters relating to multiple modes and functions (1) Count source The counting source selection and block diagram are shown in Table 8-5 and Figure 8-11, respectively.
Page 239 BAT32A237 User Manual | Chapter 8 Timer B (2) Buffer operation The TBGRC register and the TBGRD register can be set as buffer registers for the TBGRA register and the TBGRB register by the TBBUFA bit and the TBBUFB bit of the TBIOR register, respectively.
Page 240 BAT32A237 User Manual | Chapter 8 Timer B Figure 8-13 Buffer operation for output compare function Compare matching signal TBGRC TBGRA comparator register register register TB register TBGRA register transmit TBGRC register (buffer) TBIO0 output The conditions of the above diagram are as follows: ・The TBBUFA bit of the TBIOR register is 1 (the TBGRC register is a buffer register for the TBGRA...
Page 241: Digital Filter
BAT32A237 User Manual | Chapter 8 Timer B (3) Digital filter The TBIOj input (j=0, 1) is sampled and if the signal is the same 3 times, the level is considered determined. The TBMR register must be used to select the digital filter function and sampling clock of the waveformer.
Page 242 BAT32A237 User Manual | Chapter 8 Timer B (4) Events input from EVENTC With the event input from EVENTC, Timer B performs input capture to operate B. At this time, the TBIMFB bit of the TBSR register is “1”. To use this function, the input capture function of the timer mode/phase counting mode must be selected and the TBELCICE bit of the TBMR register must be set to “1”.
Page 243: Timer Mode (Input Capture Function)
BAT32A237 User Manual | Chapter 8 Timer B 8.4.2 Timer mode (input capture function) The TB register value can be transferred to the TBGRA register and the TBGRB register after the input edge of the input capture/output compare pin (TBIO0, TBIO1) is detected. Detection edges can be selected from the rising, falling, and double edges.
Page 244: Input Selection
BAT32A237 User Manual | Chapter 8 Timer B Example of setup steps for input capture operation An example of the setup procedure for an input capture run is shown in Figure 8-15. Figure 8-15 Example of setup steps for input capture operation...
Page 245 BAT32A237 User Manual | Chapter 8 Timer B (3) Operation example An example of an input capture run is shown in Figure 8-17. In this example, the double edge is selected as the input edge for the input capture of the TBIO0 pin, the falling edge is selected as the input edge for the input capture of the TBIO1 pin, and clears the count of the TB register on the input capture of the TBGRB register.
Page 246: Timer Mode (Output Compare Function)
BAT32A237 User Manual | Chapter 8 Timer B 8.4.3 Timer mode (output compare function) This is the mode to detect whether the contents of the TB register and the contents of the TBGRA register or the TBGRB register are the same (compare match). If the contents are the same, an arbitrary level is output from the TBIO0 pin or TBIO1 pin.
Page 247 BAT32A237 User Manual | Chapter 8 Timer B (1) Example of set-up steps for comparing matched waveform outputs The setup procedure for comparing the matched waveform outputs is shown in Figure 8-18. Figure 8-18 Set-up steps for comparing matched waveform outputs...
Page 248 BAT32A237 User Manual | Chapter 8 Timer B (3) Operation example An example of the operation of the “L” level output and the “H” level output is shown in Figure 8-20. In this example, the TB register is set to free-run and outputs the “L” level when comparing match A and the “H”...
Page 249 BAT32A237 User Manual | Chapter 8 Timer B Figure 8-21 Operation example of toggle output Value of TB register Clear the counter when the TBGRB register compare matches TBGRB register TBGRA register 0000H Time TBIO1 output Toggle output TBIO0 output Toggle output www.mcu.com.cn...
Page 250: Pwm Mode
BAT32A237 User Manual | Chapter 8 Timer B 8.4.4 PWM mode The PWM mode pairing uses the TBGRA register and the TBGRB register to output the PWM waveform from the TBIO0 output pin. The output setting of the TBIOR register is not valid for output pins set to PWM mode. The “H”...
Page 251 BAT32A237 User Manual | Chapter 8 Timer B (1) Example of set-up steps for PWM mode An example of the PWM mode setup procedure is shown in Figure 8-22. Figure 8-22 Example of set-up steps for PWM mode PWM mode...
Page 252 BAT32A237 User Manual | Chapter 8 Timer B Figure 8-23 Operation example of PWM mode (1) Value of TB register Clear the counter on comparison match A. TBGRA register TBGRB register 0000H Time TBIO0 output (a) Clear counter on TBGRA register comparison match Value of TB register Clear the counter on comparison match B.
Page 253 BAT32A237 User Manual | Chapter 8 Timer B Figure 8-24 Operation example of PWM mode (2) Value of TRG register Clear the counter on comparison match B. TBGRB register TBGRA register 0000H Time TBIO0 output Write TBGRA register set Write TBGRA register set...
Page 254: Phase Counting Mode
BAT32A237 User Manual | Chapter 8 Timer B 8.4.5 Phase counting mode In phase counting mode, the external input signals' phase difference between two TBCLK0 pins and TBCLK1 pin is detected, and the TB register performs incremental/decremental counting. When the PM register's PMxx bit is set to “1” and configured for phase counting mode, the TBCLK0 and TBCLK1 pins are automatically used as external clock input pins.
Page 255 BAT32A237 User Manual | Chapter 8 Timer B (1) Example of set-up steps for phase count mode An example of the set-up step of the phase count mode is shown in Figure 8-25. Figure 8-25 Example of set-up steps for phase count mode (2) Operation example Examples of phase counting mode operation are shown in Figure 8-26 to Figure 8-29.
Page 256 BAT32A237 User Manual | Chapter 8 Timer B Figure 8-27 Operation example of phase count mode 2 ・When the value of the TBCNTC register is TBCLK1 input TBCLK0 input Value of TB register increment decrement Time Figure 8-28 Operation example of phase count mode 3 ・When the value of the TBCNTC register is...
Page 257: Timer B Interrupt
BAT32A237 User Manual | Chapter 8 Timer B 8.5 Timer B interrupt Timer b generate a timer b interrupt request from four interrupt sources. The relevant registers for timer B interrupts are shown in Table 8-16, and the block diagram for timer B interrupts is shown in Figure 8-30.
Page 258 BAT32A237 User Manual | Chapter 8 Timer B should be cleared. • Status of timer B interrupt enable register (TBIER) Enable Interrupt — — — — TBOVIE TBIMIEB TBIMIEA TBUDIE TBIER Disable interrupt • Status of timer B status register (TBSR) Bit to clear request —...
Page 259: Cautions On Using Timer B
BAT32A237 User Manual | Chapter 8 Timer B 8.6 Cautions on using timer B 8.6.1 Phase difference, overlap and pulse width in phase counting mode TBCLK0 and TBCLK1 external input signals must have a phase difference and overlap of at least 1.5 each, with a pulse width of at least 2.5 F...
Page 260: Set-Up Steps For Tbio0 And Tbio1 Pins
BAT32A237 User Manual | Chapter 8 Timer B 8.6.4 Set-up steps for TBIO0 and TBIO1 pins After reset, the multiplexed I/O ports on the TBIO0 pin and TBIO1 pin are used as input ports. • To output from the TBIO0 pin and the TBIO1 pin, the following procedure must be followed.
Page 261: Read And Write Access To Sfr
BAT32A237 User Manual | Chapter 8 Timer B 8.6.6 Read and write access to SFR To set up Timer B, it is necessary to first set the TMBEN bit in the PER1 register to “1”. When the TMBEN bit is “0”, write operations to the control registers of Timer B are ignored, and the read values are all initial values (except...
Page 262: Chapter 9 Timer C
BAT32A237 User Manual | Chapter 9 Timer C Chapter 9 Timer C 9.1 Function of timer C Timer C is a timer that can perform input capture functions triggered by software, Comparator 1, and Timer M. The actions are as follows:...
Page 263: Structure Of Timer C
BAT32A237 User Manual | Chapter 9 Timer C 9.2 Structure of timer C The block diagram of timer C is shown in Figure 9-1. Figure 9-1 Block diagram of timer C Timer C Counter source selection Timer control Trigger event from Timer M Trigger event from Comparator 1 www.mcu.com.cn...
Page 264: Registers For Controlling Timer C
BAT32A237 User Manual | Chapter 9 Timer C 9.3 Registers for controlling timer C The registers for controlling timer C are shown in Table 9-1. Table 9-1 Registers for controlling timer C Register name Symbol Peripheral enable register 1 PER1...
Page 265: Timer C Count Register (Tc)
BAT32A237 User Manual | Chapter 9 Timer C 9.3.2 Timer C count register (TC) This is a 16-bit register. When writing to this register, the data is written to the reload register. When reading from this register, the count value is read.
Page 266: Timer C Control Register 1 (Tccr1)
BAT32A237 User Manual | Chapter 9 Timer C 9.3.4 Timer C control register 1 (TCCR1) Figure 9-5: Format of timer C control register 1 (TCCR1) Address: 0x40042C54 After reset: 00H Symbol TCCR1 TCK2 TCK1 TCK0 START_MD TRIG_MD_SW TRIG_MD_HW TM_TRIG OVIE...
Page 267: Timer C Control Register 1 (Tccr2)
BAT32A237 User Manual | Chapter 9 Timer C 9.3.5 Timer C control register 1 (TCCR2) Figure 9-6: Format of timer C control register 1 (TCCR2) Address: 0x40042C55 After reset: 00H Symbol TCCR2 CMP_TCR1 CMP_TCR0 TSAT Action selection when Timer C is triggered by the output of...
Page 268: Timer C Status Register (Tcsr)
BAT32A237 User Manual | Chapter 9 Timer C 9.3.6 Timer C status register (TCSR) Figure 9-7: Format of timer C status register (TCSR) Address: 0x40042C56 After reset: 00H Symbol TCSR TCSB TCOVF Timer C counter status flag Note 1 TCSB...
Page 269: Operation Of Timer C
BAT32A237 User Manual | Chapter 9 Timer C 9.4 Operation of timer C Timer C can be triggered to start counting by the signal of Timer M and stop counting by the signal of Comparator 1. 9.4.1 Count source The action clock of Timer C is determined by the option byte and the prescaler setting of Timer C.
Page 270: Setting And Action Of Triggering With Timer M Signal
BAT32A237 User Manual | Chapter 9 Timer C 9.4.2.1 Setting and action of triggering with timer M signal When TRIG_MD_HW=0, the steps for resetting and starting the counting of Timer C are as follows: Select Timer M output signal as the trigger source for counting start: TCCR1.START_MD=1 Select the trigger function for Timer C: TCCR1.TRIG_MD_HW=0...
Page 271: Setting And Action For Software Triggering
BAT32A237 User Manual | Chapter 9 Timer C 9.4.2.2 Setting and action for software triggering: 1. Select software trigger as the counting start source: TCCR1.START_MD=0 2. Start the counting of Timer C: TCCR2.TSTART=1 Figure 9-10 Example of starting Timer C counting by software triggering TC counting source TCCR1.START_MD...
Page 272: Actions To Stop Timer C Counting
BAT32A237 User Manual | Chapter 9 Timer C 9.4.3 Actions to stop timer C counting While Timer C is counting, the counting action can be stopped either by the trigger of Comparator 1 or by software settings. 9.4.3.1 Setting and action when selecting comparator 1 as the trigger 1.
Page 273: Input Capture Action
BAT32A237 User Manual | Chapter 9 Timer C 9.4.4 Input capture action If an interrupt is generate by that comparator 1 during the Timer C action, the action of the Timer C may change. Case 1: When TCCR2.CMP1_TCR=01, the count value of Timer C is transferred to the count buffer.
Page 274: Timer C Count Reset Action
BAT32A237 User Manual | Chapter 9 Timer C 9.4.5 Timer C count reset action When initiating Timer C action through software settings, the output signal of Timer M and the output signal of Comparator 1 can reset Timer C’ s counter.
Page 275 BAT32A237 User Manual | Chapter 9 Timer C (3) When TCCR2.CMP1_TCR=10, the output signal of CMP1 resets the count value. 1) Count value reset, count action continues: TCCR2.CMP1_TCR=10 (input capture cannot be used) 2) Timer C count start: TCCR2.TSTART=1 Figure 9-16 Example of CMP1 triggering Timer C count reset TC counting source TCCR2.CMP1_TCR...
Page 276: Timer C Interrupt
BAT32A237 User Manual | Chapter 9 Timer C 9.4.6 Timer C interrupt When an overflow occurs in the counter of Timer C, an overflow interrupt signal is generated if TCCR1.OVIE=1 is set. Figure 9-17 Example of interrupt generation on Timer C overflow...
Page 277: Cautions On Using Timer C
BAT32A237 User Manual | Chapter 9 Timer C 9.5 Cautions on using timer C 9.5.1 Register reading and writing To set Timer C, the TMCEN bit of the PER1 must be set to “1” first. When the TMCEN bit is “0”, write operations to the control register of Timer C are ignored, and the read values are initialized.
Page 278: Chapter 10 Timer M
BAT32A237 User Manual | Chapter 10 Timer M Chapter 10 Timer M 10.1 Function of timer M Timer M has the following four modes: • Timer mode Input capture function: An external signal is used as a trigger to fetch the count value to the register.
Page 279: Structure Of Timer M
BAT32A237 User Manual | Chapter 10 Timer M 10.2 Structure of timer M The block diagram and pin structure of Timer M are shown in Figure 10-1 and Table 10-1, respectively. Figure 10-1 Block diagram of timer M /2, F...
Page 280: Registers For Controlling Timer M
BAT32A237 User Manual | Chapter 10 Timer M 10.3 Registers for controlling timer M The registers that control Timer M are shown in Table 10-2. Table 10-2 Register for controlling timer M Register name Symbol Peripheral enable register 1 PER1...
Page 281: Peripheral Enable Register 1 (Per1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.1 Peripheral enable register 1 (PER1) The PER1 register is a register that is set to enable or disable supplying clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 282: Timer M Eventc Register (Tmelc)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.2 Timer M EVENTC register (TMELC) Figure 10-3 Format of timer M EVENTC register (TMELC) Note Address: 0x40042A60 After reset: 00H Symbol TMELC ELCOBE1 ELCICE1 ELCOBE0 ELCICE0 ELCOBE1 EVENTC event input 1 (for forced cutoff of the pulse output of timer M) Disable forced cutoff.
Page 283: Timer M Start Register (Tmstr)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.3 Timer M start register (TMSTR) The TMSTR register can be set by an 8-bit memory manipulation instruction. Refer to “10.7.1(1) TMSTR Register” for precautions when using Timer M. Figure 10-4 Format of timer M start register (TMSTR)
Page 284: Timer M Mode Register (Tmmr)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.4 Timer M mode register (TMMR) Figure 10-5 Format of timer M mode register (TMMR) Note 1 Address: 0x40042A64 After reset: 00H Symbol TMMR. TMBFD1 TMBFC1 TMBFD0 TMBFC0 TMSYNC Note 2 TMBFD1...
Page 285: Timer M Pwm Function Selection Register (Tmpmr)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.5 Timer M PWM function selection register (TMPMR) Figure 10-6 Format of Timer M PWM function selection register (TMPMR) [timer mode] Note Address: 0x40042A65 After reset: 00H Symbol TMPMR. TMPWMD1 TMPWMC1 TMPWMB1...
Page 286: Timer M Function Control Register (Tmfcr)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.6 Timer M function control register (TMFCR) Figure 10-7 Format of timer M function control register (TMFCR) Note 1 Address: 0x40042A66 After reset: 80H Symbol TMFCR PWM3 STCLK OLS1 OLS0 CMD1 CMD0...
Page 287: Timer M Output Master Enable Register 1 (Tmoer1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.7 Timer M output master enable register 1 (TMOER1) Figure 10-8 Format of Timer M output master enable register 1 (TMOER1) [Output compare function, PWM function, reset sync PWM mode, complementary PWM mode and PWM3 mode]...
Page 288: Timer M Output Master Enable Register 2 (Tmoer2)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.8 Timer M output master enable register 2 (TMOER2) Figure 10-9 Format of Timer M output master enable register 2 (TMOER2) [PWM function, reset sync PWM mode, complementary PWM mode, and PWM3 mode]...
Page 289: Timer M Output Control Register (Tmocr)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.9 Timer M output control register (TMOCR) The TMOCR register must be written when both the TSTART0 bit and the TSTART1 bit of the TMSTR register are “0” (stop counting). Figure 10-10 Format of Timer M output control register (TMOCR) [output compare function]...
Page 290 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-11 Format of Timer M output control register (TMOCR) [PWM function] Note 1 Address: 0x40042A69 After reset: 00H Symbol TMOCR TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 Note 2 TOD1 Selection of TMIOD1 initial output level The initial output is an invalid level.
Page 291 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-12 Format of Timer M output control register (TMOCR) [PWM3 mode] Note 1 Address: 0x40042A69 After reset: 00H Symbol TMOCR TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 TOD1 Selection of TMIOD1 initial output level Invalid in PWM3 mode.
Page 292: Timer M Digital Filter Function Selection Register I (Tmdfi) (I=0,1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.10 Timer M digital filter function selection register i (TMDFi) (i=0,1) Figure 10-13 Format of Timer M digital filter function selection register i (TMDFi) (i=0,1) [input capture] Note 1 Address: 0x40042A6A (TMDF0), 0x40042A6B (TMDF1) After reset: 00H...
Page 293 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-14 Format of Timer M digital filter function selection register i(TMDFi) (i=0,1) [PWM function, reset synchronous PWM mode, complementary PWM mode and PWM3 mode] Note 1 Address: 0x40042A6A (TMDF0), 0x40042A6B (TMDF1) After reset: 00H...
Page 294: Timer M Control Register I (Tmcri) (I=0,1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.11 Timer M control register i (TMCRi) (i=0,1) The TMCR1 register is not used in the reset synchronous PWM mode and the PWM3 mode. Figure 10-15 Format of Timer M control register i (TMCRi) (i=0,1)
Page 295 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-16 Format of Timer M control register i (TMCRi) (i=0,1) [PWM function] Note 1 Address: 0x40042A70 (TMCR0), 0x40042A80 (TMCR1) After reset: 00H Symbol TMCRi CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1...
Page 296 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-17 Format of Timer M control register 0 (TMCR0) [reset synchronous PWM mode] Note1 Address: 0x40042A70 After reset: 00H Symbol TMCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1...
Page 297 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-18 Format of Timer M control register 0 (TMCR0) [complementary PWM mode] Note 1 Address: 0x40042A70 After reset: 00H Symbol TMCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1...
Page 298 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-19 Format of Timer M control register 0 (TMCR0) [PWM3 mode] Note 1 Address: 0x40042A70 After reset: 00H Symbol TMCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1 CCLR0 Clear Selection of TM0 Counter Set to “001B ”...
Page 299: Timer M I/O Control Register Ai(Tmiorai) (I=0,1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.12 Timer M I/O control register Ai(TMIORAi) (i=0,1) Figure 10-20 Format of Timer MI/O control register Ai (TMIORAi) (i=0,1) [input capture function] Note 1 Address: 0x40042A71 (TMIORA0), 0x40042A81H (TMIORA1) After reset: 00H...
Page 300 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-21 Format of Timer MI/O control register Ai (TMIORAi) (i=0,1) [output compare function] Note 1 Address: 0x40042A71 (TMIORA0), 0x40042A81H (TMIORA1) After reset: 00H Symbol TMIORAi IOB2 IOB1 IOB0 IOA2 IOA1 IOA0...
Page 301: Timer M I/O Control Register Ci(Tmiorci) (I=0,1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.13 Timer M I/O control register Ci(TMIORCi) (i=0,1) Figure 10-22 Format of Timer M I/O control register Ci(TMIORCi) (i=0,1) [input capture function] Note 1 Address: 0x40042A72 (TMIORC0), 0x40042A82 (TMIORC1) After reset: 88H...
Page 302 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-23 Format of Timer M I/O control register Ci (TMIORCi) (i=0,1) [output compare function] Note 1 Address: 0x40042A72 (TMIORC0), 0x40042A82 (TMIORC1) After reset: 88H Symbol TMIORCi IOD3 IOD2 IOD1 IOD0 IOC3...
Page 303: Timer M Status Register 0 (Tmsr0)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.14 Timer M status register 0 (TMSR0) Figure 10-24 Format of Timer M status register 0 (TMSR0) [input capture function] Note 1 Address: 0x40042A73 After reset: 00H Symbol TMSR0 IMFD IMFC IMFB...
Page 304 BAT32A237 User Manual | Chapter 10 Timer M Note 3: The results of writing are as follows: The bit remains unchanged when “1” is written. • When the read value is “0”, even if the same bit is written as “0”, it remains unchanged (in the •...
Page 305 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-25 Format of Timer M status register 0 (TMSR0) [functions other than input capture] Note 1 Address: 0x40042A73 After reset: 00H Symbol TMSR0 IMFD IMFC IMFB IMFA Note 3 Overflow flag [When the condition is “0”]...
Page 306 BAT32A237 User Manual | Chapter 10 Timer M interrupt enable — — — OVIE IMIED IMIEC IMIEB IMIEA TMIERi interrupt disable • Status of Timer M status register i (TMSRi) Bit to clear requests — — IMFD IMFC IMFB IMFA...
Page 307: Timer M Status Register 1 (Tmsr1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.15 Timer M status register 1 (TMSR1) Figure 10-26 Format of Timer M status register 1 (TMSR1) [input capture function] Note 1 Address: 0x40042A83 After reset: 00H Symbol TMSR1 IMFD IMFC IMFB...
Page 308 BAT32A237 User Manual | Chapter 10 Timer M The bit remains unchanged when “1” is written. Note 3: When the read value is “0”, even if the same bit is written as “0”, it remains unchanged (in the • case where it changes from “0” to “1” after reading, even if “0” is written, it remains “1”).
Page 309 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-27 Format of Timer M status register 1 (TMSR1) [input capture] Note 1 Address: 0x40042A83 After reset: 00H Symbol TMSR1 IMFD IMFC IMFB IMFA Underflow flag Complementary PWM mode [When the condition is “0”] Write “0”...
Page 310 BAT32A237 User Manual | Chapter 10 Timer M • Status of Timer M interrupt enable register i (TMIERi) interrupt enable — — — OVIE IMIED IMIEC IMIEB IMIEA TMIERi interrupt disable • Status of Timer M status register i (TMSRi)
Page 311: Tmer M Interrupt Enable Register I (Tmieri) (I=0,1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.16 Tmer m interrupt enable register i (TMIERi) (i=0,1) Figure 10-28 Format of Timer M interrupts the format of register i(TMIERi) (i=0,1) Note Address: 0x40042A74 (TMIER0), 0x40042A84 (TMIER1) After reset: 00H Symbol...
Page 312: Timer Mpwm Function Output Level Control Register I (Tmpocri) (I=0,1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.17 Timer MPWM function output level control register i (TMPOCRi) (i=0,1) The TMPOCRi register settings are valid only when using the PWM function, otherwise the TMPOCRi register settings are not valid. Figure 10-29 Format of Timer MPWM function output level control register i (TMPOCRi) (i=0,1) [PWM]...
Page 313: Timer M Counter I (Tmi) (I=0,1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.18 Timer M counter i (TMi) (i=0,1) [Timer mode] The TMi register must be accessed in 16-bit units and not in 8-bit units. [Reset synchronous PWM mode and PWM3 mode] The TM0 register must be accessed in 16-bit units and not in 8-bit units. The TM1 register is not used in reset synchronous PWM mode and PWM3 mode.
Page 314 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-32 Format of Timer M Counter i(TMi) (i=0,1) [complementary PWM mode (TM0)] Note Address: 0x40042A76(TM0), 0x40042A86(TM1) After reset: 0000H Symbol — Function Set range The dead time must be set. The count source is incremented or decremented.
Page 315: Timer M General Register Ai, Bi, Ci, Di (Tmgrai, Tmgrbi, Tmgrci, Tmgrdi) (I=0,1)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.19 Timer m general register Ai, Bi, Ci, Di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) [Input capture feature] The TMGRAi~TMGRDi register must be accessed in 16-bit units and not in 8-bit units. The following registers...
Page 316 BAT32A237 User Manual | Chapter 10 Timer M [PWM3 mode] The TMGRAi~TMGRDi register must be accessed in 16-bit units and not in 8-bit units. In PWM3 mode, the following registers are invalid: TMPMR, TMDF0, TMDF1, TMIORA0, TMIORC0, TMPOCR0, TMIORA1, TMIORC1, TMPOCR1 In PWM3 mode, TMGRC0, TMGRC1, TMGRD0, TMGRD1 registers are not used.
Page 317 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-35 Format of Timer M general register Ai, Bi, Ci, Di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) [output compare function] Note Address: After reset: FFFFH 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0),...
Page 318 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-36 Format of Timer m general register Ai, Bi, Ci, Di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) [PWM] Note Address: After reset:FFFFH 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0), 0x40042A88 (TMGRA1), 0x40042A8A (TMGRB1),...
Page 319 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-37 Format of Timer m general register Ai, Bi, Ci, Di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) [reset synchronous PWM mode] Note Address: After reset:FFFFH 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0),...
Page 320 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-38 Format of Timer m general register Ai, Bi, Ci, Di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) [complementary PWM mode] Note Address: After reset:FFFFH 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0),...
Page 321 BAT32A237 User Manual | Chapter 10 Timer M Table 10-7 TMGRji register function in complementary PWM mode Register Configuration Register function PWM output pin General-purpose register that must be set for PWM period at initial setup. (Perform TMIOC0 Setting range: Setting value of TM0 register (count initial value) ≤...
Page 322 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-39 Format of Timer M general register Ai, Bi, Ci, Di(TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) [PWM3 mode] Note Address: After reset:FFFFH 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0), 0x40042A88 (TMGRA1), 0x40042A8A (TMGRB1),...
Page 323 BAT32A237 User Manual | Chapter 10 Timer M Table 10-8 TMGRji register function in PWM3 mode Register Configuration Register function PWM output pin General register, PWM cycle must be set. Setting range: TMGRA1 register setting value ≤ TMGRA0 setting TMGRA0...
Page 324: Port Mode Registers (Pmxx, Pmcxx)
BAT32A237 User Manual | Chapter 10 Timer M 10.3.20 Port mode registers (PMxx, PMCxx) These are the registers that set the input/output or analog input of the port. When using the multiplexed ports (Pxx/TMIOD1, Pxx/TMIOC1, etc.) of the timer output pins as timer outputs, the bit of the port mode register (PMxx, PMCxx) and the bit of the port register (Pxx) corresponding to each port must be set to “0”.
Page 325: Matters Common To Multiple Modes
BAT32A237 User Manual | Chapter 10 Timer M 10.4 Matters common to multiple modes 10.4.1 Count source The method of selecting the counting source is the same for all modes. However, an external clock cannot be selected in PWM3 mode.
Page 326: Buffer Operation
BAT32A237 User Manual | Chapter 10 Timer M 10.4.2 Buffer operation The TMGRCi register and the TMGRDi register can be set as the buffer register of the TMGRAi register and the TMGRBi register through the TMBFCi (i=0, 1) and TMBFDi bits of the TMMR register.
Page 327 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-42 Buffer operation for input capture TMIOAi input (input capture signal) TMGRAi TMGRCi register (buffer) register TMIOAi input TMi register transfer TMGRAi register transfer TMGRCi register (buffer) Remark: i=0, 1 The conditions in the above diagram are as follows: The TMBFCi bit of the TMMR register is “1”...
Page 328 BAT32A237 User Manual | Chapter 10 Timer M In timer mode (input capture function and output comparison function), the following settings must be made. Use TMGRCi (i=0,1) registers as buffer registers for TMGRAi registers: • The IOC3 bit of the TMIORCi register must be set to “1” (general purpose register or buffer register).
Page 329: Synchronous Operation
BAT32A237 User Manual | Chapter 10 Timer M 10.4.3 Synchronous operation Synchronize the TM0 register with the TM1 register. • Synchronized presets If the TMi register is written when the TMSYNC bit of the TMMR register is “1” (synchronous operation), data is written to both the TM0 register and the TM1 register.
Page 330: Forced Cutoff Of Pulse Output
BAT32A237 User Manual | Chapter 10 Timer M 10.4.4 Forced cutoff of pulse output When using the PWM function or in reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, it is possible to cut off the pulse output of the TMIOji output pins (i=0, 1, j=A, B, C, D) by the input of the INTP0 pin.
Page 331 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-45 Forced cutoff of pulse output ELCOBE0 DFCK1，DFCK0 EVENTC event input 0 TMSHUTS bit TIMER M output data INTP0 input TMIOA0 Multiplex I/O TMPTO port output data HI-Z select signal ELCOBE1...
Page 332: Events Input From The Event Linkage Controller (Eventc)
BAT32A237 User Manual | Chapter 10 Timer M 10.4.5 Events input from the event linkage controller (EVENTC) The timer M performs 2 types of operation by the event input of EVENTC. Input capture for TMIOD0/TMIOD1 Timer M performs TMIOD0/TMIOD1 input capture by the event input from EVENTC. At this time, the IMFD bit of the TMSRi register is “1”.
Page 333: Events Output To Event Link Controller (Eventc)/Direct Memory Access (Dma)
BAT32A237 User Manual | Chapter 10 Timer M 10.4.6 Events output to event link controller (EVENTC)/direct memory access (DMA) The modes of Timer M and the events output to EVENTC/DMA are shown in Table 10-11. Table 10-11 Mode of timer M and event output to ELC/DMA...
Page 334: Operation Of Timer M
BAT32A237 User Manual | Chapter 10 Timer M 10.5 Operation of timer M 10.5.1 Input capture function This is a function to measure the width and period of an external signal. An external signal at the TMIOji pin (i=0, 1, j=A, B, C, D) is used as a trigger to transfer the TMi register (counter) to the TMGRji register (input capture).
Page 335 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-46 Block diagram of input capture function www.mcu.com.cn 335 / 1066 V1.0.4...
Page 336 BAT32A237 User Manual | Chapter 10 Timer M Table 10-12 Specification of the input capture function Item Specification Note /2, F /4, F /8, F HOCO Count source External input signal to the TMCLK pin (active edge selected by program)
Page 337: Operation Example
BAT32A237 User Manual | Chapter 10 Timer M Operation example By setting the CCLR0~CCLR2 bits of the TMCRi register (i=0, 1), the count value of timerMi is reset when an input capture or comparison match occurs. Figure 10-47 shows an example of operation when the CCLR2~CCLR0 bits are set to “001B”.
Page 338 BAT32A237 User Manual | Chapter 10 Timer M Digital filter The TMIOji inputs (i=0, 1. j=A, B, C, D.) are sampled and if the signal is the same for 3 times, the level is considered to be determined. The function of the digital filter and the sampling clock must be selected via the TMDFi register.
Page 339: Output Compare Function
BAT32A237 User Manual | Chapter 10 Timer M 10.5.2 Output compare function This is a mode to detect whether the contents of TMi registers (counters) (i=0,1) and TMGRji registers (j=A,D) are same (compare matching). If the contents are the same, output any level from the TMIOji pin. Because the TMIOji pin and the TMGRji register are used in combination, the pin can be selected as the output comparison function, or other modes and functions.
Page 340 BAT32A237 User Manual | Chapter 10 Timer M Table 10-13 Output Comparison Feature Specifications Item Specification Note /2, F /4, F /8, F HOCO Count source External input signal to the TMCLK pin (active edge selected by program) Count Incremental count •...
Page 341 BAT32A237 User Manual | Chapter 10 Timer M Operation example Setting the CCLR0~CCLR2 bits of the TMCRi register (i=0, 1) resets the count value of timer Mi when an input capture or comparison match occurs. If the comparison expected value is “FFFFH”, it will be changed from “FFFFH"...
Page 342 BAT32A237 User Manual | Chapter 10 Timer M The conditions in the above diagram are as follows: The CSELi bit of the TMSTR register is “1” (TMi does not stop when comparing matches). The TMBFCi and TMBFDi bits of the TMMR register are “0” (TMGRCi and TMGRDi do not operate as buffers).
Page 343 BAT32A237 User Manual | Chapter 10 Timer M Change of output pins of TMGRCi register and TMGRDi register (i=0, 1) The TMGRCi register and the TMGRDi register can be used for the output control of the TMIOAi pin and the TMIOBi pin, respectively. Therefore, each pin can be output control as follows: •...
Page 344 BAT32A237 User Manual | Chapter 10 Timer M • Set the TMBFji bit of the TMMR register to "0" (general purpose register). • Set different values for the TMGRAi register and the TMGRCi register, and set different values for the TMGRBi register and the TMGRDi register.
Page 345 BAT32A237 User Manual | Chapter 10 Timer M The conditions in the above diagram are as follows: The CSELi bit of the TMSTR register is “1” (TMi does not stop when comparing matches). The TMBFCi and TMBFDi bits of the TMMR register are “0” (TMGRCi and TMGRDi do not operate as buffers).
Page 346: Pwm Function
BAT32A237 User Manual | Chapter 10 Timer M 10.5.3 PWM function This is the function of the output PWM waveform. Up to 3 PWM waveforms can be output through the timer Mi (i=0,1). By synchronizing the timer M0 with the timer M1, up to 6 PWM waveforms can be output in the same cycle.
Page 347 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-53 Block diagram of PWM function www.mcu.com.cn 347 / 1066 V1.0.4...
Page 348 BAT32A237 User Manual | Chapter 10 Timer M Table 10-14 Specification of PWM function Item Specification Note /2, F /4, F /8,F HOCO Count source External input signal at TMCLK pin (active edge can be selected by program) Count Incremental count PWM period: 1/fk×(m+1)
Page 349 BAT32A237 User Manual | Chapter 10 Timer M Operation example Figure 10-54 Operation example of PWM function Counting source Tmi register value Time "L" voltage is invalid TMIOBi output "H" level is valid Initially output "L" voltage level before compare matching TMIOCi output Initially output "H"...
Page 350: Reset Synchronous Pwm Mode
BAT32A237 User Manual | Chapter 10 Timer M Figure 10-55 Example of PWM function operation (duty cycle 0% and 100%) TMi寄存器的值 TMi register value Time TSTRATi bit of TMSTR register 因为不发生TMGRBi寄存器的比较匹配， TMIOBi does not output an L level because no 所以TMIOBi不输出...
Page 351 BAT32A237 User Manual | Chapter 10 Timer M This mode outputs 3 non-reverse and 3 reverse (total of 6) PWM waveforms of the same period (three-phase, sawtooth wave modulation, no dead time). The block diagram and the operation example of the reset synchronous PWM mode are shown in Figure 10-56 and Figure 10-57 respectively, and the specification of the reset synchronous PWM mode is shown in Table 10-15.
Page 352 BAT32A237 User Manual | Chapter 10 Timer M Table 10-15 Reset synchronous PWM mode specifications Item Specification Note /2, F /4, F /8, F HOCO Count source External input signal at TMCLK pin (active edge can be selected by program) Count TM0 is an incremental count (TM1 is not used).
Page 353 BAT32A237 User Manual | Chapter 10 Timer M Operation example Figure 10-57 Operation example of reset synchronous PWM mode Counting source TMi寄存器的值 TMi register value Time TSTRATi bit of TMSTR register TMIOB0 output TMIOD0 output TMIOA1 output TMIOC1 output TMIOB1 output...
Page 354: Complementary Pwm Mode
BAT32A237 User Manual | Chapter 10 Timer M 10.5.5 Complementary PWM mode This mode outputs 3 non-reverse and 3 reverse (total of 6) PWM waveforms of the same period (three-phase, triangular wave modulation with dead time). The block diagram of the complementary PWM mode is shown in Figure 10-58, the specifications of the complementary PWM mode are shown in Table 10-16, and the output model and operation example of the complementary PWM mode are shown in Figure 10-59 and Figure 10-60, respectively.
Page 355 BAT32A237 User Manual | Chapter 10 Timer M Table 10-16 Complementary PWM mode specification Item Specification Note 1 /2, F /4, F /8, F HOCO External input signal at TMCLK pin (active edge can be selected by program) count source The same value (same count source) must be set for the TCK0~TCK2 bits of the TMCR0 register and the TCK0~TCK2 bits of the TMCR1 register.
Page 356 BAT32A237 User Manual | Chapter 10 Timer M Operation example Figure 10-59 Output mode of complementary PWM mode TMi register value The value of the TM0 register The value of the TMGRA0 register The value of the TM1 register The value of the TMGRB0 register...
Page 357 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-60 Operation example of complementary PWM mode Counting source TMi register value TM0 register value TM1 register value Time change to FFFFH TSTRATi bit of TMSTR register TMIOB0 output Initially output H voltage level "L"...
Page 358 BAT32A237 User Manual | Chapter 10 Timer M Data transfer timing for buffer registers The data transfer from the TMGRD0, TMGRC1, TMGRD1 registers to the TMGRB0, TMGRA1, TMGRB1 registers occurs when the CMD1 and CMD0 bits of the TMFCR register are “10B” and there is an underflow in TM1.
Page 359: Pwm3 Mode
BAT32A237 User Manual | Chapter 10 Timer M 10.5.6 PWM3 mode This mode outputs 2 PWM waveforms of the same period. The block diagram and operation example of PWM3 mode are shown in Figure 10-61 and Figure 10-62, respectively, and the specification of PWM3 mode is shown in Table 10-17.
Page 360 BAT32A237 User Manual | Chapter 10 Timer M Table 10-17 PWM3 mode specification Item Specification Note Count source /2, F /4, F /8, F HOCO Count TM0 is an incremental count (TM1 is not used). PWM period: 1/fk × (m+1) Active level width of TMIOA0 output: 1/fk×(m-n)
Page 361 BAT32A237 User Manual | Chapter 10 Timer M Operation example Figure 10-62 Operation example of PWM3 mode Counting source TMi register value Time TSTRAT0 bit of TMSTR register Stop counting Set to 0 by program CSEL0 bit of TMSTR register initial output "H"...
Page 362: Timer M Interrupt
BAT32A237 User Manual | Chapter 10 Timer M 10.6 Timer M interrupt Timer M generates Timer Mi (i=0, 1) interrupt requests from each of the six interrupt sources of Timer M0 and Timer M1. The registers associated with the Timer M interrupt are shown in Table 10-18, and the block diagram of the Timer M interrupt is shown in Figure 10-63.
Page 363 BAT32A237 User Manual | Chapter 10 Timer M “00H” (disabling all interrupts). When there is a bit set to “1” (enabled) in the Timer M interrupt enable register i (TMIERi) and the interrupt source status flag of that bit is “0”, the target status flag must be set to “0”.
Page 364: Cautions On Using Timer M
BAT32A237 User Manual | Chapter 10 Timer M 10.7 Cautions on using timer M 10.7.1 Read and write access to SFR To set timer M, the TMMEN bit of the PER1 register must be set to “1” first. When the TMMEN bit is “0”, the write operation of the control register of timer M is ignored and the read values are all initialized (except for the Port Register and Port Mode Register).
Page 365: Mode Switching
BAT32A237 User Manual | Chapter 10 Timer M 10.7.2 Mode switching • To switch modes during operation, switching must be done after entering the counting stop state (setting the TSTART0 and TSTART1 bits to “0”). • Before changing the TSTART0 and TSTART1 bits from “0” to “1”, the TMIF0 and TMIF1 bits must be set to “0”.
Page 366 BAT32A237 User Manual | Chapter 10 Timer M TMIODi pins to the input mode (input from the TMIOAi, TMIOBi, TMIOCi, and TMIODi pins). Set to input capture function. Start counting (Set TSTART0 and TSTART1 bits to “1”). • When switching the TMIOAi, TMIOBi, TMIOCi, and TMIODi pins from output mode to input mode, input capture may be run depending on the state of the pins.
Page 367: External Clock Tmclk
BAT32A237 User Manual | Chapter 10 Timer M 10.7.6 External clock TMCLK The pulse width of the external clock input to the TMCLK pin must be at least 3 timer M operation clock cycles. Reset synchronous PWM mode • When this mode is used for motor control, the condition OLS0=OLS1 must be meet.
Page 368 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-64 Operation example of TM0 and TMGRA0 register caompare matching in complementary PWM mode TM0 register counting value configure value m of TMGRA0 register Time set to 0 by program remain unchanged...
Page 369 BAT32A237 User Manual | Chapter 10 Timer M • The timing of the data transfer from the buffer register to the general-purpose register must be selected by the CMD0 and CMD1 bits of the TMFCR register. However, in the case of 0% duty cycle and 100% duty cycle, independent of the values of the CMD0 bit and CMD1 bit, is the following transfer timing.
Page 370 BAT32A237 User Manual | Chapter 10 Timer M outputting the PWM waveform, the value of the buffer register is transferred to the general register through the timing set by the CMD0 bit. However, you cannot set non-reverse 100% duty cycle and reverse 0% duty cycle output with the initial value 'FFFFH' of the buffer register.
Page 371 BAT32A237 User Manual | Chapter 10 Timer M the timing set by the CMD0 bit. It is not possible to change the output directly from non-reverse 0% duty cycle and reverse 100% duty cycle to non-reverse 100% duty cycle and reverse 0% duty cycle.
Page 372: Pwmop
BAT32A237 User Manual | Chapter 10 Timer M 10.8 PWMOP The PWMOP unit enables the TimerM output forced cutoff function. The cutoff source can be selected from CMP0, INTP0 and EVENT. This is different from the pulse forced cutoff function of TimerM itself.
Page 373: Function Of Pwmop
BAT32A237 User Manual | Chapter 10 Timer M 10.8.1 Function of PWMOP PWMOP enables the following functions: The output of comparator 0, the INTP0 input, and the event input of EVENTC can be selected as the output forced cutoff source.
Page 374 BAT32A237 User Manual | Chapter 10 Timer M (1) PWMOP control register 0 (OPCTL0) Figure 10-69 Format of PWMOP control register 0 Address: 0x40043C58 After reset: 00H Symbol HAZARD_S IN_EG IN_SEL1 IN_SEL0 HZ_REL HS_SEL OPCTL0 Note 1 HAZARD_SET Output force cutoff hazard control...
Page 375 BAT32A237 User Manual | Chapter 10 Timer M HS_REL Output forced cutoff mode selection Hardware release: When the hardware is used to release the forced cut-off of the output, the timing is different according to the different operation modes of the timer M.
Page 376 BAT32A237 User Manual | Chapter 10 Timer M (2) PWMOP force cutoff control register 0 (OPDF0) Figure 10-70 Format of PWMOP forced cutoff control register 0 Address: 0x40043C59 After reset: 00H Symbol OPDF0 DFD01 DFD00 DFC01 DFC00 DFB01 DFB00 DFA01...
Page 377 BAT32A237 User Manual | Chapter 10 Timer M (3) PWMOP force cutoff control register 1 (OPDF1) Figure 10-71 Format of PWMOP forced cutoff control register 1 Address: 0x40043C5A After reset: 00H Symbol PDF1 DFD11 DFD10 DFC11 DFC10 DFB11 DFB10 DFA11...
Page 378 BAT32A237 User Manual | Chapter 10 Timer M (4) PWMOP edge selection register (OPEDGE) When the timer M is in complementary PWM mode and the output is forced cutoff by hardware release, the release time point can be set by the OPEDGE register.
Page 379: Operation Of Pwmop
BAT32A237 User Manual | Chapter 10 Timer M 10.8.3 Operation of PWMOP The output of comparator 0, the INTP0 input, and the event input of EVENTC can be selected as the output forced cutoff source. Edge detection can be selected when the output of comparator 0 and INTP0 input are selected as the source.
Page 380: Hardware Release (Hs_Sel=0)
BAT32A237 User Manual | Chapter 10 Timer M 10.8.3.2 Hardware release (HS_SEL=0) Timer M operates in different modes with different release timings: Other than the complementary PWM function • When the timer M works in the output comparison function, PWM function or PWM3 mode, the forced cut-off of TMIOj0 (j=A, B, C, D) is released when the count value of TM0 is 0000H.
Page 381 BAT32A237 User Manual | Chapter 10 Timer M Figure 10 75 Detailed timing diagram of forced cutoff PWMOP operational clock TIMER M counter0 comparator0 output HZIF0 TMIOB0 output Note 1 from PWMOP. TMIOB0 output Note 2 from Timer M. TMIOC0 output Note 1 from PWMOP.
Page 382 BAT32A237 User Manual | Chapter 10 Timer M Figure 10 76 Detailed timing diagram for forced cutoff release (Timer M count source = Fclk) PWMOP operational clock TIMER M counter0 valid timing signal when TM0 counter at 0000H. comparator0 output...
Page 383 BAT32A237 User Manual | Chapter 10 Timer M Figure 10 77 Detailed timing diagram for forced cutoff release (Timer M count source = FCLK/2) PWMOP operational clock TIMER M counter0 valid timing signal when TM0 counter at 0000H. comparator0 output...
Page 384 BAT32A237 User Manual | Chapter 10 Timer M Complementary PWM function output After monitoring the release source, the forced cutoff is released according to the edge of TMIOC0 selected by OPEDGE. Figure 10-78 Example of hardware release of forced cutoff (TMIOB0, TMIOD0 as an example)
Page 385 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-79 Detailed timing diagram for forced cutoff release (Timer M count source = F , decrementing count) PWMOP operational clock TIMER M counter 1 TMIOC0 output from Timer M comparator0 output...
Page 386 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-80 Detailed timing diagram for forced cutoff release (Timer M count source = F , counter = TMGRA0) PWMOP operational clock TIMER M counter0 TMIOC0 output from Timer M Comparator 0 output...
Page 387 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-81 Detailed timing diagram for forced cutoff release (Timer M count source = F /2, decremental count) PWMOP operational clock TIMER M counter 1 TMIOC0 output from Timer M Comparator 0 output...
Page 388 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-82 Detailed timing diagram for forced cutoff release (Timer M count source = F /2, counter = TMGRA0) PWMOP operational clock TIMER M counter0 TMIOC0 output from Timer M Comparator 0 output...
Page 389: Software Release (Hs_Sel=1)
BAT32A237 User Manual | Chapter 10 Timer M 10.8.3.3 Software release (HS_SEL=1) The force cutoff release timing is different when the ACT settings of OPCTL0 are different. Use software to immediately release (ACT=0) If ACT=0 is set, once the HZ_REL bit of the OPCTL0 register is set to 1, the force cutoff is immediately released.
Page 390 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-84 Detailed timing diagram for forced cutoff release PWMOP operational clock TIMER M counter0 forced cut-off release control HZ_REL TMIOB0 output Note 1 from PWMOP. TMIOB0 output Note 2 from Timer M.
Page 391 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-85 Example of software release of forced cutoff (Timer M, 2-channel counting) PWMOP operational clock TMSTR.TSTART0 TMSTR.TSTART1 valid signal when count of TM0 is 0000H. valid signal when count of TM1 is 0000H.
Page 392 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-86 Example of software release of forced cutoff (Timer M, 1-channel count) PWMOP operational clock TMSTR.TSTART0 TMSTR.TSTART1 valid signal when count of TM0 is 0000H. valid signal when count of TM1 is 0000H.
Page 393 BAT32A237 User Manual | Chapter 10 Timer M Timer M operates in reset synchronous PWM mode Setting HZ_REL to 1, the output forced cutoff of all TMIO pins is released when the TM0 count value is 0000H. Figure 10-87 Example of software force cutoff release...
Page 394 BAT32A237 User Manual | Chapter 10 Timer M Timer operates in complementary PWM mode With HZ_REL set to 1, the forced cutoff is released according to the edge of TMIOC0 selected by OPEDGE. Figure 10-88 Examples of software force cutoff release (TMIOB0, TMIOD0)
Page 395: Hazard Countermeasures
BAT32A237 User Manual | Chapter 10 Timer M 10.8.3.4 Hazard countermeasures There is a risk of malfunction if the TMIO pin is switched between the multiplexing function and the PORT function in the forced cutoff state/forced cutoff release state/timer M action. This risk can be avoided by setting HAZAD_SET to 1 to allow the hazard countermeasure.
Page 396: Output Forced Cutoff Source Detected And Not Detected States
BAT32A237 User Manual | Chapter 10 Timer M 10.8.3.5 Output forced cutoff source detected and not detected states Whether the output forced cutoff source is detected or not is determined by the level of the signal (INTP0, CMP0) selected by the cutoff source selection bit (OPCTL0.IN_SEL1,OPCTL0.IN_SEL0).
Page 397: Timing Diagram When The Counter Value Of Timer M Reaches 0000H
BAT32A237 User Manual | Chapter 10 Timer M 10.8.3.6 Timing diagram when the counter value of timer M reaches 0000H When the hardware releases the output forced cutoff, the forced cutoff condition differs depending on the operation mode of Timer M.
Page 398 BAT32A237 User Manual | Chapter 10 Timer M Figure 10-91 Determination timing for count = 0000H (Count source=F /2, the counter stops at the next cycle when the timer M count value reaches 0000H.) PWMOP operational clock TIMER M counting TMSTR.TSTART0...
Page 399: Configuration Steps
BAT32A237 User Manual | Chapter 10 Timer M 10.8.3.7 Configuration steps PWMOP can be linked with Timer M. The PWMOP settings can be appended to the Timer M settings. The steps are as follows: After the clock and mode of the Timer M are set...
Page 400: Cautions
BAT32A237 User Manual | Chapter 10 Timer M 10.8.4 Cautions When the output of the timer M and the output of the PWMOP are working simultaneously, the priority is as follows: Table 10-22 Priority at forced cutoff Pin state at PWMOP forced cutoff...
Page 401: Chapter 11 Real-Time Clock
BAT32A237 User Manual | Chapter 11 Real-Time Clock Chapter 11 Real-Time Clock 11.1 Function of real-time clock The real-time clock has the following functions. • Holds counters for years, months, weeks, days, hours, minutes, and seconds up to a maximum of 99 years.
Page 402 BAT32A237 User Manual | Chapter 11 Real-Time Clock Figure 11-1 Block diagram of real-time clock real time clock control register 1 real time clock control register 0 subsystem clock supply mode control register (OSMC) alarm week alarm hour alarm minute...
Page 403: Registers For Controlling Real-Time Clock
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3 Registers for controlling real-time clock The real-time clock is controlled through the following registers. • Peripheral enable register 0 (PER0) • Real-time clock selection register (RTCCL) • Real-time clock control register 0 (RTCC0) •...
Page 404: Peripheral Enable Register 0 (Per0)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 405: Real-Time Clock Selection Register (Rtccl)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.2 Real-time clock selection register (RTCCL) The counting clock (F ) of the real-time clock and the 15-bit interval timer can be selected by RTCCL. Figure 11-3 Format of real-time clock selection register (RTCCL)
Page 406: Real-Time Clock Control Register 0 (Rtcc0)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.3 Real-time clock control register 0 (RTCC0) This is an 8-bit register that sets the start or stop of real-time clock operation, the control of RTC1HZ pins, the 12/24-hour system and the fixed cycle interrupt function.
Page 407: Real-Time Clock Control Register 1 (Rtcc1)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.4 Real-time clock control register 1 (RTCC1) This is an 8-bit register that controls the alarm clock interrupt function and the counter wait. The RTCC1 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “00H”.
Page 408 BAT32A237 User Manual | Chapter 11 Real-Time Clock Figure 11-5 Format of real-time clock control register 1 (RTCC1) (2/2) No fixed-cycle interruptions are generated. RIFG Generate fixed-cycle interrupts. No fixed-cycle interruptions are generated. This is a status flag that indicates a fixed-cycle interrupt. When a fixed-cycle interrupt is generated, this flag is “1”.
Page 409: Clock Error Correction Register (Subcud)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.5 Clock error correction register (SUBCUD) This is a register that can correct the clock speed with high accuracy by changing the overflow value (reference value: 7FFFH) from the internal counter (16 bits) to the second count register (SEC).
Page 410: Second Count Register (Sec)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.6 Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the internal counter (16-bit) overflows.
Page 411: Hour Count Register (Hour)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.8 Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows.
Page 412 BAT32A237 User Manual | Chapter 11 Real-Time Clock Table 11-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 11-2 Displayed time digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 0)
Page 413: Day Count Register (Day)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.9 Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
Page 414: Week Count Register (Week)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.10 Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter.
Page 415: Month Count Register (Month)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.11 Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows.
Page 416: Alarm Minute Register (Alarmwm)
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.3.13 Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes “00H”.
Page 417: Port Mode Register And Port Register
BAT32A237 User Manual | Chapter 11 Real-Time Clock Here is an example of setting the alarm. 12-hour display 24-hour display Sunda Mond Tuesd Wedn Thurs Saturd Friday esday Time of alarm Hour Hour Minute Minute Hour Hour Minute Minute Every 0:00 a.m...
Page 418: Operation Of Real-Time Clock
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.4 Operation of real-time clock 11.4.1 Starting operation of real-time clock Figure 11-17 Procedure for starting operation of real-time clock Start Note1 RTCEN=1 Supply input clock RTCE=0 Stop count operation Set RTCCL...
Page 419: Shifting To Sleep Mode After Starting Operation
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.4.2 Shifting to sleep mode after starting operation Perform some of the following processing when shifting to sleep mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to sleep mode after the INTRTC interrupt has occurred.
Page 420: Reading/Writing Real-Time Clock
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.4.3 Reading/writing real-time clock Read or write the counter after setting “1” to RWAIT first. Set RWAIT to “0” after completion of reading or writing the counter. Figure 11-19 Procedure for reading real-time clock Start Stops SEC to YEAR counters.
Page 421 BAT32A237 User Manual | Chapter 11 Real-Time Clock Figure 11-20 Procedure for reading real-time clock Start Stop SEC to Year counters RWAIT=1 Mode to read and write count values Check wait status of RWST=1? counter 设定SEC Write SEC Write second count register...
Page 422: Setting Alarm Of Real-Time Clock
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.4.4 Setting alarm of real-time clock Set alarm time after setting 0 to WALE (alarm operation invalid.) first. Figure 11-21 Alarm setting steps Start WALE=0 Match operation of alarm is invalid Configure SEC WALIE=1 Alarm match interrupts is valid.
Page 423: Hz Output Of Real-Time Clock
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.4.5 1 Hz output of real-time clock Figure 11-22 Set-up steps for 1Hz output Caution: 1. First set the RTCEN bit to 1, while oscillation of the count clock (F ) is stable.
Page 424: Example Of Watch Error Correction Of Real-Time Clock
BAT32A237 User Manual | Chapter 11 Real-Time Clock 11.4.6 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register.
Page 425 BAT32A237 User Manual | Chapter 11 Real-Time Clock Correction example Example of correcting from 32767.4Hz to 32768Hz (32767.4Hz+18.3ppm) [Measuring the oscillation frequency] When the watch error correction register (SUBCUD) is the initial value (“0000H”), the oscillation frequency of Note each product is measured by outputting a signal of approximately 1Hz from the RTC1HZ pin Note: For the setting of RTC1Hz output, please refer to “10.4.5 1Hz output of real-time clock”.
Page 426: Chapter 12 15-Bit Interval Timer
BAT32A237 User Manual | Chapter 12 15-Bit Interval Timer Chapter 12 15-Bit Interval Timer 12.1 Function of 15-bit interval timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from deep sleep mode.
Page 427: Registers For Controlling 15-Bit Interval Timer
BAT32A237 User Manual | Chapter 12 15-Bit Interval Timer 12.3 Registers for controlling 15-bit interval timer The 15-bit interval timer is controlled by the following registers. • Peripheral enable register 0 (PER0) • Real-time clock selection register (RTCCL) • 15-bit interval timer control register (ITMC) 12.3.1...
Page 428: Real-Time Clock Selection Register (Rtccl)
BAT32A237 User Manual | Chapter 12 15-Bit Interval Timer 12.3.2 Real-time clock selection register (RTCCL) The real-time clock and the count clock (F ) of the 15-bit interval timer can be selected via RTCCL. Figure 12-3 Format of real-time clock selection register (RTCCL)
Page 429: 15-Bit Interval Timer Control Register (Itmc)
BAT32A237 User Manual | Chapter 12 15-Bit Interval Timer 12.3.3 15-bit interval timer control register (ITMC) This register is used to set up the starting and stopping of the 15-bit interval timer operation and to specify the timer compare value.The ITMC register is set by a 16-bit memory manipulation instruction.
Page 430: 15-Bit Interval Timer Operation
BAT32A237 User Manual | Chapter 12 15-Bit Interval Timer 12.4 15-bit interval timer operation 12.4.1 15-bit interval timer operation timing The count value specified for the ITCMP14 to ITCMP0 bits is used as an interval to operate an 15-bit interval timer that repeatedly generates interrupt requests (INTIT).
Page 431: Start Of Count Operation And Re-Enter To Sleep Mode After Returned From Sleep Mode
BAT32A237 User Manual | Chapter 12 15-Bit Interval Timer 12.4.2 Start of count operation and re-enter to sleep mode after returned from sleep mode When setting the RINTE bit after returned from sleep mode and entering sleep mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.
Page 432: Chapter 13 Clock Output/Buzzer Output Controller
BAT32A237 User Manual | Chapter 13 Clock Output/Buzzer Output Controller Chapter 13 Clock Output/Buzzer Output Controller 13.1 Function of clock output/buzzer output controller The output of the clock is the function of output to the peripheral IC clock, and the output of the buzzer is the function of output the frequency square wave of the buzzer.
Page 433: Structure Of Clock Output/Buzzer Output Controller
BAT32A237 User Manual | Chapter 13 Clock Output/Buzzer Output Controller 13.2 Structure of clock output/buzzer output controller The clock output/buzzer output controller is composed of the following hardware. Table13-1 Register for clock output/buzzer output control circuit Item Register list Clock output select register n (CKSn)
Page 434 BAT32A237 User Manual | Chapter 13 Clock Output/Buzzer Output Controller Caution: Change the output clock after disabling clock output (PCLOEn = 0). To shift to deep sleep mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0 before executing the WFI instruction.
Page 435: Register Controlling Port Functions Of Pins To Be Used For Clock Or Buzzer Output
BAT32A237 User Manual | Chapter 13 Clock Output/Buzzer Output Controller 13.3.2 Register controlling port functions of pins to be used for clock or buzzer output When used as a clock output/buzzer output function, the control registers (Port Mode Register (PMxx) and Port Register (Pxx)) for the port function multiplexed with the target channel must be set.
Page 436: Operation Of Clock Output/Buzzer Output Controller
BAT32A237 User Manual | Chapter 13 Clock Output/Buzzer Output Controller 13.4 Operation of clock output/buzzer output controller It can be use as clock output or buzzer output with 1 pin selection. The CLKBUZ0 pin outputs a clock/buzzer selected by the clock output selection register 0 (CKS0).
Page 437: Chapter 14 Watchdog Timer
BAT32A237 User Manual | Chapter 14 Watchdog Timer Chapter 14 Watchdog Timer 14.1 Function of watchdog timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock (F ).
Page 438 BAT32A237 User Manual | Chapter 14 Watchdog Timer Figure 14-1 Block diagram of watchdog timer WDTINT of option Interval time controller (overflow interval time byte(000C0H) time of count value x 3/4 +1/2F WDCS2~WDCS0 of option byte (000C0H) Internal overflow signal...
Page 439: Registers For Controlling Watchdog Timer
BAT32A237 User Manual | Chapter 14 Watchdog Timer 14.3 Registers for controlling watchdog timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 14.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again. The WDTE register is set by an 8-bit memory manipulation instruction.
Page 440: Lockup Control Register (Lockctl) And Its Protection Register (Prcr)
BAT32A237 User Manual | Chapter 14 Watchdog Timer 14.3.2 LOCKUP control register (LOCKCTL) and its protection register (PRCR) The LOCKCTL register is a configuration register for controlling the Cortex-M0+ LockUp function to operate the watchdog timer, and PRCR is its write-protect register.
Page 441: Wdtcfg Configuration Register (Wdtcfg0/1/2/3)
BAT32A237 User Manual | Chapter 14 Watchdog Timer 14.3.3 WDTCFG configuration register (WDTCFG0/1/2/3) The WDTCFG configuration register is the register that forces the watchdog timer to run. The WDTCFG register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of the WDTCFG register becomes “00H”.
Page 442: Operation Of Watchdog Timer
BAT32A237 User Manual | Chapter 14 Watchdog Timer 14.4 Operation of watchdog timer 14.4.1 Operation control of watchdog timer When using the watchdog timer, set the following items by option byte (000C0H): The bit 4 (WDTON) of the option byte (000C0H) must be set to “1” to enable the watchdog timer count •...
Page 443 BAT32A237 User Manual | Chapter 14 Watchdog Timer overflow occurs during the oscillation stabilization time, causing a reset. Consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the deep sleep mode release by an interval interrupt.
Page 444: Setting Overflow Time Of Watchdog Timer
BAT32A237 User Manual | Chapter 14 Watchdog Timer 14.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by bit3~1(WDCS2~WDCS0) of the option byte (000C0H). An internal reset signal is generated when an overturn occurs. If the “ACH” is written to the WDTE of the watchdog timer during the window opening before the overage time, the count is cleared and counting restarts.
Page 445: Setting Window Open Period Of Watchdog Timer
BAT32A237 User Manual | Chapter 14 Watchdog Timer 14.4.3 Setting window open period of watchdog timer Set the window opening period of the watchdog timer by bit6 and bit5 (WINDOW1, WINDOW0) of option bytes (000C0H). The window summary is as follows: •...
Page 446: Setting Of Watchdog Timer Interval Interrupt
BAT32A237 User Manual | Chapter 14 Watchdog Timer 14.4.4 Setting of watchdog timer interval interrupt Interval interrupts (INTWDTI) can be generated when 75%+1/2F is reached by setting bit7 (WDTINT) of option byte (000C0H). Table 14-5 Setting of watchdog timer interval interrupt...
Page 447: Chapter 15 A/D Converter
BAT32A237 User Manual | Chapter 15 A/D Converter Chapter 15 A/D Converter The number of analog input channels for A/D converters varies by product. Pin number 32-pin 48-pin 64-pin 10ch 15ch 16ch Analog input channel (ANI0~ANI3, (ANI0~ANI12) (ANI0~ANI15) ANI8~ANI12, ANI14) (ANI14~ANI15) 15.1 Function of A/D converter...
Page 448 BAT32A237 User Manual | Chapter 15 A/D Converter Figure 15-1 Block Diagram of A/D converter www.mcu.com.cn 448 / 1066 V1.0.4...
Page 449: Registers For Controlling A/D Converter
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2 Registers for controlling A/D converter The registers that control the A/D converter are as follows: Register base address: CSC_BASE=4002_0420H; ADC_BASE=4004_5000H; PORT_BASE=4004_000H Register name Register description Reset value Register address PER0 Peripheral enable register 0...
Page 450: Peripheral Enable Register 0 (Per0)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets a clock that is enabled or disabled to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 451: A/D Converter Mode Register 0 (Adm0)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.2 A/D converter mode register 0 (ADM0) This register sets the clock for A/D converter, and starts/stops conversion. The ADM0 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes “00H”.
Page 452 BAT32A237 User Manual | Chapter 15 A/D Converter Table 15-2 DCS bit set and clear conditions A/D conversion mode Set condition Clear condition Continuous When writing “0” to the ADCS bit conversion mode · When writing “0” to the ADCS bit...
Page 453 BAT32A237 User Manual | Chapter 15 A/D Converter Figure 15-4 Timing diagram with A/D Modes ADCS = 0 ADCS = 1 Clear to 0 automatically when AD conversion is completed Software trigger Note 1 ADCS mode conversion conversion conversion stopped...
Page 454 BAT32A237 User Manual | Chapter 15 A/D Converter Table 15-3 A/D conversion time selection (1/2) (1) No A/D power stabilization wait time (software trigger mode/hardware trigger no-wait mode) Frequency of the A/D converter mode register 0 A/D converter mode Conversion time at 12-bit resolution...
Page 455 BAT32A237 User Manual | Chapter 15 A/D Converter Table 15-3 A/D conversion time selection (2/2) Note 1 (1) With A/D power stabilization wait time (hardware triggere wait mode A/D converter Frequency of the A/D power A/D converter mode register A/D power supply stabilization...
Page 456: A/D Converter Mode Register 1 (Adm1)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.3 A/D converter mode register 1 (ADM1) This is a register that sets the A/D conversion mode. The ADM1 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “00H”.
Page 457: A/D Converter Mode Register 2 (Adm2)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.4 A/D converter mode register 2 (ADM2) The ADM2 register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “00H”.
Page 458: A/D Converter Trigger Mode Register (Adtrg)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.5 A/D converter trigger mode register (ADTRG) This is a register that sets the A/D conversion trigger mode and hardware trigger signal. The ADTRG register is set by an 8-bit memory manipulation instruction.
Page 459: Analog Input Channel Specification Register (Ads)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.6 Analog input channel specification register (ADS) This is a register that specifies the analog voltage input channel to be A/D converted. The ADS register is set by an 8-bit memory manipulation instruction.
Page 460 BAT32A237 User Manual | Chapter 15 A/D Converter ◆ Scan mode (ADM1.ADMD=1) Analog input channel ADISS ADS3 ADS2 ADS1 ADS0 Scan 0 Scan 1 Scan 2 Scan 3 ANI0 ANI1 ANI2 ANI3 ANI1 ANI2 ANI3 ANI4 ANI2 ANI3 ANI4 ANI5...
Page 461: 12-Bit A/D Conversion Result Register (Adcr)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.7 12-bit A/D conversion result register (ADCR) This is a 16-bit register that holds the A/D conversion result, and this register is read-only. Whenever the A/D Note conversion is finished, the conversion result is loaded from the successive approximation register (SAR) The high 4 bits of this register are read out as a fixed value of “0”...
Page 462: 8-Bit A/D Conversion Result Register (Adcrh)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.8 8-bit A/D conversion result register (ADCRH) This is an 8-bit register that holds the result of the A/D conversion, and holds the high 8 bits of the 12-bit Note resolution The ADCRH register is read by an 8-bit memory manipulation instruction.
Page 463: Conversion Result Comparison Upper Limit Setting Register (Adul)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.9 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified by the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 15-7).
Page 464: A/D Converter Sampling Time Control Register (Adnsmp)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.11 A/D converter sampling time control register (ADNSMP) This register controls the A/D sampling time. The ADNSMP register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “0dH”.
Page 465: A/D Converter Sampling Time Extension Control Register (Adsmpwait)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.12 A/D converter sampling time extension control register (ADSMPWAIT) This register is used to extend the A/D sampling time. The ADSMPWAIT register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes “00H”.
Page 466: A/D Test Register (Adtes)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.13 A/D test register (ADTES) This register is used to set the test mode of A/D converter. The ADTES register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “00H”.
Page 467: A/D Status Register (Adflg)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.14 A/D status register (ADFLG) This register indicates the status of A/D converter. The ADFLG register is read by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “00H”.
Page 468: A/D Converters Charge/Discharge Control Register (Adndis)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.15 A/D converters charge/discharge control register (ADNDIS) The register is used to control the charging and discharging action and time of A/D converter. The ADNDIS register can be read and written by an 8-bit memory manipulation instruction.
Page 469: Registers For Controlling Port Functions Of Analog Input Pins
BAT32A237 User Manual | Chapter 15 A/D Converter 15.2.16 Registers for controlling port functions of analog input pins The control register (Port Mode Control Register (PMCxx)) for the port function that is multiplexed with the analog input of the A/D converter must be set. For details, refer to “2.3.6 Port Mode Control Register (PMCxx)”.
Page 470: Input Voltage And Conversion Results
BAT32A237 User Manual | Chapter 15 A/D Converter 15.3 Input voltage and conversion results The analog input voltage of the analog input pin (ANI0~ANI15) and the theoretical A/D conversion result register (ADCR) are related by the following expressions. ×4096+0.5) or (ADCR-0.5)×...
Page 471: Operation Mode Of A/D Converter
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4 Operation mode of A/D Converter The A/D converter conversion operations are described below. For the setting of each mode, please refer to “15.5 A/D converter setup flowchart”. 15.4.1 Software trigger mode (select mode, continuous conversion mode) ①...
Page 472: Software Trigger Mode (Select Mode, Single Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.2 Software trigger mode (select mode, single conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to “1”.
Page 473: Software Trigger Mode (Scan Mode, Sequential Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.3 Software trigger mode (scan mode, sequential conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to "1”.
Page 474: Software Trigger Mode (Scan Mode, Single Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.4 Software trigger mode (scan mode, single conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to “1”.
Page 475: Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to “1”.
Page 476: Hardware Trigger No-Wait Mode (Select Mode, Single Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.6 Hardware trigger no-wait mode (select mode, single conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to ”1”.
Page 477: Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to “1”.
Page 478: Hardware Trigger No-Wait Mode (Scan Mode, Single Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.8 Hardware trigger no-wait mode (scan mode, single conversion mode) ① In the stop state, enter A/D conversion standby state by setting the ADCE bit of the A/D converter mode register 0 (ADM0) to “1”.
Page 479: Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.9 Hardware trigger wait mode (select mode, sequential conversion mode) ① In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 480: Hardware Trigger Wait Mode (Select Mode, Single Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.10 Hardware trigger wait mode (select mode, single conversion mode) ① In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 481: Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.11 Hardware trigger wait mode (scan mode, sequential conversion mode) ① In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 482: Hardware Trigger Wait Mode (Scan Mode, Single Conversion Mode)
BAT32A237 User Manual | Chapter 15 A/D Converter 15.4.12 Hardware trigger wait mode (scan mode, single conversion mode) ① In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status.
Page 483: A/D Converter Setup Flowchart
BAT32A237 User Manual | Chapter 15 A/D Converter 15.5 A/D converter setup flowchart The A/D converter setup flowchart in each operation mode is described below. 15.5.1 Setting up software trigger mode Figure 15-32 Setting up software trigger mode Start of setup...
Page 484: Setting Up Hardware Trigger No-Wait Mode
BAT32A237 User Manual | Chapter 15 A/D Converter 15.5.2 Setting up hardware trigger no-wait mode Figure 15-33 Setting up hardware trigger no-wait mode Start of setup The ADCEN bit of the PER0 register is set to 1, and Configure PER0 register supplying the clock starts.
Page 485: Setting Up Hardware Trigger Wait Mode
BAT32A237 User Manual | Chapter 15 A/D Converter 15.5.3 Setting up hardware trigger wait mode Figure 15-34 Setting up hardware trigger wait mode Start of setup The ADCEN bit of the PER0 register is set to 1, and Configure PER0 register supplying the clock starts.
Page 486: Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected
BAT32A237 User Manual | Chapter 15 A/D Converter 15.5.4 Setup when temperature sensor output voltage/internal reference voltage is selected (An example for software trigger mode and single conversion mode) Figure 15-35 Setup when temperature sensor output voltage/internal reference voltage is selected...
Page 487: Setting Up Test Mode
BAT32A237 User Manual | Chapter 15 A/D Converter 15.5.5 Setting up test mode Figure 15-36 Setting up test mode (VSS/half_VDD/VDD as conversion object) Start of setup The ADCEN bit of the PER0 register is set to 1, and Configure PER0 register supplying the clock starts.
Page 488: Chapter 16 D/A Converter
BAT32A237 User Manual | Chapter 16 D/A Converter Chapter 16 D/A Converter The channels of the D/A converter vary depending on the product. Table 16-1 Output pin of D/A converter D/A output pin 64PIN 52PIN 48PIN 40PIN 36PIN 32PIN 24PIN ○...
Page 489: Structure Of D/A Converter
BAT32A237 User Manual | Chapter 16 D/A Converter 16.2 Structure of D/A converter The block diagram of the D/A converter is shown in Figure 16-1. Figure 16-1Block diagram of for D/A converter Internal bus D/A conversion value setting register0 (DACS0)
Page 490: Registers For Controlling D/A Converter
BAT32A237 User Manual | Chapter 16 D/A Converter 16.3 Registers for controlling D/A converter The D/A converter is controlled by the following registers. • Peripheral enable register 1 (PER1) • D/A converter mode register (DAM) • D/A conversion value setting registers 0, 1 (DACS0, DACS1) •...
Page 491: D/A Converter Mode Register (Dam)
BAT32A237 User Manual | Chapter 16 D/A Converter 16.3.2 D/A converter mode register (DAM) This register controls the operation of the D/A converter. The DAM register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register becomes “00H”.
Page 492: Event Output Destination Select Register N(Elselrn), N=00~21
BAT32A237 User Manual | Chapter 16 D/A Converter 16.3.4 Event output destination select register n(ELSELRn), n=00~21 When using the real-time output mode of the D/A converter, the event signal of the event link controller is used as the initiation trigger, and the D/A conversion is performed. For details, please refer to “24.3.1 Event output destination select register n(ELSELRn)(n=00~21)”.
Page 493: Operation Of D/A Converter
BAT32A237 User Manual | Chapter 16 D/A Converter 16.4 Operation of D/A converter 16.4.1 Operation in normal mode The D/A conversion is initiated using the write operation of the DACSi register as the initiation trigger. The setup method is as follows: ①...
Page 494: Operation In Real-Time Output Mode
BAT32A237 User Manual | Chapter 16 D/A Converter 16.4.2 Operation in real-time output mode Each channel of the D/A conversion is performed on using the signals from the EVENTC as triggers. The setup method is as follows: ① Set the DACEN bit of the peripheral enable register 1 (PER1) to 1 to start the supply of the input clock to the D/A converter.
Page 495: D/A Conversion Output Timing
BAT32A237 User Manual | Chapter 16 D/A Converter 16.4.3 D/A conversion output timing Figure16-5 shows the output timing of the D/A conversion. Normal mode Real time output mode (DACEi=1) Real time output mode (DACEi=0) DAMDi bit Operation clock DACSi register write enable...
Page 496: Cautions On Using The D/A Converter
BAT32A237 User Manual | Chapter 16 D/A Converter 16.5 Cautions on using the D/A converter Cautions for using the D/A converter are shown below. (1) The digital port I/O function, which is the alternate function of the ANO0 pin and ANO1 pin, does not operate if the ports are set to analog pins by using the port mode control register (PMC).
Page 497: Chapter 17 Comparator
BAT32A237 User Manual | Chapter 17 Comparator Chapter 17 Comparator This product has a built-in 2-channel comparator. 17.1 Function of comparator The comparator has the following functions: • The input pins of the CMP1 can be selected from an external port, an internal reference voltage, and a built- in DAC reference voltage.
Page 498: Structure Of Comparator
BAT32A237 User Manual | Chapter 17 Comparator 17.2 Structure of comparator The block diagram of the comparator is shown in Figure 17-1. Figure 17-1 Block diagram of comparator 0 CMP0SEL C0ENB C0FCK C0EPO C0EDG C0IE VCIN0 PGA0 A/D converter CMP0...
Page 499 BAT32A237 User Manual | Chapter 17 Comparator Figure 17-2 Block diagram of comparator 1 CMP1SEL C1MON C1ENB C1FCK C1EPO C1EDG C1IE VCIN10 Edge CMP1 选 detection interrupt VCIN11 择 circuit 器 VCIN12 CMP1 EVENTC event VCIN13 CMP1 Noise filter/ digital filter Output 选...
Page 500: Registers For Controlling The Comparator
BAT32A237 User Manual | Chapter 17 Comparator 17.3 Registers for controlling the comparator The registers that control the comparator are shown in Table17-2. Table17-2 Registers controlling the comparator Register name Symbol Peripheral enable register 1 PER1 Comparator mode setting register COMPMDR.
Page 501: Peripheral Enable Register 1 (Per1)
BAT32A237 User Manual | Chapter 17 Comparator 17.3.1 Peripheral enable register 1 (PER1) The PER1 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 502: Comparator Mode Setting Register (Compmdr)
BAT32A237 User Manual | Chapter 17 Comparator 17.3.2 Comparator mode setting register (COMPMDR) The COMPMDR register is a register that enables/disables the comparator and detects the comparator output. Setting the CiENB bit to 0 is disabled when the comparator output is enabled (set the CiOE bit of the COMPOCR register to 1).
Page 503: Comparator Filter Control Register (Compfir)
BAT32A237 User Manual | Chapter 17 Comparator 17.3.3 Comparator filter control register (COMPFIR) The COMPFIR register is a control register for the digital filter. The COMPFIR register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to "00H".
Page 504 BAT32A237 User Manual | Chapter 17 Comparator If the C0FCK1 to C0FCK0 bits, the C0EPO bit, and the C0EDG bit are changed, an interrupt request for comparator 0 and an event signal to the EVENTC output may be generated. These bits must be changed after setting the ELSELR20 register of EVENTC (which is not linked to the output of comparator 0) to 0.
Page 505: Comparator Output Control Register (Compocr)
BAT32A237 User Manual | Chapter 17 Comparator 17.3.4 Comparator output control register (COMPOCR) The COMPOCR register is a control register that sets the polarity of the comparator output, enables/disables the output and the interrupt output. In the following cases, it is prohibited to set the CiOE bit of the COMPOCR register to 1 (output enable) (i=0,1).
Page 506 BAT32A237 User Manual | Chapter 17 Comparator Note 1: When comparator 1 uses the TIMER WINDOW mode, the bit7 (C1EDG) of register COMPFIR must be set to 1. C1OE and C1OTWMD bits cannot be set at the same time. Set the C1OTWMD bit before setting the C1OE bit to 1.
Page 507: Comparator Built-In Reference Voltage Control Register (Cvrctl)
BAT32A237 User Manual | Chapter 17 Comparator 17.3.5 Comparator built-in reference voltage control register (CVRCTL) The CVRCTL register is a register that sets the built-in reference voltage enable/stop action of the comparator. The CVRCTL register is set by an 8-bit memory manipulation instruction.
Page 508: Comparator Built-In Reference Voltage Selection Register (Cirvm)
BAT32A237 User Manual | Chapter 17 Comparator 17.3.6 Comparator built-in reference voltage selection register (CiRVM) The CiRVM register is a register that sets the built-in reference voltage of the comparator. Rewrite the CiRVM register when the built-in reference voltage stops action (CVREi=0) The CVRCTL register is set by an 8-bit memory manipulation instruction.
Page 509: Comparator 0 Input Signal Selection Control Register (Cmpsel0)
BAT32A237 User Manual | Chapter 17 Comparator 17.3.7 Comparator 0 input signal selection control register (CMPSEL0) The CMPSEL0 register is a selection register for the positive, negative input signal of comparator 0. Rewrite the CMPSEL0 register when comparator 0 stops action (C0ENB=0).
Page 510: Comparator 1 Input Signal Selection Control Register (Cmpsel1)
BAT32A237 User Manual | Chapter 17 Comparator 17.3.8 Comparator 1 input signal selection control register (CMPSEL1) The CMPSEL1 register is a selection register for the input signal of the positive end and the negative end of the comparator 1. When comparator 1 stops (C1ENB=0), rewrite the CMPSEL1 register.
Page 511: Registers For Controlling Port Functions Of Analog Input Pins
BAT32A237 User Manual | Chapter 17 Comparator 17.3.9 Registers for controlling port functions of analog input pins When using the VCIN0 pin, the VCIN10-VCIN13 pins, and the VREF0 pin as analog inputs to the comparator, the bit of the Port Mode Register (PMxx) and the bit of the Port Control Register (PMCxx) corresponding to each port must be 1.
Page 512: Operation Instructions
BAT32A237 User Manual | Chapter 17 Comparator 17.4 Operation instructions Comparator 0 and Comparator 1 can each operate independently. The setting method and operation are the same. CMP0 and PGA0 can be combined and linked. The setup procedure for independent operation and linkage of the comparator is shown in Table 17-3.
Page 513 BAT32A237 User Manual | Chapter 17 Comparator An example of the operation of comparator i (i = 0, 1) is shown in Figure 17-11. In the basic mode, the CiMON bit of the COMPMDR register is 1 when the analog input voltage is higher than the reference input voltage, and 0 when the analog input voltage is lower than the reference input voltage.
Page 514: Comparator I Digital Filter (I=0, 1)
BAT32A237 User Manual | Chapter 17 Comparator 17.4.1 Comparator i digital filter (i=0, 1) The comparator i has a built-in digital filter, which can select the sampling clock through the CiFCK1~CiFCK0 bits of the COMPFIR register. The output signal of comparator i is sampled according to each sampling clock, and the digital filter outputs the sampling value.
Page 515: Event Signal Output To The Linkage Controller (Eventc)
BAT32A237 User Manual | Chapter 17 Comparator 17.4.3 Event signal output to the linkage controller (EVENTC) Under the same conditions as the generation of an interrupt request, the event signal output to EVENTC is generated by detecting the output edge of the digital filter set in the COMPFIR register. However, unlike the interrupt request that is independent of the CiIE bit of the COMPOCR register, the event signal is always output to EVENTC.
Page 516: Output Of Comparator I (I=0,1)
BAT32A237 User Manual | Chapter 17 Comparator 17.4.4 Output of comparator i (i=0,1) The comparison result of the comparator can be output to external pin, and output polarity can be set through CiOP bit and CiOE bit of COMPOCR register. Refer to 17.3.4 Comparator Output Control Register (COMPOCR) for the register settings and comparator outputs.
Page 517: Chapter 18 Programmable Gain Amplifier
BAT32A237 User Manual | Chapter 18 Programmable Gain Amplifier (PGA) Chapter 18 Programmable Gain Amplifier (PGA) 18.1 Function of programmable gain amplifier This product has two built-in programmable gain amplifiers (PGA0 and PGA1) with the following functions: ⚫ Seven choices of amplification gain per PGA: 4x, 8x, 10x, 12x, 14x, 16x, 32x.
Page 518: Structure Of Programmable Gain Amplifier
BAT32A237 User Manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.2 Structure of programmable gain amplifier Figure 18-1 Block diagram of programmable gain amplifier www.mcu.com.cn 518 / 1066 V1.0.4...
Page 519: Registers For Controlling Programmable Gain Amplifier
BAT32A237 User Manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.3 Registers for controlling programmable gain amplifier Table18-1 Registers for controlling programmable gain amplifier Peripheral enable register 1 PER1 Programmable gain amplifier control register PGACTL Port mode control register 2...
Page 520: Programmable Gain Amplifier Control Register
BAT32A237 User Manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.3.2 Programmable gain amplifier control register (PGAnCTL) The PGA0CTL and PGA1CTL registers are used to control the programmable gain amplifier start operation, stop operation and amplification. The PGA0CTL and PGA1CTL registers can be set by a 1-bit or an 8-bit memory manipulation instruction.
Page 521: Operation Of Programmable Gain Amplifier
BAT32A237 User Manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.4 Operation of programmable gain amplifier The analog voltage input to the PGAIN pin is amplified with seven choices of amplification gain: 4x, 8x, 10x, 12x, 14x, 16x, and 32x.
Page 522: Stopping Operation Steps Of Programmable Gain Amplifier
BAT32A237 User Manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.4.2 Stopping operation steps of programmable gain amplifier Take PGA0 as an example, the setup procedure is as follows: Caution: 1. When restarting the PGA and A/D conversion or amplifier, a PGA stabilization time of 10us is required after setting the PGAEN bit to 1.
Page 523: Chapter 19 Universal Serial Communication Unit
Unit 0 of the general-purpose serial communication unit has four serial channels and Unit 1 has two serial channels, and each channel supports 3-wire serial (SSPI), UART, and simplified I C communication functions. The functions of each channel supported by the BAT32A237 are assigned as follows: ○32-pin products Unit...
Page 524 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit ○64-pin products unit channel Use as SSPI Use as UART Used as Simplified I SSPI00 (support slave selection IIC00 UART0 (support LIN-bus) input) SSPI01 IIC01 SSPI10 IIC10 UART1 SSPI11 IIC11...
Page 525: Function Of Universal Serial Communication Unit
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.1 Function of universal serial communication unit The characteristics of each serial interface supported by the BAT32A237 are shown below. 19.1.1 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Data is transmitted and received synchronously with a serial clock (SCLK) output from the master device.
Page 526: Uart (Uart0~Uart2)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.1.2 UART (UART0~UART2) This is an asynchronous function using two lines: serial data transmission (TxD) and serial data reception (RxD) lines. By using these two communication lines, data is sent and received asynchronously (using the internal baud rate) with other communicating parties by data frame (consisting of start bits, data, parity bits, and stop bits).
Page 527: Simplified I C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.1.3 Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) This is a function for clock synchronization communication with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.
Page 528: Structure Of Universal Serial Communication Unit
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.2 Structure of universal serial communication unit The universal serial communication unit consists of the following hardware. Table 19-1 Structure of universal serial communication unit Item Structure Note 1 Shift register...
Page 529 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit The block diagram of the universal serial communication unit 0 is shown in Figure 19-1. Figure 19-1 Block diagram of universal serial communication unit 0 Noise filter enable Serial output register (SO0)
Page 530 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit The block diagram of the universal serial communication unit 1 is shown in Figure 19-2. Figure 19-2 Block diagram of universal serial communication unit 1 Serial output register 1(SO1) Noise filter enable...
Page 531: Shift Register
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.2.1 Shift register This is a 16-bit register that converts parallel data into serial data or vice versa. Note 1 In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used .
Page 532 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-3 Format of serial data register mn(SDRmn) (mn=00,01,10,11) Address: 40041310H (SDR00), 40041312H (SDR01) After reset: 0000H 40041748H (SDR10), 4004174AH(SDR11) 40041211H (SDR00) 40041310H (SDR00) 13 12 SDRmn Shift register Remark: For the functions of the upper 7 bits of the SDRmn register, refer to “19.3 Registers for Controlling Universal Serial Communication Unit”.
Page 533: Registers For Controlling Universal Serial Communication Unit
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3 Registers for controlling universal serial communication unit The registers that control the universal serial communication unit are as follows: • Peripheral enable register 0 (PER0) • Serial clock select register m (SPSm) •...
Page 534: Peripheral Enable Register 0 (Per0)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.1 Peripheral enable register 0 (PER0) The PER0 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use.
Page 535: Serial Clock Select Register M (Spsm)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that selects two common operating clocks (CKm0, CKm1). CKm1 is selected by the bits 7 to 4 of the SPSm register, and CKm0 is selected by the bits 3 to 0.
Page 536: Serial Mode Register Mn (Smrmn)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register for setting the channel n operation mode, selecting the F , specifying whether the serial clock can be used for F input.
Page 537 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-7 Format of serial mode register mn (SMRmn) (2/2) Address: 40041110H(SMR00)~40041116H(SMR03) After eset: 0020H 40041550H(SMR10)~40041552H(SMR11) Symbol 15 SMRmn SISm Note 1 Note 1 Note 1 SISmn0 Level inversion control of channel n receives data in UART mode Detect the falling edge as the starting bit.
Page 538: Serial Communication Run Setting Register Mn (Scrmn)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.4 Serial communication run setting register mn (SCRmn) The SCRmn register is the communication operation setting register of channel n, which sets the data transmission and reception modes, data and clock phases, whether to mask the error signal, parity test bits, start bits, stop bits, and data length.
Page 539 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-8 Format of serial communication run setting register mn (SCRmn) (2/2) Address: 40041118H(SCR00)~4004111EH(SCR03) After reset: 0087H 40041558H (SCR10)~4004155AH (SCR13) Symbol 15 SCRmn Note 1 Note 2 Setting of parity bits in UART mode...
Page 540: Serial Data Register Mn (Sdrmn)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.5 Serial data register mn (SDRmn) The SDRmn register is the data register (16 bits) for channel n transmission and reception. Bits 8~0 (low 9 bits) of SDR00, SDR01 or bits 7~0 (low 8 bits) of SDR02, SDR03, SDR10, SDR11 are used as...
Page 541 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Caution: 1. The bit8 of the SDR02, SDR03, SDR10, SDR11 registers must be set to 0. 2. When using the UART, it is prohibited to set SDRmn[15:9] to “0000000B” and “0000001B”.
Page 542: Serial Flag Clear Trigger Register Mn (Sirmn)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.6 Serial flag clear trigger register mn (SIRmn) This is the trigger register used to clear the error flags of channel n. If each bit (FECTmn, PECTmn, OVCTmn) is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of the serial status register mn (SSRmn) is cleared to 0.
Page 543: Serial State Register Mn (Ssrmn)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.7 Serial state register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error. The SSRmn register is read by a 16-bit memory manipulation instruction.
Page 544 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-11 Format of serial status register mn (SSRmn) (2/2) Address: 40041100H(SSR00)~40041106H(SSR03) After reset: 0000H R 40041540H (SSR10)~40041542H (SSR11) Symbol SSRmn Note 1 Note 1 FEFmn Detection flag for channel n frame errors No error occurred.
Page 545: Serial Channel Start Register M (Ssm)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled).
Page 546: Serial Channel Stop Register M (Stm)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).
Page 547: Serial Channel Enable Status Register M (Sem)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
Page 548: Serial Output Enable Register M (Soem)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.11 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output...
Page 549: Serial Output Register M (Som)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.
Page 550: Serial Output Level Register M (Solm)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.13 Serial output level register m (SOLm) The SOLm register is a register that sets the reverse phase of the data output level of each channel. This register can only be set in UART mode. In SSPI mode and Simplified I C mode, the corresponding bit must be set to 0.
Page 551 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-18 shows examples in which the level of transmission data is inverted during UART transmission. Figure 19-18 Example of inverted transmission data (a) Normal output (SOLmn=0) SOLmn=0 output TxDq...
Page 552: Input Switch Control Register (Isc)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.14 Input switch control register (ISC) When LIN-bus communication is implemented via UART0, the ISC1 bit and ISC0 bit of the ISC register are used for external interrupt and timer array unit coordination. If bit0 is set to 1, the input signal of the serial data input (RxD0) pin is selected as the input for the external interrupt (INTP0), so that the wake-up signal can be detected by the INTP0 interrupt.
Page 553: Noise Filter Enable Register 0 (Nfen0)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.15 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel.
Page 554: Registers For Controlling Port Functions Of Serial Input/Output Pins
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.3.16 Registers for controlling port functions of serial input/output pins When using the Universal Serial Communication Unit, the control registers for the port functions that are multiplexed with the target channel (Port Mode Register (PMxx), Port Register (Pxx), Port Input Mode Register (PIMxx), Port Output Mode Register (POMxx), and Port Mode Control Register (PMCxx)).
Page 555: Operation Stop Mode
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.4 Operation stop mode Each serial interface of universal serial communication unit has the operation stop mode. Serial communication is not possible in operation stop mode, so power consumption is reduced. In addition, pins for the serial interface can be used as port functions in operation stop mode.
Page 556: Stopping The Operation By Channels
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 19-22 Settings for each register when stopping operation by channel (a) Serial channel stop register m (STm)..This is a register that sets the communication/stop count for each channel.
Page 557: 3-Wire Serial I/O (Sspi00, Sspi01, Sspi10, Sspi11, Sspi20, Sspi21) Communication
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication This is a clock synchronization communication function implemented by three wires of serial clock (SCLK) and serial data (SDI and SDO).
Page 558: Master Transmission
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5.1 Master transmission Master transmission refers to the operation of the BAT32A237 output transmission clock and sending data to other devices. 3-wire serial SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21 Channel 0 of...
Page 559: Register Settings
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register settings Figure 19-23 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register setting content when the master transmits (a) serial mode register mn (SMRmn) channel n operational clock （f ）...
Page 560 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-24 Initial set-up steps of master transmission Start initial configuration Release the universal serial Configure PER0 register communication unit from the reset state, and start clock supply. Configure the operation clock Configure SPSm register Configure an operation mode, etc.
Page 561 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-25 Stop steps of master transmission Start stopping configuration If there is any data being transferred, (Selective) TSFmn = 0？ wait for their completion. (if need urgent stop, do not wait).
Page 562 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-26 Restart steps of master transmission Start restart configuration Wait till the communication target (slave (Essential) Slave ready? device) stops or communication ends By setting the port register and the port...
Page 563 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single transmit mode) Figure 19-27 Timing diagram of master transmission (single transmit mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn transmit data1 transmit data2 transmit data3 SDRmn SCLKp pin...
Page 564 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-28 Flowchart of master transmission (single transmit mode) Start of SSPI communication For the relevant initial configuration, refer to Figure 19-24 SCI initial configuration (select transfer end interrupt) Set the transfer data and data count, and clear the communication completion flag (via...
Page 565 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (continuous transmit mode) Figure 19-29 Timing diagram of master transmission (continuous transmit mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn transmit data1 transmit data2 transmit data3 SDRmn SCLKp pin...
Page 566 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-30 Flowchart of master transmission (continuous transmit mode) Start of SSPI communication For the relevant initial configuration, refer to figure 19~34 SCI initial configuration (select buffer empty interrupt) Configure transmit data and data count, clear communication end flag (via...
Page 567: Master Reception
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5.2 Master reception Master reception is an operation wherein the BAT32A237 outputs a transfer clock and receives data from other device. 3-wire serial I/O SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21...
Page 568: Register Setting
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-31 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register setting content for master reception (a) serial mode register mn(SMRmn) Channel n operational clock （f ）...
Page 569 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-32 Initial set-up steps for master reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, and start providing clock. configure operation clock configure SPSm register configure operation mode, etc.
Page 570 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-33 Stop step for master reception termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 571 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-34 Restart set-up steps for master reception restart configuration starts wait till commuication target (slave device) stops or communication ends (essential) slave ready? By setting the port register and port mode...
Page 572 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single receive mode) Figure 19-35 Timing diagram of the master receive (single receive mode) (Type 1:DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 2 data reception 3 data reception 1...
Page 573 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-36 Flowchart for master reception (single receive mode) SSPI communication starts for the relevant initial configuration, refer to figure 19-34 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear...
Page 574 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (continuous receive mode) Figure 19-37 Timing diagram of master reception (continuous receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception3 SDRmn data reception2 dummy data dummy data...
Page 575 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-38 Flowchart for master reception (continuous receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19~34(select buffer empty interrupt) SCI initial configuration For the received data, set the storage area and the...
Page 576: Master Transmission/Reception
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5.3 Master transmission/reception Master transmission/reception is an operation wherein the BAT32A237 outputs a transfer clock and transmits/receives data to/from other device. 3-wire serial I/O SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21...
Page 577 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register settings Figure 19-39 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Example of register settings for master transmission and reception (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 578 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-40 Initial set-up steps for transmission and reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 579 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-42 Restart set-up steps for master send and receive restart configuration starts. wait till commuication target (slave device) (mandatory) slave device ready? stops or communication ends via Configure port register and port mode...
Page 580 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single send and receive mode) Figure 19-43 Timing diagram for master transmission and reception (single transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception1...
Page 581 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-44 Flowchart for master transmission and reception (single transmit and receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19~42 (select transmission SCI initial configuration completion interrupt)
Page 582 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Processing flow (continuous transmit and receive mode) Figure 19-45 Timing diagram for master transmission and reception (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3...
Page 583 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-46 Flow chart for master tranmission and reception (continuous transmit and receive mode) SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19~40(select buffer empty interrupt)
Page 584: Slave Transmission
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5.4 Slave transmission Slave sending is the operation of the BAT32A237 microcontroller sending data to other devices in a state where a transfer clock is input from other devices. 3-wire serial I/O...
Page 585: Register Setting
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-47 3-wire derial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Examples of register setting contents for slave transmission (a) serial mode register mn (SMRmn) channel n operational clock （f ）...
Page 586 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-48 Initial set-up steps for slave transmission initial configuration starts release universal serial communication configure PER0 register unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 587 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-50 Restart set-up steps for slave transmission restart configuration starts. wait till commuication target (master device) master device stops or communication ends (mandatory) preparation complete? via Configure port register and port mode...
Page 588 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single transmit mode) Figure 19-51 Timing chart of slave transmission (single transmit mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 SCLKp pin...
Page 589 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-52 Flowchart for slave transmission (single transmit mode) SSPI communication starts relevant initial configure, please refer to SCI initial configuration diagram 19~48 (select transmission completion interrupt) regarding transmit data, configure storage region and...
Page 590 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (continuous transmit mode) Figure 19-53 Timing chart for slave tranmission (continuous transmit mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1 SCLKp pin...
Page 591 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-54 Flowchart for slave transmission (continuous transmit mode) SSPI communication starts relevant initial configure, please refer to SCI initial configuration diagram 19~48 (select buffer empty interrupt) regarding transmit data, configure storage region and data...
Page 592: Slave Reception
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5.5 Slave reception A slave receive is a run in which BAT32A237 receives data from other devices in a state in which a transfer clock is input from other devices. 3-wire serial I/O...
Page 593 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-55 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Example of register settings for slave reception (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 594 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-56 Initial set-up steps for slave reception initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 595 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-58 Restart set-up steps for slave reception restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 596 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single receive mode) Figure 19-59 Timing chart of slave reception (single receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception3 SDRmn data reception1 data reception2 Read...
Page 597 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-60 Flow chart for slave reception (single receive mode) SSPI communication starts relevant initial configuration, refer to figure 19-56 SCI initial configuration (select transmission completion interrupt) configure receiving data storage region, clear receiving...
Page 598: Slave Transmission/Reception
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5.6 Slave transmission/reception Slave transmission/reception is an operation wherein the BAT32A237 transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-wire serial I/O...
Page 599 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-61 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of Register settings for slave transmission and reception (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 600 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-62 Initial set-up steps for slave transmission and reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 601 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-63 Stop steps for slave transmission and reception stop configuration starts if there are ongoing data transmission, (selective) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 602 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-64 Restart set-up steps for slave transmission and reception restart configuration starts. wait till commuication target (master device) master device (essential) stops or communication ends preparation complete? via Configure port register and port mode...
Page 603 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single transmit and receive mode) Figure 19-65 Timing chart for slave transmission and reception (single trasmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception1...
Page 604 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-66 Flowchart for slave transmission and reception (single transmit and receive mode) SSPI communication starts relevant initial configuration, refer tofigure 19-62 SCI initial configuration (select transmission completion interrupt) regarding transmit and receive data, configure storage...
Page 605 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Processing flow (continuous transmit and receive mode) Figure 19-67 Timing chart for slave transmission and reception (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3...
Page 606 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-68 Flowchart for slave transmission and reception (continuous transmit and receive mode) SSPI communication starts relevant initial configuration, refer to figure SCI initial configuration 19-62(select buffer empty interrupt) regarding transmit data, configure storage region and data count (via...
Page 607: Calculation Of Transmission Clock Frequency
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5.7 Calculation of transmission clock frequency The transfer clock frequency for 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI20,SSPI21) communication can be calculated using the following formula. Master (Transfer clock frequency)={Operation clock frequency(F ) }(SDRmn[15:9] +1)2[Hz]...
Page 608 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Table 19-2 Selection of 3-wire serial I/O operation clock SMRmn Note SPSm register Operation clock (F register CKSmn =32 MHz 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz...
Page 609: Procedure For Handling Errors During 3-Wire I/O Communication
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.5.8 communication Procedure for handling errors during 3-wire I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) The procedure for handling an error that occurs during 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication is shown in Figure 19-69.
Page 610: Operation Of Clock-Synchronous Serial Communication With Slave Selection Input Function
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.6 Operation of clock-synchronous serial communication with slave selection input function Channel 0 of SCI0 is a channel that supports clock-synchronous serial communication with a slave select input function. [Data transmission and reception] •...
Page 611 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit The slave selection input function enables a master to communicate with multiple slave devices. The master outputs a slave selection signal to a slave device (1) of the communication object, and each slave device judges whether it is selected as the communication object and controls the output of the SDO pin.
Page 612 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-71 Timing chart of slave select input function DAPmn=0 configure transmit data BFFmn TSFmn SSEmn SCLKmn (CKPmn=0) SDImn sample timing sequence SDOmn SSmn When the SSmn is high, no transmission is performed even at the falling edge of SCKmn (serial clock) and no sampling of received data synchronized with the rising edge is performed.
Page 613: Slave Transmission
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.6.1 Slave transmission Slave transmission refers to the operation of the BAT32A237 to send data to other devices in the state of transmitting clocks from other device inputs. Slave select input function...
Page 614: Register Setting
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-72 Example of register settings when slave select input function (SSPI00) slave transmits (1/2) (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n...
Page 615 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-72 Example of register settings when slave select input function (SSPI00) slave transmits (2/2) (f) serial channel start register m (SSm) Only set bit of target channel to 1.
Page 616 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Operation procedure Figure 19-73 Initial set-up steps for slave transmission initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 617 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-74 Stop steps for slave transmission stop configuration starts if there are ongoing data transmission, TSFmn = 0？ (selective) then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 618 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-75 Restart set-up steps for slave transmission restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 619 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit (2) Process flow (single transmit mode) Figure 19-76 Timing chart for slave transmission (single transmit mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn transmit data1 SDRmn transmit data 2 transmit data 3...
Page 620 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-77 Flowchart of slave transmission (single transmit mode) SSPI communication starts relevant intial configure, please refer to diagram 19-79 (select transmission SCI initial configuration completion interrupt) regarding transmit data, configure storage region and data...
Page 621 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (continuous transmit mode) Figure 19-78 Timing chart for slave transmission (continuous transmit mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1 SCLKp pin...
Page 622 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-79 Flowchart of slave transmission (continuous transmit mode) SSPI communication starts relevant initial configure, please refer to SCI initial configuration diagram 19-73 (select buffer empty interrupt) regarding transmit data, configure storage region...
Page 623: Slave Reception
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.6.2 Slave reception Slave reception refers to the operation of the BAT32A237 receiving data from other devices in the state of transmitting clocks from other devices. Slave select input function...
Page 624 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-80 Slave select input function (SSPI00) Example of register setting content when slave receives (1/2) (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n...
Page 625 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-80 Slave select input function (SSPI00) Example of register setting content when slave receives (2/2) (f) serial channel start register m (SSm) Only set bit of target channel to 1.
Page 626 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-81 Initial set-up steps for slave reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 627 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-83 Restart set-up steps for slave reception restart configuration starts. wait till commuication target (master device) master device stops or communication ends preparation complete? (essential) via Configure port register and port mode...
Page 628 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single receive mode) Figure 19-84 Timing chart of slave reception (single receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3 SDRmn transmit data1 transmit data 2...
Page 629 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-85 Flow chart of slave reception (single receive mode) SSPI communication starts relevant initial configuration, refer to figure 19-81 SCI initial configuration (select transmission completion interrupt) configure receiving data storage region, clear receiving...
Page 630: Slave Transmission And Reception
19.6.3 Slave transmission and reception Slave transmission and reception refers to the operation of data transmission and reception of the BAT32A237 and other devices in the state of input transmission clock from other devices. Slave select input function SSPI00 Target channel...
Page 631: Register Setting
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-86 Slave selection input function (SSPI00) Example of register setting content when slave transmits and receives (1/2) (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 632 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-86 Slave selection input function (SSPI00) Example of register setting content when slave transmits and receives (2/2) (f) serial channel start register m (SSm) Only set bit of target channel to 1.
Page 633 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-87 Initial set-up steps for slave transmission and reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 634 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-88 Stop steps for slave transmission and reception stop configuration starts if there are ongoing data transmission, (selective) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 635 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-89 Restart set-up steps for slave transmission and reception restart configuration starts. wait till commuication target (master device) master device preparation (essential) stops or communication ends complete? via Configure port register and port mode...
Page 636 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single transmit and receive mode) Figure 19-90 Timing chart for slave transmission and reception (single transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception1...
Page 637 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-91 Flowchart of slave transmission and reception (single transmit and receive mode) SSPI communication starts relevant initial configuration, refer to figure 19-87 SCI initial configuration (select transmission completion interrupt)
Page 638 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Processing flow (continuous transmit and receive mode) Figure 19-92 Timing chart for slave transmission and reception (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3...
Page 639 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-93 Flowchart for slave transmission and reception (continuous transmit and receive mode) SSPI communication starts relevant initial configuration, refer to figure SCI initial configuration 19-87(select buffer empty interrupt) regarding transmit data, configure storage region and...
Page 640: Calculation Of Transmission Clock Frequency
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.6.4 Calculation of transmission clock frequency The transfer clock frequency of the SSPI00 communication can be calculated using the following formula. slave Note (Transfer Clock Frequency)={Serial Clock (SCLK) Frequency provided by the master device}...
Page 641: Selection Input Function
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.6.5 Procedure for handling errors during clock-synchronous serial communication with the slave selection input function The processing steps for errors that occur during clock synchronization serial communication with the slave select input function are shown in Figure 19-94.
Page 642: Operation Of Uart (Uart0~Uart2) Communication
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.7 Operation of UART (UART0~UART2) communication This is a function for asynchronous communication via a total of 2 lines, serial data transmission (TxD) and serial data reception (RxD). Using these two lines, asynchronous (using the internal baud rate) data is sent and received to and from other communicators in a data frame (consisting of the start bit, data, parity bit, and stop bit).
Page 643: Uart Transmission
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.7.1 UART transmission UART Send is an operation where the BAT32A237 microcontroller asynchronously sends data to other devices. The even of the 2 channels used by UART are for UART transmission.
Page 644: Register Setting
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-95 Example of register setting content when UART is transmitted by UART (UART0~UART2) (1/2) (a) serial mode register mn (SMRmn) channel n operational clock (fMCK) channel n interrupt source...
Page 645 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-95 Example of register setting content when UART is transmitted by UART (UART0~UART2) (2/2) (e) serial output register m (SOm) Only configure bit of target channel Note Note 0: serial data output value as "0"...
Page 646 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-96 Initial set-up steps for UART transmission initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 647 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-98 Restart set-up steps for UART transmission restart configuration starts. wait till commuication target (slave device) stops or (essential) Ready to communicate? communication ends The data output of the target channel is disabled by...
Page 648 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (single transmit mode) Figure 19-99 Timing chart for UART transmission (single transmit mode) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2...
Page 649 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-100 Flowchart of UART transmission (single transmit mode) UART communication starts relevant initial configuration, refer to figure 19-96 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag...
Page 650 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow (continuous transmit mode) Figure 19-101 Timing chart for UART transmission (continuous transmit mode) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2...
Page 651 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-102 Flowchart for UART transmission (continuous transmit mode) UART communication starts relevant initial configuration, refer to figure 19-96 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication...
Page 652: Uart Reception
19.7.2 UART reception UART Receive is an operation in which other devices of the BAT32A237 microcontroller receive data asynchronously. The odd number of the 2 channels used by UART is used for UART receiving. However, you need to set up SMR.
Page 653 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-103 Example of register setting contents for UART reception of UART (UART0~UART2)(1/2) (a) serial mode register mn (SMRmn) 0: normal receiving channel n operational clock (fMCK) channel N operational mode:...
Page 654 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-103 Example of register setting contents for UART reception of UART (UART0~UART2)(2/2) (e) serial output register m (SOm) Not used in this mode. (f) serial output enable register m (SOEm) Not used in this mode.
Page 655 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-104 Initial set-up steps for UART reception initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 656 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-106 Restart set-up steps for UART reception restart configuration starts. wait till commuication target stops or commuication target (essential) communication ends ready？ modify SPSm register re-configure when modifing operational clock...
Page 657: Process Flow
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow Figure 19-107 Timing chart of UART reception SSmn STmn SEmn transmit data 3 SDRmn transmit data1 transmit data 2 RxDq pin data reception 1 data reception 2 data reception 3...
Page 658 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-108 Flowchart of UART reception UART communication starts relevant initial configuration, refer to figure SCI initial configuration 19-104 (select transmission completion interrupt) configure reciving data storage region and communication data...
Page 659: Calculation Of Baud Rate
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.7.3 Calculation of baud rate Formula for Baud Rate The baud rate of UART(UART0~UART2) communication can be calculated by the following formula: (Baud rate)={Operation clock (F ) frequency}÷(SDRmn [15:9]+1) }÷2[bps] Caution: Disable from setting SDRmn[15:9] of serial data register mn(SDRmn) to 0000000B and 0000001B.
Page 660 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Table 19-5 Selection of UARToperation clock SMRmn Note SPSm register Operation clock (F register CKSmn =32 MHz in operation 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.63kHz...
Page 661 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Baud rate error when transmitting The baud rate error of UART (UART0~UART2) communication transmission can be calculated by the following formula, and the baud rate of the sender must be set within the allowable baud rate of the receiver.
Page 662 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Acceptable range of baud rate when revceiving The baud tolerance of UART (UART0~UART2) communication when receiving can be calculated by the following formula, and the baud rate of the sender must be set within the baud tolerance of the receiver.
Page 663: Handling Steps When An Error Occurs During Uart (Uart0~Uart2) Communication
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.7.4 Handling steps when an error occurs during UART (UART0~UART2) communication communication The processing steps when error occur during UART (UART0~UART2) communication are shown in Figure 19- 110 and Figure 19-111.
Page 664: Operation Of Lin Communication
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.8 Operation of LIN communication 19.8.1 LIN transmission UART0 supports LIN communication in UART delivery. LIN sends channel 0 of usage unit 0. UART UART0 UART1 UART2 LIN communication support —...
Page 665 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit LIN is the abbreviation of Local Interconnect Network, which is a low-speed (1~20kbps) serial communication protocol to reduce automobile network cost. LIN communications are single-master communications, with up to 15 slave devices connected to a single master device.
Page 666 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-113 Flowchart of LIN transmission hardware operation(reference) LIN transmit start Transmit wakeup signal frame (80H->TxD0) generate wakeup signal frame 8 bit Transmit wakeup TxD0 TSF00=0? Note signal frame transmit data wait for transmit result stop UART0(1->ST00 bit)
Page 667: Lin Reception
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.8.2 LIN reception In UART reception, UART0 supports LIN communication. LIN reception uses channel 1 of unit 0. UART UART0 UART1 UART2 UART3 LIN communication support — — — Target channel Channel 1 of SCI0 —...
Page 668 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit A summary of the LIN receive operation is shown in Figure 19-114. Figure 19-114 LIN receive operation wake up signal frame break field sync field ID field data field data field...
Page 669 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-115 Flowchart of LIN reception LIN Bus signal state and hardware operation. LIN communication starts wake up signal frame wait for wake up signal INTTM03 occurs? NOTE. RxD0 pin frame.
Page 670 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit The port structure diagram for LIN receive operations is shown in Figure 19-116. The wake-up signal sent by the LIN master is received through edge detection of the INTP0. The invention can measure the length of the synchronization segment sent by the LIN master and calculate the baud rate error through external event capture operation.
Page 671 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit The peripheral functions used for LIN communication operation are summarized below: <Peripheral function used> • External interrupt (INTP0): Detection of wake-up signal Purposes of use: Detects edges of wake-up signals and the start of communication.
Page 672: Communication (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21)
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.9 Operation of simplified I C communication (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) This is a function to communicate with multiple devices by clock synchronization through a total of 2 lines of serial clock (SCL) and serial data (SDA).
Page 673: Address Field Transmission
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.9.1 Address field transmission Address filed transmission is the first transmission operation performed during I2C communication to specifically designate the transmission target (slave device). After generating the start condition, the address (7 bits) and transmission direction (1 bit) are sent as 1 frame.
Page 674 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-117 Example of register setting content for Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) address field transmission (a) serial mode register mn (SMRmn) Note1 Note1 channel n operational clock （fMCK）...
Page 675 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Procedure Figure 19-118 Initial set-up steps for address field transmission initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 676 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow Figure 19-119 Timing chart for address field transmission address field transmit SDLr output bit operation SDAr output Somn bit operation address SDAr input shift operation shift register mn...
Page 677 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-120 Flowchart of address field transmission address field transmit relevant initial configuration, refer to initial configuration figure 19-118 set SOmn bit to '0'. set SOmn bit to '0'. generate start condition...
Page 678: Data Transmission
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.9.2 Data transmission Data transmission is the operation of transmitting data to the transmission object (slave device) after the address segment is transmitted. A stop condition is generated after all data is sent to the object slave and the bus is released.
Page 679 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-121 Example of register setting content for simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) dat transmission (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 680 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow Figure 19-122 Timing chart of data transmission transmit data 1 SDLr output SDAr output SDAr input shift register mn shift operation Figure 19-123 Flow chart of data transmission address field transmit completes.
Page 681: Data Reception
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.9.3 Data reception Data reception is a run that receives data from a transfer object (slave) after sending an address segment. A stop condition is generated and the bus is released after receiving all the data from the object slave.
Page 682 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Register setting Figure 19-124 Example of register setting content for simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) data reception (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 683 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Process flow Figure 19-125 Timing chart of data reception (a) Start of receiving data dummy data(FFH) receiving data SCLr output SDAr output SDAr input shift register mn shift operation (b) Status of receiving the last data...
Page 684 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Figure 19-126 Flow chart of data reception address field transmit completes. data reception stop operation in order to modify set STmn bit to 1. SCRmn register cofigure channel operation mode to write "0"...
Page 685: Generation Of Stop Conditions
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.9.4 Generation of stop conditions After all data has been transmitted and received with the target slave, a stop condition is generated and the bus is released. Process flow Figure 19-127 Timing chart of stop condition generation...
Page 686: Calculation Of Transfer Rate
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.9.5 Calculation of transfer rate The transfer rate for simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication can be calculated using the following formula. (Transfer rate)={Operation clock frequency (F )of the target channel} (SDRmn÷[15:9]+1)2...
Page 687 BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit Table 19-6 Simplified I C operation clock selection SMRmn Note SPSm register Operation clock (F register CKSmn =32 MHz in operation 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz...
Page 688: Processing Steps When An Error Occurs In A Simplified I
BAT32A237 User Manual | Chapter 19 Universal Serial Communication Unit 19.9.6 Processing steps when an error occurs in a simplified I C (IIC00, IIC01, IIC10, communication IIC11, IIC20, IIC21) The processing steps when an error occurs during a simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication are shown in Figures 19-129 and 19-130.
Page 689: Chapter 20 Serial Interface Iica
BAT32A237 User Manual | Chapter 20 Serial Interface IICA Chapter 20 Serial Interface IICA 20.1 Function of serial interface IICA The serial interface IICA has the following 3 modes. (1) Run stop mode This is a mode for non-serial transfer, which reduces power consumption.
Page 690 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-1 Block diagram of serial interface IICA www.mcu.com.cn 690 / 1066 V1.0.4...
Page 691 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Examples of serial bus structures are shown in Figure 20-2. Figure 20-2 Example of a serial bus structure for I C bus serial data bus master CPU2 master CPU1 SDAAn SDAAn...
Page 692: Structure Of Serial Interface Iica
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.2 Structure of serial interface IICA The serial interface IICA consists of the following hardware. Table 20-1 Structure of serial interface IICA Item Structure IICA shift register n (IICAn) Register Slave address register n (SVAn)
Page 693: Slave Address Register N (Svan)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.2.2 Slave address register n (SVAn) This is a register that holds the 7-bit local station address {A6, A5, A4, A3, A2, A1, A0} when used as a slave. The SVAn register is set by an 8-bit memory manipulation instruction. However, rewriting this register is prohibited when the STDn bit is 1 (start condition detected).
Page 694: Ack Generation Circuit, Stop Condition Detection Circuit, Start Condition Detection Circuit, Ack Detection Circuit
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.2.9 Ack generation circuit, stop condition detection circuit, start condition detection circuit, Ack detection circuit These circuits generate and detect various states. 20.2.10 Data hold time correction circuit This circuit generates a data hold time against a falling serial clock.
Page 695: Registers For Controlling Serial Interface Iica
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.3 Registers for controlling serial interface IICA The serial interface, IICA, is controlled through the following 8 registers. • Peripheral enable register 0 (PER0). • IICA control register n0 (IICCTLn0) •...
Page 696: Peripheral Enable Register 0 (Per0)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.3.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 697 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (1/4) Address: 0x40041A30 After reset: 00H Symbol ICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn IICCTLn0 ICEn C operation enable Note 1 Stop operation.
Page 698 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (2/4) Note 1 SPIEn Enable or disable interrupt requests generated by stop condition detection Disable Enable When the WUPn bit of IICA control register n1 (IICCTLn1) is 1, even if the SPIEN is 1, there is also no stop condition interrupt.
Page 699 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (3/4) STTn Triggering of the start condition Notes 1, 2 No start conditions are generated. When the bus is released (standby state, IICBSYn bit is 0): If this bit is 1, a start condition (boot as the master device) is generated.
Page 700 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (4/4) Note SPTn Trigger of stop condition No stop condition is generated. Generate a stop condition (end of transfer as master device).
Page 701: Iica Status Register N (Iicsn)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.3.3 IICA status register n (IICSn) This is a register that represents the I C status. The ICSn register can be read by an 8-bit memory manipulation instruction only when the STTn bit is 1 and waiting.
Page 702: Master And Slave
BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-7 Format of IICA state register n(IICSn) (2/3) EXCn Reception detection of extended codes No extension code is received. An extension code is received. Clear condition (EXCn=0) Set condition (EXCn=1) ·...
Page 703 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-7 Format of IICA state register n(IICSn) (3/3) ACKDn Detection of acknowledge No Ack is detected. An Ack is detected. Clear condition (ACKDn=0) Set condition (ACKDn=1) · When a stop condition is detected ·...
Page 704: Iica Flag Register N (Iicfn)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.3.4 IICA flag register n (IICFn) This is a register that sets the I C operating mode and indicates the status of the I C-bus. The IICFn register is set by an 8-bit memory manipulation instruction. However, only the STTn clear flag (STCFn) and I C bus status flag (IICBSYn) can be read.
Page 705 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-8 Format of IICA flag register n(IICFn) Note Address: 0x40041B52 After reset: 00H Symbol IICFn STCFn ICBSYn STCENn IICRSVn STCFn STTn clear flag Release start conditions. The STTn flag cannot be cleared while the start condition cannot be issued.
Page 706: Iica Control Register N1 (Iicctln1)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.3.5 IICA control register n1 (IICCTLn1) This is a register used to set the I C operation mode and detect the status of the SCLAn and SDAAn pins. The IICCTLn1 register is set by an 8-bit memory manipulation instruction. However, only CLDn and DADn bits can be read.
Page 707 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-9 Format of IICA control register n1 (IICCTLn1) (2/2) CLDn Level detection of the SCLAn pin (valid only when the IICEn bit is 1). SCLAn pin is detected low. SCLAn pin is detected high.
Page 708: Iica Low Level Width Setting Register N (Iicwln)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.3.6 IICA low level width setting register n (IICWLn) This register controls the SCLAn pin signal low level width (tLOW) and the SDAAn pin signal output by the serial interface IICA.
Page 709: Port Mode Register X (Pmx)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.3.8 Port mode register x (PMx) This register sets the input/output of the port. When using the Pxx/SCLA0 pin as a clock input/output and the Pxx/SDAA0 pin as a serial data input/output, the port mode register PMx and the port output latch Px must be set to 0.
Page 710: Functions Of I
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.4 Functions of I C bus mode 20.4.1 Pin structure The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are structured as follows. (1) SCLAn..Input/output pin for serial clock...
Page 711: Setting Transfer Clock Via Iicwln And Iicwhn Registers
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.4.2 Setting transfer clock via IICWLn and IICWHn registers (1) Setting transfer clock on master side Transfer clock= IICWL+IICWH+F At this point, the optimal setpoints for the IICWLn register and the IICWHn register are as follows: (The fractional parts of all setting values are rounded up.)
Page 712 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Standard mode: F =1MHz(Min.) Remark: Calculate the rise time (TR) and fall time (TF) of the SDAAn and SCLAn signals separately, because they differ depending on the pull-up resistance and wire load.
Page 713: Definition And Control Method Of I C Bus
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5 Definition and control method of I C bus C bus’s serial data communication format and the signals used by the I The following section describes the I bus. The figure below shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition”...
Page 714: Address
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.2 Address The subsequent 7-bit data for the start condition is defined as an address. The address is 7 bits of data output by the master device for selecting a specific slave device from among a plurality of slave devices connected to the bus.
Page 715: Acknowledge (Ack)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.4 Acknowledge (ACK) The serial data status of the sender and receiver can be confirmed by an acknowledgement (ACK). The receiver returns an ACK each time it receives an 8-bit data.
Page 716: Stop Condition
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.5 Stop condition A stop condition is generated if the SDAAn pin changes from low to high while the SCLAn pin is high. The stop condition is a signal generated when the master device ends serial transfer to the slave device. The stop condition is detected when the device is used as a slave.
Page 717: Wait
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.6 Wait Notify the other party that the master or slave device is preparing data for transmitting/receiving (wait state) by waiting. Notify the other party that it is in a waiting state by setting the SCLAn pin low. If both the master and slave wait states are released, the next transfer can begin.
Page 718 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-19 Wait (2/2) (2) When both the master and slave devices are waiting for 9 clocks (master transmits, slave receives, and ACKEn = 1) master device and master slave device all enter...
Page 719: Waitinging Release Method
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.7 Waitinging release method In general, the I C can release the wait by the following methods. • Write data to the IICA shift register n(IICAn). • Set the bit5(WRELn) of the IICA control register n0(IICCTLn0) (release wait).
Page 720: Generation Timing And Waiting Control Of Interrupt Requests (Intiican)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.8 Generation timing and waiting control of interrupt requests (INTIICAn) By setting the bit3 (WTIMn) of the IICA control register n0 (IICCTLn0), INTIICAn is generated at the timing shown in Table 20-2 and wait control is performed.
Page 721: Detection Method For Address Matching
BAT32A237 User Manual | Chapter 20 Serial Interface IICA (4) Release method of waiting There are 4 ways to release from waiting: ① Writes data to IICA shift register n (IICAn). ② Sets the bit5 (WRELn) of the IICA control register n0 (IICCTLn0) (wait released).
Page 722: Extension Code
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.11 Extension code (1) When the high 4 bits of the receiving address are "0000" or "1111", as the received extension code, the extended code receive flag (EXCn) is set to "1", and in the 8th The falling edge of the clock generates an interrupt request (INTIICAn).
Page 723: Arbitration
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.12 Arbitration When multiple master devices generate start conditions at the same time (Set STTn bit to 1 before the STDn bit becomes 1), the communication of the master device is carried out while adjusting the clock until the data is different.
Page 724 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Table 20-4 Status at the time of arbitration and timing of generation of interrupt requests The state in which the arbitration occurred Timing of the generation of interrupt requests During address transmission...
Page 725: Wake-Up Function
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.13 Wake-up function This is a slave function of I C, which is the function of generating an interrupt request signal (INTIICAn) when the local station address and extension code are received. The processing efficiency is improved by not generating unwanted INTIICAn signals under different addresses.
Page 726 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-22 Flow when the WUPn bit is set to 0 by address matching (including receiving extension codes) Deep sleep mode state INTIICAn=1？ WUPn=0 Wait Wait for 5 F clocks. Read IICSn After confirming the operational status of the serial interface IICA, process according to what is to be executed.
Page 727 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-23 Operation as master device after being released from deep sleep mode by an interrupt other than INTIICAn START SPIEn=1 WUPn=1 Wait Deep sleep instruction Deep sleep mode state Release from deep sleep...
Page 728: Communication Reservation
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.14 Communication reservation (1) When communication reservation function is enabled (bit0 (IICRSVn)=0 of the IIC flag register n (IICFn)) To perform the next master communication without using the bus, you can send a start condition when the bus is released through a communication reservation.
Page 729 BAT32A237 User Manual | Chapter 20 Serial Interface IICA The timing of the communication reservation is shown in Figure 20-24. Figure 20-24 Timing of communication reservation Write STTn=1 Program processing IICAn Set SPDn Communi- Hardware processing cation STDn reservation INTIICAn...
Page 730 BAT32A237 User Manual | Chapter 20 Serial Interface IICA The steps of the communication reservation are shown in Figure 20-26. Figure 20-26 Steps for communication reservation Stop interrupt request Sets STTn flag STTn=1 (communication reservation) Defines that communication reservation is...
Page 731 BAT32A237 User Manual | Chapter 20 Serial Interface IICA (2) When communication reservation function is disabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 1) When bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
Page 732: Cautions
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.15 Cautions (1) When STCENn = 0 Immediately after I C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 733: Communication Operation
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.16 Communication operation The following shows three operation procedures with flowcharts. (1) Master operation in single master system The flowchart when using as the master in a single master system is shown below.
Page 734 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Master operation of single-master system Figure 20-27 Master operation of single-master system START release serial interface IICA from reset state, configure PER0 register start providing clock. I2C bus initialization. Note. configure pins and multiplexed ports to be used.
Page 735: Master Operation In Multi-Master System
BAT32A237 User Manual | Chapter 20 Serial Interface IICA (2) Master operation in multi-master system Figure 20-28 Master operation in multi-master system (1/3) START release serial interface IICA from reset state, configure PER0 register start providing clock. configure pins and multiplexed ports to be used.
Page 736 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-28 Master operation in multi-master system (2/3) allow communication preservation prepare starting STTn=1 communication. (generate stop condition) ensure wait time via Wait Note. software. MSTSn=0？ does INTIICAn interrupt occur? wait to release bus.
Page 737 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-28 Master operation in multi-master system (3/3) Start communication. Write IICAn (Specify address and transfer direction) does INTIICAn interrupt wait for detecing occur? acknowledgement MSTSn=1？ ACKDn=1？ TRCn=1？ ACKEn=1 WTIMn=0 WTIMn=1...
Page 738 BAT32A237 User Manual | Chapter 20 Serial Interface IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
Page 739 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-29 Slave operation flowchart (1) START release serial interface IICA from reset state, configure PER0 register start providing clock. configure pins and multiplexed ports to be used. Configure Port First port configured to be input mode and output latch set to "0“...
Page 740 BAT32A237 User Manual | Chapter 20 Serial Interface IICA An example of the steps for slave device processing via the INTIICAn interrupt is shown below (it is assumed that there is no processing with the extension code here). Confirm the status via the INTIICAn interrupt and perform the following processing.
Page 741: Timing Of I C Interrupt Request (Intiican) Generation
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.5.17 Timing of I C interrupt request (INTIICAn) generation The values of the data send and receive timing, the timing of the generation of the INTIICAn interrupt request signal, and the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Page 742 BAT32A237 User Manual | Chapter 20 Serial Interface IICA master run Start~Address~Data~Data~Stop (transmit and receive) When WTIMn=0 SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B Note 3:IICSn=1000X000B(set the WTIMn bit to 1) 4:IICSn=1000XX00B(set the SPTn bit to 1) 5:IICSn=00000001B Note: To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal.
Page 743 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Start~Address~Data~Start~Address~Data~Stop (restart) When WTIMn=0 STTn=1 SPTn=1 ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=1000X110B Note1 2:IICSn=1000X000B(set the WTIMn bit to 1) 3:IICSn=1000XX00B(set the WTIMn bit to 0. Note 2 and set the STTn bit to 1)
Page 744 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Start~Code~Data~Data~Stop (extension code transmission) When WTIMn=0 SPTn=1 ST AD6~AD0 D7~D0 D7~D0 1:IICSn=1010X110B 2:IICSn=1010X000B Note 3:IICSn=1010X000B(Set the WTIMn bit to 1) 4:IICSn=1010XX00B(Set the SPTn bit to 1) 5:IICSn=00000001B Note To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request sign al.
Page 745 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Slave operation (when receiving a slave address) Start~Address~Data~Data~Stop When WTIMn=0 ST AD6~AD0 D7~D0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X000B 4:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1 (ii) When WTIMn=1 ST AD6~AD0 R/W ACK...
Page 746 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Start~Address~Data~Start~Address~Data~Stop When WTIMn=0 (after restart, matches with SVAn) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1 (ii) When WTIMn=1 (after restart, matches with SVAn)
Page 747 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Start~Address~Data~Start~Code~Data~Stop (i) When WTIMn=0 (after restart, does not match address (= extension code)) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1...
Page 748 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Start~Address~Data~Start~Address~Data~Stop When WTIMn=0 (after restart, does not match address (= not extension code)) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=00000110B 4:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1...
Page 749 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Slave operation (when receiving extension code) The device is always participating in communication when it receives an extension code. Start~Code~Data~Data~Stop When WTIMn=0 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X000B...
Page 750 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Start~Code~Data~Start~Address~Data~Stop When WTIMn=0 (after restart, matches SVAn) ST AD6~AD0 R/W D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1 (ii) When WTIMn=1 (after restart, matches SVAn)
Page 751 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Start~Code~Data~Start~Code~Data~Stop When WTIMn=0 (after restart, extension code reception) ST AD6~AD0 R/W D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1 (ii) When WTIMn=1 (after restart, extension code reception)
Page 752 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Start~Code~Data~Start~Address~Data~Stop (i) When WTIMn=0 (after restart, does not match address (= not extension code)) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=00000X10B 4:IICSn=00000001B Always generated Generated only when SPIEn = 1...
Page 753 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Operation without communication Start~Code~Data~Data~Stop Remark (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result.
Page 754 BAT32A237 User Manual | Chapter 20 Serial Interface IICA When WTIMn=1 (ii) ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=0101X110B 2:IICSn=0001X100B 3:IICSn=0001XX00B 4:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1 (b) When arbitration loss occurs during transmission of extension code...
Page 755: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
BAT32A237 User Manual | Chapter 20 Serial Interface IICA When WTIMn=1 (ii) ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=0110X010B 2:IICSn=0010X110B 3:IICSn=0010X100B 4:IICSn=0010XX00B 5:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1 (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result.
Page 756 BAT32A237 User Manual | Chapter 20 Serial Interface IICA (b) When arbitration loss occurs during transmission of extension code ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=01000110B Set LRELn = 1 by software 2:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1...
Page 757 BAT32A237 User Manual | Chapter 20 Serial Interface IICA (ii) When WTIMn=1 ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=10001110B 2:IICSn=01000100B 3:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1 When loss occurs due to restart condition during data transfer Not extension code (Example: unmatches with SVAn)
Page 758 BAT32A237 User Manual | Chapter 20 Serial Interface IICA (ii) Extension code ST AD6~AD0 R/W ACK D7~Dm ST AD6~AD0 R/W ACK D7~D0 1:IICSn=1000X110B 2:IICSn=01000010B Set LRELn = 1 by software 3:IICSn=00000001B Remark Always generated Generated only when SPIEn = 1...
Page 759 BAT32A237 User Manual | Chapter 20 Serial Interface IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition When WTIMn=0 STTn=1 ST AD6~AD0 R/W D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(Set the WTIMn bit to 1)
Page 760 BAT32A237 User Manual | Chapter 20 Serial Interface IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn=0 STTn=1 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(Set the WTIMn bit to 1)
Page 761 BAT32A237 User Manual | Chapter 20 Serial Interface IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition When WTIMn=0 SPTn=1 ST AD6~AD0 R/W D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(Set the WTIMn bit to 1)
Page 762: Timing Diagram
BAT32A237 User Manual | Chapter 20 Serial Interface IICA 20.6 Timing diagram When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (the bit 3 of the IICA status register n (IICSn)), which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 763 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-31 Example of master to slave communication (Master: selects 9 clocks to wait, slave: selects 9 clocks to wait) (1/4) (1) Start Condition ~ Address ~ Data master control Note...
Page 764 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Note 2: Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is at least 4.0 μs when specifying standard mode and at least 0.6 μs when specifying fast mode.
Page 765 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-31 shows the descriptions of ① to ⑥ of “(1) Start condition ~ Address ~ Data” ① If the master sets the start condition trigger set (STTn=1), the bus data line (SDAAn) drops and the start condition is generated (SDAAn is changed from "1"...
Page 766 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-31 Example of master to slave communication (Master: selects 9 clocks to wait, slave: selects 9 clocks to wait) (2/4) (2) Address~Data~Data master control note note 1 IICAn ACKDn （ACK detection ）...
Page 767 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-31 shows the descriptions of ③ to ⑩ of “(2) Address~Data~Data”: ③ On the slave, if the receiving address and the local station address (the value of the SVAn) are the same Note the ACK is sent to the master through the hardware.
Page 768 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-31 Example of master to slave communication (Master: selects 9 clocks to wait, slave: selects 9 clocks to wait) (3/4) 20.2.2 Data~Data~Stop Condition master control IICAn note1 ACKDn （ACK detection ）...
Page 769 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Note 1: Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master device. Note 2: After the stop condition is issued, the time from the SCLAn pin signal to generate the stop condition is at least 4.0μs when set to standard mode and at least 0.6μs when set to fast mode.
Page 770 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-31 Example of master to slave communication (Master: selects 9 clocks to wait, slave: selects 9 clocks to wait) (4/4) (4) Data ~ Restart Condition ~ Address master control IICAn <3>...
Page 771 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Note 1: Make sure that the time between the rise of the SCLAn pin signal and the generation of the start condition after a restart condition has been issued is at least 4.7 μs when specifying standard mode and at least 0.6 μs when specifying fast mode.
Page 772 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-32 Example of slave to master communication (Master: selects 8 clocks to wait, slave: selects 9 clocks to wait) (1/3) (1) Start Condition ~ Address ~ Data master control IICAn ACKDn （ACKdetection）...
Page 773 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Note 3: To release the slave from waiting during transmission, you must write data to the IICn instead of setting the WRELn bit. Figure 20-32 shows ① to ⑦ of “(1) Start condition~Address~Data” as follows.
Page 774 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-32 Example of slave to master communication (Master: selects 8 clocks to wait, slave: selects 9 clocks to wait) (2/3) (2) Address~Data~Data master control IICAn ACKDn （ACKdetection） WTIMn （8 or 9 clock cycles waiting）...
Page 775 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-32 shows ③~⑫ of “(2) Address~Data~Data” as follows. ③ On the slave, if the receiving address and the local station address (the value of the SVAn) are the same Note the ACK is sent to the master through the hardware.
Page 776 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Figure 20-32 Example of slave to master communication (Master: selects 8 clocks to wait, slave: selects 9 clocks to wait) (3/3) Data~Data~Stop Condition master control IICAn ACKDn （ACKdetection） WTIMn （8 or 9 clock cycles waiting）...
Page 777 BAT32A237 User Manual | Chapter 20 Serial Interface IICA Note 1: To release the wait, the IICAn must be set to “FFH” or the WRELn bit must be set. Note 2: After the stop condition is issued, the time from the SCLAn pin signal to generate the stop condition is at least 4.0μs when set to standard mode and at least 0.6μs when set to fast mode.
Page 778: Chapter 21 Can Controller
BAT32A237 User Manual | Chapter 21 CAN Controller Chapter 21 CAN Controller 21.1 Overview The chip features an on-chip CAN controller (Controller Area Network) function and is compliant with the CAN protocol in the ISO 11898 standard. 21.1.1 Features Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) Standard and extended frames for receiving and transmitting Communication speed: max.
Page 779: Overview Of Functions
BAT32A237 User Manual | Chapter 21 CAN Controller 21.1.2 Overview of functions Table 21-1 lists functions of the CAN controller. Table 21-1 Functional Overview Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Max: 1 Mbps (CAN input ≥ clock 8MHz)
Page 780: Configuration
BAT32A237 User Manual | Chapter 21 CAN Controller 21.1.3 Configuration The CAN controller is composed of the following four blocks. Interface This functional block provides an internal bus interface and means of transmitting and receiving signals between the CAN module and the host CPU.
Page 781: Can Protocol
BAT32A237 User Manual | Chapter 21 CAN Controller 21.2 CAN protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications.
Page 782: Frame Types
BAT32A237 User Manual | Chapter 21 CAN Controller 21.2.2 Frame types The four frame types in the following table are used in the CAN protocol. Table 21-2 Frame types Frame type Description Data frame Frames used to transmit data Remote frame...
Page 783 BAT32A237 User Manual | Chapter 21 CAN Controller (5) Remote frame A remote frame is composed of six fields. Figure 21-4 Remote frame Remote frame Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remark: 1.
Page 784 BAT32A237 User Manual | Chapter 21 CAN Controller <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 21-6 Arbitral field (in standard format mode) Arbitration field Control field Identifier Identifier...
Page 785 BAT32A237 User Manual | Chapter 21 CAN Controller <3> Control field The control field sets “DLC” as the number of data bytes in the data field (DLC=0 to 8). Figure 21-8 Control field (Arbitration field) Control field (Data field) Remark: D: Dominant = 0 R: Recessive = 1 In a standard format frame, the control field’s IDE bit is the same as the r1 bit.
Page 786 BAT32A237 User Manual | Chapter 21 CAN Controller <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 21-9 Data field Remark: D: Dominant = 0 R: Recessive = 1 <5>...
Page 787 BAT32A237 User Manual | Chapter 21 CAN Controller <6> ACK field The ACK field is used to acknowledge normal reception. Figure 21-11 ACK field Remark: D: Dominant = 0 R: Recessive = 1 - If no CRC error is detected, the receiving node sets the ACK slot to the dominant level.
Page 788 BAT32A237 User Manual | Chapter 21 CAN Controller <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. - The bus state differs depending on the error status.
Page 789: Error Frame
BAT32A237 User Manual | Chapter 21 CAN Controller 21.2.4 Error frame An error frame is output by a node that has detected an error. Figure 21-15 Error frame Remark: D: Dominant = 0 R: Stealth=1 Table 21-7 Definition of error frame fields...
Page 790: Overload Frame
BAT32A237 User Manual | Chapter 21 CAN Controller 21.2.5 Overload frame An overload frame is transmitted under the following conditions. Note1 - When the receiving node has not completed the reception operation - If a dominant level is detected at the first two bits during intermission...
Page 791: Functions
BAT32A237 User Manual | Chapter 21 CAN Controller 21.3 Functions 21.3.1 Bus priority configuration (1) When a node starts transmission: - During bus idle, the node that output data first transmits the data. (2) When more than one node starts transmission:...
Page 792: Error Control Function
BAT32A237 User Manual | Chapter 21 CAN Controller 21.3.6 Error control function (4) Error types Table 21-11 Error types Error description Detection status Type Detection Detection method Transmit/Receive Field/Frame condition Bit that outputting data on the bus Comparison of output level and...
Page 793 BAT32A237 User Manual | Chapter 21 CAN Controller (7) Error state (a) Types of error states he following three types of error states are defined by the CAN specification. - Error active - Error passive - Bus-off These types of error states are classified by the values of the TEC7 to TEC0 bits (transmission error counter bits) and the REC6 to REC0 bits (reception error counter bits) of the CAN error counter register (C0ERC) as shown in Table 21-13.
Page 794 BAT32A237 User Manual | Chapter 21 CAN Controller (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter is updated immediately after error detection. Table 21-14 Error counter...
Page 795 BAT32A237 User Manual | Chapter 21 CAN Controller (8) Recovery from bus-off state When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTxD) to recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
Page 796 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-17 Recovery operation from bus-off state by normal recovery sequence TEC>FFH »error passive« »bus off « »bus-off-recovery-sequence« »error active« BOFFbit of C0INFO C0CTRL in OPMODE[2:0] （user writings） C0CTRL in OPMODE[2:0] （user readings）...
Page 797: Baud Rate Control
BAT32A237 User Manual | Chapter 21 CAN Controller 21.3.7 Baud rate control (10) Prescaler The CAN controller has a pre-scaling for dividing a clock (f ) provided to the CAN. This pre-scaling generates a CAN protocol layer basic clock (f...
Page 798 BAT32A237 User Manual | Chapter 21 CAN Controller Reference: The CAN standard ISO 11898 specification defines the segments constituting the data bit time as shown in Figure 21-19. Figure 21-19 Reference: Data bit time configuration defined by CAN specification Data bit time (DBT)
Page 799 BAT32A237 User Manual | Chapter 21 CAN Controller (12) Synchronization data bit - The receiving node establishes synchronization by a level change on the bus because it has no asynchronous signal. - The transmission node transmits data synchronously at the bit time of the transmission node...
Page 800 BAT32A237 User Manual | Chapter 21 CAN Controller (b) Resynchronization Synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). - The phase error of the edge is given by the relative position of the detected edge and the synchronization segment.
Page 801: Connection With Target System
BAT32A237 User Manual | Chapter 21 CAN Controller 21.4 Connection with target system The microcontroller incorporated a CAN has to be connected to the CAN bus using an external transceiver. Figure 21-22 Connection to the CAN bus CAN_L CAN_H www.mcu.com.cn 801 / 1066 V1.0.4...
Page 802: Internal Registers Of Can Controller
BAT32A237 User Manual | Chapter 21 CAN Controller 21.5 Internal registers of CAN controller 21.5.1 CAN controller configuration Table 21-15 List of CAN controller registers (1/2) Item Register name Peripheral enable register 0 (PER0) Serial communication pin select register (PIOR3)
Page 803 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-15 List of CAN controller registers (2/2) Item Register name CAN message data byte 01 register m (C0MDB01m) CAN message data byte 0 register m (C0MDB0m) CAN message data byte 1 register m (C0MDB1m)
Page 804: Register Access Type
BAT32A237 User Manual | Chapter 21 CAN Controller 21.5.2 Register access type The peripheral I/O register for the CAN controller is assigned to 0x40045400 to 0x400455FF. Table 21-16 Register access types (1/9) Bit manipulation unit Address Register name Symbol Default value √...
Page 805 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-16 Register access types (2/9) Bit manipulation unit Address Register name Symbol Default value √ 0x40045500H CAN0 message data byte 01 register 00 C0MDB0100 Undefined √ 0x40045500H CAN0 message data byte 0 register 00...
Page 806 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-16 Register access types (3/9) Bit manipulation unit Address Register name Symbol Default value √ 0x40045520H CAN0 message data byte 01 register 02 C0MDB0102 Undefined √ 0x40045520H CAN0 message data byte 0 register 02...
Page 807 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-16 Register access types (4/9) Bit manipulation unit Address Register name Symbol Default value √ 0x40045540H CAN0 message data byte 01 register 04 C0MDB0104 Undefined √ 0x40045540H CAN0 message data byte 0 register 04...
Page 808 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-16 Register access types (5/9) Bit manipulation unit Address Register name Symbol Default value √ 0x40045560H CAN0 message data byte 01 register 06 C0MDB0106 Undefined √ 0x40045560H CAN0 message data byte 0 register 06...
Page 809 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-16 Register access types (6/9) Bit manipulation unit Address Register name Symbol Default value √ 0x40045580H CAN0 message data byte 01 register 08 C0MDB0108 Undefined √ 0x40045580H CAN0 message data byte 0 register 08...
Page 810 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-16 Register access types (7/9) Bit manipulation unit Address Register name Symbol Default value √ 0x400455A0H CAN0 message data byte 01 register 10 C0MDB0110 Undefined √ 0x400455A0H CAN0 message data byte 0 register 10...
Page 811 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-16 Register access types (8/9) Bit manipulation unit Default Address Register name Symbol value √ 0x400455C0H CAN0 message data byte 01 register 12 C0MDB0112 Undefined √ 0x400455C0H CAN0 message data byte 0 register 12...
Page 812 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-16 Register access types (9/9) Bit manipulation unit Default Address Register name Symbol value √ 0x400455E0H CAN0 message data byte 01 register 14 C0MDB0114 Undefined √ 0x400455E0H CAN0 message data byte 0 register 14...
Page 813: Register Bit Configuration
BAT32A237 User Manual | Chapter 21 CAN Controller 21.5.3 Register bit configuration Table 21-17 Bit configuration of CAN global register Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 0x40045400H Clear GOM...
Page 814 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-18. Bit configuration of CAN module registers (1/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 0x40045440H CM1ID[7:0] C0MASK1L 0x40045441H CM1ID [15:8]...
Page 815 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-18. Bit configuration of CAN module registers (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 0x40045458H CINTS5 CINTS4 CINTS3 CINTS2...
Page 816 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-19 Bit configuration of message buffer registers Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 0x400455x0H Message data (byte 0) C0MDB01m...
Page 817: Bit Set/Clear Function
BAT32A237 User Manual | Chapter 21 CAN Controller 21.6 Bit set/clear function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 818 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-24 16-bit data during write operation Clear Clear Clear Clear Clear Clear Clear Clear Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Set n...
Page 819: Control Registers
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7 Control registers Remark: m = 0 to 15 21.7.1 Peripheral clock select register (PER0) PER0 is used to enable or disable each peripheral hardware macro. The PER0 can be set by an 8-bit memory manipulation instruction.
Page 820: Can Global Module Control Register (C0Gmctrl)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.2 CAN global module control register (C0GMCTRL) The C0GMCTRL register is used to control the operation of the CAN module. Figure 21-26 Format of CAN global module control register (C0GMCTRL) (1/2) (a) Read...
Page 821 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-26 Format of CAN global module control register (C0GMCTRL) (2/2) EFSD Bit enabling forced shut down Forced shut down by GOM = 0 disabled. Forced shut down by GOM = 0 enabled.
Page 822: Can Global Module Clock Select Register (C0Gmcs)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.3 CAN global module clock select register (C0GMCS) The C0GMCS, C1GMCS register is used to select the CAN module system clock. Figure 21-27 Format of CAN global module clock select register (C0GMCS)
Page 823: Can Global Automatic Block Transmission Control Register (C0Gmbt)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.4 CAN global automatic block transmission control register (C0GMBT) The C0GMABT register is used to control the automatic block transmission (ABT) operation. Figure 21-28. Format of CAN global automatic block transmission control register (C0GMBT) (1/2)
Page 824 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-28 Format of CAN global automatic block transmission control register (C0GMBT) (2/2) ATTRG Automatic block transmit status bit Automatic block transfer is stopped. Automatic block transfer in under execution. Caution: Do not set the ABTTRG bit (ABTTRG = 1) in the initialization mode. If the ABTTRG bit is set in the initialization mode, the operation is not guaranteed after the CAN module has entered the normal operation mode with ABT.
Page 825: Can Global Automatic Block Transmission Delay Setting Register (C0Gmabtd)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.5 CAN global automatic block transmission delay setting register (C0GMABTD) The C0GMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT.
Page 826: Can Module Mask Register (C0Maskal, C0Maskah) (A = 1, 2, 3, Or 4)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.6 CAN module mask register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) The C0MASKaL and C0MASKaH registers are used to extend the number of receivable messages into the same message buffer by masking part of the ID comparison of a message and invalidating the ID of the masked part.
Page 827 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-30 Format of CAN module mask register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) (2/2) CAN module mask 3 register (C0MASK3L, C0MASK3H) CAN module mask 4 register (C0MASK4L, C0MASK4H)
Page 828: Can Module Control Register (C0Ctrl)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.7 CAN module control register (C0CTRL) The C0CTRL register is used to control the operation mode of the CAN module. Figure 21-31 Format of CAN module control register (C0CTRL) (1/4) (a) Read...
Page 829 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-31 Format of CAN module control register (C0CTRL) (2/4) TSTAT Transmit status bit Transmission is stopped Transmission is in progress Remark: The RSTAT bit is set to 1 under the following conditions (timing):...
Page 830 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-31 Format of CAN module control register (C0CTRL) (3/4) PSMODE1 PSMODE0 Power save mode No power save mode is selected CAN sleep mode Setting prohibited CAN stop mode Caution: 1. Transition to or wake from the CAN stop mode through the CAN sleep mode.
Page 831 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-31 Format of CAN module control register (C0CTRL) (4/4) Clear VALID Set VALID bit VALID is not changed. VALID is cleared to 0. Set PSMODE0 Clear PSMODE0 Set PSMODE0 bit PSMODE0 is cleared to 0.
Page 832: Can Module Last Error Code Register (C0Lec)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.8 CAN module last error code register (C0LEC) The C0LEC register provides the error information of the CAN protocol. Figure 21-32 Format of CAN module last error code register (C0LEC) Remark: 1. The contents of the C0 LEC register are not cleared when the CAN switches from the operation mode to the initialization mode.
Page 833: Can Module Information Register (C0Info)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.9 CAN module information register (C0INFO) The C0INFO register indicates the status of the CAN module Figure 21-33. Format of CAN module information register (C0INFO) BOFF Bus off status bit Not bus-off state (transmiterror counter less than 255) (transmit counter value less than 256)
Page 834: Can Module Error Counter Register (C0Erc)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.10 CAN module error counter register (C0ERC) The C0ERC register indicates the count value of the transmission/reception error counter. Figure 21-34 Format of CAN module error counter register (C0ERC) REPS Receive error passive status bit Receive error counter is not error passive (<128)
Page 835: Can Module Interrupt Enable Register (C0Ie)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.11 CAN module interrupt enable register (C0IE) The C0IE register is used to enable or disable the interrupts of the CAN module. Figure 21-35 Format of CAN module interrupt enable register (C0IE) (1/2)
Page 836 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-35 Format of CAN module interrupt enable register (C0IE) (2/2) Set CIE3 Clear CIE3 Set CIE3 bit CIE3 is cleared to 0. CIE3 is set to 1. Other than the above CIE3 is not changed.
Page 837: Can Module Interrupt Status Register (C0Ins)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.12 CAN module interrupt status register (C0INS) The C0INTS register register indicates the interrupt status of the CAN module. Figure 21-36 Format of CAN module interrupt status register (C0INS) (a) Read (b) Write...
Page 838: Can Module Bit Rate Prescaler Register (C0Brp)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.13 CAN module bit rate prescaler register (C0BRP) The C0BRP register is used to select the CAN protocol layer basic clock (fTQ). The communication baud rate is set to the C0BTR register...
Page 839: Can Module Bit Rate Register (C0Btr)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.14 CAN module bit rate register (C0BTR) The C0BTR register controls the bit time of the baud rate. Figure 21-39 Format of CAN module bit rate register (C0BTR) (1/2) SJW1 SJW0 Length of the synchronization jump width...
Page 840 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-39 Format of CAN module bit rate register (C0BTR) (2/2) TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited 10TQ 11TQ 12TQ 13TQ 14TQ 15TQ 16TQ (default value) Note 1: These settings must be performed when the C0BRP register is 00 H...
Page 841: Can Module Last In-Pointer Register (C0Lipt)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.15 CAN module last in-pointer register (C0LIPT) The C0LIPT register indicates the number of message buffers at which the data frame or remote frame was last stored. Figure 21-41 Format of CAN module last in-pointer register (C0LIPT)
Page 842: Can Module Receive History List Register (C0Rgpt)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.16 CAN module receive history list register (C0RGPT) The C0RGPT register is used to read the received history list. Figure 21-42 Format of CAN module receive history list register (C0RGPT) (1/2) (a) Read...
Page 843 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-42 Format of CAN module receive history list register (C0RGPT) (2/2) (b) Write Clear ROVF Setting of ROVF bit ROVF is not changed. ROVF is clear to 0. www.mcu.com.cn 843 / 1066...
Page 844: Can Module Last Out-Pointer Register (C0Lopt)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.17 CAN module last out-pointer register (C0LOPT) The C0LOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. Figure 21-43 Format of CAN module last out-pointer register (C0LOPT)
Page 845: Can Module Transmit History List Register (C0Tgpt)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.18 CAN module transmit history list register (C0TGPT) The C0TGPT register is used to read the transmit history list. Figure 21-44 Format of CAN module transmit history list register (C0TGPT) (1/2) (a) Read...
Page 846 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-44 Format of CAN module transmit history list register (C0TGPT) (2/2) (b) Write ClearTOVF Setting of TOVF bit TOVF is not changed. TOVF is cleared to 0. www.mcu.com.cn 846 / 1066...
Page 847: Can Module Time Stamp Register (C0Ts)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.19 CAN module time stamp register (C0TS) C0 TS register for controlling timestamp function Figure 21-45 Format of CAN module time stamp register (C0TS) (1/2) (a) Read (b) Write Remark: The lock function of the time stamp function must not be used when the CAN module is in the normal operation mode with ABT.
Page 848 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-45 Format of CAN module time stamp register (C0TS) (2/2) TSSEL Time stamp capture event selection bit The time stamp capture event is SOF. The time stamp capture event is the last bit of EOF.
Page 849: Can Message Data Byte Register (C0Mdbxm) (X = 0 To 7), (C0Mdbzm) (Z = 01, 23, 45, 67)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.20 CAN message data byte register (C0MDBxm) (x = 0 to 7), (C0MDBzm) (z = 01, 23, 45, The C0MDBxm, C0MDBzm registers are used to store the data of a transmit/receive message. The C0MDBxm register can be accessed in 8-bit units.
Page 850 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-46 Format of CAN message data byte register (C0MDBxm) (x = 0 to 7), (C0MDBzm) (z = 01, 23, 45, 67) (2/2) C0MDBzm register C0MDB01m MDATA01 MDATA01 MDATA0 MDATA01 MDATA01 MDATA01...
Page 851: Can Message Data Length Register M (C0Mdlcm)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.21 CAN message data length register m (C0MDLCm) The C0MDLCm register is used to set the number of bytes of the data field of a message buffer. Figure 21-47 Format of CAN message data length register m (C0MDLCm)
Page 852: Can Message Configuration Register (C0Mconfm)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.22 CAN message configuration register (C0MCONFm) The C0MCONFm register is used to specify the type of the message buffer and to set a mask. Figure 21-48 Format of CAN message configuration register (C0MCONFm) (1/2)
Page 853 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-48 Format of CAN message configuration register (C0MCONFm) (2/2) Message buffer assignment bit Message buffer not used. Message buffer used. Caution: Make sure to write 0 to bits 1 and 2.
Page 854: Can Message Id Register M (C0Midlm And C0Midhm)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.23 CAN message ID register m (C0MIDLm and C0MIDHm) The C0MIDLm and C0MIDHm registers are used to set an identifier (ID). Figure 21-49 Format of CAN message ID register m (C0MIDLm and C0MIDHm)
Page 855: Can Message Control Register M (C0Mctrlm)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.24 CAN message control register m (C0MCTRLm) The C0MCTRLm register is used to control the operation of the message buffer. Figure 21-50 Format of CAN message control register m (C0MCTRLm) (1/3) Address: See Table 21-16...
Page 856 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-50 Format of CAN message control register m (C0MCTRLm) (2/3) Message buffer data update bit A data frame or remote frame is not stored in the message buffer. A data frame or remote frame is stored in the message buffer.
Page 857 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-50 Format of CAN message control register m (C0MCTRLm) (3/3) Set TRQ Clear TRQ Setting of TRQ bit TRQ is cleared to 0. TRQ is set to 1. Other than the above TRQ is not changed.
Page 858: Serial Communication Pin Select Register 1 (Pior3)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.7.25 Serial communication pin select register 1 (PIOR3) The PIOR3 register is used to switch the input source to the timer array unit and the CAN communication pins. This register can be read or written in 8-bit unitsd.
Page 859: Can Controller Initialization
BAT32A237 User Manual | Chapter 21 CAN Controller 21.8 CAN controller initialization 21.8.1 CAN module initialization Before the CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the C0GMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 860 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-53 Setting transmission request (TRQ) to transmit message buffer after redefinition Waiting for 1-bit CAN data Set TRQ bit TRQ = 1 TRQ = 0 Caution: 1. When a message is received, reception filtering is performed in accordance with the ID and mask set to each receive message buffer.
Page 861: Transition From Initialization Mode To Operation Mode
BAT32A237 User Manual | Chapter 21 CAN Controller 21.8.4 Transition from initialization mode to operation mode The CAN module can be switched to the following operation modes. - Normal operation mode - Normal operation mode with ABT - Receive-only mode...
Page 862: Message Reception
BAT32A237 User Manual | Chapter 21 CAN Controller 21.9 Message reception 21.9.1 Message reception In all operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process).
Page 863: Receive Data Read
BAT32A237 User Manual | Chapter 21 CAN Controller 21.9.2 Receive data read To keep data consistency when reading CAN message buffers, perform the data reading according to Figure 21-76 to 21-78. During message reception, the CAN module sets DN of the C0MCTRLm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process.
Page 864: Receive History List Function
BAT32A237 User Manual | Chapter 21 CAN Controller 21.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding C0LIPT register and the receive history list get pointer (RGPT) with the corresponding C0RGPT register.
Page 865 BAT32A237 User Manual | Chapter 21 CAN Controller As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without reading the RHL by the host processor, complete sequence of receptions can not be recovered.
Page 866: Mask Function
BAT32A237 User Manual | Chapter 21 CAN Controller 21.9.4 Mask function For any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. By using the mask function, the message ID comparison can be reduced by masked bits, herewith allowing the reception of several different IDs into one buffer.
Page 867: Multi-Buffer Receive Block Function
BAT32A237 User Manual | Chapter 21 CAN Controller 21.9.5 Multi-buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.
Page 868: Remote Frame Reception
BAT32A237 User Manual | Chapter 21 CAN Controller 21.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions.
Page 869: Message Transmission
BAT32A237 User Manual | Chapter 21 CAN Controller 21.10 Message transmission 21.10.1 Message transmission In all the operation modes, if the TRQ bit is set to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched.
Page 870 BAT32A237 User Manual | Chapter 21 CAN Controller Priority Condition Description The message frame with the lowest value represented by the first 11 bits of the ID is transmitted first. If the value of an 11-bit standard ID is Value of first 11 bits of ID [ID28...
Page 871: Transmit History List Function
BAT32A237 User Manual | Chapter 21 CAN Controller 21.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding C0LOPT register, and the transmit history list get pointer (TGPT) with the corresponding C0TGPT register.
Page 872 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-58 Transmit history list Transmit history list (THL) Transmit history list (THL) Event: - CPU confirms message Message buffer 4 buffer 6,9 and 2 Transmit Message buffer 3 completion. Message buffer 7...
Page 873: Automatic Block Transmission (Abt)
BAT32A237 User Manual | Chapter 21 CAN Controller 21.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7).
Page 874 BAT32A237 User Manual | Chapter 21 CAN Controller Caution: Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume ABT operation at buffer No.0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to 1, the subsequent operation is not guaranteed.
Page 875: Transmission Abort Handling
BAT32A237 User Manual | Chapter 21 CAN Controller 21.10.4 Transmission abort handling Transmission abort process except for in normal operation mode with automatic block transmission (ABT) The user can clear the TRQ bit of the C0MCTRLm register to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful.
Page 876: Remote Frame Transmission
BAT32A237 User Manual | Chapter 21 CAN Controller resumption operation is not performed even if ABTTRG is set to 1, and ABT ends immediately. Remark: m = 0 to 15 21.10.5 Remote frame transmission Remote frames can be transmitted only from transmit message buffers. Set whether a data frame or remote frame is transmitted via the RTR bit of the C0MCONFm register.
Page 877: Power Save Modes
BAT32A237 User Manual | Chapter 21 CAN Controller 21.11 Power save modes 21.11.1 CAN sleep mode The CAN sleep mode may be use to set that CAN controller to standby mode to reduce power consumption. The CAN module may enter CAN sleep mode from all operation modes. Release of the CAN sleep mode returns the CAN module to exactly the same operation mode from which the CAN sleep mode was entered.
Page 878 BAT32A237 User Manual | Chapter 21 CAN Controller Even when initialization mode and sleep mode are not requested simultaneously (i.e the first request has not been granted while the second request is made), the request for initialization has priority over the sleep mode request.
Page 879: Can Stop Mode
BAT32A237 User Manual | Chapter 21 CAN Controller 21.11.2 CAN stop mode The CAN stop mode can be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode.
Page 880: Example Of Using Power Saving Modes
BAT32A237 User Manual | Chapter 21 CAN Controller 21.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.
Page 881: Interrupt Function
BAT32A237 User Manual | Chapter 21 CAN Controller 21.12 Interrupt function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
Page 882: Diagnostic Functions And Special Operational Modes
BAT32A237 User Manual | Chapter 21 CAN Controller 21.13 Diagnostic functions and special operational modes The CAN module provides a receive-only mode, single-shot mode, and self-test mode to support CAN bus diagnosis functions or the operation of specific CAN communication methods.
Page 883 BAT32A237 User Manual | Chapter 21 CAN Controller Caution: If only two CAN nodes are connected to the CAN bus and one of them is operating in the receive- only mode, there is no ACK on the CAN bus. Due to the missing ACK, the transmitting node will transmit an active error flag, and repeat transmitting a message frame.
Page 884: Single-Shot Mode
BAT32A237 User Manual | Chapter 21 CAN Controller 21.13.2 Single-shot mode In the single-shot mode, automatic re-transmission as defined in the CAN protocol is switched off (According to the CAN protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has to be repeated without control by software.).
Page 885: Self-Test Mode
BAT32A237 User Manual | Chapter 21 CAN Controller 21.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus.
Page 886: Receive/Transmit Operation In Each Operation Mode
BAT32A237 User Manual | Chapter 21 CAN Controller 21.13.4 Receive/transmit operation in each operation mode Table 21-21 shows a summary of receive/transmit operations in each mode of operation. Table 21-21 Summary of transmit/receive in each operation mode Transmission Transmission Automatic Block...
Page 887: Time Stamp Function
BAT32A237 User Manual | Chapter 21 CAN Controller 21.14 Time stamp function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies).
Page 888 BAT32A237 User Manual | Chapter 21 CAN Controller Caution: The time stamp function using TSLOCK bit is to stop toggle of TSOUT bit by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer.
Page 889: Baud Rate Setting
BAT32A237 User Manual | Chapter 21 CAN Controller 21.15 Baud rate setting 21.15.1 Baud rate setting Make sure that the settings are within the range of limit values for ensuring correct operation of the CAN controller, as follows. 5TQ≤SPT (sampling point) ≤17TQ SPT = TSEG1 +1TQ 8TQ≤DBT (data bit time) ≤25TQ...
Page 890 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-22 Settable bit rate combinations (1/3) Valid bit rate setting C0BTR register setting value Sampling point Sync Prop Phase Phase (unit %) DBT length TSEG1 [3:0] TSEG2 [2:0] Segment segment segment 1...
Page 891 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-22 Settable bit rate combinations (2/3) Valid bit rate setting C0BTR register setting value Sampling point Sync Prop Phase Phase (unit %) DBT length TSEG1 [3:0] TSEG2 [2:0] Segment segment segment 1...
Page 892 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-22 Settable bit rate combinations (3/3) Valid bit rate setting C0BTR register setting value Sampling point Sync Prop Phase Phase (unit %) DBT length TSEG1 [3:0] TSEG2 [2:0] Segment segment segment 1...
Page 893: Representative Examples Of Baud Rate Settings
BAT32A237 User Manual | Chapter 21 CAN Controller 21.15.2 Representative examples of baud rate settings Tables 21-23 and 21-24 show representative examples of baud rate settings. Table 21-23 Representative examples of baud rate settings (F = 8 MHz) (1/2) CANMOD...
Page 894 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-23 Representative examples of baud rate settings (F = 8 MHz) (2/2) CANMOD C0BTR register set Valid bit rate settings (unit: kbps) value Set baud Division C0BRP Sampling rate value ratio of...
Page 895 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-24 Representative examples of baud rate settings (F = 16 MHz) (1/2) CANMOD C0BTR register set Valid bit rate settings (unit: kbps) value Set baud Division C0BRP Sampling rate value ratio of...
Page 896 BAT32A237 User Manual | Chapter 21 CAN Controller Table 21-24 Representative examples of baud rate settings (F = 16 MHz) (2/2) CANMOD C0BTR register set Valid bit rate settings (unit: kbps) value Set baud Division C0BRP Sampling rate value ratio of...
Page 897: Operation Of Can Controller
BAT32A237 User Manual | Chapter 21 CAN Controller 21.16 Operation of CAN controller The processing procedure for showing in this chapter is recommended processing procedure to operate CAN controller. Develop the program referring to recommended processing procedure in this chapter.
Page 898 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-64 Re-initialization Start Clear OPMODE INIT mode Set C0BRP register, C0BTR register Set C0IE register Setting C0MASK register Initialize message buffers C0ERC and C0INFO register clear? Set CCERC bit Set C0CTRL register...
Page 899 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-65 Message buffer initialization Start RDY= 1? Clear RDY bit RDY= 0? C0MCONFm register Set C0MIDHm register, C0MIDLm register Transmit message buffer? Set C0MDLCm register Clear C0MDBm register C0MCTRLm register Set RDY bit Caution: 1.
Page 900 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-66shows the processing for a receive message buffer (MT [2:0] bits of C0MCONFm register = 001B to 101B). Figure 21-66 Message buffer redefinition Start Note2 Wait 4 CAN data bits Set message buffers Set RDY bit Note 1.
Page 901 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-67 shows the processing for a transmit message buffer during transmission (MT [2:0] bits of C0MCONFm register = 000B). Figure 21-67 Redefinition of message buffer during transmission Start Transmit abort process...
Page 902 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-68 shows the processing for a transmit message buffer (MT [2:0] bits of C0MCONFm register = 000B). Figure 21-68 Message transmit processing Start TRQ = 0? Clear RDY bit RDY= 0?
Page 903 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-69 shows the processing for a transmit message buffer (MT [2:0] bits of C0MCONFm register = 000B). Figure 21-69 ABT message transmit processing Start ABTTRG =0? Clear RDY bit RDY= 0?
Page 904 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-70. Transmit via interrupt (using C0LOPT register) Start Transmit completion Interrupt processing Read C0LOPT register Clear RDY bit RDY= 0? Data frame Remote frame Data frame or remote frame? Set C0MDATAxm register...
Page 905 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-71 Transmit via interrupt (using C0TGPT register) Caution: 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time.
Page 906 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-72 Transmission via software polling Caution: 1. The TRQ bit should be set after the RDY bit is set. 2. The RDY bit and TRQ bit should not be set at the same time.
Page 907 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-73 Transmission abort process (except normal operation mode with ABT) Start Clear TRQ bit Waiting for Note 11CAN data bits TSTAT=0? Read C0LOPT register Message buffer to be aborted matches C0LOPT...
Page 908 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-74 Transmission abort processing except for ABT transmission (normal operation mode with ABT) Start Clear ABTTRG bit ABTTRG =0? Clear TRQ bit Note Waiting for 11 CAN data bits TSTAT=0? Read C0LOPT register...
Page 909 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-75 shows the processing not to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 21-75 ABT transmission abort processing (normal operation mode with ABT) Caution: 1.
Page 910 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-76 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. Figure 21-76 ABT transmission request abort processing (normal operation mode with ABT) Clear ABTTRG bit Caution: 1.
Page 911 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-77 Reception via interrupt (using C0LIPT register) Note: Check the MUC and DN bits using one read access. Remark: Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed.
Page 912 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-78 Receiving via interrupt (using C0RGPT register) Start Generation of receive completion interrupt Read register C0RGPT ROVF= 1? Clear ROVF bit RHPM=1? Clear DN bit Read C0MDATAxm, C0MDLCm, C0MIDLm, C0MIDHm register...
Page 913 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-79 Reception via software polling Note Note: Check the MUC and DN bits using one read access. Remark: Also check the MBON flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed.
Page 914 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-80 Setting CAN sleep mode/stop mode Start (when PSMODE[1:0]= 00B) Set PSMODE0 bit PSMODE0= 1? CAN sleep mode Set PSMODE1 bit PSMODE1= 1? Reapply for CAN sleep mode? CAN stop mode...
Page 915 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-81 Clear CAN sleep/stop mode Start CAN stop mode Clear PSMODE1 bit (In case CAN clock is active) (In case CAN clock is disabled) when CAN clock disabled, Releasing CAN sleep mode by...
Page 916 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-82: Bus Shutdown Recovery (Normal Operation Mode with ABT) Start BOFF= 1? Note Clear all TRQ bits Set C0CTRL register (Clear OPTION) Access to registers other than C0CTRL and C0GMCTRL Forced recovery from...
Page 917 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-83 Bus-off recovery (normal operation mode with ABT) Start BOFF= 1? Clear ABTTRG bit Note Clear all TRQ bits Set C0CTRL register (Clear OPMODE) Access to registers other than C0GMCTRL and C0CTRL...
Page 918 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-84 Normal shutdown process Figure 21-85 Forced shutdown process Must be a subsequent write Caution: Do not read or write any registers through software between setting the EFSD bit and clearing the GOM bit.
Page 919 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-86 Error handling Start Error interrupt CINTS2 =1? Check CAN module status (read register C0INFO) Clear CINTS2 bit CINTS3 =1? Check CAN protocol error status (read register C0LEC) Clear CINTS3 bit...
Page 920 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-87 Setting CPU standby (from CAN sleep mode) Caution: Before the CPU is set in the CPU standby mode, please check the CAN sleep mode or not. However, after check of the CAN sleep mode, until the CPU is set in the CPU standby mode, the CAN sleep mode may be cancelled by wakeup from CAN bus.
Page 921 BAT32A237 User Manual | Chapter 21 CAN Controller Figure 21-88 Setting CPU standby (from CAN stop mode) Note: During wakeup interrupts Caution: The CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bit of the C0CTRL register and not by a change in the CAN bus state.
Page 922: Chapter 22 Irda
BAT32A237 User Manual | Chapter 22 IrDA Chapter 22 IrDA The IrDA implements the transmission and reception of IrDA communication waveforms in accordance with IrDA (Infrared Data Association) 1.0 by cooperating with SCI. 22.1 Function of IrDA If the IrDA function is made active by the IRE bit of the IRCR register, the TxD2 signal and the RxD2 signal of the SCI can encode or decode the waveforms conforming to the IrDA1.0 protocol (IrTxD/IrRxD pins), and later...
Page 923: Registers For Controlling Irda
BAT32A237 User Manual | Chapter 22 IrDA 22.2 Registers for controlling IrDA IrDA functions are controlled through the following registers. ⚫ Peripheral enable register 0 (PER0) ⚫ IrDA control register (IRCR) 22.2.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware.
Page 924: Irda Control Register (Ircr)
BAT32A237 User Manual | Chapter 22 IrDA 22.2.2 IrDA control register (IRCR) This is the register that controls the IrDA function. It performs polarity switching of received data and transmitted data, clock selection of IrDA, and selection of serial input/output pin function (usually serial function and IrDA function) switching.
Page 925: Operation Of Irda
BAT32A237 User Manual | Chapter 22 IrDA 22.3 Operation of IrDA 22.3.1 Procedure for IrDA communication (1) Initial set-up process for IrDA communications Follow these steps to initially set up IrDA. ① Set the IRDAEN bit of the PER0 register to 1.
Page 926: Transmission
BAT32A237 User Manual | Chapter 22 IrDA 22.3.2 Transmission At transmission, the output signal (UART frames) from the SCI is converted to IR frames via IrDA (see Figure 22-4). When the IRTXINV bit is 0 and the serial data is 0, output bit period (1 bit width period)×3/16 high-level pulse (initial value).
Page 927: Selection Of High Level Pulse Width
BAT32A237 User Manual | Chapter 22 IrDA 22.3.4 Selection of high level pulse width If the pulse width at the time of transmission is less than the bit rate × 3/16, the applicable IRCKS2 to IRCKS0 bit settings (minimum pulse width) and the high level pulse width at the time of setting are shown in Table 22-2.
Page 928: Cautions When Using Irda
BAT32A237 User Manual | Chapter 22 IrDA 22.4 Cautions when using IrDA It is possible to enable or disable to supply the IrDA operation clock by setting the peripheral enable register. The initial state disables the supply of clocks, so the registers cannot be accessed.
Page 929: Chapter 23 Enhanced Dma
BAT32A237 User Manual | Chapter 23 Enhanced DMA Chapter 23 Enhanced DMA 23.1 Function of DMA DMA is the function of transferring data between memories without using the CPU. Start the DMA for data transfer via peripheral interrupts. When the DMA and CPU access the same unit in flash, SRAM0, SRAM1, or peripheral modules at the same time, their bus usage is higher than the CPU.
Page 930 BAT32A237 User Manual | Chapter 23 Enhanced DMA Table 23-1 Specifications for DMA (2/2) Item Specification When a data transfer with a DMCTj register changed from 1 to 0, an interrupt of the start- Normal mode up source is requested to the CPU and interrupt processing is performed.
Page 931: Structure Of Dma
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.2 Structure of DMA The block diagram for DMA is shown in Figure 23-1 Figure 23-1 Block diagram for DMA Peripheral interrupt signal Interrupt source/ transmit startup Data transfer control source selection...
Page 932: Registers For Controlling Dma
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3 Registers for controlling DMA The registers that control the DMA are shown in Table 23-2. Table 23-2 Registers for controlling DMA Register name Symbol Peripheral Enable Register 1 PER1 DMA Start Enable Register 0...
Page 933: Assignment Of Dma Control Data Area And Dma Vector Table Area
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.1 Assignment of DMA control data area and DMA vector table area The 704-byte area of the DMA control data and vector table is assigned to the RAM area via the DMABAR register.
Page 934: Controlling Data Assignment
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.2 Controlling data assignment Starting from the starting address, control data is allocated in the order of DMACRj, DMBLSj, DMACTj, DMRLDj, DMSARj, and DMDARj registers. The starting address is set by the DMABAR register, and the lower 10 bits are set by the vector tables assigned by each starting source.
Page 935 BAT32A237 User Manual | Chapter 23 Enhanced DMA Table 23-4 Start address of control data Address Address Remark: baseaddr: Setting values of the DMABAR register www.mcu.com.cn 935 / 1066 V1.0.4...
Page 936: Vector Table
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.3 Vector table Once the DMA is started, control data assigned to the DMA control data area is read by data read from a vector table assigned to each start source. The DMA startup sources and vector addresses are shown in Table 23-5. The vector table of each startup source stores the data from “00H”...
Page 937 BAT32A237 User Manual | Chapter 23 Enhanced DMA Table 23-5 DMA startup sources and vector addresses Source Vector address Priority DMA start source (interrupt request generation source) number Reserved DMABAR register set address+00H High INTP0 DMABAR register set address+01H INTP1...
Page 938: Peripheral Enable Register 1 (Per1)
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.4 Peripheral enable register 1 (PER1) The PER1 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 939: Dma Control Register J(Dmacrj) (J=0~39)
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.5 DMA control register j(DMACRj) (j=0~39) The DMACRj register controls the mode of operation of the DMA. Figure 23-6 Format of DMA control register j(DMACRj) Address: see 23.3.2 After reset: undefined Symbol:...
Page 940: Dma Block Size Register J(Dmblsj) (J=0~39)
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.6 DMA block size register j(DMBLSj) (j=0~39) This register sets the block size for 1-time startup transfer data. Figure 23-7 Format of DMA block size register j(DMBLSj) Addres s: see 23.3.2 After reset: undefined...
Page 941: Dma Transfer Count Register J(Dmactj) (J=0~39)
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.7 DMA transfer count register j(DMACTj) (j=0~39) This register sets the number of DMA data transfers. It is decremented by 1 whenever 1 DMA transfer is initiated. Figure 23-8 Format of DMA transfer count register j(DMACTj) Address: see 23.3.2 After reset: undefined...
Page 942: Dma Transfer Count Reload Register J (Dmrldj) (J=0~39)
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.8 DMA transfer count reload register j (DMRLDj) (j=0~39) This register sets the initial value of the transfer number register in repeat mode. In Repeat mode, since the value of this register is reloaded into the DMACT register, the set value must be the same as the initial value of the DMACT register.
Page 943: Dma Source Address Register J(Dmsarj) (J=0~39)
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.9 DMA source address register j(DMSARj) (j=0~39). This register specifies the transfer source address when the data is transferred. When the SZ bit of the DMACRj register is 01 (16-bit transfer), the lowest bit is ignored and processed as an even address.
Page 944: Dma Start Enable Register I (Dmaeni) (I=0~4)
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.11 DMA start enable register i (DMAENi) (i=0~4) This is an 8-bit register that controls whether or not starting DMA through each interrupt source. The correspondence between the interrupt sources and the DMAENi0 to DMAENi7 bits is shown in Table 23-6.
Page 945 BAT32A237 User Manual | Chapter 23 Enhanced DMA DMAENi2 DMA start enable i2 Start disabled Start enabled The DMAENi2 bit changes to 0 (start disabled) according to the condition of the transfer end interrupt. DMAENi1 DMA start enable i1 Start disabled Start enabled The DMAENi1 bit changes to 0 (start disabled) according to the condition of the transfer end interrupt.
Page 946: Dma Base Address Register (Dmabar)
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.3.12 DMA base address register (DMABAR) This is a 32-bit register that sets the vector address that holds the starting address of the DMA control data area and the address of the DMA control data area.
Page 947: Operation Of Dma
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.4 Operation of DMA Once the DMA is started, the control data is read from the DMA control data area, data transfer is performed based on the control data, and the control data transferred is written back. It is possible to store 40 sets of control data to a DMA control data area and to perform transfer of 40 sets of data.
Page 948: Normal Mode
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.4.2 Normal mode At 8-bit transfer, the transfer data of 1 start-up is 1~65535 bytes. In 16-bit transfer, the transfer data of 1 start-up is 2~131070 bytes; At 32-bit transfer, the transfer data of 1 start-up is 4-262140 bytes. The number of transfers is 1 to 65535.
Page 949 BAT32A237 User Manual | Chapter 23 Enhanced DMA (1) Example 1 of normal mode usage: Continuous A/D conversion results The DMA is started by an A/D conversion end interrupt, and the value of the A/D conversion result register is transferred to the RAM.
Page 950 BAT32A237 User Manual | Chapter 23 Enhanced DMA (2) Example 2 of normal mode usage: UART0 continuous transmission The DMA is initiated via the transmit buffer empty interrupt of the UART0 and the value of the RAM is transferred to the transmit buffer of the UART0.
Page 951: Repeat Mode
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.4.3 Repeat mode The 1-time-initiated transfer data is 1-65535 bytes. The transmission source or the transmission target is designated as a repeat region, and the number of transmissions is 1-65535 times. Once the specified number of transfers is over, the DMACTj (j=0~39) register and the address specified as the repeat region are initialized and then repeatedly transferred.
Page 952 BAT32A237 User Manual | Chapter 23 Enhanced DMA Figure 23-18 Repeat mode data transfer DMSARj register=SRC DMDARj register=DST Control of the The source The destination Settings for the DMACR register Control of the destination address after address after source address...
Page 953 BAT32A237 User Manual | Chapter 23 Enhanced DMA (1) Example 1 of repeat mode usage: Use the stepper motor of the port to control the pulse output A channel 0 interval timer function of Timer4 is used to start DMA and transfer the mode of the motor control pulse saved in the code flash memory to the universal port.
Page 954 BAT32A237 User Manual | Chapter 23 Enhanced DMA Example 2 of repeat mode usage: sine wave output using 8-bit D/A converter Using the channel 0 interval timer function using Timer4 and by interrupting starting DMA, the sine wave table saved in the data flash memory is transferred to 8-bit D/A conversion value setting register 0 (40044734H).
Page 955: Chain Transfer
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.4.4 Chain transfer When the CHNE bit of the DMACRj (j=0~38) register is 1 (chain transfer is enabled), multiple data transfers can be performed consecutively through 1 start source. Once the DMA is initiated, the control data assigned to the DMA control data area is read by selecting the control data by the data read from the vector address corresponding to the startup source.
Page 956 BAT32A237 User Manual | Chapter 23 Enhanced DMA Examples of chain transfer: Continuously taking A/D conversion result for UART0 transmission The DMA is started by the A/D conversion end interrupt and the A/D conversion result is transferred to RAM for UART0 transmission.
Page 957: Cautions When Using Dma
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.5 Cautions when using DMA 23.5.1 DMA control data and vector table settings ⚫ The DMA base address register (DMABAR) must be changed with all DMA start sources set to disabled. ⚫...
Page 958: Number Of Execution Clocks For Dma
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.5.3 Number of execution clocks for DMA The execution of the DMA at start-up and the number of clocks required are shown in Table 23-9. Table 23-9 Execution and number of clocks required when DMA is started...
Page 959: Response Time For Dma
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.5.4 Response time for DMA The DMA response time is shown in Table 23-12. The DMA response time is the time from the detection of the DMA start source to the start of the DMA transfer, excluding the number of DMA execution clocks.
Page 960: Operation In Standby Mode
BAT32A237 User Manual | Chapter 23 Enhanced DMA 23.5.6 Operation in standby mode Status DMA operation Sleep mode Can operate (disable operation in low-power RTC mode). Note 1 Deep sleep mode Can accept DMA start source, and perform DMA transfer Note 1: In deep sleep mode, it is possible to perform a DMA transfer after detecting a DMA start source and return to deep sleep mode after the transfer is completed.
Page 961: Chapter 24 Coordination Controller (Eventc)
BAT32A237 User Manual | Chapter 24 Coordination Controller (EVENTC) Chapter 24 Coordination Controller (EVENTC) 24.1 Function of EVENTC The event link controller (ELC) mutually connects (links) events output from each peripheral function. By linking events, it becomes possible to coordinate operation between peripheral functions directly without going through the CPU.
Page 962: Control Registers
BAT32A237 User Manual | Chapter 24 Coordination Controller (EVENTC) 24.3 Control registers Table 24-1 lists the control registers. Table 24-1 Registers controlling EVENTC Register name Symbol Event output destination selection register 00 ELSEL00 Event output destination selection register 01 ELSEL01...
Page 963: Event Output Destination Select Register N(Elselrn) (N=00~21)
BAT32A237 User Manual | Chapter 24 Coordination Controller (EVENTC) 24.3.1 Event output destination select register n(ELSELRn) (n=00~21) An ELSELRn register links each event signal to an operation of an event-receiving peripheral function (link destination peripheral function) after reception. Do not set multiple event inputs to the same event output destination (event receive side).
Page 964 BAT32A237 User Manual | Chapter 24 Coordination Controller (EVENTC) Table 24-2 Correspondence between ELSELRn register (n=00~21) and peripheral functions Register name Event generator (output source for event input n) Event description ELSEL00 External interrupt edge detection 0 INTP0 ELSEL01 External interrupt edge detection 1...
Page 965 BAT32A237 User Manual | Chapter 24 Coordination Controller (EVENTC) Table 24-3 Correspondence between values set to ELSELRn (n = 00 to 21) registers and operation of link destination peripheral functions at reception Link bits ELSELn3~ELSELn0 in Link destination peripheral destination...
Page 966: Operation Of Eventc
BAT32A237 User Manual | Chapter 24 Coordination Controller (EVENTC) 24.4 Operation of EVENTC The path for using an event signal generated by a peripheral function as an interrupt request to the interrupt control circuit is independent from the path for using it as an EVENTC event. Therefore, each event signal can be used as an event signal for operation of an event-receiving peripheral function, regardless of interrupt control.
Page 967 BAT32A237 User Manual | Chapter 24 Coordination Controller (EVENTC) The response of the peripheral function that accepts the event is shown in Table 24-4. Table 24-4 Response of peripheral functions to receive events Event receive Function of event link destination...
Page 968: Chapter 25 Interrupt Function
BAT32A237 User Manual | Chapter 25 Interrupt Function Chapter 25 Interrupt Function The Cortex-M0+ processor has a built-in nested vector interrupt controller (NVIC) that supports up to 32 interrupt request (IRQ) inputs and 1 unmaskable interrupt (NMI) input, plus multiple internal exceptions.
Page 969: Interrupt Source And Structure
BAT32A237 User Manual | Chapter 25 Interrupt Function 25.2 Interrupt source and structure Refer to Table 25-1 for the list of interrupt sources. Table 25-1 List of interrupt sources (1/4) Interrupt source Name Trigger Note 2 Internal INTLVI Voltage detection ⚪...
Page 970 BAT32A237 User Manual | Chapter 25 Interrupt Function Table 25-1 List of interrupt sources (2/4) Interrupt source Name Trigger UART1 transmission transfer end or buffer INTST1/INTSSPI empty interrupt Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 ⚪...
Page 971 BAT32A237 User Manual | Chapter 25 Interrupt Function Table 2 5-1: List of interrupt sources (3/4) Interrupt source Name Trigger Reserved INTP6 ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ INTP7 ⚪ ⚪ INTP8 ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ ⚪...
Page 972 BAT32A237 User Manual | Chapter 25 Interrupt Function Table 25-1 List of interrupt sources (4/4) Interrupt source Interrupt Interrupt source Internal/External Basic structure type Note 1 handling number Name Trigger Watchdog timer interval — Unmaskable INTWDT Internal Note 2 interrupt Note1: Types (A) to (D) correspond to (A) to (D) of Figure 25-1.
Page 973 BAT32A237 User Manual | Chapter 25 Interrupt Function Figure 25-1 Basic structure of interrupt function (A) Internally masked interrupt Internal bus CPU.IRQ Standby release signal (B) Externally masked interrupt (INTPn) Internal bus External interrupt edge enable register (EGN, EGP) Edge CPU.IRQ...
Page 974 BAT32A237 User Manual | Chapter 25 Interrupt Function (C) Externally masked interrupt (INTKR) Internal bus Key return mode register (KRM) CPU.IRQ key interrupt detection circuit Standby release signal Note: 40 pins: n=0, 2~5 48 pins: n=0~5 52,64 pins: n=0~7 (D) Unmaskable interrupt Internal bus CPU.NMI...
Page 975: Registers For Controlling Interrupt Function
BAT32A237 User Manual | Chapter 25 Interrupt Function 25.3 Registers for controlling interrupt function The interrupt function is controlled through the following four registers. ⚫ Interrupt request flag register (IF00~IF31) ⚫ Interrupt mask register (MK00~MK31) ⚫ External interrupt rising edge enable registers (EGP0, EGP1) ⚫...
Page 976: Interrupt Mask Register (Mk00~Mk31)
BAT32A237 User Manual | Chapter 25 Interrupt Function 25.3.2 Interrupt mask register (MK00~MK31) The interrupt mask flag is set to enable or disable the corresponding maskable interrupt processing. Set the MK00L to MK31L, MK00H to MK31H registers by 8-bit memory manipulation instructions or the MK00 to MK31 registers by 32-bit memory manipulation instructions.
Page 977 BAT32A237 User Manual | Chapter 25 Interrupt Function Table 25-2 Correspondence between interrupt source and each flag register Interrupt Interrupt Interrupt Interrupt Interrupt request Interrupt mask request flag source mask register source flag register register register INTLVI IF00.IFL MK00.MKL Reserved IF00.IFH...
Page 978 BAT32A237 User Manual | Chapter 25 Interrupt Function Figure 25-4 Relationship between each flag register and CPU.IRQ Internal bus MKnL IFnL CPU.IRQn IFnH MKnH Internal bus www.mcu.com.cn 978 / 1066 V1.0.4...
Page 979: External Interrupt Rising Edge Enable Register (Egp0, Egp1), External Interrupt Falling Edge Enable Register (Egn0, Egn1)
BAT32A237 User Manual | Chapter 25 Interrupt Function 25.3.3 External interrupt rising edge enable register (EGP0, EGP1), external interrupt falling edge enable register (EGN0, EGN1) These registers are used to set the effective edges of INTP0~INTP11. The EGP0, EGP1, EGN0, EGN1 registers are set by 8-bit memory manipulation instructions. After a reset signal is generated, the value of the register changes to “00H”.
Page 980 BAT32A237 User Manual | Chapter 25 Interrupt Function Table 25-3 Interrupt request signal corresponding to EGPn bit and EGNn bit Interrupt Detect enable bit 64 pins 52,48,40 pins 36 pins 32 pins request signal ○ ○ ○ ○ EGP0 EGN0 INTP0 ○...
Page 981: Operation Of Interrupt Handling
BAT32A237 User Manual | Chapter 25 Interrupt Function 25.4 Operation of interrupt handling 25.4.1 Acceptance of maskable interrupt requests If the interrupt request flag is set to 1 and the mask (MK) flag for the interrupt request is cleared to 0, the interrupt request is accepted and can be passed to the NVIC.
Page 982: Chapter 26 Key Interrupt Function
BAT32A237 User Manual | Chapter 26 Key Interrupt Function Chapter 26 Key Interrupt Function The number of channels for key interrupt input varies by product. Function of key interrupt 26.1 A key interrupt (INTKR) can be generated by inputting a falling edge to the key interrupt input pins (KR0~KR7).
Page 983 BAT32A237 User Manual | Chapter 26 Key Interrupt Function Figure 26-1 Block diagram of key interrupt INTKR KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register www.mcu.com.cn 983 / 1066 V1.0.4...
Page 984: Registers For Controlling Key Interrupt
BAT32A237 User Manual | Chapter 26 Key Interrupt Function Registers for controlling key interrupt 26.3 The key interrupt function is controlled through the following registers. • Key return mode register (KRM) • Port mode register (PMx) 26.3.1 Key return mode register (KRM) The KRM0~KRM7 bit controls the KR0~KR7 signal.
Page 985: Port Mode Register (Pmx)
BAT32A237 User Manual | Chapter 26 Key Interrupt Function 26.3.2 Port mode register (PMx) When used as key interrupt input pin (KR0~KR7), the PMxn bits must be set 1. In this case, the output latch for Pxn may be 0 or 1.
Page 986: Chapter 27 Standby Function
BAT32A237 User Manual | Chapter 27 Standby Function Chapter 27 Standby Function Standby function 27.1 The standby function is a function that further reduces the operating current of the system, and there are two modes as follows. (1) Sleep mode Sleep mode is the mode in which the CPU is stopped from running the clock.
Page 987: Sleep Mode
BAT32A237 User Manual | Chapter 27 Standby Function Sleep mode 27.2 27.2.1 Sleep mode configuration When the SLEEPDEEP bit of the SCR register is 0, execute the WFI instruction and enter sleep mode. In sleep mode, the CPU stops operating, but the values of the internal registers are still maintained, and the peripheral modules remain in the state they were in before they entered sleep mode.
Page 988 BAT32A237 User Manual | Chapter 27 Standby Function Table 27-1 Operation status in sleep mode (1/2) Execution of WFI instructions while the CPU is running at the main system clock Sleep mode setting CPU with high speed internal CPU with external master...
Page 989 BAT32A237 User Manual | Chapter 27 Standby Function : High-speed internal oscillator clock F : Low-speed internal oscillator clock : X1 clock F : External master system clock : XT1 clock F : External subsystem clock www.mcu.com.cn 989 / 1066...
Page 990 BAT32A237 User Manual | Chapter 27 Standby Function Table 27-1 Operation status in sleep mode (2/2) Execution of WFI instructions while the CPU is running at the subsystem clock Sleep mode setting CPU running on external subsystem clock Item CPU running at XT1 clock (F System clock Stop providing clocks to the CPU.
Page 991 BAT32A237 User Manual | Chapter 27 Standby Function : X1 clock F : External master system clock : XT1 clock F : External subsystem clock www.mcu.com.cn 991 / 1066 V1.0.4...
Page 992: Exit From Sleep Mode
BAT32A237 User Manual | Chapter 27 Standby Function 27.2.2 Exit from sleep mode The sleep mode can be released by any interrupt or external reset, POR reset, low voltage detection reset, RAM parity error reset, WDT reset, and software reset.
Page 993: Deep Sleep Mode
BAT32A237 User Manual | Chapter 27 Standby Function Deep sleep mode 27.3 27.3.1 Deep sleep mode configuration When the SLEEPDEEP bit of the SCR register is 1, the WFI instruction is executed and deep sleep mode is entered. In this mode, the CPU, most of the peripheral modules, and the vibrator operation stops. However, the values of the CPU internal registers, the RAM data, the peripheral modules, the state of the I/O are maintained.
Page 994 BAT32A237 User Manual | Chapter 27 Standby Function Table 27-2 Running State in Deep Sleep Mode Deep sleep mode setting Execution of WFI instructions while the CPU is running at the main system clock CPU runs on a high-speed on-...
Page 995 BAT32A237 User Manual | Chapter 27 Standby Function Remark: Stop Run: Automatically stops running when shifting to sleep mode. Disable Run: Stops running before shifting to sleep mode. : High-speed internal oscillator clock F : Low-speed internal oscillator clock : X1 clock F...
Page 996: Deep Sleep Mode Release
BAT32A237 User Manual | Chapter 27 Standby Function 27.3.2 Deep sleep mode release The deep sleep mode can be released by the following two sources. (a) Released by non-maskable interrupt requests If a non-maskable interrupt request occurs, deep sleep mode is released. After the oscillation stabilization time, if the interrupt is allowed to be accepted, the vector interrupt is processed.
Page 997: Chapter 28 Reset Function
BAT32A237 User Manual | Chapter 28 Reset Function Chapter 28 Reset Function The following seven operations are available to generate a reset signal. (1) External reset input via RESETB pin. (2) Internal reset is generated by programmed runaway detection of the watchdog timer.
Page 998 BAT32A237 User Manual | Chapter 28 Reset Function Figure 28-1 Block diagram of reset function internal bus Reset control flag register (RESF) SYSRF WDTRF RPERF IAWRF LVIRF reset reset reset reset reset Watchdog timer reset signal clear clear clear clear...
Page 999: Reset Timing
BAT32A237 User Manual | Chapter 28 Reset Function Reset timing When the RESETB pin is input low, a reset is generated. The reset state is then released if the RESETB pin is entered high and the program begins with a high-speed on-chip oscillator clock after the reset process is completed.
Page 1000 BAT32A237 User Manual | Chapter 28 Reset Function Note 1: If a reset occurs, P130 outputs a low level. Therefore, if P130 is set to high output before a reset occurs, the output of P130 can be virtually output as a reset signal of an external device. To release the reset signal of the external device, P130 must be set to a high output level by software.