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CMS80F731x Series

Reference Manual

Enhanced flash 8-bit 1T 8051 microcontroller

Rev. 1.00

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CMS80F731x Reference Manual

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Page 1: Table Of Content Cms80F731X Series
CMS80F731x Reference Manual CMS80F731x Series Reference Manual Enhanced flash 8-bit 1T 8051 microcontroller Rev. 1.00 Please be reminded about following CMS’s policies on intellectual property ＊Cmsemicron Limited(denoted as ‘our company’ for later use) has already applied for relative patents and entitled legal rights. Any patents related to CMS’s MCU or other producrts is not authorized to use.
Page 2: Table Of Contents
CMS80F731x Reference Manual Table of Content CMS80F731x Series ......................... 2 Table of Content ........................3 1. Central Processing Unit (CPU) ..................12 Reset Vector (0000H) ..............................12 BOOT Partition ................................12 Accumulator (ACC) ..............................14 B Register(B) ................................14 Stack Pointer Register (SP)............................14 Data Pointer Register (DPTR0/DPTR1) ........................
Page 3 CMS80F731x Reference Manual 5.4.5 Sleep Power Consumption in Debug Mode......................44 5.4.6 Example of a Sleep Mode Application ........................44 6. Interrupt ..........................45 Interrupt Overview ..............................45 External Interrupts ..............................46 6.2.1 INT0/INT1 Interrupt ............................... 46 6.2.2 GPIO Interrupt ............................... 46 Interrupt With Sleep Wake-up ...........................
Page 4 CMS80F731x Reference Manual 7.2.6 Multiplexing Features Application Notes ....................... 69 8. Watchdog Timer (WDT) ....................71 Overview ................................... 71 Related Registers ..............................71 8.2.1 Watchdog Control Register WDCON ........................71 8.2.2 Watchdog Overflow Control Register CKCON ...................... 72 WDT Interrupt ................................73 8.3.1 Interrupt Mask Register EIE2 ..........................
Page 5 CMS80F731x Reference Manual 10.3.1.2 Timer2 Interrupt Mask Register T2IE ......................93 10.3.1.3 Interrupt Priority Control Register IP ......................93 10.3.1.4 Timer2 Interrupt Flag Bit Register T2IF ..................... 94 10.3.2 Timer Interrupts ..............................95 10.3.3 Externally Triggered Interrupts ..........................95 10.3.4 Compare Interrupts ............................... 95 10.3.5 Capture Interrupts ..............................
Page 6 CMS80F731x Reference Manual 13.2.1 WUTCRH Register .............................. 115 13.2.2 WUTCRL Register ............................... 115 13.3 Feature Description ..............................116 14. Baud Rate Timer (BRT) ....................117 14.1 Overview ................................. 117 14.2 Related Registers ..............................117 14.2.1 BRT Module Control Register BRTCon ....................... 117 14.2.2 The BRT Timer Data is Loaded With a Low 8-bit Register BRTDL ..............
Page 7 CMS80F731x Reference Manual 17.5.18 PWM2/3 Dead-zone Delay Data Register PWM23DT ..................133 17.5.19 PWM4/5 Dead-zone Delay Data Register PWM45DT ..................133 17.6 PWM Interrupt ................................. 134 17.6.1 Interrupt Mask Register EIE2 ..........................134 17.6.2 Interrupt Priority Control Register EIP2 ....................... 135 17.6.3 PWM Zero Interrupt Mask Register PWMZIE......................
Page 8 CMS80F731x Reference Manual 19.4.10 LED Dot Matrix Drive Cycle Select Register LEDnSEL (n=0-7)................159 19.4.11 P00-P03 Drive Current Control Register LEDSDRP0L ..................159 19.4.12 P04-P07 Drive Current Control Register LEDSDRP0H ..................160 19.4.13 LED Pin Drive Enable Low 8-bit LEDENL ......................160 19.4.14 LED Pin Drive Enable High 8-bit LEDENH ......................
Page 9 CMS80F731x Reference Manual 21.5.2 Interrupt Priority Control Register EIP2 ....................... 191 21.5.3 Peripheral Interrupt Flag Bit Register EIF2......................192 21.6 I2C Slave Mode Transmission Mode ........................193 21.6.1 Single Receive ..............................193 21.6.2 Single Send ................................. 194 21.6.3 Continuous Reception ............................195 21.6.4 Continuous Sending ............................
Page 10 CMS80F731x Reference Manual 23.6.5 AD Comparator Control Register ADCPC ......................217 23.6.6 AD Hardware Trigger Delay Data Register ADDLYL ................... 217 23.6.7 AD Data Register High ADRESH, ADFM=0 (Left Aligned) .................. 217 23.6.8 AD Data Register Low ADRESL, ADFM=0 (Left Aligned) ..................217 23.6.9 AD Data Register High ADRESH, ADFM=1 (Right-aligned) ................
Page 11: Central Processing Unit (Cpu)
CMS80F731x Reference Manual 1. Central Processing Unit (CPU) This series is a microcontroller with 8-bit 8051 frame structure. The CPU is the core component of the microcontroller, which is composed of arithmetic units, controllers, and special register groups. The arithmetic unit module mainly implements data arithmetic and logic operations, bit variable processing and data transfer operations;...
Page 12 CMS80F731x Reference Manual BOOT Control Register (BOOTCON) F691H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BOOTCON Reset value BOOT zone control bit (this register can only be written when the chip is configured to Bit7~Bit0 D<7:0>: BOOT_1K/BOOT_2K/BOOT_4K); If you switch from the APROM area to the BOOT area, you need to write 0x55 to it, and then perform 0x55= a software reset or generate a watchdog reset;...
Page 13: Accumulator (Acc)
CMS80F731x Reference Manual Accumulator (ACC) The ALU is an 8Bit wide arithmetic logic unit through which all mathematical and logical operations of the MCU are completed. It can add, subtract, shift and logical operations on data; The ALU also controls the status bits (in the PSW status register) that represent the state of the result of the operation.
Page 14: Data Pointer Selection Register (Dps)
CMS80F731x Reference Manual Data Pointer Selection Register (DPS) The data pointer selects register DPS 0x86 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SALT Reset value Bit7~Bit6 ID<1:0>: Subtract/add function selection. DPTR0 plus 1 or DPTR1 plus 1; DPTR0 minus 1 or DPTR1 plus 1; DPTR0 plus 1 or DPTR1 minus 1;...
Page 15: Program Counter (Pc)
CMS80F731x Reference Manual Program Counter (PC) The program counter (PC) controls the order of instruction execution in the program memory FLASH, it can address the entire flash range, after obtaining the instruction code, the program counter (PC) will automatically add one, pointing to the address of the next instruction code.
Page 16: Memory And Register Mapping
CMS80F731x Reference Manual 2. Memory and Register Mapping This series of Microcontrollers has the following types of memory: ◆ Up to 16 KB of FLASH program memory (shared by APROM and BOOT). ◆ Non-volatile data memory (Data FLASH) up to 1 KB. ◆...
Page 17: Non-Volatile Data Memory Data Flash
CMS80F731x Reference Manual Non-volatile Data Memory Data FLASH The non-volatile data memory Data FLASH can be used to store important data such as constant data, calibration data, protection safety-related information, etc. The data stored in this area has the characteristic that the data is not lost in the event of a chip power outage or a sudden or unexpected power outage.
Page 18 CMS80F731x Reference Manual The high 128 Bytes shown above and SFR occupy the same area (80H to FFH), but they are independent. Storage spaces with direct addressing above 7FH (SFR) and indirect addressing above 7FH (128 Bytes high) go into different storage spaces. The low 128Bytes spatial register allocation shown in the figure above is shown in the figure below.
Page 19: General External Data Register Xram
CMS80F731x Reference Manual General External Data Register XRAM There is a maximum 1KB XRAM area inside the chip, this area is not connected to FLASH/RAM, and the XRAM space allocation block diagram is shown in the following figure: 03FFH XRAM (Indirect Addressing Mode) 0000H...
Page 20: Special Function Register Sfr
CMS80F731x Reference Manual Special Function Register SFR Special function registers refer to a set of registers with special purposes, essentially some on-chip RAM units with special functions, discretely distributed in the address range of 80H to FFH. Users can byte access them through direct addressing instructions, and addresses four bits lower than 0000 or 1000 can be addressed bitwise, such as P0, TCON, P1.
Page 21: External Special Function Register Xsfr
CMS80F731x Reference Manual External Special Function Register XSFR XSFR is a special register shared by the addressing space and XRAM, mainly including: port control registers, other function control registers. Its addressing range is shown in the following figure: FFFFH XSFR region: 4K F000H EFFFH Reserved space...
Page 22 CMS80F731x Reference Manual address register Register description F01DH P1SR P1 port slope control register F01EH P1DS Port P1 data input select register F020H P20CFG P20 port configuration register F021H P21CFG P21 port configuration register F022H P22CFG P22 port configuration register F023H P23CFG P23 port configuration register...
Page 23 CMS80F731x Reference Manual address register Register description F092H P22EICFG P22 port interrupt control register F093H P23EICFG P23 interrupt control register F0B8H P50EICFG P50 port interrupt control register F0B9H P51EICFG P51 interrupt control register F0BAH P52EICFG P52 port interrupt control register F0BBH P53EICFG P53 port interrupt control register...
Page 24 CMS80F731x Reference Manual address register Register description F134H PWMP2L The PWM2 cycle data register is 8 bits lower F135H PWMP2H The PWM2 cycle data register is 8 bits high F136H PWMP3L The PWM3 cycle data register is 8 bits lower F137H PWMP3H The PWM3 cycle data register is 8 bits high...
Page 25 CMS80F731x Reference Manual address register Register description F5E6H UID6 UID<55:48> F5E7H UID7 UID<63:56> F5E8H UID8 UID<71:64> F5E9H UID9 UID<79:72> F5EAH UID10 UID<87:80> F5EBH UID11 UID<95:88> F690H Power supply monitor registers LVDCON F691H BOOTCON BOOT control registers F692H ADCLDO ADC reference voltage control register F694H LSECRL The LSE timer data register is 8 bits lower...
Page 26 CMS80F731x Reference Manual address register Register description F709H CRCDL CRC operation results in a low 8-bit data register F70AH CRCDH The CRC operation results in a high 8-bit data register F710H LEDSDRP0L The P00-P03 drive current control register F711H LEDSDRP0H The P04-P07 drive current control registers F712H LEDSDRP1L...
Page 27 CMS80F731x Reference Manual address register Register description LED3 dot matrix drive cycle selection register (dot matrix drive). LED COM6 corresponding the SEG7-SEG0 data register LEDC6DATA0 (matrix driver). F758H LED4 dot matrix drive cycle selection register (dot matrix LED4SEL drive). THE LED COM6 corresponding the SEG15-SEG8 data LEDC6DATA1 register (matrix driver).
Page 28: Reset
CMS80F731x Reference Manual 3. Reset Reset Time refers to the time from the time the chip resets to the time when the chip starts executing instructions, and its default design value is about 16ms. This time includes oscillator start time, configuration time. This reset time will exist whether the chip is powered on reset or otherwise caused by a reset.
Page 29 CMS80F731x Reference Manual Whether the system is power-on reset can be determined by the PORF (WDCON.6) flag bit. The types of resets that can be placed with a PORF flag of 1 are: power-on reset, LVR reset, external reset, CONFIG protected reset. 0x97 Bit7 Bit6...
Page 30: External Reset
CMS80F731x Reference Manual External Reset External reset refers to a reset signal from an external port (NRST) that resets the chip after being input by a Schmitt trigger. If the NRST pin remains low above about 16us (internal LSI clock sampled with 3 rising edges) during operating voltage range and stable oscillation, a reset is requested.
Page 31: Watchdog Reset
CMS80F731x Reference Manual Watchdog Reset Watchdog reset is a protective setting of the system. In normal condition, the watchdog timer is cleared to zero by the program. If an error occurs, the system is in an unknown state, the watchdog timer overflows, and the system resets. After the watchdog is reset, the system reboots into a normal state.
Page 32: Config Status Protection Reset
CMS80F731x Reference Manual CONFIG Status Protection Reset CONFIG state protection reset is an enhanced protection mechanism of the system. During power-on reset, there is an internal set of 16-bit CONFIG registers that load the fixed code set in flash (A569H) and do not operate during normal operation. If, in the case of a particular non-program operation, the value of the register changes and is not equal to the original fixed code, and after several clock samples, the register continues to remain in a state that is not fixed code, the system will reset.
Page 33: Clock Structure
CMS80F731x Reference Manual 4. Clock Structure There are four types of clock sources for system clocks, and clock source and clock divider can be selected by setting the system configuration register or user register. The system clock sources are as follows: ◆...
Page 34: Related Registers
CMS80F731x Reference Manual Related Registers Oscillator Control Register CLKDIV 4.2.1 0x8F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKDIV CLKDIV7 CLKDIV6 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0 Reset value Bit7~Bit0 CLKDIV<7:0>: System clock Fsys divider; 00H= Fsys=Fsys_pre; Other = Fsys=Fsys_pre/（2*CLKDIV）（2,4...
Page 35: System Clock Status Register Sckstau
CMS80F731x Reference Manual System Clock Status Register SCKSTAU 4.2.3 0xD7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCKSTAU LSI_F LSE_F HSE_F HSI_F Reset value Bit7 Low-speed internal steady-state bit; LSI_F: Stability; Not stable. Bit6 Steady state bit of low-speed external crystal; LSE_F: Stability;...
Page 36: System Clock Monitor Register Scm
CMS80F731x Reference Manual System Clock Monitor Register SCM 4.2.4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 F697H XT_SCM SCMEN SCMIE SCMIF SCMSTA Reset value Bit7 SCMEN: Oscillation stop detection module enable; Enable; Disable. Bit6 Stop detection interrupt enable bit (this interrupt and LSE timer interrupt share a single SCMIE: interrupt entry);...
Page 37: Function Clock Control Registers
CMS80F731x Reference Manual Function Clock Control Registers 4.2.5 Watchdog overflow time/timer clock source selection register CKCON 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON WTS2 WTS1 WTS0 Reset value Bit7~Bit5 WTS<2:0>: WDT overflow time selection bits; 000= *Tsys; 001= *Tsys;...
Page 38: System Clock Switching
CMS80F731x Reference Manual System Clock Switching A set of crystal ports on the chip can only have one set of crystal ports valid at the same time, so it is forbidden to use the switching function of HSE/LSE. When the current chip selects an external HSE clock, the use of LSE-related functions is Disable. When the current chip selects an external LSE clock, the use of HSE-related functions is Disable.
Page 39: System Clock Monitoring
CMS80F731x Reference Manual System Clock Monitoring System Clock Monitoring (SCM) is a monitoring and protection circuit designed to prevent the system from not working due to crystal oscillation suspension. When using HSE/LSE as the system clock, once the HSE/LSE clock stops, the system will force the HSI clock source to start, and the system will run at 8MHz after the HSI is stabilized, and then if the HSE/LSE clock is restored and stable, the system clock will automatically switch back from the HSI back to HSE/LSE.
Page 40: Power Management
CMS80F731x Reference Manual 5. Power Management Low-power modes fall into 2 categories: ◆ IDLE: Idle mode ◆ STOP: Sleep mode When users use C language for program development, it is strongly recommended to use IDLE and STOP macros to control the system mode, and do not directly set THE IDLE and STOP bits.
Page 41: Power Supply Monitor Register Lvdcon
CMS80F731x Reference Manual Power Supply Monitor Register LVDCON The MCU comes with a power supply detection function. If the LVD module enable (LVDEN=1) is set and the voltage monitoring point LVDSEL is set, when the power supply voltage drops below the LVD setpoint, an interrupt will be generated to alert the user.
Page 42: Stop Sleep Mode
CMS80F731x Reference Manual STOP Sleep Mode In this mode, all circuits except the LVD module and LSE module are shut down (the LVD/LSE module must be closed by software), the system is in a low-power mode, and the digital circuits are not working. Sleep Wakes up 5.4.1 After entering the sleep mode, you can turn on the sleep wake function (SWE=1...
Page 43: Reset Operation Under Sleep
CMS80F731x Reference Manual Reset Operation Under Sleep 5.4.4 In sleep mode, the system can also be restarted by power-down reset or external reset, independent of the value of SWE, even if SWE=0 can also restart the system by the above reset operation. Power-down reset: No other conditions are required, VDD is reduced to 0V and then powered back on to the working voltage and enters the power-on reset state.
Page 44: Interrupt
CMS80F731x Reference Manual 6. Interrupt Interrupt Overview The chip has 28 interrupt sources and interrupt vectors: Interrupt source Interrupt description Interrupt vector Sibling priority sequence INT0 External interrupt 0 0-0x0003 Timer0 Timer 0 interrupt 1-0x000B INT1 External interrupt 1 2-0x0013 Timer1 Timer 1 interrupt 3-0x001B...
Page 45: External Interrupts
CMS80F731x Reference Manual External Interrupts INT0/INT1 Interrupt 6.2.1 The chip supports the 8051 native INT0, INT1 external interrupt, INT0/INT1 can choose to falling edge or low level trigger interrupt, the relevant control register is TCON. INT0 and INT1 occupy two interrupt vectors. GPIO Interrupt 6.2.2 Each GPIO pin of the chip supports an external interrupt and can support falling/rising/dual edge interrupts, with the edge...
Page 46: Interrupt Register
CMS80F731x Reference Manual Interrupt Register Interrupt Mask Registers 6.4.1 Interrupt Mask Register IE 6.4.1.1 Interrupt mask register IE is a read-write register that can be operated bitwise. When an interrupt condition arises, the interrupt flag bit will be set to 1 regardless of the state of the corresponding interrupt enable bit or the global enable bit EA. The user software should ensure that the corresponding interrupt flag bits are cleared to zero before enabling an interrupt.
Page 47: Interrupt Mask Register Eie2
CMS80F731x Reference Manual Interrupt Mask Register EIE2 6.4.1.2 0xAA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIE2 SPIIE I2CIE WDTIE ADCIE PWMIE Reset value Bit7 SPIIE: SPI interrupt enable bit; Enable SPI interrupts; Prohibited SPI Interrupt. Bit6 I2CIE: I2C interrupt enable bit; Enable I2C interrupts;...
Page 48: P0 Interrupt Control Register P0Extie
CMS80F731x Reference Manual Bit1 T2C1IE: Timer2 compares channel 1 interrupt enable bits; Interrupts are Enabled; Disable Interrupt. Bit0 T2C0IE: Timer2 compares channel 0 interrupt Enabled bits; Interrupts are Enabled; Disable Interrupt. If you want to enable the interrupt of Timer2, you also need to turn on the global interrupt enable bit ET2=1 of Timer2 (IE.5=1) P0 Interrupt Control Register P0EXTIE 6.4.1.4 0xAC...
Page 49: P5 Interrupt Control Register P5Extie
CMS80F731x Reference Manual P5 Interrupt Control Register P5EXTIE 6.4.1.7 0x9C Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P51IE P5EXTIE P55IE P54IE P53IE P52IE P50IE Reset value Bit7~Bit6 Reserved, must be 0. Bit5~Bit0 P5iIE: P5i port interrupt enable bits (i=0-5); Interrupts are Enabled;...
Page 50: Interrupt Priority Controls The Register
CMS80F731x Reference Manual Interrupt Priority Controls the Register 6.4.2 Interrupt Priority Control Register IP 6.4.2.1 Interrupt priority control register IP is a read-write register that can be operated bitwise. 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0.
Page 51: Interrupt Priority Control Register Eip2
CMS80F731x Reference Manual Set to High-level Interrupt; Set to low-level interrupt. Bit0 PP0: P0 port interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Interrupt Priority Control Register EIP2 6.4.2.3 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2...
Page 52: Interrupt Priority Control Register Eip3
CMS80F731x Reference Manual Interrupt Priority Control Register EIP3 6.4.2.4 0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP3 PLVD PLSE Reset value Reserved, must be 0. Bit7~Bit5 Bit4 PTOUCH TOUCH interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit3 PLVD: LVD interrupt priority control bit;...
Page 53: Interrupt Flag Bit Register
CMS80F731x Reference Manual Interrupt Flag Bit Register 6.4.3 Timer0/1, INT0/1 Interrupt Flag Bit Register TCON 6.4.3.1 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; Timer1 counter overflow, when entering the interrupt service program, the hardware is automatically cleared, and the software can also be cleared;...
Page 54: Peripheral Interrupt Flag Bit Register Eif2
CMS80F731x Reference Manual Bit5~Bit4 Reserved, must be 0. Bit3 T2C3IF: Timer2 Compare/Capture Channel 3 Flag Bits; Timer2 Compare channel 3 {CCH3:CCL3}={TH2:TL2} or capture channel 3 produces a capture operation that requires software zeroing. Bit2 T2C2IF: Timer2 Compare/Capture Channel 2 Flag Bits; Timer2 Compare channel 2 {CCH2:CCL2}={TH2:TL2} or capture channel 2 to produce a capture operation that requires software zeroing.
Page 55: Spi Interrupt Flag Bit Register Spsr
CMS80F731x Reference Manual SPI Interrupt Flag Bit Register SPSR 6.4.3.4 0xED Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPSR SPISIF WCOL SSCEN Reset value Bit7 SPISIF: SPI transmission completion interrupt flag bit, read-only; SPI transmission is completed (read SPSR first, then read/write SPDR and then clear zero); The SPI was not transmitted.
Page 56: I2C Slave Mode Status Register I2Cssr
CMS80F731x Reference Manual I2C Slave Mode Status Register I2CSSR 6.4.3.6 0xF2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I2CSSR SENDFIN TREQ RREQ Reset value Bit7~Bit3 Reserved, must be 0. Bit2 SENDFIN: I2C slave mode send operation completion flag bit, read-only; The data is no longer required by the master device, the TREQ is no longer set to 1, and the data transfer has been completed.
Page 57: P0 Port Interrupt Flag Register P0Extif
CMS80F731x Reference Manual P0 port Interrupt Flag Register P0EXTIF 6.4.3.8 0xB4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0EXTIF P07IF P06IF P05IF P04IF P03IF P02IF P01IF P00IF Reset value Bit7~Bit0 P0iIF: P0i interrupt flag bit (i=0-7); P0i port produces an interrupt, which requires software clearance; There is no interrupt in the P0i port.
Page 58: The Clear Operation For The Interrupt Flag Bit
CMS80F731x Reference Manual The Clear Operation For the Interrupt Flag Bit 6.4.4 The clear operation of the interrupt flag is divided into the following categories: ◆ Automatic hardware cleanup (requires entry into interrupt service) ◆ Software cleanup ◆ Read/write operations are cleared The hardware automatically clears the flag bits The bits that support hardware auto-clearing are the interrupt flag bits generated by IN0, INT1, T0, T1, T3, and T4.
Page 59: Special Interrupt Flag Bits In Debug Mode
CMS80F731x Reference Manual Special Interrupt Flag Bits in Debug Mode 6.4.5 The flag bit in the system is not written to zero to the flag bit, but requires reading/writing other registers to clear the flag bit. In debug mode, after breakpoint execution, step-through, or stop operation, the emulator reads out all register values from the system to the emulation software, and the emulator reads/writes exactly the same as in normal mode.
Page 60: I/O Port
CMS80F731x Reference Manual 7. I/O Port GPIO Function The chip has four sets of I/O ports: PORT0, PORT1, PORT2, PORT5. PORTx is a bidirectional port. Its corresponding data direction register is PxTRIS. A bit set to 1 (=1) of the PxTRIS allows the corresponding pin to be configured as an output.
Page 61: Portx Open-Drain Control Register Pxod
CMS80F731x Reference Manual PORTx Open-drain Control Register PxOD 7.1.3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxOD PxOD7 PxOD6 PxOD5 PxOD4 PxOD3 PxOD2 PxOD1 PxOD0 Reset value Register P0OD Address: F009H; Register P1OD Address: F019H; Register P2OD Address: F029H; Register P5OD address: F059H.
Page 62: Portx Slope Control Register Pxsr
CMS80F731x Reference Manual PORTx Slope Control Register PxSR 7.1.6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxSR PxSR7 PxSR6 PxSR5 PxSR4 PxSR3 PxSR2 PxSR1 PxSR0 Reset value Register P0SR Address: F00DH; Register P1SR Address: F01DH; Register P2SR Address: F02DH; Register P5SR address: F05DH.
Page 63: Multiplexed Functions
CMS80F731x Reference Manual Multiplexed Functions Port Multiplexing Feature Table 7.2.1 Pins are shared in a variety of functions, and each I/O port can be flexibly configured with digital functions or specified analog functions. The digital function of the external input is selected by the port input function allocation register (PS_XX); The multiplexing function is selected by the port multiplexing function configuration register (PxnCFG), where the communication input function is also specified by the communication input function allocation register (PS_XX).
Page 64 CMS80F731x Reference Manual LED port assignment, analog module, CONFIG configuration ports are shown in the following table: GPIO(0) ANA(1) CONFIG LEDSEG LEDCOM LEDx TOUCH COM0 LED0 COM1 LED1 COM2 LED2 COM3 LED3 SEG0 COM4 LED4 SEG1 COM5 LED5 SEG2 COM6 LED6 SEG3 COM7...
Page 65: Port Multiplexing Feature Configuration Register
CMS80F731x Reference Manual Port Multiplexing Feature Configuration Register 7.2.2 The PORTx function configuration register PxnCFG Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxnCFG PxnCFG2 PxnCFG1 PxnCFG0 Reset value Bit7~Bit3 Reserved, must be 0. PxnCFG< 2:0>: Feature configuration bit, the default simulation is a function. For details, see port Bit2~Bit0 function configuration instructions;...
Page 66 CMS80F731x Reference Manual PS_XX input function port allocation register PS_XX (as described in the table above) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PS_XX PS_XX6 PS_XX5 PS_XX4 PS_XX3 PS_XX2 PS_XX1 PS_XX0 Reset value Bit7 Reserved, must be 0. PS_XX<6:0>: The input function assigns control bits Bit6~Bit0 (Subject to the actual port of the chip, the unused value is retained and...
Page 67: Communication Input Function Allocation Registers
CMS80F731x Reference Manual Communication Input Function Allocation Registers 7.2.4 When the port is used as a communication port (UART0/UART1/SPI/IIC), it has multiple input ports to select, and different port inputs can be selected by setting the following registers. The communication input function port assignment registers are as follows: register address...
Page 68: Port External Interrupt Control Registers
CMS80F731x Reference Manual Port External Interrupt Control Registers 7.2.5 When using an external interrupt, the port needs to be configured as GPIO function and the direction is set to the input port. Alternatively, the multiplexing function is the input port (e.g. RXD0, RXD1), each port can be configured as a GPIO interrupt function.
Page 69 CMS80F731x Reference Manual from high to low. The output capability of a communication port has no priority restrictions, and if multiple ports are configured with the same output capability, the functionality outputs simultaneously on those ports. The RXD0/1 of the UART0/1 is selected by the port allocation register as an input function, and the port allocation register is independent of the synchronous output function.
Page 70: Watchdog Timer (Wdt)
CMS80F731x Reference Manual 8. Watchdog Timer (WDT) Overview The Watch Dog Timer is an on-chip timer with configurable overflow time and clock source provided by the system clock Fsys. When the watchdog timer counts to the configured overflow value, a watchdog overflow interrupt flag bit (WDTIF=1) is generated.
Page 71: Watchdog Overflow Control Register Ckcon
CMS80F731x Reference Manual Note: If the WDT in CONFIG is configured as: ENABLE, the WDT is always enabled, regardless of the state of the WDTRE control bit. And the overflow reset function of WDT is forced on. If WDT in CONFIG is configured as : SOFTWARE CONTROL , WDTRE can be enabled or disabled using the WDTRE control bit.
Page 72: Wdt Interrupt
CMS80F731x Reference Manual WDT Interrupt The watchdog timer can enable or disable interrupts via the EIE2 register, and the high/low priority is set via the EIP2 register, where the relevant bits are described as following. Interrupt Mask Register EIE2 8.3.1 0xAA Bit7 Bit6...
Page 73: Interrupt Priority Control Register Eip2
CMS80F731x Reference Manual Interrupt Priority Control Register EIP2 8.3.2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...
Page 74: Timer Counter 0/1 (Timer0/1)
CMS80F731x Reference Manual 9. Timer Counter 0/1 (Timer0/1) Timer 0 is similar in type and structure to Timer 1 and is two 16-bit timers. Timer 1 has three modes of operation and Timer 0 has four modes of operation. They provide basic timing and event counting operations. In "timer mode", the timing register is incremented every 12 or 4 system cycles when the timer clock is enabled.
Page 75: Related Registers
CMS80F731x Reference Manual Related Registers Timer0/1 Mode Register TMOD 9.2.1 0x89 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 GATE1 T1M1 T1M0 GATE0 T0M1 T0M0 TMOD Reset value Bit7 GATE1: Timer 1 gate control bit; Enable; Disable. Bit6 CT1: Timer 1 timing/count select bits; Count;...
Page 76: Timer0/1 Control Register Tcon
CMS80F731x Reference Manual Timer0/1 Control Register TCON 9.2.2 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; The Timer1 counter overflows and enters the interrupt service program hardware to automatically zero;...
Page 77: Timer0 Data Register Low Bit Tl0
CMS80F731x Reference Manual Timer0 Data Register Low Bit TL0 9.2.3 0x8A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL07 TL06 TL05 TL04 TL03 TL02 TL01 TL00 Reset value Bit7~ Bit0 TL0<7:0>: Timer 0 low data register (also as counter low). Timer0 Data Register High Bit TH0 9.2.4 0x8C...
Page 78: Function Clock Control Register Ckcon
CMS80F731x Reference Manual Function Clock Control Register CKCON 9.2.7 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON WTS2 WTS1 WTS0 Reset value Bit7~Bit5 WTS<2:0>: WDT overflow time selection bits; 000= *Tsys; 001= *Tsys; 010= *Tsys; 011= *Tsys; 100= *Tsys 101= *Tsys;...
Page 79: Timer0/1 Interrupt
CMS80F731x Reference Manual Timer0/1 Interrupt Timer0/1 can enable or disable interrupts via the IE register, and can also set high/low priority via the IP register, where the relevant bits are described as following: Interrupt Mask Register IE 9.3.1 0xA8 Bit7 Bit6 Bit5 Bit4...
Page 80: Interrupt Priority Control Register Ip
CMS80F731x Reference Manual Interrupt Priority Control Register IP 9.3.2 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Reserved, must be 0. Bit7 Bit6 PS1: UART1 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit5 PT2: TIMER2 interrupt priority control bit;...
Page 81: Timer0/1, Int0/1 Interrupt Flag Bit Register Tcon
CMS80F731x Reference Manual Timer0/1, INT0/1 Interrupt Flag Bit Register TCON 9.3.3 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; Timer1 counter overflow, when entering the interrupt service program, the hardware is automatically cleared, and the software can also be cleared;...
Page 82: Timer0 Working Mode
CMS80F731x Reference Manual Timer0 Working Mode T0 - Mode 0 (13-bit Timing/Counting Mode) 9.4.1 In this mode, timer 0 is a 13-bit register. When all the bits of the counter are flipped from 1 to 0, the timer 0 interrupt flag TF0 is set to 1.
Page 83: T0 - Mode 2 (8-Bit Auto-Reload Timing/Counting Mode)
CMS80F731x Reference Manual T0 - Mode 2 (8-bit Auto-reload Timing/Counting Mode) 9.4.3 The mode 2 timer register is an 8-bit counter (TL0) with auto reload mode, as shown in the figure below. The overflow from TL0 not only sets TF0 to 1, but also reloads the contents of TH0 from software to TL0. The value of TH0 remains unchanged during Reloading.
Page 84: Timer1 Working Mode
CMS80F731x Reference Manual Timer1 Working Mode T1 - Mode 0 (13-bit Timing/Counting Mode) 9.5.1 In this mode, timer 1 is a 13-bit register. When all the bits of the counter are flipped from 1 to 0, the timer 1 interrupt flag TF1 is set to 1.
Page 85: T1 - Mode 2 (8-Bit Auto Reload Timing/Counting Mode)
CMS80F731x Reference Manual T1 - Mode 2 (8-bit Auto Reload Timing/Counting Mode) 9.5.3 The timer 1 register in mode 2 is an 8-bit counter (TL1) with auto-reload mode, as shown in the figure below. The overflow from TL1 not only makes TF1 1, but also reloads the contents of TH1 from software to TL1. The value of TH1 remains unchanged during Reloading.
Page 86: Timer Counter 2 (Timer2)
CMS80F731x Reference Manual 10. Timer Counter 2 (Timer2) Timer 2 with additional compare/capture/reload functionality is one of the core peripheral units. It can be used for the generation of various digital signals and event capture, such as pulse generation, pulse width modulation, pulse width measurement, etc.
Page 87: Related Registers
CMS80F731x Reference Manual 10.2 Related Registers Timer2 Control Register T2CON 10.2.1 0xC8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2PS I3FR T2R1 T2R0 T2CM T2I1 T2I0 T2CON CAPES Reset value Bit7 T2PS: Timer2 clock prescaler selection bit; Fsys/24; Fsys/12. Bit6 I3FR: Capture channel 0 input one-edge selection with comparison interrupt moment...
Page 88: Timer2 Data Register High Th2
CMS80F731x Reference Manual Timer2 Data Register High TH2 10.2.3 0xCD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TH27 TH26 TH25 TH24 TH23 TH22 TH21 TH20 Reset value Bit7~Bit0 TH2<7:0>: Timer 2 high-bit data register (also as counter low). Timer2 Compare/Capture/Auto Reload Register Low Bit RLDL 10.2.4 0xCA Bit7...
Page 89: Timer2 Compares/Captures Channel 2 Register Low-Bit Ccl2
CMS80F731x Reference Manual Timer2 Compares/Captures Channel 2 Register Low-bit CCL2 10.2.8 0xC4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CCL27 CCL26 CCL25 CCL24 CCL23 CCL22 CCL21 CCL20 CCL2 Reset value Bit7~Bit0 CCL2<7:0>: Timer 2 compares/captures channel 2 registers low. Timer2 Compares/Captures Channel 2 Register High-bit CCH2 10.2.9 0xC5...
Page 90: Timer2 Compares The Capture Control Register Ccen
CMS80F731x Reference Manual 10.2.12 Timer2 Compares the Capture Control Register CCEN 0xCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CMH3 CML3 CMH2 CML2 CMH1 CML1 CMH0 CML0 CCEN Reset value Bit7~Bit6 CMH3-CML3: Capture/Compare Mode Control Bits; Capture/Compare Prohibited; The capture operation is triggered on the rising or falling edge of channel 3 (CAPES selection);...
Page 91: Timer2 Interrupts
CMS80F731x Reference Manual 10.3 Timer2 Interrupts Timer 2 can be enabled or disabled by register IE, and high/low priority can also be set via IP registers. Timer2 has 4 interrupt types: A timed overflow interrupt. ◆ ◆ The external pin T2EX drops along the interrupt. ◆...
Page 92: Timer2 Interrupt Mask Register T2Ie
CMS80F731x Reference Manual Timer2 Interrupt Mask Register T2IE 10.3.1.2 0xCF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IE T2OVIE T2EXIE T2C3IE T2C2IE T2C1IE T2C0IE Reset value Bit7 T2OVIE: Timer2 overflow interrupt enable bits; Interrupts are Enabled; Disable Interrupt. Bit6 T2EXIE: Timer2 external loading interrupt enable bits;...
Page 93: Timer2 Interrupt Flag Bit Register T2If
CMS80F731x Reference Manual Set to low-level interrupt. Bit1 PT0: TIMER0 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit0 PX0: External interrupt 0 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Timer2 Interrupt Flag Bit Register T2IF 10.3.1.4 0xC9 Bit7...
Page 94: Timer Interrupts
CMS80F731x Reference Manual Timer Interrupts 10.3.2 The timer interrupt enable bit is set by register T2IE[7], and the interrupt flag bit is viewed by register T2IF[7]. When the Timer2 timer overflows, the timer overflow interrupt flag bit TF2 will be set to 1. Externally Triggered Interrupts 10.3.3 The external pin T2EX falling edge trigger interrupt enable bit is set by register T2IE[6], and the interrupt flag bit is viewed...
Page 95: Timer2 Feature Description
CMS80F731x Reference Manual 10.4 Timer2 Feature Description Timer 2 is a 16-bit up counting timer with a clock source from the system clock. Timer2 can be configured with the following functional modes: Timing mode. ◆ ◆ Reload mode. ◆ Gating timing mode. ◆...
Page 96: Gated Timing Mode
CMS80F731x Reference Manual Gated Timing Mode 10.4.3 When Timer2 is used as a gated timer function, an external input pin, T2, serves as the gated input to timer 2. If the T2 pin is high, the internal clock input is gated to the timer. A low T2 pin terminates the counting. This function is often used to measure pulse width.
Page 97: Compare Mode
CMS80F731x Reference Manual Compare Mode 10.4.5 The comparison function consists of two modes: comparison mode 0 and comparison mode 1, selected by the T2CM bit in the special function register T2CON. These two comparison modes generate periodic signals and change the duty cycle control mode, and are often used for pulse width modulation (PWM) and control applications where continuous square waves need to be generated, covering a wide range of applications.
Page 98: Comparison Mode 1
CMS80F731x Reference Manual The output block diagram of comparision mode 0 is shown in the following figure: Timer Count = 0xFFFF Timer Count = Compare Value Timer Count = Reload Vaule Generate Timer overflow interrupt Generate Timer overflow interrupt CCx(x=0,1,2,3) Generate Compare Interrupt Comparison Mode 1 10.4.5.2...
Page 99: Capture Mode
CMS80F731x Reference Manual Capture Mode 10.4.6 Each of the four 16-bit registers {RLDH,RLDL}, {CCH1,CCL1}, {CCH2,CCL2}, {CCH3,CCL3} can be used to latch the current 16-bit value of {TH2,TL2}. This feature provides two different capture modes. In mode 0, an external event can latch the contents of timer 2 into the capture register. In mode 1, the capture operation occurs when a low-bit byte (RLDL/CCL1/CCL2/CCL3) is written to the 16-bit capture register.
Page 100: Capture Mode 1
CMS80F731x Reference Manual Capture Mode 1 10.4.6.2 In capture mode 1, the capture operation event is the execution of a write byte instruction to the capture register. A write register signal, such as a write RLDL, initiates a capture operation, and the value written is independent of this function. After the write instruction is executed, the contents of timer 2 are latched into the corresponding capture register.
Page 101: Timer 3/4 (Timer3/4)
CMS80F731x Reference Manual 11. Timer 3/4 (Timer3/4) Timer 3/4 is similar to timer 0/1 in that it is two 16-bit timers. Timer 3 has four modes of operation and Timer 4 has three modes of operation. In contrast to Timer0/1, Timer3/4 only provides timer operations. With the timer activated, the value of the register is incremented every 12 or 4 system cycles.
Page 102: Timer3 Data Register Low Bit Tl3
CMS80F731x Reference Manual Timer3 Data Register Low Bit TL3 11.2.2 0xDA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL37 TL36 TL35 TL34 TL33 TL32 TL31 TL30 Reset value Bit7~Bit0 TL3<7:0>: Timer 3 low bit data register (while acting as timer low bit). Timer3 Data Register High Bit TH3 11.2.3 0xDB...
Page 103: Timer3/4 Interrupt
CMS80F731x Reference Manual 11.3 Timer3/4 Interrupt Timer 3/4 can enable or disable interrupts via the EIE2 register, and high/low priority can also be set via the EIP2 register, where the relevant bits are described as following: Interrupt Mask Register EIE2 11.3.1 0xAA Bit7...
Page 104: Interrupt Priority Control Register Eip2
CMS80F731x Reference Manual Interrupt Priority Control Register EIP2 11.3.2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...
Page 105: Peripheral Interrupt Flag Bit Register Eif2
CMS80F731x Reference Manual Peripheral Interrupt Flag Bit Register EIF2 11.3.3 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...
Page 106: Timer3 Working Mode
CMS80F731x Reference Manual 11.4 Timer3 Working Mode T3 - Mode 0 (13-bit Timing Mode) 11.4.1 In this mode, timer 3 is a 13-bit register. When all the bits of the timer are flipped from 1 to 0, the timer 3 interrupt flag TF3 is set to 1.
Page 107: T3 - Mode 2 (8-Bit Auto Reload Timing Mode)
CMS80F731x Reference Manual T3 - Mode 2 (8-bit Auto Reload Timing Mode) 11.4.3 The timer 3 register in mode 2 is an 8-bit timer (TL3) with auto reload mode, as shown in the figure below. The overflow from TL3 not only puts TF3 at 1, but also reloads the contents of TH3 from software to TL3. The value of TH3 remains unchanged during Reloading.
Page 108: Timer4 Working Mode
CMS80F731x Reference Manual 11.5 Timer4 Working Mode T4 - Mode 0 (13-bit Timing Mode) 11.5.1 In this mode, timer 4 is a 13-bit register. When all the bits of the timer are flipped from 1 to 0, the timer 4 interrupt flag TF4 is set to 1.
Page 109: T4- Mode 2 (8-Bit Auto Reload Timing Mode)
CMS80F731x Reference Manual T4- Mode 2 (8-bit Auto Reload Timing Mode) 11.5.3 The timer 4 register in mode 2 is an 8-bit timer (TL4) with an auto-reload mode, as shown in the figure below. The overflow from TL4 not only makes TF4 1, but also reloads the contents of TH4 from software to TL4. The value of TH4 remains unchanged during Reloading.
Page 110: Lse Timer(Lse_Timer)
CMS80F731x Reference Manual 12. LSE Timer(LSE_Timer) 12.1 Overview The LSE timer is a clock source from an external low-speed clock LSE, a 16-bit up-counting timer. When using the LSE timer function, you should first set the LSE module to enable, wait for the LSE clock to stabilize (about 1.5s), and then set the LSE count enable.
Page 111: Lse Timer Control Register Lsecon
CMS80F731x Reference Manual LSE Timer Control Register LSECON 12.2.3 F696H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LSECON LSEEN LSEWUEN LSECNTEN LSESTA LSEIE LSEIF Reset value Bit7 LSEEN: LSE module enable control; Enable; Disable. Bit6 LSEWUEN: LSE timer wake-up enable control; Enable;...
Page 112: Interrupt With Sleep Wake-Up
CMS80F731x Reference Manual 12.3 Interrupt With Sleep Wake-up The LSE timer can enable or disable interrupts via LSECON registers, setting high/low priority via EIP3 registers, where the relevant bits are described as following. 0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP3...
Page 113: Feature Description
CMS80F731x Reference Manual 12.4 Feature Description To use the LSE timer function, you need to set LSEEN=1 to enable the LSE timer function module, and then wait for the LSE clock steady state bit LSESTA=1, then configure the LSE timing value {LSECRH[7:0], LSECRL[7:0]}, and finally set LSECNT=1, enable LSE count, and turn on the LSE count function.
Page 114: Wake-Up Timer (Wut)
CMS80F731x Reference Manual 13. Wake-up Timer (WUT) 13.1 Overview Wake Up Timer is a clock source from the internal low-speed clock LSI, a 12-bit, up-count timer for sleep wake-ups that can be used to time-wake systems in sleep mode. Configure the timed wake-up time before the system goes to sleep and enable the timed wake-up function.
Page 115: Feature Description
CMS80F731x Reference Manual 13.3 Feature Description The internal wake-up timer works on the principle that after the system enters sleep mode, the CPU stops working with all peripheral circuitry, and the internal low-power oscillator LSI begins to operate, and its oscillation clock is 125KHz (T ≈...
Page 116: Baud Rate Timer (Brt)
CMS80F731x Reference Manual 14. Baud Rate Timer (BRT) 14.1 Overview The chip has a 16-bit baud rate timer BRT, which mainly provides a clock for the UART module. 14.2 Related Registers BRT Module Control Register BRTCon 14.2.1 F5C0H Bit7 Bit6 Bit5 Bit4 Bit3...
Page 117: Feature Description
CMS80F731x Reference Manual 14.3 Feature Description The BRT has a 16-bit increment counter, the clock is derived from the pre-division circuit, the pre-division clock is determined by the timer pre-division select bit BRTCKDIV, and the initial value of the counter is loaded by {BRTDH, BRTDL}. When the timer enable bit BRTEN=1 is turned on, the counter starts working.
Page 118: Cyclic Redundancy Check Unit (Crc)
CMS80F731x Reference Manual 15. Cyclic Redundancy Check Unit (CRC) 15.1 Overview In order to ensure safety during operation, the IEC61508 standard requires that data be confirmed even during CPU operation. This universal CRC module performs CRC operations as a peripheral function during CPU operation. The universal CRC module performs CRC checks by specifying the data to be confirmed by the program, and is not limited to the code flash memory area but can be used for multi-purpose checks.
Page 119: Feature Description
CMS80F731x Reference Manual 15.3 Feature Description After writing the CRCIN register, a system clock is passed to save the CRC operation result to the CRCDL/CRCDH register. If necessary, the data of the previous operation must be read before writing, otherwise it will be overwritten by the new operation result.
Page 120: Buzzer Driver (Buzzer)
CMS80F731x Reference Manual 16. Buzzer Driver (BUZZER) 16.1 Overview The buzzer drive module consists of an 8-bit counter, a clock driver, and a control register. The buzzer drives a 50% duty- square wave with a frequency set by registers BUZCON and BUZDIV, and its frequency output covers a wide range. 16.2 Related Registers BUZZER Control Register BUZCON 16.2.1...
Page 121: Feature Description
CMS80F731x Reference Manual 16.3 Feature Description When using a buzzer, you need to configure the corresponding port as a buzzer-driven output. For example, configure the P16 as a buzzer drive output port, the configuration is as follows: P16CFG = 0x04; The P16 is configured as a buzzer drive output By configuring the Related Registers of the buzzer drive module, it is possible to set the different frequencies at which the buzzer drive outputs.
Page 122: Pwm Module
CMS80F731x Reference Manual 17. PWM Module 17.1 Overview The PWM module supports six PWM generators, which can be configured as 6 independent PWM outputs (PG0-PG5), or as 3 sets of synchronous PWM outputs, or 3 pairs of complementary PWM outputs with programmable dead-zone generators, where PG0-PG1, PG2-PG3, and PG4-PG5 are paired.
Page 123: Feature Description
CMS80F731x Reference Manual 17.4 Feature Description Functional Block Diagram 17.4.1 PWM consists of a clock control module, a PWM counter module, an output comparison unit, a waveform generator, and an output controller, and its block diagram is shown in the following figure: PWMPnH &...
Page 124: Edge Alignment
CMS80F731x Reference Manual Edge Alignment 17.4.2 In edge alignment mode, the 16-bit PWM counter CNTn starts counting down at the beginning of each cycle and compares to the value CMPn locked in the PWMDnH/PWMDnL register, when CNTn= CMPn PGn outputs high, PWMnDIF is set to 1.
Page 125: Complementary Model
CMS80F731x Reference Manual Complementary Model 17.4.3 6 PWM can be set up as 3 sets of complementary PWM pairs. In the complementary mode, the cycle, duty cycle and clock divider control of PG1, PG3, and PG5 are determined by the PG0, PG2, and PG4 related registers, respectively, that is, in addition to the corresponding output enable control bits (PWMnOE), the PG1, PG3, and PG5 output waveforms are no longer controlled by their own registers.
Page 126: Synchronous Mode
CMS80F731x Reference Manual Synchronous Mode 17.4.4 6-channel PWM can be set to 3 sets of synchronous PWM pairs. In synchronous mode, the period, duty cycle and clock divider control of PG1, PG3, PG5 are determined by the PG0, PG2, PG4 related registers respectively, that is, in addition to the corresponding output enable control bit (PWMnOE), the PG1, PG3, PG5 output waveforms are no longer controlled by their own registers, PG1 output waveforms are similar to PG0, PG3 output waveforms are PG2, and PG5 output waveforms are similar to PG4.
Page 127: Pwm-Related Registers
CMS80F731x Reference Manual 17.5 PWM-related Registers PWM Control Register PWMCON 17.5.1 F120H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCON PWMRUN PWMMODE1 PWMMODE0 GROUPEN Reset value Bit7 Reserved, must be 0. Bit6 PWMRUN: PWM clock pre-division, clock division enable bit; Prohibition (PWMmnPSC, PWMmnDIV are cleared 0);...
Page 128: Pwm0/1 Clock Prescale Control Register Pwm01Psc
CMS80F731x Reference Manual Enable; Disable. PWM0/1 Clock Prescale Control Register PWM01PSC 17.5.3 F123H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM01PSC PWM01PSC7 PWM01PSC6 PWM01PSC5 PWM01PSC4 PWM01PSC3 PWM01PSC2 PWM01PSC1 PWM01PSC0 Reset value Bit7~Bit0 PWM01PSC<7:0>: PWM channel 0/1 prescale control bit; The prescaler clock stops, the counter of PWM0/1 stops;...
Page 129: Pwm Clock Divide Control Register Pwmndiv (N=0-5)
CMS80F731x Reference Manual PWM Clock Divide Control Register PWMnDIV (n=0-5) 17.5.6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMnDIV PWMnDIV2 PWMnDIV1 PWMnDIV0 Reset value Registers PWMnDIV (n=0-5) Address: F12AH, F12BH, F12CH, F12DH, F12EH, F12FH. Bit7~Bit3 Reserved, must be 0. Bit2~Bit0 PWMnDIV<2:0>: PWM channel n clock divider control bit;...
Page 130: Pwm Counter Mode Control Register Pwmcntm
CMS80F731x Reference Manual PWM Counter Mode Control Register PWMCNTM 17.5.9 F127H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCNTM PWM5CNTM PWM4CNTM PWM3CNTM PWM2CNTM PWM1CNTM PWM0CNTM Reset value Bit7~Bit6 Reserved, must be 0. Bit5~Bit0 PWMnCNTM: PWM channel n counter mode control bit (n=0-5); Auto loading mode;...
Page 131: Pwm Cycle Data Register High 8 Bits Pwmpnh (N=0-5)
CMS80F731x Reference Manual 17.5.13 PWM Cycle Data Register High 8 Bits PWMPnH (n=0-5) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMPnH PWMPnH7 PWMPnH6 PWMPnH5 PWMPnH4 PWMPnH3 PWMPnH2 PWMPnH1 PWMPnH0 Reset value Registers PWMPnH (n=0-5) Address: F131H, F133H, F135H, F137H, F139H, F13BH. Bit7~Bit0 PWMPnH<7:0>: The PWM channel n-period data register is 8 bits high.
Page 132: Pwm0/1 Dead-Zone Delay Data Register Pwm01Dt
CMS80F731x Reference Manual 17.5.17 PWM0/1 Dead-zone Delay Data Register PWM01DT F161H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM01DT PWM01DT7 PWM01DT6 PWM01DT5 PWM01DT4 PWM01DT3 PWM01DT2 PWM01DT1 PWM01DT0 Reset value Bit7~Bit0 PWM01DT<7:0>: PWM channel 0/1 dead-zone delay data register. 17.5.18 PWM2/3 Dead-zone Delay Data Register PWM23DT F162H Bit7 Bit6...
Page 133: Pwm Interrupt
CMS80F731x Reference Manual 17.6 PWM Interrupt PWM has a total of 12 interrupt flags, of which 6 zero interrupt flags, 6 downward comparison interrupt flags, the generation of interrupt flag bits and the corresponding interrupt enable bit is not related to whether the corresponding interrupt enable bit is turned on.
Page 134: Interrupt Priority Control Register Eip2
CMS80F731x Reference Manual Interrupt Priority Control Register EIP2 17.6.2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...
Page 135: Pwm Down Compare Interrupt Mask Register Pwmdie
CMS80F731x Reference Manual PWM Down Compare Interrupt Mask Register PWMDIE 17.6.4 F16BH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMDIE PWM5DIE PWM4DIE PWM3DIE PWM2DIE PWM1DIE PWM0DIE Reset value Bit7~Bit6 Reserved, must be 0. Bit5~Bit0 PWMnDIE: PWM channel n down compared interrupt shield bits (n=0-5); Enable interrupts;...
Page 136: Hardware Led Matrix Driver
CMS80F731x Reference Manual 18. Hardware LED Matrix Driver 18.1 Overview The chip integrates a hardware LED matrix driver circuit, which can facilitate the user to realize the display drive of the LED. 18.2 Characteristic Hardware LED matrix drivers have the following characteristics: ◆...
Page 137: Led Control Register Ledcon
CMS80F731x Reference Manual LED Control Register LEDCON 18.3.2 F765H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCON LED_EN DUTY1 DUTY0 CC_CA CLKSEL1 CLKSEL0 Reset value Bit7 LED_EN: LED enable control bit; LED enable; LEDs are Disable. Bit6~Bit5 DUTY<1:0>: Duty cycle selection bit of the LED; 1/4DUTY;...
Page 138: Led Clock Prescale Data Register High 8 Bit Ledclkh
CMS80F731x Reference Manual LED Clock Prescale Data Register High 8 Bit LEDCLKH 18.3.4 F767H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCLKH CLK15 CLK14 CLK13 CLK12 CLK11 CLK10 CLK9 CLK8 Reset value Bit7~Bit0 CLK<15:8>: The LED clock divider is 8 bits high. Clock frequency of the LED driver: F / (CLK<15:0>+1).
Page 139: Seg Port Enable Control Register Ledsegen1
CMS80F731x Reference Manual SEG Port Enable Control Register LEDSEGEN1 18.3.8 F762H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSEGEN1 SEGEN15 SEGEN14 SEGEN13 SEGEN12 SEGEN11 SEGEN10 SEGEN9 SEGEN8 Reset value Bit7~Bit0 BLESSING<15:8>: LED_S15-LED_S8 port enable control bit; Enable; Disable. COM0 Corresponding SEG Data Register LEDC0DATAn (n=0-1). 18.3.9 Bit7 Bit6...
Page 140: Com3 Corresponding Seg Data Register Ledc3Datan (N=0-1)
CMS80F731x Reference Manual 18.3.12 COM3 Corresponding SEG Data Register LEDC3DATAn (n=0-1). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC3DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset value LEDC3DATA0 Address: F74CH; LEDC3DATA1 Address: F74DH. Bit7~Bit0 SEG<8n+7:8n>: When the COM3 port is active, the SEG[8n+7]-SEG[8n] port data output; High level;...
Page 141: Com7 Corresponding Seg Data Register Ledc7Datan (N=0-1)
CMS80F731x Reference Manual 18.3.16 COM7 Corresponding SEG Data Register LEDC7DATAn (n=0-1). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC7DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset value LEDC7DATA0 Address: F75CH; LEDC7DATA1 address: F75DH. Bit7~Bit0 SEG<8n+7:8n>: When com7 port is active, SEG[8n+7]-SEG[8n] port data output; High level;...
Page 142: P14-P17 Drive Current Control Register Ledsdrp1H
CMS80F731x Reference Manual 18.3.19 P14-P17 Drive Current Control Register LEDSDRP1H F713H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP1H DRC3 DRC2 DRC1 DRC0 Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 DRC<3:0>: Pull current drive select control position (control P14/P15/P16/P17 four ports); 0000= 0mA;...
Page 143: Led Pin Drive Enable Low 8-Bit Ledenl
CMS80F731x Reference Manual 18.3.21 LED Pin Drive Enable Low 8-bit LEDENL F75EH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDENL LEDENL7 LEDENL6 LEDENL5 LEDENL4 LEDENL3 LEDENL2 LEDENL1 LEDENL0 Reset value Bit7 LEDENL7: (LEDMODE==0xAA) dot matrix drive mode LED7 (P07) pin function and drive enable bit;...
Page 144 CMS80F731x Reference Manual Bit3 LEDENL3: (LEDMODE==0xAA) dot matrix drive mode LED3 (P03) pin function and current drive enable bit; Led3 pins of the dot matrix drive function enable; The pull current drive of the LED3 pins is configured by the LEDSDRP0L register. The dot matrix drive function of the LED3 pins is Disabled as a GPIO function;...
Page 145: Led Pin Drive Enable High 8-Bit Ledenh
CMS80F731x Reference Manual 18.3.22 LED Pin Drive Enable High 8-bit LEDENH F75FH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDENH LEDENH7 LEDENH6 LEDENH5 LEDENH4 LEDENH3 LEDENH2 LEDENH1 LEDENH0 Reset value Bit7 LEDENH7: (LEDMODE==0xAA); Invalid; Invalid. (LEDMODE!=0xAA) Matrix drive mode SEG15 (P23) / software drive P23 pin current drive enable bit;...
Page 146 CMS80F731x Reference Manual (LEDMODE!=0xAA) Matrix drive mode SEG10 (P16) / software drive P16 pin current drive enable bit; The pull current drive of the P16 pin is configured by the LEDSDRP1H register; The pull current drive of the P16 pin is the default value. Bit1 LEDENH1: (LEDMODE==0xAA);...
Page 147: Com Port Sink Current Selection Register P0Dr
CMS80F731x Reference Manual 18.3.23 COM Port Sink Current Selection Register P0DR F00CH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0DR P0DR7 P0DR6 P0DR5 P0DR4 P0DR3 P0DR2 P0DR1 P0DR0 Reset value P0DR7: Bit7 P07 drive current selection; 150mA; 50mA. P0DR6: Bit6 P06 drive current selection;...
Page 148: Led Driver Output Waveform
CMS80F731x Reference Manual 18.4 LED Driver Output Waveform According to the relevant configuration registers of the LED driver, the corresponding LED driver output waveform can be set. The LED is configured with 1/4DUTY, co-negative drive mode, and the waveform is shown in the following figure: COM0 Valid COM0 Valid COM0...
Page 149: Hardware Led Dot Matrix Driver
CMS80F731x Reference Manual 19. Hardware LED Dot Matrix Driver 19.1 Overview LED dot matrix drive is to configure LED0 ~ LED8 port, so as to drive multiple LED lights, convenient for users to drive LED dot matrix. 19.2 Characteristic LED dot matrix drive mode features: ◆...
Page 150: Feature Description
CMS80F731x Reference Manual 19.3 Feature Description LED dot matrix is scanned by 8 * 8 dot matrix dual lamp mode, that is, two lights at a time (common cathode), corresponding to LED0 ~ LED8 port, up to 8x8 = 64 lights can be configured to drive. Configure the lighting situation of the corresponding address (1 means light, 0 means no light), the hardware will resolve the light address and the current scan address, and automatically complete the output control of the corresponding IO port.
Page 151 CMS80F731x Reference Manual The 7*8 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 The 7*7 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 Rev. 1.00 www.mcu.com.cn...
Page 152 CMS80F731x Reference Manual The 6*7 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED6 The 6*6 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED6 Rev. 1.00 www.mcu.com.cn...
Page 153 CMS80F731x Reference Manual The 5*5 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 The 4*4 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 Rev. 1.00 www.mcu.com.cn...
Page 154 CMS80F731x Reference Manual Taking the light 0, 1, and 2 as an example, the detailed digital output interface control timing is shown in the following figure: LED0 LED1 LED2 Schematic diagram of two lights Clock LED0_dout 0.016~4.096ms LED0_tris LED1_dout LED1_tris LED2_dout LED2_tris LED0...
Page 155: Related Registers
CMS80F731x Reference Manual 19.4 Related Registers LED Drive Mode Select Register LEDMODE 19.4.1 F769O'CLOCK Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDMODE LEDMODE7 LEDMODE6 LEDMODE5 LEDMODE4 LEDMODE3 LEDMODE2 LEDMODE1 LEDMODE0 Reset value Bit7~Bit0 LEDMODE<7:0>: LED drive mode selection register; 0x55= The LED matrix drive mode is valid, and the relevant registers are in effect;...
Page 156: Led Dot Matrix Drive Clock Prescale Register Low 8 Bit Ledclkl1
CMS80F731x Reference Manual LED Dot Matrix Drive Clock Prescale Register Low 8 Bit LEDCLKL1 19.4.3 F766H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCLKL1 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 Reset value Bit7~Bit0 CLK<7:0>: The LED dot matrix drives clock lower 8 bits. LED Dot Matrix Drive Clock Prescale Register High 8 Bits LEDCLKH1 19.4.4 F767H...
Page 157: Led Dot Matrix Drives Second Stage Configuration Register High 8 Bits Scan2Wh
CMS80F731x Reference Manual LED Dot Matrix Drives Second Stage Configuration Register High 8 Bits 19.4.7 scan2WH F763H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCAN2WH SCAN2WH7 SCAN2WH6 SCAN2WH5 SCAN2WH4 SCAN2WH3 SCAN2WH2 SCAN2WH1 SCAN2WH0 Reset value Bit7~Bit0 SCAN2WH<7:0>: LED dot matrix drive mode, the second stage of the light lighting cycle configuration register is 8 bits high.
Page 158: Led Dot Matrix Drive Cycle Select Register Lednsel (N=0-7)
CMS80F731x Reference Manual 19.4.10 LED Dot Matrix Drive Cycle Select Register LEDnSEL (n=0-7). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDnSEL LEDnSEL7 LEDnSEL6 LEDnSEL5 LEDnSEL4 LEDnSEL3 LEDnSEL2 LEDnSEL1 LEDnSEL0 Reset value LED0SEL Address:F750H; LED1SEL Address:F751H; LED2SEL Address:F754H; LED3SEL Address:F755H; LED4SEL Address:F758H;...
Page 159: P04-P07 Drive Current Control Register Ledsdrp0H
CMS80F731x Reference Manual 19.4.12 P04-P07 Drive Current Control Register LEDSDRP0H F711H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP0H DRC3 DRC2 DRC1 DRC0 Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 DRC<3:0>: Pull current drive select control position (control P04/P05/P06/P07 four ports); 0000= 0mA;...
Page 160 CMS80F731x Reference Manual The current drive of the LED5 pin is the default. (LEDMODE!=0xAA) Matrix drive mode SEG5 (P11) / software drive P11 pin current drive enable bit; The pull current drive of the P11 pin is configured by the LEDSDRP1L register; The pull current drive of the P11 pin is the default.
Page 161: Led Pin Drive Enable High 8-Bit Ledenh
CMS80F731x Reference Manual enable bit; LED0 pins are enabled by dot matrix drive function; The pull current drive of the LED0 pins is configured by the LEDSDRP0L register. The dot matrix drive function of the LED0 pin is Disabled as a GPIO function; The pull current drive of the LED0 pin is the default value.
Page 162 CMS80F731x Reference Manual Invalid; Invalid. (LEDMODE!=0xAA) Matrix drive mode SEG11 (P17) / software drive P17 pin current drive enable bit; The pull current drive of the P17 pin is configured by the LEDSDRP1H register; The pull current drive of the P17 pin is the default value. Bit2 LEDENH2: (LEDMODE==0xAA);...
Page 163: Led Dot Matrix Drive Interrupt
CMS80F731x Reference Manual 19.5 LED Dot Matrix Drive Interrupt LED Dot Matrix Drive Status Register LEDSTATUS 19.5.1 F76AH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSTATUS LEDIE LEDIF Reset value Bit7~Bit2 Reserved, must be 0. Bit1 LEDIE: LED dot matrix drive mode interrupt enable bit; LED dot matrix drive mode interrupt enable;...
Page 164: Spi Module
CMS80F731x Reference Manual 20. SPI Module 20.1 Overview This SPI is a fully configurable SPI master/slave device that allows the user to configure the polarity and phase of the serial clock signal SCLK. The serial clock line (SCLK) is synchronized with the shifting and sampling of information on two independent serial data lines, and the SPI data is sent and received simultaneously.
Page 165: Spi Port Configuration
CMS80F731x Reference Manual 20.2 SPI Port Configuration Using the SPI function requires configuring the relevant port as an SPI channel and selecting the corresponding port input through the communication input port registers. For example, configure P00, P01, P02, and P03 as SPI communication ports. The configuration code is as follows: PS_SCLK = 0x00;...
Page 166: Spi Hardware Description
CMS80F731x Reference Manual 20.3 SPI Hardware Description When an SPI transfer occurs, when one data pin moves out of one 8-bit character, the other data pin moves in the other 8- bit character. The 8-bit shift register in the master device and another 8-bit shift register in the slave device are connected as a cyclic 16-bit shift register, and when the transfer occurs, the distributed shift register is shifted by 8 bits, thus effectively swapping the characters of the master slave.
Page 167 CMS80F731x Reference Manual When the SPI is configured as a slave device, the SI pin is the slave device input data line and the SO is the slave device output data line. When the SPI is configured as a host device, the MI pin is the host device input data line and the MO is the host device output data line.
Page 168: Spi-Related Registers
CMS80F731x Reference Manual 20.4 SPI-related Registers SPI Control Register SPCR 20.4.1 0xEC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCR SPEN SPR2 MSTR CPOL CPHA SPR1 SPR0 Reset value Bit7 Reserved, must be 0. Bit6 SPEN: SPI module enable bit; Enable;...
Page 169: Spi Device Select Control Register Sscr
CMS80F731x Reference Manual SPI Device Select Control Register SSCR 20.4.3 The slave device selection control register SSCR can be read or written at any time and is used to configure which slave selection output should be driven when confirming an SPI host transfer. When the SPI host transfer starts, the contents of the SSCR register are automatically assigned to the NSS pin.
Page 170: Spi Master Mode
CMS80F731x Reference Manual 20.5 SPI Master Mode When SPI is configured for host mode, the transfer is initiated by writing to the SPDR registers. When new bytes are written to the SPDR register, the SPI starts transferring. The serial clock SCLK is generated by the SPI, enabled by the SPI in host mode, and output.
Page 171: Write Conflict Error
CMS80F731x Reference Manual Write Conflict Error 20.5.1 If the SPI data registers are written during the transfer, a write violation occurs. The transfer continues uninterrupted, and the write data that causes the error is not written to the shifter. Write conflicts are indicated by the WCOL flag in the SPSR register.
Page 172: Spi Slave Mode
CMS80F731x Reference Manual 20.6 SPI Slave Mode When configured as an SPI slave device, SPI transmission is initiated by an external SPI host module by using the SPI slave selection input and generates an SCLK serial clock. Before the transfer begins, it is necessary to determine which SPI slave will be used to exchange data. The NSS is used (clear = 0), and the clock signal connected to the SCLK line will transfer the SPI from the Slave device to the receiving shift register contents of the MOSI line and drive the MISO line with the contents of the transmitter shift registers.
Page 173 CMS80F731x Reference Manual In case the CPHA is cleared, WCOL generation can also be caused by SPDR register writes when either NSS line is cleared, at which point the SPI host can also complete without generating a serial clock SCLK. This is because the transfer start is not explicitly specified, and the NSS is driven low after a full-byte transfer may indicate the start of the next byte transfer.
Page 174: Spi Clock Control Logic
CMS80F731x Reference Manual 20.7 SPI Clock Control Logic SPI Clock Phase and Polarity Control 20.7.1 The software can choose to use either of the four combinations of two control bits (phase and polarity of the serial clock SCLK) in the SPI control register (SPCR). Clock polarity is specified by the CPOL control bit, and the CPOL control bit selection high or low level when the transmission is idle has no significant effect on the transmission format.
Page 175: Cpha=1 Transfer Format
CMS80F731x Reference Manual CPHA=1 Transfer Format 20.7.4 The following figure is a timing diagram of the SPI transmission with CPHA = 1. SCLK shows two waveforms: one for CPOL=0 and one for CPOL=1. Since the SCLK, MISO, and MOSI pins are directly connected between the master and slave, this diagram can be interpreted as a master or slave timing diagram.
Page 176: Spi Data Transfer
CMS80F731x Reference Manual 20.8 SPI Data Transfer SPI Transfer Starts 20.8.1 All SPI transfers are initiated and controlled by the master SPI device. As a slave device, the SPI will consider the transmission starting at the first SCLK edge or the falling edge of the NSS, depending on the CPHA format chosen. When CPHA = 0, the falling edge of the NSS indicates the start of the transmission.
Page 177: Spi Timing Diagram
CMS80F731x Reference Manual 20.9 SPI Timing Diagram Master Mode Transmission 20.9.1 When the clock polarity of the SPI is CPOL=0 and the clock phase CPHA=1, the NSS in SPI master mode is the clK of the system clock after the low level, the MOSI starts to output, and the DATA of the MOSI is output on the rising edge of the SCLK clock.
Page 178: Spi Interrupt
CMS80F731x Reference Manual 20.10 SPI Interrupt The interrupt number of the SPI is 22, where the interrupt vector is 0x00B3. To enable an SPI interrupt, it must set its enable bit SPIIE to 1 and the global interrupt enable bit EA to 1. If the SPI-related interrupt enables are all turned on, the CPU will enter the interrupt service program when the SPI global interrupt indicator bit SPIIF=1.
Page 179: Interrupt Priority Control Register Eip2
CMS80F731x Reference Manual Enable Timer3 interrupts; Forbidden Timer3 Interrupt. 20.10.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt;...
Page 180: Peripheral Interrupt Flag Bit Register Eif2
CMS80F731x Reference Manual 20.10.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...
Page 181: I2C Module
CMS80F731x Reference Manual 21. I2C Module 21.1 Overview The module provides an interface between the microcontroller and the I2C bus, as shown in the connection diagram below, and supports arbitration and clock synchronization to allow operation in multi-master systems. I2C supports normal, fast mode. The I2C module has the following characteristics: ◆...
Page 182: I2C Port Configuration
CMS80F731x Reference Manual 21.2 I2C Port Configuration If you use the I2C function, you should first configure the corresponding port as an SCL, SDA channel. For example, configure P00, P01 port as I2C function: PS_SCL = 0x00; Select the P00 port as the SCL pin PS_SDA = 0x01;...
Page 183: I2C Master Mode Control And Status Registers
CMS80F731x Reference Manual I2C Master Mode Control and Status Registers 21.3.2 The control registers include 4 bits: RUN, START, STOP, ACK bits. The START bit will produce the START or RESTART START condition. The STOP bit determines whether the data transfer stops at the end of the cycle, or continues. To generate a single transmission cycle, the slave address register writes to the desired address, the R/S bit is set to 0, and the control register writes to ACK=x, STOP=1, START=1, RUN=1 (I2CMCR=xxx0_x111x) to perform the operation and stop.
Page 184 CMS80F731x Reference Manual Combination of control bits (IDLE state) STOP START OPERATION START followed by SEND (master remains in send mode) START is followed by SEND and STOP Receive after START with reply (master remains in receiver mode) START is followed by REVIVE and STOP START followed by RECOVER (master remains in receiver mode) Combinations are prohibited...
Page 185 CMS80F731x Reference Manual Master mode status register I2CMSR 0xF5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I2CMIF BUS_BUSY IDLE ARB_LOST DATA_ACK ADD_ACK ERROR BUSY I2CMSR Reset value Bit7 I2CMIF: I2C Master mode interrupt flag bit; In master mode, send/receive completes, or a transmission error occurs. (Software zero, write 0 to clear);...
Page 186: I2C Slave Address Register
CMS80F731x Reference Manual I2C Slave Address Register 21.3.3 The slave address register consists of 8 bits: 7 bits of address (A6-A0) and receive/transmit bits R/S. The R/S bit determines whether the next operation is to receive (1) or send (0). Master mode slave address register I2CMSA 0xF4 Bit7...
Page 187: I2C Slave Mode
CMS80F731x Reference Manual 21.4 I2C Slave Mode There are five registers for connecting to the target device: self address, control, status, send data, and receive data registers. register address write Read Self address register I2CSADR Self address register I2CSADR 0xF1 Control register I2CSCR Status register I2CSSR 0xF2...
Page 188: I2C Slave Mode Transmit And Receive Buffer Registers I2Csbuf
CMS80F731x Reference Manual The status register consists of three bits: sendfin bit, RREQ bit, TREQ bit. The SENDFIN bit of Send Complete indicates that the Master I2C controller has completed the receipt of data during a single or continuous I2CS transmit operation. The Receive Request RREQ bit indicates that the I2CS device has receiveda data byte from the I2C master, and the I2CS device should read a data byte from the receiving data register I2CSBUF.
Page 189: I2C Interrupt
CMS80F731x Reference Manual 21.5 I2C Interrupt The interrupt number for I2C is 21, where the interrupt vector is 0x00AB. The Enable I2C interrupt must set its enable bit I2CIE to 1 and the global interrupt enable bit EA to 1. If the I2C-related interrupt enables are turned on,the CPU will enter the interrupt service program when the I2C global interrupt indicator bit I2CIF=1 is turned on.
Page 190: Interrupt Priority Control Register Eip2
CMS80F731x Reference Manual Interrupt Priority Control Register EIP2 21.5.2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2Cinterrupt priority control bit;...
Page 191: Peripheral Interrupt Flag Bit Register Eif2
CMS80F731x Reference Manual Peripheral Interrupt Flag Bit Register EIF2 21.5.3 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...
Page 192: I2C Slave Mode Transmission Mode
CMS80F731x Reference Manual 21.6 I2C Slave Mode Transmission Mode All rendered waveforms in this section default I2C to have their own address 0x39 ("00111001"). Single Receive 21.6.1 The following figure shows the sequence of signals received by I2C during a single data session.
Page 193: Single Send
CMS80F731x Reference Manual Single Send 21.6.2 The following figure shows the sequence of signals sent by I2C during a single data session. Single send sequence: Starting conditions; I2C is addressed by the I2C master as a transmitter; The address is confirmed by I2C; Datais transmitted by I2C;...
Page 194: Continuous Reception
CMS80F731x Reference Manual Continuous Reception 21.6.3 The following figure shows the sequence of signals received by I2C during continuous data reception. Continuous receive sequence: Start conditions. I2C is addressed by the I2C master as a receiver. The address is confirmed by I2C. Data is received by I2C.
Page 195: Continuous Sending
CMS80F731x Reference Manual Continuous Sending 21.6.4 The following figure shows the sequence of signals sent by I2C during continuous data transmission. Consecutive send sequences: Send conditions. I2C is addressed by the I2C master as a transmitter. The address is confirmed by I2C. The data is sent by I2C.
Page 196: Uartn Module
CMS80F731x Reference Manual 22. UARTn Module 22.1 Overview The Universal Synchronous Asynchronous Transceiver (UART0/UART1) provides a flexible way to exchange full-duplex data with external devices. UARTn has two physically separate receive and transmit buffers, SBUFn, which distinguish between operations on a receive buffer or a transmit buffer by reading and writing instructions to SBUFn.
Page 197: Uartn Baud Rate
CMS80F731x Reference Manual 22.3 UARTn Baud Rate UARTn In mode 0, the baud rate is fixed to the twelfth-way frequency of the system clock (Fsys/12); In mode 2, the baud rate is fixed to the system clock's division 32 or 64 (Fsys/32, Fsys/64); In modes 1 and 3, the baud rate is generated by the timer Timer1 or Timer4 or Timer2 or BRT module, and the chip chooses which timer to use as the baud rate clock source is determined by the register FUNCCR.
Page 198: Baud Rate Error
CMS80F731x Reference Manual BRTCKDIV is a BRT timer prescale selection bit, set by the register BRTCON. That is, the value of the BRT at the corresponding baud rate should be set to: {BRTDH,BRTDL} SMODn Fsys×2 {BRTDH,BRTDL}=65536- BRTCKDIV 32×2 ×BaudRate Baud Rate Error 22.3.3 In mode 1 and mode 3, UARTn selects different baud rate clock sources, and the errors at different baud rates are as follows:...
Page 199 CMS80F731x Reference Manual 3）SMODn=0，BRTCKDIV=0 baud Fsys=8MHz Fsys=16MHz Fsys=24MHz Fsys=48MHz rate {BRTH, Current {BRTH, Current {BRTH, Current {BRTH, Current Kbps BRTL} Rate Error BRTL} Rate Error BRTL} Rate Error BRTL} Rate Error 4800 65484 4808 -0.16 65432 4808 -0.16 65380 4808 -0.16 65224 4808...
Page 200: Uartn Register
CMS80F731x Reference Manual 22.4 UARTn Register UARTn has the same functionality as the standard 8051 UART. Its Related Registers are: FUNCCR, SBUFn, SCONn, PCON, IE, IP. The UARTn Data Buffer (SBUFn) consists of 2 independent registers: the transmit and receive registers. The data written to SBUFn will be set in the UARTn output register and the transmission will begin;...
Page 201: Uart Control Register Sconn
CMS80F731x Reference Manual UART Control Register SCONn 22.4.3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCONn UnSM0 UnSM1 UnSM2 UnREN UnTB8 UnRB8 Believe Reset value BANK0: Register SCON0 address 0x98; Register SCON1 address 0xEA. Bit7~Bit6 UnSM0- UnSM1: Multi-Slave communication control bit; Master synchronization mode;...
Page 202: Pcon Registers
CMS80F731x Reference Manual PCON Registers 22.4.4 0x87 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD0 SMOD1 THEIR STOP IDLE Reset value Registers in BANK0 Bit7 SMOD0: UART0 baud rate multiplier; UART0 baud rate doubled; The UART0 baud rate is normal. Bit6 SMOD1: UART1 baud rate multiplier;...
Page 203: Uartn Interrupt
CMS80F731x Reference Manual 22.5 UARTn Interrupt The interrupt number of UART0 is 4, where the interrupt vector is 0x0023. The interrupt number of UART1 is 6, where the interrupt vector is 0x0033. To enable a UARTn interrupt, it must set its enable bit ESn to 1 and the global interrupt enable bit EA to 1. If the interrupt enables associated with UARTn are turned on, TIn=1 or RIn=1, the CPU will enter the corresponding interrupt service program.
Page 204: Interrupt Priority Control Register Ip
CMS80F731x Reference Manual Interrupt Priority Control Register IP 22.5.2 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0. Bit6 PS1: UART1 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit5 PT2: TIMER2 interrupt priority control bit;...
Page 205: Uartn Mode
CMS80F731x Reference Manual 22.6 UARTn Mode Mode 0 - Synchronous Mode 22.6.1 Pin RXDn is the input or output and TXDn is the clock output. The TXDn output is a shift clock. The baud rate is fixed at 1/12 of the system clock frequency. 8 bits are transmitted preferentially with LSB. Initialize the receive by setting the flag in SCONN, set to: RIn = 0 and RENn = 1.
Page 206: Mode 2-9 Bit Asynchronous Mode (Fixed Baud Rate)
CMS80F731x Reference Manual Mode 2-9 Bit Asynchronous Mode (Fixed Baud Rate) 22.6.3 This mode is similar to Mode 1, but differs in two ways. The baud rate is fixed at 1/32 or 1/64 of the CLK clock frequency, with 11 bits of transceiver: start bit (0), 8 bits of data (LSB first), programmable bit 9, and stop bit (1). Bit 9 can be used to control parity of the UARTn interface: at send time, bit TBn8 in SCONn acts as the 9th bit output, and on receive, bit 9 affects RBn8 in SCONn.
Page 207: Analog-To-Digital Converter (Adc)
CMS80F731x Reference Manual 23. Analog-to-digital Converter (ADC) 23.1 Overview An analog-to-digital converter (ADC) converts an analog input signal into a 12-bit binary number representing the signal, as shown in the ADC block diagram below. The port analog input signal and the internal analog signal are connected to the input of the analog-to-digital converter after being multiplexed.
Page 208: Adc Configuration
CMS80F731x Reference Manual 23.2 ADC Configuration When configuring and using an ADC, the following factors must be considered: ⚫ Port configuration. ⚫ Channel selection. ⚫ ADC converts the clock source. ⚫ Interrupt control. The format in which the results are stored. ⚫...
Page 209: Convert The Clock
CMS80F731x Reference Manual Convert the Clock 23.2.4 The converted clock source can be selected by software setting the ADCKS bit of the ADCON1 register. The following 8 possible clock frequencies are available: ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ /128 /256 The time to complete a bit conversion is defined as T...
Page 210: The Adc Hardware Trigger Start
CMS80F731x Reference Manual 23.3 The ADC Hardware Trigger Start In addition to software-triggered ADC conversion, the ADC module provides a way for hardware to trigger start. One is the external port edge triggering method, and the other is the edge or periodic triggering mode of the PWM. Using a hardware trigger ADC requires setting ADCX to 1, even if the ADC function can be triggered externally.
Page 211: Adc Results Comparison
CMS80F731x Reference Manual 23.4 ADC Results Comparison The ADC module provides a set of digital comparators for comparing the results of an ADC with the value size of preloaded {ADCMPH, ADCMPL}. The result of each ADC conversion is compared to the preset value ADCMP, and the result of the comparison is stored in the ADCPO flag bit, which is automatically updated after the conversion is completed.
Page 212: Go To Sleep During The Conversion Process
CMS80F731x Reference Manual Select the format of the result; ⚫ Start the ADC module. ⚫ Wait for the required acquisition time. Set ADGO to 1 to start the conversion. Wait for the ADC conversion to finish by one of the following methods: ⚫...
Page 213: Related Registers
CMS80F731x Reference Manual 23.6 Related Registers There are 11 main registers associated with AD conversion, namely: ⚫ AD control registers ADCON0, ADCON1, ADCON2, ADCCHS, ADCLDO; ⚫ Comparator control register ADCPC; ⚫ Delay data register ADDLYL; ⚫ AD result data register ADRSH/L; Comparator data register ADCCMPH/L.
Page 214: Ad Control Register Adcon1
CMS80F731x Reference Manual AD Control Register ADCON1 23.6.2 0xDE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON1 ADEN ADCKS2 ADCKS1 ADCKS0 Reset value Bit7 ADEN: ADC enable bit; Enable ADC; ADC is Disabled and does not consume operating current. Bit6~Bit4 ADCKS<2:0>: ADC conversion clock select bits;...
Page 215: Ad Channel Selection Register Adcchs
CMS80F731x Reference Manual AD Channel Selection Register ADCCHS 23.6.4 0xD9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCCHS CHS5 CHS4 CHS3 CHS2 CHS1 CHS0 Reset value Bit7 Reserved, must be 0. Bit5~Bit0 CHS<5:0>: Analog channel selection bits; 000000= AIN0; 010000= AIN16;...
Page 216: Ad Comparator Control Register Adcpc
CMS80F731x Reference Manual AD Comparator Control Register ADCPC 23.6.5 0xD1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCMPC ADCMPPS ADCMPO ADDLY9 ADDLY8 Reset value Bit7 Reserved, must be 0. Bit6 ADCMPPS: ADC comparator output polarity select bit; If ADRES < ADCMP, ADCPO=1; If ADRES >...
Page 217: Ad Data Register High Adresh, Adfm=1 (Right-Aligned)
CMS80F731x Reference Manual AD Data Register High ADRESH, ADFM=1 (Right-aligned) 23.6.9 0xDD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRESH ADRES11 ADRES10 ADRES9 ADRES8 Reset value Bit7~Bit4 Unused. Bit3~Bit0 ADDRESS<11:8>: ADC result register bit. Bits 11-8 of the 12-bit conversion result. 23.6.10 AD Data Register Low ADRSL, ADFM = 1 (Right-aligned) 0xDC Bit7...
Page 218: Ad Reference Voltage Control Register
CMS80F731x Reference Manual 23.6.13 AD Reference Voltage Control Register F692H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCLDO LDOEN VSEL1 VSEL0 Reset value Bit7 LDOEN ADC_LDO enabled; LDO enable, the reference voltage can only select the voltage corresponding to VSEL [1:0];...
Page 219: Adc Interrupt
CMS80F731x Reference Manual 23.7 ADC Interrupt The ADC module allows an interrupt to be generated after the analog-to-digital conversion is complete. The ADC interrupt enable bit is the ADCIE bit in the EIE2 register, and the ADC interrupt flag bit is the ADCIF bit in the EIF2 register. The ADCIF bit must be cleared with software, and the ADCIF bit is set to 1 after each conversion, regardless of whether the ADC interrupt is Enabled.
Page 220: Interrupt Priority Control Register Eip2
CMS80F731x Reference Manual Interrupt Priority Control Register EIP2 23.7.2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...
Page 221: Peripheral Interrupt Flag Bit Register Eif2
CMS80F731x Reference Manual Peripheral Interrupt Flag Bit Register EIF2 23.7.3 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...
Page 222: Touch Module (Touch)
CMS80F731x Reference Manual 24. Touch Module (TOUCH) The touch module is an integrated circuit designed to realize the human touch interface, which can replace the mechanical light touch button to achieve waterproof and dustproof, sealed isolation, strong and beautiful operation interface. Technical parameters: ◆...
Page 223: Flash Memory
CMS80F731x Reference Manual 25. Flash Memory 25.1 Overview Flash memory contains program memory (APROM/BOOT) and nonvolatile data memory (Data FLASH). The maximum memory space of the program is 16KB, divided into 32 sectors, each containing 512B. The maximum data memory space is 1KB, which is divided into 2 sectors, each containing 512B.
Page 224: Related Registers
CMS80F731x Reference Manual 25.2 Related Registers Flash Protect Lock Register MLOCK 25.2.1 0xFB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MLOCK MLOCK7 MOCK6 MLOCK5 MLOCK4 MLOCK3 MLOCK2 MLOCK1 MLOCK0 Reset value Bit7~Bit0 MLOCK<7:0>: memory operation enable bit (this register only supports write operations); AAH= Allows memory-related R/W/E operation;...
Page 225: Program Crc Operation Result Data Register Lower 8-Bit Pcrcdl
CMS80F731x Reference Manual Program CRC Operation Result Data Register Lower 8-bit PCRCDL 25.2.5 0xF9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCRCDL PCRCD<7:0> Reset value Bit7~Bit0 PCRCD<7:0> The program CRC operation results 8 bits lower data Program CRC Operation Result Data Register Higher 8-bit PCRCDH 25.2.6 0xFA Bit7...
Page 226: Feature Description
CMS80F731x Reference Manual 25.3 Feature Description During flash memory read/write/erase operations, the CPU is in a paused state, and when the operation is complete, the CPU continues to run instructions. Flash operation times are as follows: ⚫ Write time approx. 30us (including data detection time before writing, programming time, end processing time) ⚫...
Page 227 CMS80F731x Reference Manual Read the program CRC check result: PCRCDL stores the lower 8 bits CRC operation result of the program; PCRCDH stores the higher 8 bits CRC operation result of the program. Rev. 1.00 www.mcu.com.cn...
Page 228: Unique Id (Uid)
CMS80F731x Reference Manual 26. Unique ID (UID) 26.1 Overview Each chip has a different 96-bit unique identification number, or Unique identification. It has been set at the factory and cannot be modified by the user. 26.2 UID Register Description UID0 F5E0H Bit7 Bit6...
Page 229 CMS80F731x Reference Manual UID4 F5E4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID4 UID39 UID38 UID37 UID36 UID35 UID34 UID33 UID32 Reset value Bit7~Bit0 UID<39:32> UID5 F5E5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID5 UID47 UID46 UID45 UID44 UID43 UID42...
Page 230 CMS80F731x Reference Manual UID9 F5E9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID9 UID79 UID78 UID77 UID76 UID75 UID74 UID73 UID72 Reset value Bit7~Bit0 UID<79:72> UID10（0xF5EA） F5EAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID10 UID87 UID86 UID85 UID84 UID83 UID82...
Page 231: User Configuration
CMS80F731x Reference Manual 27. User Configuration The System Configuration Register (CONFIG) is a FLASH option for the initial conditions of the MCU and cannot be accessed or operated by the program. It contains the following: WDT (Watchdog Working Method Selection) ⚫...
Page 232 CMS80F731x Reference Manual 10. EXT_RESET (external reset configuration) ⚫ DISABLE (default) External reset prohibits ⚫ ENABLE External reset enable An external reset is enabled and the internal pull-up resistor ⚫ ENABLE(OPEN PULLUP) of the reset port is turned on 11. WAKE UP_WAIT TIME (sleep wake-up waits for oscillator to stabilize by default to 1.0s) ⚫...
Page 233: In-Circuit Programming And Debugging
CMS80F731x Reference Manual 28. In-circuit Programming and Debugging 28.1 Online Programming Mode The chip can be programmed serially in the end application circuit. Programming can be done simply by the following 4 wires: ⚫ Power cord ⚫ Ground wire ⚫ Data cable ⚫...
Page 234: Online Debug Mode
CMS80F731x Reference Manual 28.2 Online Debug Mode The chip supports 2-wire (DSCK, DSDA) in-circuit debugging. If you use the in-circuit debugging function, you need to set DEBUG in the system configuration register to ENABLE. When using debug mode, you need to be aware of the following points: ◆...
Page 235: Instruction Description
CMS80F731x Reference Manual 29. Instruction Description Assembly instructions consist of a total of 5 categories: arithmetic operations, logical operations, data transfer operations, Boolean operations, and program branch instructions, all of which are compatible with standard 8051. 29.1 Symbol Description Description Symbol Working registers R0-R 7 The cell address (00H-FFH) of the internal data memory RAM or the address in the special function register SFR...
Page 236: List Of Instructions
CMS80F731x Reference Manual 29.2 List of Instructions Mnemonics description Operation class A,R n Accumulator plus register A,direct Accumulator plus direct addressing unit A,@Rto Accumulator plus indirectly addressed RAM A,#data The accumulator adds the immediate number ADDC A,Rn Accumulator plus registers and carry flags ADDC A,direct Accumulator plus direct addressing unit and carry signs...
Page 237 CMS80F731x Reference Manual Mnemonics description The accumulator is shifted in the left loop The accumulator is even the carry flag for a left loop shift The accumulator is shifted in the right loop RR RC The accumulator is connected to the carry mark right loop shift SWAP The accumulator is swapped 4 bits high and 4 bits low Data transfer class...
Page 238 CMS80F731x Reference Manual Mnemonics description ACALL add r11 Absolute invocation within the 2K address range LCALL addr16 Long calls within 64K address range RAND Subroutine returns RETI Interrupt returns AJMP addr11 Absolute transfer within 2K address range LJMP add r16 Long transfer within 64K address range SJMP randl...
Page 239: Version Revision Notes
CMS80F731x Reference Manual 30. Version Revision Notes The version number Time Revision content V1.00 September 2020 Initial release Rev. 1.00 www.mcu.com.cn...

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