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Cmsemicon CMS8S78 Series Reference Manual

Enhanced flash 8-bit 1t 8051 microcontroller
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CMS8S78xx Reference Manual

CMS8S78xx series

Reference Manual
Enhanced flash 8-bit 1T 8051 microcontroller
Rev. 1.0.8
Please be reminded about following CMS's policies on intellectual property
＊Cmsemicron Limited(denoted as 'our company' for later use) has already applied for relative patents and entitled legal rights. Any patents
related to CMS's MCU or other producrts is not authorized to use. Any individual, organization or company which infringes s our company's
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＊ The name of Cmsemicron Limited and logo are both trademarks of our company.
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However, our company is not responsible for any usage about this munal. The applications and their purposes in this manual are just for
clarification， our company does not guarantee that these applications are feasible without further improvements and changes， and our company
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  • Page 1: Cms8S78Xx Series

    CMS8S78xx Reference Manual CMS8S78xx series Reference Manual Enhanced flash 8-bit 1T 8051 microcontroller Rev. 1.0.8 Please be reminded about following CMS’s policies on intellectual property ＊Cmsemicron Limited(denoted as ‘our company’ for later use) has already applied for relative patents and entitled legal rights. Any patents related to CMS’s MCU or other producrts is not authorized to use.

  • Page 2: Table Of Contents

    CMS8S78xx Reference Manual Table of Content CMS8S78xx series ........................1 1. Central Processing Unit (CPU) ..................11 Reset Vector (0000H) ..............................11 BOOT Partition ................................11 Accumulator (ACC) ..............................13 B Register(B) ................................13 Stack Pointer Register (SP)............................13 Data Pointer Register (DPTR0/DPTR1) ........................13 Data Pointer Selection Register (DPS) ........................
  • Page 3 CMS8S78xx Reference Manual 5.4.6 Example of a Sleep Mode Application ........................42 6. Interrupt ..........................43 Interrupt Overview ............................... 43 External Interrupts ............................... 44 6.2.1 INT0/INT1 Interrupt ..............................44 6.2.2 GPIO Interrupt ................................44 Interrupt With Sleep Wake-up ............................. 44 Interrupt Register ................................. 45 6.4.1 Interrupt Mask Registers ............................45 6.4.2...
  • Page 4 CMS8S78xx Reference Manual 9.3.3 Timer0/1, INT0/1 interrupt flag bit register TCON .....................80 Timer0 Working Mode ..............................81 9.4.1 T0 - Mode 0 (13-bit Timing/Counting Mode) ......................81 9.4.2 T0 - Mode 1 (16-bit Timing/Counting Mode) ......................81 9.4.3 T0 - Mode 2 (8-bit Auto-reload Timing/Counting Mode) ...................82 9.4.4 T0 - Mode 3 (Two Separate 8-bit Timers/Counters) ....................82 Timer1 Working Mode ..............................
  • Page 5 CMS8S78xx Reference Manual 11.4 Timer3 Working Mode ............................... 106 11.4.1 T3 - Mode 0 (13-bit Timing Mode) ..........................106 11.4.2 T3 - Mode 1 (16-bit Timing Mode) ..........................106 11.4.3 T3 - Mode 2 (8-bit Auto Reload Timing Mode)......................107 11.4.4 T3 - Mode 3 (Two Separate 8-bit Timers) .......................107 11.5 Timer4 Working Mode ...............................
  • Page 6 CMS8S78xx Reference Manual 16.5 PWM-related Registers ............................. 130 16.5.1 PWM Control Register PWMCON ..........................130 16.5.2 PWM Output Enable Control Register PWMOE .....................130 16.5.3 PWM0/1 Clock Prescale Control Register PWM01PSC ..................131 16.5.4 PWM2/3 Clock Prescale Control Register PWM23PSC ..................131 16.5.5 PWM Clock Divider Control Register PWMnDIV (n=0-3)..................131 16.5.6 PWM Data Loading Enable Control Register PWMLOADEN .................132 16.5.7 PWM Output Polarity Control Register PWMPINV ....................132 16.5.8 PWM Counter Mode Control Register PWMCNTM ....................132...
  • Page 7 CMS8S78xx Reference Manual 18. LED Driver ........................147 18.1 Overview ................................... 147 18.2 Characteristic ................................147 18.3 Related Registers ..............................147 18.3.1 SEG Port P00-P03 Drive Current Control Register LEDSDRP0L ................147 18.3.2 SEG Port P04-P07 Drive Current Control Register LEDSDRP0H ................147 18.3.3 SEG Port P10-P13 Drive Current Control Register LEDSDRP1L ................148 18.3.4 SEG Port P14-P17 Drive Current Control Register LEDSDRP1H ................148 18.3.5 SEG Port P20-P23 Drive Current Control Register LEDSDRP2L ................148...
  • Page 8 CMS8S78xx Reference Manual 20.4.2 I2C Slave Mode Control and Status Registers I2CSCR/I2CSSR ................174 20.4.3 I2C Slave Mode Transmit and Receive Buffer Registers I2CSBUF ...............175 20.5 I2C Interrupt ................................176 20.5.1 Interrupt Mask Register EIE2 ..........................176 20.5.2 Interrupt Priority Control Register EIP2 ........................177 20.5.3 Peripheral Interrupt Flag Bit Register EIF2......................178 20.6 I2C Slave Mode Transmission Mode .........................
  • Page 9 CMS8S78xx Reference Manual 22.6 Related Registers ..............................199 22.6.1 AD Control Register ADCON0 ..........................199 22.6.2 AD Control Register ADCON1 ..........................200 22.6.3 AD Control Register ADCON2 ..........................200 22.6.4 AD Channel Selection Register ADCCHS ......................201 22.6.5 AD Comparator Control Register ADCPC ......................201 22.6.6 AD Hardware Trigger Delay Data Register ADDLYL ....................202 22.6.7 AD Data Register High ADRESH, ADFM=0 (Left-aligned).
  • Page 10 CMS8S78xx Reference Manual 25.3 Feature Description ..............................220 26. Unique ID (UID) ........................ 220 26.1 Overview ................................... 221 26.2 UID Register Description ............................221 27. User configuration ......................224 28. In-circuit Programming and Debugging ................ 226 28.1 Online Programming Mode............................226 28.2 Online Debug Mode ..............................

  • Page 11: Central Processing Unit (Cpu)

    CMS8S78xx Reference Manual 1. Central Processing Unit (CPU) The series is a microcontroller with 8-bit 8051 frame structure. The CPU is the core component of the microcontroller, which is composed of arithmetic units, controllers, and special register groups. The arithmetic unit module mainly implements data arithmetic and logic operations, bit variable processing and data transfer operations;...
  • Page 12 CMS8S78xx Reference Manual BOOT Control Register (BOOTCON) F691H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BOOTCON Reset value BOOT region control bit (this register can only be written when the chip is configured for Bit7~Bit0 D<7:0>: BOOT_1K/BOOT_2K/BOOT_4K); If you switch from the APROM area to the BOOT area, you need to write 0x55 to it, and then perform 0x55= a software reset or generate a watchdog reset;...

  • Page 13: Accumulator (Acc)

    CMS8S78xx Reference Manual Accumulator (ACC) The ALU is an 8Bit wide arithmetic logic unit through which all mathematical and logical operations of the MCU are completed. It can add, subtract, shift and logical operations on data; The ALU also controls the status bits (in the PSW status register) that represent the state of the result of the operation.

  • Page 14: Data Pointer Selection Register (Dps)

    CMS8S78xx Reference Manual Data Pointer Selection Register (DPS) The data pointer selects register DPS 0x86 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SALT Reset value Bit7~Bit6 ID<1:0>: Subtract/add function selection. DPTR0 plus 1 or DPTR1 plus 1; DPTR0 minus 1 or DPTR1 plus 1; DPTR0 plus 1 or DPTR1 minus 1;...

  • Page 15: Program Counter (Pc)

    CMS8S78xx Reference Manual Program Counter (PC) The program counter (PC) controls the order of instruction execution in the program memory FLASH, it can address the entire flash range, after obtaining the instruction code, the program counter (PC) will automatically add one, pointing to the address of the next instruction code.

  • Page 16: Memory And Register Mapping

    CMS8S78xx Reference Manual 2. Memory and Register Mapping This series of Microcontrollers has the following types of memory: ◆ Flash program memory up to 16KB (shared by APROM and BOOT). ◆ Non-volatile data memory (Data FLASH) up to 1KB. ◆ Up to 256B of General Purpose Internal Data Memory (RAM).

  • Page 17: Non-Volatile Data Memory Data Flash

    CMS8S78xx Reference Manual Non-volatile Data Memory Data FLASH The non-volatile data memory Data Flash can be used to store important data such as constant data, calibration data, protection safety-related information, etc. The data stored in this area has the characteristic that the data is not lost in the event of a chip power outage or a sudden or unexpected power outage.
  • Page 18 CMS8S78xx Reference Manual The high 128 Bytes shown above and SFR occupy the same area (80H to FFH), but they are independent. Storage spaces with direct addressing above 7FH (SFR) and indirect addressing above 7FH (128 Bytes high) go into different storage spaces. The low 128Bytes spatial register allocation shown in the figure above is shown in the following figure.

  • Page 19: General External Data Register Xram

    CMS8S78xx Reference Manual General External Data Register XRAM There is a maximum 1KB XRAM area inside the chip, this area is not connected to FLASH/RAM, and the XRAM space allocation block diagram is shown in the following figure: 03FFH XRAM (Indirect Addressing Mode) 0000H...

  • Page 20: Special Function Register Sfr

    CMS8S78xx Reference Manual Special Function Register SFR Special function registers refer to a collection of registers with special purposes, essentially some on-chip RAM units with special functions, discretely distributed in the address range of 80H to FFH. Users can byte access them through direct addressing instructions, and addresses four bits lower than 0000 or 1000 can be addressed bitwise, such as P0, TCON, P1.

  • Page 21: External Special Function Register Xsfr

    CMS8S78xx Reference Manual External Special Function Register XSFR XSFR is a special register shared by the addressing space and XRAM, mainly including: port control registers, other function control registers. Its addressing range is shown in the following figure: FFFFH XSFR region: 4K F000H EFFFH Reserved space...
  • Page 22 CMS8S78xx Reference Manual F01DH P1SR P1 port slope control register F01EH P1DS Port P1 data input select register F020H P20CFG P20 port configuration register F021H P21CFG P21 port configuration register F022H P22CFG P22 port configuration register F023H P23CFG P23 port configuration register F024H P24CFG P24 port configuration register...
  • Page 23 CMS8S78xx Reference Manual F08FH P17EICFG P17 interrupt control register F090H P20EICFG P20 port interrupt control register F091H P21EICFG P21 interrupt control register F092H P22EICFG P22 port interrupt control register F093H P23EICFG P23 interrupt control register F094H P24EICFG P24 interrupt control register F095H P25EICFG P25 interrupt control register...
  • Page 24 CMS8S78xx Reference Manual F12CH PWM2DIV PWM2 clock divider control register F12DH PWM3DIV PWM3 clock divider control register F130H PWMP0L The PWM0 cycle data register is 8 bits lower F131H PWMP0H The PWM0 cycle data register is 8 bits high F132H PWMP1L The PWM1 cycle data register is 8 bits lower F133H...
  • Page 25 CMS8S78xx Reference Manual F16CH PWMPIF PWM cycle interrupt flag register F16DH PWMZIF PWM zero-point interrupt flag register F16EH PWMUIF PWM up compares the interrupt flag registers F16FH PWMDIF PWM compares the interrupt flag registers downwards F500H C0CON0 Comparator 0 control register 0 F501H C0CON1 Comparator 0 control register 1...
  • Page 26 CMS8S78xx Reference Manual F693H TS_REG Temperature sensor register F694H LSECRL The LSE timer data register is 8 bits lower F695H LSECRH The LSE timer data register is 8 bits high F696H LSECON LSE timer control registers F697H XT_SCM LSE/HSE clock stop detection control register F698H PS_SCLK The SPI clock input port assigns registers...

  • Page 27: Reset

    CMS8S78xx Reference Manual 3. Reset Reset Time refers to the time from the time the chip resets to the time when the chip starts executing instructions, and its default design value is about 16ms. This time includes oscillator start time, configuration time. This reset time will exist whether the chip is powered on reset or otherwise caused by a reset.
  • Page 28 CMS8S78xx Reference Manual = 1.8 V POR TIME = 16ms nPOR (Internal Signal) configuration effective CPU WORK RESETB (Internal Signal) Oscillation (CLK) Whether the system is power-on reset can be determined by the PORF (WDCON.6) flag bit. The types of resets that can be placed with a PORF flag of 1 are: power-on reset, LVR low voltage reset, power-on configuration monitoring reset, external reset, CONFIG status protection reset.

  • Page 29: External Reset

    CMS8S78xx Reference Manual External Reset External reset refers to a reset signal from an external port (NRST) that resets the chip after being input by a Schmitt trigger. If the NRST pin remains low above about 16us (internal LSI clock sampled with 3 rising edges) during operating voltage range and stable oscillation, a reset is requested.

  • Page 30: Watchdog Reset

    CMS8S78xx Reference Manual Watchdog Reset Watchdog reset is a protective setting of the system. In normal condition, the watchdog timer is cleared to zero by the program. If an error occurs, the system is in an unknown state, the watchdog timer overflows, and the system resets. After the watchdog is reset, the system reboots into a normal state.

  • Page 31: Power-On Configuration Monitor Reset

    CMS8S78xx Reference Manual Power-on Configuration Monitor Reset In the power-on configuration process, there is a configuration monitoring circuit inside the chip, if the power-on configuration time is too long, or the power-on configuration into a certain state can not be reconfigured, the internal monitoring circuit from the configuration to start timing, if more than the setting time, the monitoring circuit reset configuration module, so that the configuration module reconfiguration process.

  • Page 32: Clock Structure

    CMS8S78xx Reference Manual 4. Clock Structure There are four types of clock sources for system clocks, and clock source and clock divider can be selected by setting the system configuration register or user register. The system clock sources are as follows: ◆...

  • Page 33: Related Registers

    CMS8S78xx Reference Manual Related Registers 4.2.1 Oscillator Control Register CLKDIV 0x8F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKDIV CLKDIV7 CLKDIV6 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0 Reset value Bit7~Bit0 System clock Fsys divider; CLKDIV<7:0>: 00H= Fsys=Fsys_pre; Other = Fsys=Fsys_pre/（2*CLKDIV）（2,4...

  • Page 34: System Clock Status Register Sckstau

    CMS8S78xx Reference Manual 4.2.3 System Clock Status Register SCKSTAU 0xD7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCKSTAU LSI_F LSE_F HSE_F HSI_F Reset value Bit7 LSI_F: Low-speed internal steady-state bit; Stability; Not stable. Bit6 LSE_F: Steady state bit of low-speed external crystal; Stability;...

  • Page 35: System Clock Monitor Register Scm

    CMS8S78xx Reference Manual 4.2.4 System Clock Monitor Register SCM Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 F697H XT_SCM SCMEN SCMIE SCMIF SCMSTA Reset value Bit7 SCMEN: Oscillation stop detection module enable; Enable; Disable. Bit6 Stop detects interrupt enable bits (the interrupt and LSE timer interrupt share an interrupt SCMIE: entry);...

  • Page 36: Function Clock Control Registers

    CMS8S78xx Reference Manual 4.2.5 Function Clock Control Registers Watchdog overflow time/timer clock source selection register CKCON 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON WTS2 WTS1 WTS0 Reset value Bit7~Bit5 WTS<2:0>: WDT overflow time selection bits; 000= *Tsys; 001= *Tsys;...

  • Page 37: System Clock Switching

    CMS8S78xx Reference Manual System clock switching The system clock switching steps are shown in the following figure: Start Chip Power On Chip Fsys is determined by config configuration Configuration completes Clock configuration Write SCKSEL[4]=1 selection No SCKSEL[4]=1 Clock source write SCKSEL[2:0] to select system selection clock source whether clock source...

  • Page 38: System Clock Monitoring

    CMS8S78xx Reference Manual System Clock Monitoring System Clock Monitoring (SCM: system clock monitoring) is a monitoring and protection circuit designed to prevent the failure of the system due to crystal oscillation suspension. When using HSE/LSE as the system clock, once the HSE/LSE clock stops, the system will force the HSI clock source to start, and after the HSI is stabilized, the system will run at 8MHz main frequency, and then if the HSE/LSE clock is restored and stable, the system clock will automatically switch back from the HSI back to HSE/LSE.

  • Page 39: Power Management

    CMS8S78xx Reference Manual 5. Power Management Low-power modes fall into 2 categories: ◆ IDLE: Idle mode ◆ STOP: Sleep mode When users use C language for program development, it is strongly recommended to use IDLE and STOP macros to control the system mode, and do not directly set THE IDLE and STOP bits. The macros are as follows: Enter idle mode: IDLE();...

  • Page 40: Power Supply Monitor Register Lvdcon

    CMS8S78xx Reference Manual Power Supply Monitor Register LVDCON The MCU comes with a power supply detection function. If the LVD module enable (LVDEN=1) is set and the voltage monitoring point LVDSEL is set, when the power supply voltage drops below the LVD setpoint, an interrupt will be generated to alert the user.

  • Page 41: Stop Sleep Mode

    CMS8S78xx Reference Manual STOP Sleep Mode In this mode, all circuits except the LVD module and LSE module are shut down (the LVD/LSE module must be closed by software), the system is in a low-power mode, and the digital circuits are not working. 5.4.1 Sleep Wakes up After entering the sleep mode, you can turn on the sleep wake function (SWE=1...

  • Page 42: Reset Operation Under Sleep

    CMS8S78xx Reference Manual 5.4.4 Reset Operation Under Sleep In sleep mode, the system can also be restarted by power-down reset or external reset, independent of the value of SWE, even if SWE=0 can also restart the system by the above reset operation. Power-down reset: No other conditions are required, VDD is reduced to 0V and then powered back on to the working voltage and enters the power-on reset state.

  • Page 43: Interrupt

    CMS8S78xx Reference Manual 6. Interrupt Interrupt Overview The chip has 20 interrupt sources and interrupt vectors: Interrupt source Interrupt description Interrupt vector Sibling priority sequence INT0 External interrupt 0 0-0x0003 Timer0 Timer 0 interrupt 1-0x000B INT1 External interrupt 1 2-0x0013 Timer1 Timer 1 interrupt 3-0x001B...

  • Page 44: External Interrupts

    CMS8S78xx Reference Manual External Interrupts 6.2.1 INT0/INT1 Interrupt The chip supports the 8051 native INT0, INT1 external interrupt, INT0/INT1 can choose to falling edge or low level trigger interrupt, the relevant control register is TCON. INT0 and INT1 occupy two interrupt vectors. 6.2.2 GPIO Interrupt Each GPIO pin of the chip supports an external interrupt and can support falling/rising/dual edge interrupts, with the edge...

  • Page 45: Interrupt Register

    CMS8S78xx Reference Manual Interrupt Register 6.4.1 Interrupt Mask Registers 6.4.1.1 Interrupt Mask Register IE Interrupt mask register IE is a read-write register that can be operated bitwise. When an interrupt condition arises, the interrupt flag bit will be set to 1 regardless of the state of the corresponding interrupt enable bit or the global enable bit EA. The user software should ensure that the corresponding interrupt flag bits are cleared to zero before enabling an interrupt.
  • Page 46 CMS8S78xx Reference Manual 6.4.1.2 Interrupt Mask Register EIE2 0xAA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIE2 SPIIE I2CIE WDTIE ADCIE PWMIE Reset value Bit7 SPIIE: SPI interrupt enable bit; Enable SPI interrupts; Disable SPI Interrupt. Bit6 I2CIE: I2C Interrupt enable bit; Enabl I2C nterrupts;...
  • Page 47 CMS8S78xx Reference Manual 6.4.1.3 Timer2 Interrupt Mask Register T2IE 0xCF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IE T2OVIE T2EXIE T2C3IE T2C2IE T2C1IE T2C0IE Reset value Bit7 T2OVIE: Timer2 overflow interrupt enable bits; Interrupts enabled; Disable Interrupt. Bit6 T2EXIE: Timer2 external loading interrupt enable bits;...
  • Page 48 CMS8S78xx Reference Manual 6.4.1.6 P2 Interrupt Control Register P2EXTIE 0xAE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P2EXTIE P25IE P24IE P23IE P22IE P21IE P20IE Reset value Bit7~Bit6 Reserved, must be 0. Bit5~Bit0 P2iIE: P2i port interrupt Enable bits (i=0-5); Interrupts enabled;...

  • Page 49: Interrupt Priority Controls The Register

    CMS8S78xx Reference Manual 6.4.2 Interrupt Priority Controls the Register 6.4.2.1 Interrupt Priority Control Register IP Interrupt priority control register IP is a read-write register that can be operated bitwise. 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7~Bit6 Reserved, must be 0.
  • Page 50 CMS8S78xx Reference Manual 6.4.2.2 Interrupt Priority Control Register EIP1 0xB9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP1 PACMP Reset value Bit7 PACMP: Analog comparator interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6~Bit4 Reserved, must be 0. Bit3 PP3: P3 port interrupt priority control bit;...
  • Page 51 CMS8S78xx Reference Manual Bit0 PT3: TIMER3 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. 6.4.2.4 Interrupt Priority Control Register EIP3 0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP3 PLVD PLSE Reset value Bit7~Bit4 Reserved, all must be 0. Bit3 PLVD: LVD interrupt priority control bit;...

  • Page 52: Interrupt Flag Bit Register

    CMS8S78xx Reference Manual 6.4.3 Interrupt Flag Bit Register 6.4.3.1 Timer0/1, INT0/1 Interrupt Flag Bit Register TCON 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; Timer1 counter overflow, when entering the interrupt service program, the hardware is automatically cleared, and the software can also be cleared;...
  • Page 53 CMS8S78xx Reference Manual 6.4.3.2 Timer2 Interrupt Flag Bit Register T2IF 0xC9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IF T2EXIF T2C3IF T2C2IF T2C1IF T2C0IF Reset value Bit7 TF2: Timer2 counter overflow interrupt flag bit; Timer2 counter overflow, software zeroing is required; The Timer2 counter has no overflow.
  • Page 54 CMS8S78xx Reference Manual 6.4.3.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...
  • Page 55 CMS8S78xx Reference Manual 6.4.3.5 I2C Master Mode Interrupt Flag Registers I2CMCR/I2CMSR 0xF5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I2CMCR RSTS STOP START I2CMSR I2CMIF BUS_BUSY IDLE ARB_LOST DATA_ACK ADDR_ACK ERROR BUSY Reset value Bit7 RSTS: I2C master module reset control bit; Reset the master module (I2C registers for the entire master module, including I2CMSR);...
  • Page 56 CMS8S78xx Reference Manual 6.4.3.7 UART Control Register SCON0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON0 U0SM0 U0SM1 U0SM2 U0REN U0TB8 U0RB8 Reset value BANK0: Register SCON0 address 0x98. Bit7~Bit2 U0SM0、 U0SM1, U0SM2, U0REN, U0TB8, U0RB8: See the UART0 function description for details Bit1 Tl0: Send interrupt flag bits (requires software zeroing);...
  • Page 57 CMS8S78xx Reference Manual 6.4.3.10 P2 Port Interrupt Flag Bit Register P2EXTIF 0xB6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P2EXTIF P25IF P24IF P23IF P22IF P21IF P20IF Reset value Bit7~Bit6 Reserved, must be 0. Bit5~Bit0 P2iIF: P2i interrupt flag bit (i=0-7); P2i port produces an interrupt, which requires software clearance;...

  • Page 58: The Clear Operation For The Interrupt Flag Bit

    CMS8S78xx Reference Manual 6.4.4 The clear operation for the interrupt flag bit The clear operation of the interrupt flag is divided into the following categories: ◆ Automatic hardware cleanup (requires entry into interrupt service) ◆ Software cleanup ◆ Read/write operations are cleared The hardware automatically clears the flag bits The bits that support hardware auto-clearing are the interrupt flag bits generated by IN0, INT1, T0, T1, T3, and T4.

  • Page 59: Special Interrupt Flag Bits In Debug Mode

    CMS8S78xx Reference Manual 6.4.5 Special Interrupt Flag Bits in Debug Mode The flag bit in the system is not written to zero to the flag bit, but requires reading/writing other registers to clear the flag bit. In debug mode, after breakpoint execution, step-through, or stop operation, the emulator reads out all register values from the system to the emulation software, and the emulator reads/writes exactly the same as in normal mode.

  • Page 60: I/O Port

    CMS8S78xx Reference Manual 7. I/O Port GPIO Function The chip has four sets of I/O ports: PORT0, PORT1, PORT2, PORT3. PORTx is a bidirectional port. Its corresponding data direction register is PxTRIS. A bit set to (=1) of the PxTRIS allows the corresponding pin to be configured as an output.

  • Page 61: Portx Open-Drain Control Register Pxod

    CMS8S78xx Reference Manual 7.1.3 PORTx Open-drain Control Register PxOD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxOD PxOD7 PxOD6 PxOD5 PxOD4 PxOD3 PxOD2 PxOD1 PxOD0 Reset value Register P0OD Address: F009H; Register P1OD address: F019H; Register P2OD address: F029H; Register P3OD address: F039H.

  • Page 62: Portx Slope Control Register Pxsr

    CMS8S78xx Reference Manual 7.1.6 PORTx Slope Control Register PxSR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxSR PxSR7 PxSR6 PxSR5 PxSR4 PxSR3 PxSR2 PxSR1 PxSR0 Reset value Register P0SR Address: F00DH; Register P1SR Address: F01DH; Register P2SR Address: F02DH; Register P3SR address: F03DH.

  • Page 63: Multiplexed Functions

    CMS8S78xx Reference Manual Multiplexed Functions 7.2.1 Port multiplexing feature table Pins are shared in a variety of functions, and each I/O port can be flexibly configured with digital functions or specified analog functions. The digital function of the external input is selected by the port input function allocation register (PS_XX); The multiplexing function is selected by the port multiplexing function configuration register (PxnCFG), where the communication input function is also specified by the communication input function allocation register (PS_XX).
  • Page 64 CMS8S78xx Reference Manual The analog module, CONFIG configuration ports are shown in the following table: ANA(1) CONFIG LCDSEG LCDCOM ACMP SEG0 COM0 C1P2 SEG21 COM21 SEG22 COM22 SEG1 COM1 SEG23 COM23 SEG2 COM2 C1P3 SEG3 COM3 SEG4 COM4 C0P0 AN10 SEG5 COM5 AN11...

  • Page 65: Port Multiplexing Feature Configuration Register

    CMS8S78xx Reference Manual 7.2.2 Port Multiplexing Feature Configuration Register The PORTx function configuration register PxnCFG Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxnCFG PxnCFG2 PxnCFG1 PxnCFG0 Reset value Bit7~Bit3 Reserved, must be 0. PxnCFG< 2:0>: Bit2~Bit0 Feature configuration bit, which defaults to GPIO function. For details, see port function configuration instructions;...
  • Page 66 CMS8S78xx Reference Manual The Timer2 input captures the channel 2 port assignment PS_CAP2 F0CAH CAP2 register The Timer2 input captures the channel 3 port assignment PS_CAP3 F0CBH CAP3 register PS_ADET F0CCH The ADC's external trigger input port allocates registers CUSTOM PS_FB0 F0CDH PWM external brake signal FB0...

  • Page 67: Communication Input Function Allocation Registers

    CMS8S78xx Reference Manual 7.2.4 Communication Input Function Allocation Registers When the port is used as a communication port (UART0/SPI/IIC), multiple input ports are selectable, and different port inputs can be selected by setting the following registers. The communication input function port assignment registers are as follows: register address...

  • Page 68: Port External Interrupt Control Registers

    CMS8S78xx Reference Manual 7.2.5 Port external interrupt control registers When using an external interrupt, the port needs to be configured as GPIO function and the direction is set to the input port. Alternatively, the multiplexing function is the input port (such as RXD0), each port can be configured as a GPIO interrupt function.

  • Page 69: Multiplexing Features Application Notes

    CMS8S78xx Reference Manual 7.2.6 Multiplexing Features Application Notes The multiplexing function configuration register is configured as an analog function by default (0x01), and if the digital function is used, the value of the register needs to be set to 0x00. The input of the multiplexing function is relatively independent of the structure of the port's external interrupt (GPIO interrupt) and port input function.

  • Page 70: Watchdog Timer (Wdt)

    CMS8S78xx Reference Manual 8. Watchdog Timer (WDT) Overview The Watch Dog Timer is an on-chip timer with configurable overflow time and clock source provided by the system clock Fsys. When the watchdog timer counts to the configured overflow value, a watchdog overflow interrupt flag bit (WDTIF=1) is generated.

  • Page 71: Watchdog Overflow Control Register Ckcon

    CMS8S78xx Reference Manual Note: If the WDT in CONFIG is configured as: ENABLE, the WDT is always enabled, regardless of the state of the WDTRE control bit. And the overflow reset function of WDT is forced on. If WDT in CONFIG is configured as : SOFTWARE CONTROL , WDTRE can be enabled or disabled using the WDTRE control bit.

  • Page 72: Wdt Interrupt

    CMS8S78xx Reference Manual WDT Interrupt The watchdog timer can enable or disable interrupts via the EIE2 register, and the high/low priority is set through the EIP2 register, where the relevant bits are as follows. 8.3.1 Interrupt Mask Register EIE2 0xAA Bit7 Bit6 Bit5...

  • Page 73: Interrupt Priority Control Register Eip2

    CMS8S78xx Reference Manual 8.3.2 Interrupt priority control register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C Interrupt priority control bit;...

  • Page 74: Timer Counter 0/1 (Timer0/1)

    CMS8S78xx Reference Manual 9. Timer Counter 0/1 (Timer0/1) Timer 0 is similar in type and structure to Timer 1 and is two 16-bit timers. Timer 1 has three modes of operation and Timer 0 has four modes of operation. They provide basic timing and event counting operations. In "timer mode", the timing register is incremented every 12 or 4 system cycles when the timer clock is enabled.

  • Page 75: Related Registers

    CMS8S78xx Reference Manual Related Registers 9.2.1 Timer0/1 mode register TMOD 0x89 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMOD GATE1 T1M1 T1M0 GATE0 T0M1 T0M0 Reset value Bit7 GATE1: Timer 1 gate control bit; Enable; Disable. Bit6 CT1: Timer 1 timing/count select bits; Count;...

  • Page 76: Timer0/1 Control Register Tcon

    CMS8S78xx Reference Manual 9.2.2 Timer0/1 control register TCON 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; The Timer1 counter overflows and enters the interrupt service program hardware to automatically zero;...

  • Page 77: Timer0 Data Register High Bit Th0

    CMS8S78xx Reference Manual 9.2.4 Timer0 data register high bit TH0 0x8C Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TH07 TH06 TH05 TH04 TH03 TH02 TH01 TH00 Reset value Bit7~Bit0 TH0<7:0>: Timer 0 high bit data register (also as counter high bit). 9.2.5 Timer1 data register low bit TL1 0x8B...

  • Page 78: Timer0/1 Interrupt

    CMS8S78xx Reference Manual Timer0/1 Interrupt Timer0/1 can enable or disable interrupts via the IE register, and can also set high/low priority via the IP register, where the relevant bits are described as following: 9.3.1 Interrupt Mask register IE 0xA8 Bit7 Bit6 Bit5 Bit4...

  • Page 79: Interrupt Priority Control Register Ip

    CMS8S78xx Reference Manual 9.3.2 Interrupt priority control register IP 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0. Bit6 Reserved, must be 0. Bit5 PT2: TIMER2 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt.

  • Page 80: Timer0/1, Int0/1 Interrupt Flag Bit Register Tcon

    CMS8S78xx Reference Manual 9.3.3 Timer0/1, INT0/1 interrupt flag bit register TCON 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; Timer1 counter overflow, when entering the interrupt service program, the hardware is automatically cleared, and the software can also be cleared;...

  • Page 81: Timer0 Working Mode

    CMS8S78xx Reference Manual Timer0 Working Mode 9.4.1 T0 - Mode 0 (13-bit Timing/Counting Mode) In this mode, timer 0 is a 13-bit register. When all the bits of the counter are flipped from 1 to 0, the timer 0 interrupt flag TF0 is set to 1.

  • Page 82: T0 - Mode 2 (8-Bit Auto-Reload Timing/Counting Mode)

    CMS8S78xx Reference Manual 9.4.3 T0 - Mode 2 (8-bit Auto-reload Timing/Counting Mode) The mode 2 timer register is an 8-bit counter (TL0) with auto reload mode, as shown in the figure below. The overflow from TL0 not only sets TF0 to 1, but also reloads the contents of TH0 from software to TL0. The value of TH0 remains unchanged during Reloading.

  • Page 83: Timer1 Working Mode

    CMS8S78xx Reference Manual Timer1 Working Mode 9.5.1 T1 - Mode 0 (13-bit Timing/Counting Mode) In this mode, timer 1 is a 13-bit register. When all the bits of the counter are flipped from 1 to 0, the timer 1 interrupt flag TF1 is set to 1.

  • Page 84: T1 - Mode 2 (8-Bit Auto Reload Timing/Counting Mode)

    CMS8S78xx Reference Manual 9.5.3 T1 - Mode 2 (8-bit Auto Reload Timing/Counting Mode) The timer 1 register in mode 2 is an 8-bit counter (TL1) with auto-reload mode, as shown in the figure below. The overflow from TL1 not only makes TF1 1, but also reloads the contents of TH1 from software to TL1. The value of TH1 remains unchanged during Reloading.

  • Page 85: Timer Counter 2 (Timer2)

    CMS8S78xx Reference Manual 10. Timer Counter 2 (Timer2) Timer 2 with additional compare/capture/reload functionality is one of the core peripheral units. It can be used for the generation of various digital signals and event capture, such as pulse generation, pulse width modulation, pulse width measurement, etc.

  • Page 86: Related Registers

    CMS8S78xx Reference Manual 10.2 Related Registers 10.2.1 Timer2 Control Register T2CON 0xC8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2CON T2PS I3FR CAPES T2R1 T2R0 T2CM T2I1 T2I0 Reset value Bit7 T2PS: Timer2 clock prescaler selection bit; Fsys/24; Fsys/12。 Bit6 I3FR: Capture channel 0 input one-edge selection with comparison interrupt moment...

  • Page 87: Timer2 Data Register High Bit Th2

    CMS8S78xx Reference Manual 10.2.3 Timer2 Data Register High Bit TH2 0xCD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TH27 TH26 TH25 TH24 TH23 TH22 TH21 TH20 Reset value Bit7~Bit0 TH2<7:0>: Timer 2 high-bit data register (also as counter low). 10.2.4 Timer2 Compare/Capture/Auto Reload Register Low Bit RLDL 0xCA...

  • Page 88: Timer2 Compares/Captures Channel 2 Register Low-Bit Ccl2

    CMS8S78xx Reference Manual 10.2.8 Timer2 Compares/Captures Channel 2 Register Low-bit CCL2 0xC4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CCL2 CCL27 CCL26 CCL25 CCL24 CCL23 CCL22 CCL21 CCL20 Reset value Bit7~Bit0 CCL2<7:0>: Timer 2 compares/captures channel 2 registers low. 10.2.9 Timer2 Compares/Captures Channel 2 Register High-bit CCH2 0xC5...

  • Page 89: Timer2 Compares The Capture Control Register Ccen

    CMS8S78xx Reference Manual 10.2.12 Timer2 Compares the Capture Control Register CCEN 0xCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CCEN CMH3 CML3 CMH2 CML2 CMH1 CML1 CMH0 CML0 Reset value Bit7~Bit6 CMH3-CML3: Capture/Compare Mode Control Bits; Capture/Compare Disabled; The capture operation is triggered on the rising or falling edge of channel 3 (CAPES selection);...

  • Page 90: Timer2 Interrupts

    CMS8S78xx Reference Manual 10.3 Timer2 Interrupts Timer 2 can be enabled or disabled by , and high/low priority can also be set via IP registers. Timer2 has 4 register IE interrupt types: ◆ A timed overflow interrupt. ◆ The external pin T2EX drops along the interrupt. ◆...
  • Page 91 CMS8S78xx Reference Manual 10.3.1.2 Timer2 Interrupt Mask Register T2IE 0xCF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IE T2OVIE T2EXIE T2C3IE T2C2IE T2C1IE T2C0IE Reset value Bit7 T2OVIE: Timer2 overflow interrupt enable bits; Interrupts enabled; Disable Interrupt. Bit6 T2EXIE: Timer2 external loading interrupt enable bits;...
  • Page 92 CMS8S78xx Reference Manual 10.3.1.3 Interrupt Priority Control Register IP 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0. Bit6 Reserved, must be 0. Bit5 PT2: TIMER2 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt.

  • Page 93: Timer Interrupts

    CMS8S78xx Reference Manual 10.3.1.4 Timer2 Interrupt Flag Bit Register T2IF 0xC9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IF T2EXIF T2C3IF T2C2IF T2C1IF T2C0IF Reset value Bit7 TF2: Timer2 counter overflow interrupt flag bit; Timer2 counter overflow, software zeroing is required; The Timer2 counter has no overflow.

  • Page 94: Compare Interrupts

    CMS8S78xx Reference Manual 10.3.4 Compare Interrupts All four comparison channels support comparison interrupts. The comparison interrupt enable bit is set by register T2IE[3:0] and the interrupt flag bit is viewed by register T2IF[3:0]. Comparing channel 0 can choose to compare the moment when the interrupt occurred, and if an interrupt is generated, the interrupt flag T2C0IF of the comparison channel 0 is set to 1.

  • Page 95: Timer2 Feature Description

    CMS8S78xx Reference Manual 10.4 Timer2 Feature Description Timer 2 is a 16-bit up counting timer with a clock source from the system clock. Timer2 can be configured with the following functional modes: ◆ Timing mode. ◆ Reload mode. ◆ Gating timing mode. ◆...

  • Page 96: Gated Timing Mode

    CMS8S78xx Reference Manual 10.4.3 Gated Timing Mode When Timer2 is used as a gated timer function, the external input pin T2 acts as the gated input to timer 2. If the T2 pin is high, the internal clock input is gated to the timer. A low T2 pin terminates the counting. This function is often used to measure pulse width.
  • Page 97 CMS8S78xx Reference Manual 10.4.5.1 Compare Mode 0 In mode 0, when the timer's count value and the comparison register are equal, the comparison output signal changes from low to high. When the timer count value overflows, the comparison output signal goes low. The comparison output channel is directly controlled by two events: the timer overflow and the comparison operation.
  • Page 98 CMS8S78xx Reference Manual 10.4.5.2 Comparison Mode 1 In comparison mode 1, it is typically used where the output signal is independent of a constant signal cycle, where the software adaptively determines the output signal transition. If mode 1 is enabled, the software writes to the corresponding output register of the CCx port, and the new value does not appear on the output pin until the next comparison match occurs.

  • Page 99: Capture Mode 0

    CMS8S78xx Reference Manual 10.4.6 Capture Mode Each of the four 16-bit registers {RLDH,RLDL}, {CCH1,CCL1}, {CCH2,CCL2}, {CCH3,CCL3} can be used to latch the current 16-bit value of {TH2,TL2}. This feature provides two different capture modes. In mode 0, an external event can latch the contents of timer 2 into the capture register. In mode 1, the capture operation occurs when a low-bit byte (RLDL/CCL1/CCL2/CCL3) is written to the 16-bit capture register.
  • Page 100 CMS8S78xx Reference Manual 10.4.6.2 Capture Mode 1 In capture mode 1, the capture operation event is the execution of a write byte instruction to the capture register. A write register signal, such as a write RLDL, initiates a capture operation, and the value written is independent of this function. After the write instruction is executed, the contents of timer 2 are latched into the corresponding capture register.

  • Page 101: Timer 3/4 (Timer3/4)

    CMS8S78xx Reference Manual 11. Timer 3/4 (Timer3/4) Timer 3/4 is similar to timer 0/1 in that it is two 16-bit timers. Timer 3 has four modes of operation and Timer 4 has three modes of operation. In contrast to Timer0/1, Timer3/4 only provides timer operations. With the timer activated, the value of the register is incremented every 12 or 4 system cycles.

  • Page 102: Timer3 Data Register Low Bit Tl3

    CMS8S78xx Reference Manual 11.2.2 Timer3 data register low bit TL3 0xDA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL37 TL36 TL35 TL34 TL33 TL32 TL31 TL30 Reset value Bit7~Bit0 TL3<7:0>: Timer 3 low bit data register (while acting as timer low bit). 11.2.3 Timer3 data register high bit TH3 0xDB...

  • Page 103: Timer3/4 Interrupt

    CMS8S78xx Reference Manual 11.3 Timer3/4 Interrupt Timer 3/4 can enable or disable interrupts via the EIE2 register, and high/low priority can also be set via the EIP2 register, where the relevant bits are described as following: 11.3.1 Interrupt mask register EIE2 0xAA Bit7 Bit6...

  • Page 104: Interrupt Priority Control Register Eip2

    CMS8S78xx Reference Manual 11.3.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C Interrupt priority control bit;...

  • Page 105: Peripheral Interrupt Flag Bit Register Eif2

    CMS8S78xx Reference Manual 11.3.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...

  • Page 106: Timer3 Working Mode

    CMS8S78xx Reference Manual 11.4 Timer3 Working Mode 11.4.1 T3 - Mode 0 (13-bit Timing Mode) In this mode, timer 3 is a 13-bit register. When all the bits of the timer are flipped from 1 to 0, the timer 3 interrupt flag TF3 is set to 1.

  • Page 107: T3 - Mode 2 (8-Bit Auto Reload Timing Mode)

    CMS8S78xx Reference Manual 11.4.3 T3 - Mode 2 (8-bit Auto Reload Timing Mode) The timer 3 register in mode 2 is an 8-bit timer (TL3) with auto reload mode, as shown in the figure below. The overflow from TL3 not only puts TF3 at 1, but also reloads the contents of TH3 from software to TL3. The value of TH3 remains unchanged during Reloading.

  • Page 108: Timer4 Working Mode

    CMS8S78xx Reference Manual 11.5 Timer4 Working Mode 11.5.1 T4 - Mode 0 (13-bit Timing Mode) In this mode, timer 4 is a 13-bit register. When all the bits of the timer are flipped from 1 to 0, the timer 4 interrupt flag TF4 is set to 1.

  • Page 109: T4- Mode 2 (8-Bit Auto Reload Timing Mode)

    CMS8S78xx Reference Manual 11.5.3 T4- Mode 2 (8-bit auto Reload Timing Mode) The timer 4 register in mode 2 is an 8-bit timer , as shown in the figure below. The overflow (TL4) with an auto-reload mode from TL4 not only makes TF4 1, but also reloads the contents of TH4 from software to TL4. The value of TH4 remains unchanged during Reloading.

  • Page 110: Lse Timer(Lse_Timer)

    CMS8S78xx Reference Manual 12. LSE Timer(LSE_Timer) 12.1 Overview The LSE timer is a clock source from an external low-speed clock LSE, a 16-bit up-counting timer. When using the LSE timer function, you should first set the LSE module to enable, wait for the LSE clock to stabilize (about 1.5s), and then set the LSE count enable.

  • Page 111: Lse Timer Control Register Lsecon

    CMS8S78xx Reference Manual 12.2.3 LSE Timer Control Register LSECON F696H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LSECON LSEEN LSEWUEN LSECNTEN LSESTA LSEIE LSEIF Reset value Bit7 LSEEN: LSE module enable control; Enable; Disable. Bit6 LSEWUEN: LSE timer wake-up enable control; Enable;...

  • Page 112: Interrupt With Sleep Wake-Up

    CMS8S78xx Reference Manual 12.3 Interrupt With Sleep Wake-up The LSE timer can enable or disable interrupts via LSECON registers, setting high/low priority via EIP3 registers, where the relevant bits are described as following. 0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP3...

  • Page 113: Wake-Up Timer (Wut)

    CMS8S78xx Reference Manual 13. Wake-up Timer (WUT) 13.1 Overview Wake Up Timer is a clock source from the internal low-speed clock LSI, a 12-bit, up-counting timer for sleep wake-up, after the timer count and the configured 12-bit count value are equal, the timing overflow state bit set to 1 which can be cleared to 0 by software.

  • Page 114: Feature Description

    CMS8S78xx Reference Manual 13.3 Feature Description The internal wake-up timer works on the principle that after the system enters sleep mode, the CPU stops working with all ≈ 8us). peripheral circuitry, and the internal low-power oscillator LSI begins to operate, and its oscillation clock is 125KHz (T Provides a clock for the WUT counter.

  • Page 115: Baud Rate Timer (Brt)

    CMS8S78xx Reference Manual 14. Baud Rate Timer (BRT) 14.1 Overview The chip has a 16-bit baud rate timer BRT, which mainly provides a clock for the UART module. 14.2 Related Registers 14.2.1 BRT Module Control Register BRTCon F5C0H Bit7 Bit6 Bit5 Bit4 Bit3...

  • Page 116: Feature Description

    CMS8S78xx Reference Manual 14.3 Feature Description The BRT has a 16-bit increment counter, the clock is derived from the pre-division circuit, the pre-division clock is determined by the timer pre-division select bit BRTCKDIV, and the initial value of the counter is loaded by {BRTDH, BRTDL}. When the timer enable bit BRTEN=1 is turned on, the counter starts working.

  • Page 117: Buzzer Driver (Buzzer)

    CMS8S78xx Reference Manual 15. Buzzer Driver (BUZZER) 15.1 Overview The buzzer drive module consists of an 8-bit counter, a clock driver, and a control register. The buzzer drives a 50% duty-square wave frequency by registers BUZCON and BUZDIV, and its frequency output covers a wide range. with a 15.2 Related Registers 15.2.1...

  • Page 118: Feature Description

    CMS8S78xx Reference Manual 15.3 Feature Description When using a buzzer, you need to configure the corresponding port as a buzzer-driven output. For example, configure P17 as a buzzer drive output as follows: P17CFG = 0x05; The P1 7 is configured as a buzzer-driven output By configuring the Related Registers of the buzzer drive module, it is possible to set the different frequencies at which the buzzer drive outputs.

  • Page 119: Enhanced Pwm Module

    CMS8S78xx Reference Manual 16. Enhanced PWM Module 16.1 Overview The enhanced PWM module supports four PWM generators, which can be configured as four independent PWM outputs (PG0-PG3), or as 2 sets of synchronous PWM outputs, or 2 pairs of complementary PWM outputs with programmable dead-zone generators, where PG0-PG1 and PG2-PG3 are pairs 。...

  • Page 120: Port Configuration

    CMS8S78xx Reference Manual 16.3 Port Configuration Before using the enhanced PWM module, the corresponding port needs to be configured as a PWM channel, and the PWM channel is marked with PG0~PG3 on the multiplexing function allocation table, corresponding to PWM channel 0~3. The allocation of PWM channels is controlled by the corresponding port configuration registers, for example: P00CFG=0x04;...

  • Page 121: Feature Description

    CMS8S78xx Reference Manual 16.4 Feature Description 16.4.1 Functional Block Diagram The enhanced PWM consists of a clock control module, a PWM counter module, an output comparison unit, a waveform generator, a brake protection module (fault detection) and an output controller, and its block diagram is shown in the following figure: ACMP0 ACMP1...

  • Page 122: Edge Alignment

    CMS8S78xx Reference Manual 16.4.2 Edge Alignment In edge alignment mode, the 16-bit PWM counter CNTn starts counting down at the beginning of each cycle and compares with the value C in the PWMDnH/PWMDnL register MPn is compared, when CNTn= CMPn, PGn output high, PWMnDIF set to 1.

  • Page 123: Center Alignment

    CMS8S78xx Reference Manual 16.4.3 Center alignment In center-aligned counting mode, both symmetric and asymmetric counting are supported. To enable the asymmetric counting method, the ASYMEN needs to be placed at 1, and the asymmetric counting method can achieve accurate center alignment waveforms.
  • Page 124 CMS8S78xx Reference Manual The center-aligned counter waveform (symmetrical count) is shown in the following figure: When PWMnCNTM=1, continuous mode is enabled, when CNTn counts to zero, reload PERIODn and CMPn PWMn clock PERIODn(new) PERIODn(old) CMPn(new) CMPn(old) 16.4.3.2 Asymmetric Count In the center-aligned asymmetric counting mode, the 16-bit PWM counter CNTn counts upwards from 0, and when CNTn=CMPn, the PGn output is high, and the PWMnUIF is set to 1;...
  • Page 125 CMS8S78xx Reference Manual Center-aligned asymmetric count timing is shown in the following figure: Continuous mode enable PWMnCNTM=1, when CNTn counts to zero, reload PERIODn and CMPn 1A34H PERIODn(new) PERIODn(old) 07FFH CMPDn(new) 022FH CMPDn(old) 012FH CMPn(old) 0080H 0000H PIFn ZIFn UIFn DIFn Continuous mode enable PWMnCNTM=1, when CNTn counts to zero, reload PERIODn and CMPn...

  • Page 126: Complementary Model

    CMS8S78xx Reference Manual 16.4.4 Complementary Model The 4-way PWM can be set up as 2 sets of complementary PWM pairs. In complementary mode, the period, cycle, duty cycle, and clock division control and PG3 are determined by PG0, PG2-related registers, respectively, in addition to the of PG1 corresponding output enable control bit (PWMnOE), PG1, PG1, The PG3 output waveform is no longer controlled by its own registers.

  • Page 127: Synchronous Mode

    CMS8S78xx Reference Manual 16.4.5 Synchronous Mode 4-way PWM can be set up as 2 sets of synchronous PWM pairs. In synchronous mode, the period, duty cycle and clock division control of PG1 and PG3 are determined by PG0 and PG2 related registers, that is, in addition to the corresponding output enable control bit (PWMnOE), the PG1 and PG3 output waveforms are no longer controlled by their own registers, and the PG1 output wave is similar to PG0 and PG 3 Output waveform pG2.
  • Page 128 CMS8S78xx Reference Manual PWM Brake Recovery Mode: The fail-safe mode can be divided into 4 types to meet the needs of different fault protection occasions. Recovery conditions Counter Brake Register status Undo the brake Clear the brake Counter enable Delay Recovery points mode PWMBRKC[1:0]...
  • Page 129 CMS8S78xx Reference Manual Output control PWM brake enable. When the brake is triggered, the brake flag bit set to 1, the counter enable bits for all channels are hardware cleared, and the PWM outputs preset brake data. There are four brake modes to choose from. www.mcu.com.cn Rev.

  • Page 130: Pwm-Related Registers

    CMS8S78xx Reference Manual 16.5 PWM-related Registers 16.5.1 PWM Control Register PWMCON F120H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCON PWMRUN PWMMODE1 PWMMODE0 GROUPEN ASYMEN CNTTYPE Reset value Bit7 Reserved, must be 0. Bit6 PWMRUN: PWM clock pre-division, clock division enable bit; Prohibition (PWMmnPSC, PWMmnDIV are cleared 0);...

  • Page 131: Pwm0/1 Clock Prescale Control Register Pwm01Psc

    CMS8S78xx Reference Manual 16.5.3 PWM0/1 Clock Prescale Control Register PWM01PSC F123H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM01PSC PWM01PSC7 PWM01PSC6 PWM01PSC5 PWM01PSC4 PWM01PSC3 PWM01PSC2 PWM01PSC1 PWM01PSC0 Reset value Bit7~Bit0 PWM01PSC<7:0>: PWM channel 0/1 prescale control bit; The prescaler clock stops, the counter of PWM0/1 stops; Other = The system clock is divided (PWM01PSC+1).

  • Page 132: Pwm Data Loading Enable Control Register Pwmloaden

    CMS8S78xx Reference Manual 16.5.6 PWM Data Loading Enable Control Register PWMLOADEN F129H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMLOADEN PWM3LE PWM2LE PWM1LE PWM0LE Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 PWMnLE: Data loading enable bits (n=0-3) of PWM channel n (hardware clearing after loading is completed);...

  • Page 133: Pwm Counter Enable Control Register Pwmcnte

    CMS8S78xx Reference Manual 16.5.9 PWM Counter Enable Control Register PWMCNTE F126H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCNTE PWM3CNTE PWM2CNTE PWM1CNTE PWM0CNTE Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 PWMnCNTE: PWM channel n counter enable control bit (n=0-3); PWMn counter on (PWMn starts output);...

  • Page 134: Pwm Compare Data Register Low 8 Bits Pwmdnl (N=0-3)

    CMS8S78xx Reference Manual 16.5.13 PWM Compare Data Register Low 8 BitS PWMDnL (n=0-3) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMDnL PWMDnL7 PWMDnL6 PWMDnL5 PWMDnL4 PWMDnL3 PWMDnL2 PWMDnL1 PWMDnL0 Reset value Registers PWMDnL (n=0-3) Address: F140H, F142H, F144H, F146H. Bit7~Bit0 PWMDnL<7:0>: PWM channel n compare data (duty cycle data) registers 8 bits lower.

  • Page 135: Pwm Dead-Zone Enable Control Register Pwmdte

    CMS8S78xx Reference Manual 16.5.17 PWM dead-zone enable control register PWMDTE F160H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMDTE PWM23DTE PWM01DTE Reset value Bit7~Bit2 Reserved, must be 0. Bit1 PWM23DTE: PWM2/3 channel dead-zone delay enable bit; Enable; Disable. Bit0 PWM01DTE: PWM0/1 channel dead-zone delay enable bit;...

  • Page 136: Pwm Mask Data Register Pwmmaskd

    CMS8S78xx Reference Manual 16.5.21 PWM Mask Data Register PWMMASKD F165H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMMASKD PWM3MASKD PWM2MASKD PWM1MASKD PWM0MASKD Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 PWMnMASKD: PWM channel n mask data bits (n=0-3); PWMn channel output is high; PWMn channel output is low.

  • Page 137: Pwm Brake Recovery Control Register Pwmbrkc

    CMS8S78xx Reference Manual 16.5.23 PWM Brake Recovery Control Register PWMBRKC F15CH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMBRKC BRKOSF BRKRCS2 BRKRCS21 BRKRCS20 BRKCLR BRKEN BRKMS1 BRKMS0 Reset value BRKOSF: EPWM fault-protected output status flag bit (read-only). Bit7 The EPWMn channel is in the normal output state The EPWMn channel is the data state of the output PWMnFBKD Bit6~Bit4 BRKRCS<2:0>:...

  • Page 138: Pwm Brake Data Register Pwmfbkd

    CMS8S78xx Reference Manual 16.5.26 PWM Brake Data Register PWMFBKD F167H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMFBKD PWM3FBKD PWM2FBKD PWM1FBKD PWM0FBKD Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 PWMnFBKD: PWM channel n brake data bits (n=0-3); The PWMn channel produces a high output after braking operation. The PWMn channel produces a low output after braking operation.

  • Page 139: Pwm Interrupt

    CMS8S78xx Reference Manual 16.6 PWM Interrupt The enhanced PWM has a total of 17 interrupt flags, of which 4 are cyclic interrupt flags, 4 are zero interrupt flags, 4 are up-compare interrupt flags, and 4 are down-compare interrupt flags. 1 brake interrupt flag, the generation of the interrupt flag is independent of whether the corresponding interrupt enable bit is turned on or not.

  • Page 140: Interrupt Priority Control Register Eip2

    CMS8S78xx Reference Manual 16.6.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C Interrupt priority control bit;...

  • Page 141: Pwm Zero Interrupt Mask Register Pwmzie

    CMS8S78xx Reference Manual 16.6.4 PWM Zero Interrupt Mask Register PWMZIE F169H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMZIE PWM3ZIE PWM2ZIE PWM1ZIE PWM0ZIE Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 PWMnZIE: PWM channel n zero interrupt shield bit (n=0-3); Enable interrupts;...

  • Page 142: Pwm Zero Interrupt Flag Register Pwmzif

    CMS8S78xx Reference Manual 16.6.8 PWM Zero Interrupt Flag Register PWMZIF F16DH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMZIF PWM3ZIF PWM2ZIF PWM1ZIF PWM0ZIF Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 PWMnZIF: PWM channel n zero interrupt flag bit (n=0-3); generate interrupts (software zeroing);...

  • Page 143: Lcd Driver

    CMS8S78xx Reference Manual 17. LCD Driver 17.1 Overview With the ability to drive external LCD panels, the COM and SEG pins of the LCD drive are shared with the IO, and the LCD enable control signal is implemented by the software configuration. 17.2 Characteristic LCD drives have the following characteristics: ◆...

  • Page 144: 1/3 Bias Timing Diagram

    CMS8S78xx Reference Manual 17.3.2 1/3 Bias Timing Diagram The "1" in the figure represents the lit LCD pixels frame0 frame1 frame0 COM0 2/3VDD 1/3VDD 2/3VDD COM1 1/3VDD COM2 2/3VDD 1/3VDD 2/3VDD 1/3VDD COM3 SEG0 2/3VDD 1/3VDD 2/3VDD SEG1 1/3VDD www.mcu.com.cn Rev.

  • Page 145: Related Registers

    CMS8S78xx Reference Manual 17.4 Related Registers 17.4.1 LCD Control Register LCDCON0 F650H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDCON0 LCDEN FRAME ISEL1 ISEL0 Reset value Bit7 LCDEN LCD enable bit Enables the LCD module LCD modules are Disabled Bit6 FRAME Frame0 or Frame...

  • Page 146: Lcd Com/Seg Select Register Lcd_S2

    CMS8S78xx Reference Manual 17.4.4 LCD COM/SEG Select Register LCD_S2 F653H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCD_S2 LCD_S23 LCD_S22 LCD_S21 LCD_S20 LCD_S19 LCD_S18 LCD_S17 LCD_S16 Reset value Bit7~Bit0 LCD_S2[7:0] LCD's COM/SEG[ 23:16] feature selection The corresponding pin is used as a LCD_SEG port The corresponding pin is used as a LCD_COM port 17.4.5 LCD Function Select Register LCDEN0...

  • Page 147: Led Driver

    CMS8S78xx Reference Manual 18. LED Driver 18.1 Overview Software driver LED, can be convenient for users to achieve LED display driver. 18.2 Characteristic LED drivers have the following characteristics: ◆ Supports up to 24 COM ports and 24 SEG ports. ◆...

  • Page 148: Seg Port P10-P13 Drive Current Control Register Ledsdrp1L

    CMS8S78xx Reference Manual 18.3.3 SEG Port P10-P13 Drive Current Control Register LEDSDRP1L F712H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP1L LEDSDRP1L1 LEDSDRP1L0 Reset value Bit1~Bit0 LEDSDRP1L <1:0> P10, P11, P12, P13 pull current drive 8.9mA 17.8mA 26.8mA 45mA 18.3.4 SEG Port P14-P17 Drive Current Control Register LEDSDRP1H F713H...

  • Page 149: Seg Port P24-P27 Drive Current Control Register Ledsdrp2H

    CMS8S78xx Reference Manual 18.3.6 SEG Port P24-P27 Drive Current Control Register LEDSDRP2H F715H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP2H LEDSDRP2H1 LEDSDRP2H0 Reset value Bit1~Bit0 LEDSDRP2H <1:0> P24, P25, P26, P27 pull current drive 8.9mA 17.8mA 26.8mA 45mA 18.3.7 SEG Port P30-P33 Drive Current Control Register LEDSDRP3L F716H...

  • Page 150: Led Com Port Sink Current Selection Register Pndr (N=0/1/2/3)

    CMS8S78xx Reference Manual 18.3.8 LED COM Port Sink Current Selection Register PnDR (n=0/1/2/3). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PnDR PnDR7 PnDR6 PnDR5 PnDR4 PnDR3 PnDR2 PnDR1 PnDR0 Reset value P0DR : F00CH P1DR:F01CH P2DR:F02CH P3DR:F03CH Bit7 PnDR7 Pn7 drive current selection 150mA 50mA...

  • Page 151: Spi Module

    CMS8S78xx Reference Manual 19. SPI Module 19.1 Overview This SPI is a fully configurable SPI master/slave device that allows the user to configure the polarity and phase of the serial clock signal SCLK. The serial clock line (SCLK) is synchronized with the shifting and sampling of information on two independent serial data lines, and the SPI data is sent and received simultaneously.

  • Page 152: Spi Port Configuration

    CMS8S78xx Reference Manual 19.2 SPI Port Configuration Using the SPI function requires configuring the relevant port as an SPI channel and selecting the corresponding port input through the communication input port registers. For example, P04, P02, P03, P12 are configured as SPI communication ports. The configuration code is as follows: PS_SCLK = 0x04;...

  • Page 153: Spi Hardware Description

    CMS8S78xx Reference Manual 19.3 SPI Hardware Description When an SPI transfer occurs, when one data pin moves out of one 8-bit character, the other data pin moves in the other 8-bit character. The 8-bit shift register in the master device and another 8-bit shift register in the slave device are connected as a cyclic 16-bit shift register, and when the transfer occurs, the distributed shift register is shifted by 8 bits, thus effectively swapping the characters of the master slave.

  • Page 154: Spi-Related Registers

    CMS8S78xx Reference Manual 19.4 SPI-related Registers 19.4.1 SPI Control Register SPCR 0xEC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCR SPEN SPR2 MSTR CPOL CPHA SPR1 SPR0 Reset value Bit7 Reserved, must be 0. Bit6 SPEN: SPI module enable bit; Enable;...

  • Page 155: Spi Device Select Control Register Sscr

    CMS8S78xx Reference Manual 19.4.3 SPI Device Select Control Register SSCR The slave device selection control register SSCR can read or write at any time and is used to configure which slave selection output should be driven when acknowledging the SPI master transfer. When the SPI host transfer starts, the contents of the SSCR register are automatically assigned to the NSS pin.

  • Page 156: Spi Master Mode

    CMS8S78xx Reference Manual 19.5 SPI Master Mode When SPI is configured for host mode, the transfer is initiated by writing to the SPDR registers. When new bytes are written to the SPDR register, the SPI starts transferring. The serial clock SCLK is generated by the SPI, in host mode the SPI is enabled, and the SCLK output.

  • Page 157: Write Conflict Error

    CMS8S78xx Reference Manual 19.5.1 Write Conflict Error If the SPI data registers are written during the transfer, a write violation occurs. The transfer continues uninterrupted, and the write data that causes the error is not written to the shifter. Write conflicts are indicated by the WCOL flag in the SPSR register.

  • Page 158: Spi Slave Mode

    CMS8S78xx Reference Manual 19.6 SPI Slave Mode When configured as an SPI slave device, SPI transmission is initiated by an external SPI master module by using the SPI slave selection input and generates an SCLK serial clock. Before the transfer begins, it is necessary to determine which SPI slave will be used to exchange data. The NSS is used (clear = 0), and the clock signal connected to the SCLK line will transfer the SPI slave device to the receiving shift register contents of the MOSI line and drive the MISO line with the contents of the transmitter shift registers.
  • Page 159 CMS8S78xx Reference Manual In case the CPHA is cleared, WCOL generation can also be caused by SPDR register writes when either NSS line is cleared, at which point the SPI host can also complete without generating a serial clock, SCLK. This is because the transfer start is not explicitly specified, and the NSS is driven low after a full-byte transfer may indicate the start of the next byte transfer.

  • Page 160: Spi Clock Control Logic

    CMS8S78xx Reference Manual 19.7 SPI Clock Control Logic 19.7.1 SPI Clock Phase and Polarity Control The software can select any of the four combinations using two control bits (phase and polarity of the serial clock SCLK) in the SPI control register (SPCR). Clock polarity is specified by the CPOL control bit, and the CPOL control bit selection high or low level when the transmission is idle has no significant effect on the transmission format.

  • Page 161: Cpha=1 Transfer Format

    CMS8S78xx Reference Manual 19.7.4 CPHA=1 Transfer Format The following figure is a timing diagram of the SPI transmission with CPHA = 1. SCLK shows two waveforms: one for CPOL=0 and one for CPOL=1. Since the SCLK, MISO, and MOSI pins are directly connected between the master and slave, this diagram can be interpreted as a master or slave timing diagram.

  • Page 162: Spi Data Transfer

    CMS8S78xx Reference Manual 19.8 SPI Data Transfer 19.8.1 SPI Transfer Starts All SPI transfers are initiated and controlled by the master SPI device. As a slave device, the SPI will consider the transmission starting at the first SCLK edge or the falling edge of the NSS, depending on the CPHA format chosen. When CPHA = 0, the falling edge of the NSS indicates the start of the transmission.

  • Page 163: Spi Timing Diagram

    CMS8S78xx Reference Manual 19.9 SPI Timing Diagram 19.9.1 Master Mode Transmission When the clock polarity of the SPI is CPOL=0 and the clock phase CPHA=1, the NSS in SPI master mode is the clK of the system clock after the low level, the MOSI starts to output, and the DATA of the MOSI is output on the rising edge of the SCLK clock.

  • Page 164: Spi Interrupt

    CMS8S78xx Reference Manual 19.10 SPI Interrupt The interrupt number of the SPI is 22, where the interrupt vector is 0x00B3. To enable an SPI interrupt, it must set its enable bit SPIIE to 1 and the global interrupt enable bit EA to 1. If the SPI-related interrupt enables are all turned on, the CPU will enter the interrupt service program when the SPI global interrupt indicator bit SPIIF=1.

  • Page 165: Interrupt Priority Control Register Eip2

    CMS8S78xx Reference Manual 19.10.2 Interrupt Priority Control Register EIP2 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ANDTHEP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...

  • Page 166: Peripheral Interrupt Flag Bit Register Eif2

    CMS8S78xx Reference Manual 19.10.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...

  • Page 167: I2C Module

    CMS8S78xx Reference Manual 20. I2C Module 20.1 Overview The module provides an interface between the microcontroller and the I2C bus, as shown in the connection diagram below, and supports arbitration and clock synchronization to allow operation in multi-master systems. I2C supports normal, fast mode. The I2C module has the following characteristics: ◆...

  • Page 168: I2C Port Configuration

    CMS8S78xx Reference Manual 20.2 I2C Port Configuration If you use the I2C function, you should first configure the corresponding port as an SCL, SDA channel. For example, configure P04, P03 ports as I2C function: PS_SCL = 0x04; Select the P04 port as the SCL pin PS_SDA = 0x03;...

  • Page 169: I2C Master Mode

    CMS8S78xx Reference Manual 20.3 I2C Master Mode There are six registers for connecting to the master: control, status, slave address, transmit data, receive data, and timer cycle registers. register address write Read Slave address register I2CMSA Slave address register I2CMSA 0xF4 Master mode control register I2CMCR Master mode status register I2CMSR...

  • Page 170: I2C Master Mode Control And Status Registers

    CMS8S78xx Reference Manual 20.3.2 I2C Master Mode Control and Status Registers The control registers include 4 bits: RUN, START, STOP, ACK bits. The START bit will produce the START or RESTART START condition. The STOP bit determines whether the data transfer stops at the end of the cycle, or continues. To generate a single transmission cycle, the slave address register writes to the desired address, the R/S bit is set to 0, and the control register writes to ACK=x, STOP=1, START=1, RUN=1 (I2CMCR=xxx0_x111x) to perform the operation and stop.
  • Page 171 CMS8S78xx Reference Manual Combination of control bits (IDLE state). STOP START OPERATION START followed by SEND (master remains in send mode) START is followed by SEND and STOP Non-responsive reception after START (master remains in receiver mode) START is followed by REVIVE and STOP START followed by RECOVER (master remains in receiver mode) Combinations are prohibited Combinations are prohibited...

  • Page 172: I2C Slave Address Register

    CMS8S78xx Reference Manual Master mode status register I2CMSR 0xF5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I2CMSR I2CMIF BUS_BUSY IDLE ARB_LOST DATA_ACK ADD_ACK ERROR BUSY Reset value Bit7 I2CMIF: I2C master mode interrupt flag bit; In master mode, send/receive completes, or a transmission error occurs. (Software zero, write 0 to clear);...

  • Page 173: I2C Master Mode Transmit And Receive Data Registers

    CMS8S78xx Reference Manual 20.3.4 I2C Master Mode Transmit and Receive Data Registers The transmit data register consists of eight data bits that will be sent on the bus on the next send or burst operation, the first of which is MD7 (MSB). Master mode data cache register I2CMBUF 0xF6 Bit7...

  • Page 174: I2C Slave Mode

    CMS8S78xx Reference Manual 20.4 I2C Slave Mode There are five registers for connecting to the target device: self address, control, status, send data, and receive data registers. register address write Read Self address register I2CSADR Self address register I2CSADR 0xF1 Control register I2CSCR Status register I2CSSR 0xF2...

  • Page 175: I2C Slave Mode Transmit And Receive Buffer Registers I2Csbuf

    CMS8S78xx Reference Manual The status register consists of three bits: sendfin bit, RREQ bit, TREQ bit. The SENDFIN bit of Send Complete indicates that the Master I2C controller has completed the receipt of data during a single or continuous I2CS transmit operation. The Receive Request RREQ bit indicates that the I2CS device has receiveda data byte from the I2C master, and the I2CS device should read a data byte from the receiving data register I2CSBUF.

  • Page 176: I2C Interrupt

    CMS8S78xx Reference Manual 20.5 I2C Interrupt The interrupt number for I2C is 21, where the interrupt vector is 0x00AB. The enable I2C interrupt must set its enable bit I2CIE to 1 and the global interrupt enable bit EA to 1. If the I2C-related interrupt enables are turned on,the CPU will enter the interrupt service program when the I2C global interrupt indicator bit I2CIF=1 is turned on.

  • Page 177: Interrupt Priority Control Register Eip2

    CMS8S78xx Reference Manual 20.5.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ANDTHEP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...

  • Page 178: Peripheral Interrupt Flag Bit Register Eif2

    CMS8S78xx Reference Manual 20.5.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...

  • Page 179: I2C Slave Mode Transmission Mode

    CMS8S78xx Reference Manual 20.6 I2C Slave Mode Transmission Mode All rendered waveforms in this section default I2C to have their own address 0x39 ("00111001"). 20.6.1 Single Receive The following figure shows the sequence of signals received by I2C during a single data session.

  • Page 180: Continuous Reception

    CMS8S78xx Reference Manual 20.6.3 Continuous reception The following figure shows the sequence of signals received by I2C during continuous data reception. Continuous receive sequence: Start conditions. I2C is addressed by the I2C master as a receiver. The address is confirmed by I2C. Data is received by I2C.

  • Page 181: Continuous Sending

    CMS8S78xx Reference Manual 20.6.4 Continuous Sending The following figure shows the sequence of signals sent by I2C during continuous data transmission. Consecutive send sequences: Send conditions. I2C is addressed by the I2C master as a transmitter. The address is confirmed by I2C. The data is sent by I2C.

  • Page 182: Uart0 Module

    CMS8S78xx Reference Manual 21. UART0 Module 21.1 Overview The Universal Synchronous Asynchronous Transceiver (UART0) provides a flexible way to exchange full-duplex data with external devices. UART0 has two physically separate receive and transmit buffers, SBUF0, which distinguish between operations on a receive buffer or a transmit buffer by reading and writing instructions to SBUF0.

  • Page 183: Uart0 Baud Rate

    CMS8S78xx Reference Manual 21.3 UART0 Baud Rate UART0 In mode 0, the baud rate is fixed to the division twelve of the system clock (Fsys/12); In mode 2, the baud rate is fixed to the system clock's division of thirty-two or division sixty-four (Fsys/32, Fsys/64); In modes 1 and 3, the baud rate is generated by the timer Timer1 or Timer4 or Timer2 or BRT module, and the chip chooses which timer to use as the baud rate clock source is determined by the register FUNCCR.

  • Page 184: Baud Rate Error

    CMS8S78xx Reference Manual 21.3.3 Baud Rate Error UART0 in mode 1 and mode 3, select different baud rate clock sources, the error under different baud rate is as follows: Table 1) and 2) are some baud rate information in the 8-bit automatic reload mode of timer 1/timer 4 in variable baud rate mode.
  • Page 185 CMS8S78xx Reference Manual 3）SMODn=0，BRTCKDIV=0 baud Fsys=8MHz Fsys=16MHz Fsys=24MHz Fsys=48MHz rate {BRTH, Current {BRTH, Current {BRTH, Current {BRTH, Current BRTL} Rate Error BRTL} Rate Error BRTL} Rate Error BRTL} Rate Error 4800 65484 4808 -0.16 65432 4808 -0.16 65380 4808 -0.16 65224 4808 -0.16...

  • Page 186: Uart0 Register

    CMS8S78xx Reference Manual 21.4 UART0 Register The UART0 has the same features as the standard 8051 UART. Its Related Registers are: FUNCCR, SBUF0, SCON0, PCON, IE, IP, EIP3。 The UART0 data buffer (SBUF0) consists of 2 independent registers: the transmit and receive registers. The data written to SBUF0 will be set in the UART0 output register and the transmission will begin;...

  • Page 187: Uart Control Register Scon0

    CMS8S78xx Reference Manual 21.4.3 UART Control Register SCON0 0x98 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCON0 In0SM0 In0SM1 In0SM2 U0REN In0TB8 In0RB8 Reset value Bit7~Bit6 IN0SM0- IN0SM1: Multi-Slave communication control bit; Master synchronization mode; 8-bit asynchronous mode, variable baud rate; 9-bit asynchronous mode with baudrates of F sys/32 or Fsys/64;...

  • Page 188: Pcon Registers

    CMS8S78xx Reference Manual 21.4.4 PCON Registers 0x87 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD0 THEIR STOP IDLE Reset value B Registers in ANK0 Bit7 SMOD0: UART0 baud rate multiplier; UART0 baud rate doubled; The UART0 baud rate is normal. Bit6~Bit3 Reserved, must be 0.

  • Page 189: Uart0 Interrupt

    CMS8S78xx Reference Manual 21.5 UART0 Interrupt The interrupt number of UART0 is 4, where the interrupt vector is 0x0023. To enable the UART0 interrupt, it must set its enable bit ES0 to 1 and the global interrupt enable bit EA to 1. If the interrupt enables associated with UART0 are all turned on, TI0=1 or RI0=1, the CPU will enter the corresponding interrupt service program.

  • Page 190: Interrupt Priority Control Register Ip

    CMS8S78xx Reference Manual 21.5.2 Interrupt Priority Control Register IP 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7~Bit6 Reserved, must be 0. Bit5 PT2: TIMER2 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit4 PS0: UART0 interrupt priority control bit;...

  • Page 191: Uart0 Mode

    CMS8S78xx Reference Manual 21.6 UART0 Mode 21.6.1 Mode 0 - Synchronous Mode Pin RXD00 is the input or output and TXD0 is the clock output. The TXD0 output is a shift clock. The baud rate is fixed at 1/12 of the system clock frequency. 8 bits are transmitted preferentially with LSB. The receive is initialized by setting the flag in SCON 0, set to: RI0 = 0 and REN0 = 1.

  • Page 192: Mode 2-9 Bit Asynchronous Mode (Fixed Baud Rate)

    CMS8S78xx Reference Manual 21.6.3 Mode 2-9 Bit Asynchronous Mode (Fixed Baud Rate). This mode is similar to Mode 1, but differs in two ways. The baud rate is fixed at 1/32 or 1/64 of the CLK clock frequency, with 11 bits of transceiver: start bit (0), 8 bits of data (LSB first), programmable bit 9, and stop bit (1). Bit 9 can be used to control parity of the UART0 interface: bit TB08 in SCON0 acts as the 9th bit output when sending, and bit 9 affects...

  • Page 193: Analog-To-Digital Converters (Adcs)

    CMS8S78xx Reference Manual 22. Analog-to-digital Converters (ADCs) 22.1 Overview An analog-to-digital converter (ADC) converts an analog input signal into a 12-bit binary number representing the signal, as shown in the ADC block diagram below. The port analog input signal and the internal analog signal are connected to the input of the analog-to-digital converter after being multiplexed.

  • Page 194: Adc Configuration

    CMS8S78xx Reference Manual 22.2 ADC Configuration When configuring and using an ADC, the following factors must be considered: ⚫ Port configuration. ⚫ Channel selection. ⚫ ADC converts the clock source. ⚫ Interrupt control. ⚫ The format in which the results are stored. 22.2.1 Port Configuration ADC can convert both analog and digital signals.

  • Page 195: Convert The Clock

    CMS8S78xx Reference Manual 22.2.4 Convert the Clock The converted clock source can be selected by software setting the ADCKS bit of the ADCON1 register. The time to complete a bit conversion is defined as T . A full 12-bit conversion requires 18.5 T cycles (the ADCK ADCK...

  • Page 196: The Adc Hardware Trigger Start

    CMS8S78xx Reference Manual 22.3 The ADC Hardware Trigger Start In addition to software-triggered ADC conversion, the ADC module provides a way for hardware to trigger start. One is the external port edge triggering method, and the other is the edge or periodic triggering mode of the PWM. Using a hardware trigger ADC requires setting ADCX to 1, even if the ADC function can be triggered externally.

  • Page 197: Adc Results Comparison

    CMS8S78xx Reference Manual 22.4 ADC Results Comparison The ADC module provides a set of digital comparators for comparing the results of an ADC with the value size of preloaded {ADCMPH, ADCMPL}. The result of each ADC conversion is compared to the preset value ADCMP, and the result of the comparison is stored in the ADCPO flag bit, which is automatically updated after the conversion is completed.

  • Page 198: A/D Conversion Steps

    CMS8S78xx Reference Manual 22.5.4 A/D Conversion Steps The configuration steps for analog-to-digital conversion using an ADC are as follows: Port configuration: ⚫ Disable pin output drivers (see PxTRIS registers); ⚫ Configure the pins as analog input pins. Configure ADC interrupt (optional): ⚫...

  • Page 199: Related Registers

    CMS8S78xx Reference Manual 22.6 Related Registers There are 11 main registers associated with AD conversion, which are: ⚫ AD control registers ADCON0, ADCON1, ADCON2, ADCCHS, ADCLDO; ⚫ Comparator control register ADCPC; ⚫ Delay data register ADDLYL; ⚫ AD result data register ADRSH/L; ⚫...

  • Page 200: Ad Control Register Adcon1

    CMS8S78xx Reference Manual 22.6.2 AD Control Register ADCON1 0xDE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON1 ADEN ADCKS2 ADCKS1 ADCKS0 Reset value Bit7 ADEN: ADC enable bit; Enable ADC; ADC is Disabled and does not consume operating current. Bit6~Bit4 ADCKS<2:0>: ADC conversion clock select bits;...

  • Page 201: Ad Channel Selection Register Adcchs

    CMS8S78xx Reference Manual 22.6.4 AD Channel Selection Register ADCCHS 0xD9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCCHS CHS5 CHS4 CHS3 CHS2 CHS1 CHS0 Reset value Bit7 Reserved, must be 0. Bit5~Bit0 CHS<5:0>: Analog channel selection bits; 000000= AN0; 010000= AN16;...

  • Page 202: Ad Hardware Trigger Delay Data Register Addlyl

    CMS8S78xx Reference Manual 22.6.6 AD Hardware Trigger Delay Data Register ADDLYL 0xD3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDLYL ADDLY7 ADDLY6 ADDLY5 ADDLY4 ADDLY3 ADDLY2 ADDLY1 ADDLY0 Reset value Bit7~Bit0 ADDLY<7:0>: ADC hardware trigger delay data is 8 bits lower. 22.6.7 AD Data Register High ADRESH, ADFM=0 (Left-aligned).

  • Page 203: Ad Data Register Low Adrsl, Adfm = 1 (Right-Aligned)

    CMS8S78xx Reference Manual 22.6.10 AD Data Register Low ADRSL, ADFM = 1 (Right-aligned). 0xDC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRESL ADDRESS7 ADDRESS6 ADDRESS5 ADDRESS4 ADDRESS3 ADDRESS2 ADDRESS1 ADDRESS0 Reset value Bit7~Bit0 ADDRESS<7:0>: ADC result register bit. 12 bits converted to bits 7-0 of the result. 22.6.11 AD Comparator Data Register ADCMPH 0xD5 Bit7...

  • Page 204: Adc Interrupt

    CMS8S78xx Reference Manual 22.7 ADC Interrupt The ADC module allows an interrupt to be generated after the analog-to-digital conversion is complete. The ADC interrupt enable bit is the ADCIE bit in the EIE2 register, and the ADC interrupt flag bit is the ADCIF bit in the EIF2 register. The ADCIF bit must be cleared with software, and the ADCIF bit is set to 1 after each conversion, regardless of whether the ADC interrupt is enabled.

  • Page 205: Interrupt Priority Control Register Eip2

    CMS8S78xx Reference Manual 22.7.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C Interrupt priority control bit;...

  • Page 206: Peripheral Interrupt Flag Bit Register Eif2

    CMS8S78xx Reference Manual 22.7.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...

  • Page 207: Temperature Sensor

    CMS8S78xx Reference Manual 23. Temperature Sensor 23.1 Overview The chip contains a temperature sensor whose output analog volume varies with the temperature of the chip. The analog signal output by the sensor is acquired and converted by ADC, and temperature changes can be obtained indirectly. 23.2 Register Description 23.2.1 The Temperature Sensor Control Register TS _REG...

  • Page 208: Features

    CMS8S78xx Reference Manual 23.3.2 Features This temperature sensor has the following characteristics: When the temperature changes from - 40℃ to 125℃, the analog signal voltage range generated is: 0.7V~1.4V; When the temperature changes from - 40℃ to 125℃, the slope of analog quantity with temperature is K: 3.5 ± 0.2 mV/℃;...

  • Page 209: Analog Comparator (Acmp0/1)

    CMS8S78xx Reference Manual 24. Analog Comparator (ACMP0/1). The chip contains two analog comparators, ACMP0 and ACMP1. When the positive voltage is greater than the negative voltage, the comparator outputs logic 1 and vice versa output 0, which can also be changed by the output polarity select bit. When the comparator output value changes, each comparator can generate an interrupt.
  • Page 210 CMS8S78xx Reference Manual The comparator hysteresis control block diagram is shown in the following figure: The negative terminal voltage of the comparator is fixed, and The positive terminal voltage of the comparator is fixed, the output waveform is changed when the positive terminal and the negative terminal voltage is changed, and its voltage is changed output waveform...

  • Page 211: Related Registers

    CMS8S78xx Reference Manual 24.3 Related Registers 24.3.1 Comparator Control Register CnCON0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CnCON0 Cnen CnCOFM CnN2G CnNS1 CnNS0 CnPS2 CnPS1 CnPS0 Reset value C0CON0 address:F500H;C1CON0 address:F503H。 Bit7 CnEN: Comparator n enable bit; Enable; Disable.

  • Page 212: Comparator Control Register Cncon2

    CMS8S78xx Reference Manual 24.3.3 Comparator Control Register CnCON2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CnCON2 CnPOS CnFE CnFS3 CnFS2 CnFS1 CnFS0 Reset value C0CON2 Address: F502H; C1CON2 Address: F505H. Bit7~Bit6 Reserved, must be 0. Bit5 CnPOS: Comparator n output polarity select bit (bits that may cause interrupt flag bit when switching);...

  • Page 213: Comparator Hysteresis Control Register Cnhys

    CMS8S78xx Reference Manual 24.3.5 Comparator Hysteresis Control Register CnHYS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CnHYS CnHYS_PNS1 CnHYS_PNS0 CnHYS_S1 CnHYS_S0 Reset value C0HYS Address: F50CH; C1HYS Address: F50DH. Bit7~Bit4 Reserved, must be 0. Bit3~Bit2 CnHYS_PNS<1:0> Positive and negative hysteresis select bits; Off hysteresis;...

  • Page 214: Comparator Brake Control Register Cnfbcon

    CMS8S78xx Reference Manual 24.3.7 Comparator Brake Control Register CNFBCON F507H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CNFBCON C1FBPEN C0FBPEN C1FBPS C0FBPS C1FBEN C0FBEN C1FBLS C0FBLS Reset value Bit7 C1FBPEN: Comparator 1 output level controls PWM brake enable; Disable; Enable.

  • Page 215: Comparator Interrupt

    CMS8S78xx Reference Manual 24.4 Comparator Interrupt Both comparator 0 and comparator 1 can set interrupts, both of which share an interrupt vector entry, and when entering the interrupt service program, the user can determine which type of interrupt is generated by the interrupt flag. Comparator interrupt priority and interrupt enable can be set by the following Related Register bits.

  • Page 216: Comparator Interrupt Flag Register Cnif

    CMS8S78xx Reference Manual 24.4.3 Comparator Interrupt Flag Register CNIF F509H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CNIF C1IF C0IF Reset value Bit7~ Bit2 Reserved, must be 0. Bit1 C1IF: Comparator 1 interrupt flag bit (write 0 clear); Compare 1 output changes. Bit0 C0IF: Comparator 0 interrupt flag bit (write 0 clear);...

  • Page 217: Flash Memory

    CMS8S78xx Reference Manual 25. Flash Memory 25.1 Overview FLASH memory contains program memory (APROM/BOOT) and nonvolatile data memory (Data FLASH). The maximum program memory space is 16KB, divided into 32 sectors, each containing 512B. The maximum data memory space is 1KB, divided into 2 sectors, each containing 512B.

  • Page 218: Related Registers

    CMS8S78xx Reference Manual 25.2 Related Registers 25.2.1 FLASH Protect Lock Register MLOCK 0xFB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MLOCK MLOCK7 MOCK6 MLOCK5 MLOCK4 MLOCK3 MLOCK2 MLOCK1 MLOCK0 Reset value Bit7~Bit0 MLOCK<7:0>: Memory operation enable bit (this register only supports write operations, reads are 00H);...

  • Page 219: Program Crc Operation Result Data Register Lower 8-Bit Pcrcdl

    CMS8S78xx Reference Manual 25.2.5 Program CRC Operation Result Data Register Lower 8-bit PCRCDL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xF9 PCRCDL PCRCD<7:0> Reset value Bit7~Bit0 PCRCD<7:0> The program CRC operation results 8 bits lower data 25.2.6 Program CRC Operation Result Data Register Higher 8-bit PCRCDH 0xFA Bit7 Bit6...

  • Page 220: Feature Description

    CMS8S78xx Reference Manual 25.3 Feature Description During FLASH memory read/write/erase operation, the CPU is in a paused state, when the operation completes, the CPU continues to run instructions. The operation memory instruction must be followed by 6 NOP instructions, for example: MOV MCTRL,#09H ;...

  • Page 221: Overview

    CMS8S78xx Reference Manual 26.1 Overview Each chip has a different 96-bit unique identification number, or Unique identification. It has been set at the factory and cannot be modified by the user. 26.2 UID Register Description UID0 F5E0H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2...
  • Page 222 CMS8S78xx Reference Manual UID4 F5E4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID4 UID39 UID38 UID37 UID36 UID35 UID34 UID33 UID32 Reset value Bit7~Bit0 UID<39:32> UID5 F5E5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID5 UID47 UID46 UID45 UID44 UID43 UID42...
  • Page 223 CMS8S78xx Reference Manual UID9 F5E9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID9 UID79 UID78 UID77 UID76 UID75 UID74 UID73 UID72 Reset value Bit7~Bit0 UID<79:72> UID10（0xF5EA） F5EAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID10 UID87 UID86 UID85 UID84 UID83 UID82...

  • Page 224: User Configuration

    CMS8S78xx Reference Manual 27. User configuration The System Configuration Register (CONFIG) is a FLASH option for the initial conditions of the MCU and cannot be accessed or operated by the program. It contains the following: WDT (Watchdog Working Method Selection) ⚫...
  • Page 225 CMS8S78xx Reference Manual An external reset is enabled and the internal pull-up resistor ⚫ ENABLE(OPEN PULLUP) of the reset port is turned on 10. EXT_RESET_SEL ⚫ Select P24 pin for external reset port ⚫ Select P25 pins for the external reset port 11.

  • Page 226: In-Circuit Programming And Debugging

    CMS8S78xx Reference Manual 28. In-circuit Programming and Debugging 28.1 Online Programming Mode The chip can be programmed serially in the end application circuit. Programming can be done simply by the following 4 wires: ⚫ Power cord ⚫ Ground wire ⚫ Data cable ⚫...

  • Page 227: Online Debug Mode

    CMS8S78xx Reference Manual 28.2 Online Debug Mode The chip supports 2-wire (DSCK, DSDA) in-circuit debugging. If you use the in-circuit debugging function, you need to set DEBUG in the system configuration register to ENABLE. When using debug mode, you need to be aware of the following points: ◆...

  • Page 228: Instruction Description

    CMS8S78xx Reference Manual 29. Instruction description Assembly instructions consist of a total of 5 categories: arithmetic operations, logical operations, data transfer operations, Boolean operations, and program branch instructions, all of which are compatible with standard 8051. 29.1 Symbol description Description Symbol Working registers R0-R 7 The cell address (00H-FFH...

  • Page 229: List Of Instructions

    CMS8S78xx Reference Manual 29.2 List of Instructions Mnemonics description Operation class A,R n Accumulator plus register A,direct Accumulator plus direct addressing unit A,@Rto Accumulator plus indirect addressingRAM A,#data The accumulator adds the immediate number ADDC A,Rn Accumulator plus registers and carry flags ADDC A,direct Accumulator plus direct addressing unit and carry signs...
  • Page 230 CMS8S78xx Reference Manual Mnemonics description The accumulator is shifted in the left loop The accumulator is even the carry flag for a left loop shift The accumulator is shifted in the right loop RR RC The accumulator is connected to the carry mark right loop shift SWAP The accumulator is swapped 4 bits high and 4 bits low Data transfer class...
  • Page 231 CMS8S78xx Reference Manual Mnemonics description ACALL add r11 Absolute invocation within the 2K address range LCALL addr16 Long calls within 64K address range RAND Subroutine returns RETI Interrupt returns AJMP addr11 Absolute transfer within 2K address range LJMP add r16 Long transfer within 64K address range SJMP...

  • Page 232: Version Revision Notes

    CMS8S78xx Reference Manual 30. Version Revision Notes The version number Time Revision content V1.00 April 2020 Initial release V1.01 August 2020 Modify the user configuration instructions V1.02 January 2023 2.3 General Data Register RAM: Modify title V1.03 January 2023 Delete UART1 chapter description V1.04 January 2023 Modify BOOT partition...

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