Cmsemicon BAT32A2 9 Series User Manual

An ultra-low-power 32-bit microcontroller based on the arm® cortex®-m0+

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BAT32A2x9 User Manual

An ultra-low-power 32-bit microcontroller based on the ARM

Rev 1.00

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BAT32A2x9 User Manual | Chapter 1 CPU

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Page 1 BAT32A2x9 User Manual | Chapter 1 CPU BAT32A2x9 User Manual An ultra-low-power 32-bit microcontroller based on the ARM Cortex -M0+ ® ® Rev 1.00 Please be reminded about following CMS’s policies on intellectual property ＊Cmsemicron Limited(denoted as ‘our company’ for later use) has already applied for relative patents and entitled legal rights. Any patents related to CMS’s MCU or other producrts is not authorized to use.
Page 2: Documentation Instructions
BAT32A2x9 User Manual | Chapter 1 CPU Documentation Instructions This manual is a technical reference manual for BAT32A239/BAT32A279 microcontroller products, and the technical reference manual is an application note on how to use this series of products, including the structure, functional description, and function description of each functional module.
Page 3 BAT32A2x9 User Manual | Chapter 1 CPU BAT32A2x9 User Manual Chapter List BAT32A239xx BAT32A279xx ● ● Chapter 1: CPU ● ● Chapter 2: Pin Functions ● ● Chapter 3: System structure ● ● Chapter 4: Clock generation circuit ● ● Chapter 5: Hardware Divider ●...
Page 4: Table Of Contents
BAT32A2x9 User Manual | Chapter 1 CPU Index Documentation Instructions ..........................2 Chapter 1 CPU ..............................25 overview ............................25 Cortex-M0+ core features ......................25 Debug features ..........................25 SWD interface pin .......................... 27 ARM reference documentation ...................... 28 Chapter 2 Pin function ............................. 29 Port capabilities ..........................
Page 5 BAT32A2x9 User Manual | Chapter 1 CPU Control Registers of the clock generation circuit ................78 4.3.1 Clock operating mode control register (CMC)................78 4.3.2 System Clock Control Register (CKC)..................80 4.3.3 Clock Operating State Control Register (CSC)................ 81 4.3.4 PLL Control Register (PLLCR) for System Clock ..............
Page 6 BAT32A2x9 User Manual | Chapter 1 CPU Features ............................129 Feature description ........................129 Registers for the hardware divider ....................129 5.3.1 DIVIDEND ..........................130 5.3.2 Divider (DIVISAR) ........................130 5.3.3 Quotient ..........................130 5.3.4 REMAINDER .......................... 130 5.3.5 Status register (STATUS) ....................... 131 Chapter 6 Universal timer unit Timer4/8 ......................
Page 7 BAT32A2x9 User Manual | Chapter 1 CPU The operation of the counter ....................... 172 6.5.1 Count clock (f TCLK )....................... 172 6.5.2 The start timing of the counter ....................174 6.5.3 The operation of the counter ....................175 Control of the channel output (TOmn pin)................... 180 6.6.1 Structure of the TOmn pin output circuit .................
Page 8 BAT32A2x9 User Manual | Chapter 1 CPU Operation of timer A ........................245 7.4.1 Overrides to reload registers and counters ................245 7.4.2 Timer mode ..........................246 7.4.3 Pulse output mode ........................247 7.4.4 Event counter pattern ......................248 7.4.5 Pulse width measurement mode ....................
Page 9 BAT32A2x9 User Manual | Chapter 1 CPU 8.4.3 Timer mode (output comparison function)................282 8.4.4 PWM mode ..........................286 8.4.5 Phase count mode ........................290 Timer B interrupt .......................... 293 Considerations when using timer B ..................... 295 8.6.1 Phase difference, overlap, and pulse width in phase count mode ......... 295 8.6.2 Switching modes ........................
Page 10 BAT32A2x9 User Manual | Chapter 1 CPU 10.3.2 Timer M EVENTC register (TMELC)..................318 10.3.3 Timer M Start Register (TMSTR).................... 319 10.3.4 Timer M mode register (TMMR)..................... 320 10.3.5 Timer M PWM function select register (TMPMR)..............321 10.3.6 Timer M function control register (TMFCR).
Page 11 BAT32A2x9 User Manual | Chapter 1 CPU 10.7.5 Configuration steps (i=0, 1) for TMIOAi, TMIOBi, TMIOCi, TMIODi pins ......402 10.7.6 External clock TMCLK ......................403 10.7.7 Complementary PWM mode ....................403 10.8 PWMOP ............................408 10.8.1 Features of PWMOP ....................... 409 10.8.2 Registers for PWMOP ......................
Page 12 BAT32A2x9 User Manual | Chapter 1 CPU 12.3.1 Peripheral enable register 0 (PER0)..................464 12.3.2 Real-time clock selection register (RTCCL)................465 12.3.3 Control Register (ITMC) for 15-bit interval timers ..............466 12.4 15-bit interval timer operation ...................... 467 12.4.1 Operation sequence of the 1 5-bit interval timer ..............
Page 13 BAT32A2x9 User Manual | Chapter 1 CPU 15.2.7 12-bit A/D conversion result register (ADCR)................ 498 15.2.8 8-bit A/D conversion result register (ADCRH)................ 499 15.2.9 The conversion result compares the upper limit value of the set register (ADUL)....500 15.2.10 The conversion results compare the lower limit value set register (ADLL).
Page 14 BAT32A2x9 User Manual | Chapter 1 CPU 16.3.5 Registers that control the function of the analog input pin port ..........529 16.4 Operation of the D/A converter ....................530 16.4.1 Normal mode of operation ...................... 530 16.4.2 Operation of real-time output mode ..................531 16.4.3 The output timing of the D/A conversion values ..............
Page 15 BAT32A2x9 User Manual | Chapter 1 CPU 19.1 Functions of the Universal Serial Communication Unit ............... 563 19.1.1 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) .. 563 19.1.2 UART (UART0～UART3) ....................... 564 Simple I 2 C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) ........565 19.1.3 19.2 The structure of a universal serial communication unit ...............
Page 16 BAT32A2x9 User Manual | Chapter 1 CPU Processing steps when an error occurs during communication ............. 649 19.6 The operation of the clock synchronization serial communication of the slave selection input function 650 19.6.1 Slave sending ......................... 653 19.6.2 Slave receive .......................... 663 19.6.3 Slave sending and receiving ....................
Page 17 BAT32A2x9 User Manual | Chapter 1 CPU 20.2.9 Ack generation circuit, stop condition detection circuit, start condition detection circuit, Ack detection circuit............................734 20.2.10 Data hold time correction circuit ..................... 734 20.2.11 Start conditional generation circuitry ..................734 20.2.12 Stop condition generation circuitry ..................734 20.2.13 Bus status detection circuitry ....................
Page 18 BAT32A2x9 User Manual | Chapter 1 CPU 21.1 The serial interface SPI functions ....................817 21.2 Structure of the serial interface SPI ..................... 817 21.3 Registers that control the serial interface SPI ................818 21.3.1 Peripheral enable register 2 (PER2)..................819 21.3.2 SPI Operating Mode Register (SPIMn).
Page 19 BAT32A2x9 User Manual | Chapter 1 CPU 22.6 Bit setting/clear function ......................884 22.7 Control registers .......................... 885 22.7.1 Peripheral clock selection register (PER0/PER2)..............885 22.7.2 CAN Global Module Control Register (CnGMCTRL)............. 886 22.7.3 CAN Global Module Clock Selection Register (CnGMCS)............ 888 22.7.4 CAN Global Automatic Block Transfer Control Register (CnGMABT).
Page 20 BAT32A2x9 User Manual | Chapter 1 CPU 22.9.5 Multi-buffer receive block capability ..................930 22.9.6 Remote frame reception ......................931 22.10 Message sending......................... 932 22.10.1 Message sending ........................932 22.10.2 Send history list function ......................934 22.10.3 Automatic Block Transfer (ABT)..................... 936 22.10.4 Transfer abort processing .......................
Page 21 BAT32A2x9 User Manual | Chapter 1 CPU 23.4.4 Read from the LCD bus ......................995 23.4.5 Write-read-write timing on the LCD bus .................. 997 23.5 Note for LCD bus interfaces ......................998 23.5.1 Write to lbDATA/LBDATAL registers..................998 23.6 Example of LCD bus interface transmission ................999 23.6.1 Example of transmission with an external LCD driver ............
Page 22 BAT32A2x9 User Manual | Chapter 1 CPU 25.2 Structure of EVENTC ........................ 1042 25.3 Control registers ........................1043 25.3.1 Output target selection register n(ELSELRn) (n=00~22)............. 1044 25.4 Operation of EVENTC ....................... 1047 Chapter 26 Interrupt function ......................1049 26.1 The types of interrupt function ....................
Page 23 BAT32A2x9 User Manual | Chapter 1 CPU 31.1 The function of the voltage detection circuit ................1092 31.2 Structure of the voltage detection circuit ................... 1093 31.3 Control Registers of the voltage detection circuit ..............1094 31.3.1 Voltage Sense Register (LVIM).................... 1094 31.3.2 Voltage Sense Level Register (LVIS).
Page 24 BAT32A2x9 User Manual | Chapter 1 CPU 34.3 The format of the flash data protection option bytes ..............1138 Chapter 35 FLASH control ......................1139 35.1 FLASH control function description ................... 1139 35.2 FLASH memory structure ......................1140 35.3 Controls registers of F LASH ..................... 1141 35.3.1 Flash Write Protection Register (FLPROT).
Page 25: Chapter 1 Cpu
BAT32A2x9 User Manual | Chapter 1 CPU Chapter 1 CPU 1.1 overview This section briefly introduces the features and debugging features of the ARM Cortex-M0+ core mounted on the BAT32A2x9 product, please refer to the ARM related documents for details. 1.2 Cortex-M0+ core features ⚫...
Page 26 BAT32A2x9 User Manual | Chapter 1 CPU Debug block diagram of Cortex-M0+ Figure 1-1 MCU debug support Cortex - M0+ debug support Cortex - M0+ system bus core bus matrix Bridge SWDIO SW - DP AHB - AP SWCLK NVIC DBGMCU Note: SWD does not work in Deep Sleep mode, please debug in active and sleep modes.
Page 27: Swd Interface Pin
BAT32A2x9 User Manual | Chapter 1 CPU 1.4 SWD interface pin The 2 GPIOOs of this product can be used as SWD interface pins, which are present in all packages. Table 1-1 SWD debug port pins SWD port name Debugging features Pinout SWCLK Serial clock...
Page 28: Arm Reference Documentation
BAT32A2x9 User Manual | Chapter 1 CPU 1.5 ARM reference documentation The debugging features built into the Cortex-M0®+ core are part of the ARM® CoreSight design suite. For related documents, please refer to: Cortex-M0®+ Technical Reference Manual (TRM) ⚫ ARM® debug interface V5 ⚫...
Page 29: Chapter 2 Pin Function
BAT32A2x9 user manual | Chapter 2 Pin function Chapter 2 Pin function 2.1 Port capabilities Refer to datasheet for each product range. 2.2 Port multiplexing function Refer to datasheet for each product range. 29 / 1149 Rev.1.00 www.mcu.com.cn...
Page 30: Registers That Control Port Functionality
BAT32A2x9 user manual | Chapter 2 Pin function 2.3 Registers that control port functionality • Control the ports through the following registers. • Port Mode Register (PMxx). • Port register (Pxx). • Port Set control register (PSETxx). • Port Clearing Control Register (PCLRxx). •...
Page 31 BAT32A2x9 user manual | Chapter 2 Pin function Table 2-1 Registers assigned by product and their bits (2/3). Bit name 64 Pins Pin (-A) PMxx PSETxx PCLRxx PUxx PIMxx POMxx PMCxx PREADxx (-A) Note port Pins Pins Pins Pins Note register register register...
Page 32 BAT32A2x9 user manual | Chapter 2 Pin function Table 2-1 Registers assigned by product and their bits (3/3). Bit name Pins port Pins PMxx PSETxx PCLRxx PUxx PIMxx POMxx PMCxx PREADxx Pins (-A) Pins Pins register register register register register register register register...
Page 33: Port Mode Register (Pmxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.1 Port Mode Register (PMxx). This is the register that sets the port input/output in bits. After generating a reset signal, the values of these registers become "FFH". When using a port pin as a pin for the multiplexing function, it must be set with reference to "2.5 Register Settings When Using the Multiplexing Function".
Page 34: Port Register (Pxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.2 Port register (Pxx). This is the register that sets the value of the port output latch in bits. The pin level is read in input mode and the value of the port's output latch is read in output mode. After generating a reset signal, the value of these registers changes to "00H".
Page 35: Port Set Control Register (Psetxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.3 Port Set Control Register (PSETxx) This is the register that sets the port output latch in bits. After generating a reset signal, the values of these registers become "0000H". Register address = base address + offset address; The base address of the port position control register is 0x40040000, and the offset address is shown in the figure below.
Page 36: Port Clear Control Register (Pclrxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.4 Port Clear Control Register (PCLRxx) This is the register that sets the port output latch in bits. After generating a reset signal, the values of these registers become "0000H". Register address = base address + offset address; The base address of the port zeroing control register is 0x40040000, and the offset address is shown in the figure below.
Page 37: Pull-Up Resistor Selection Register (Puxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.5 Pull-up resistor selection register (PUxx). Select register for internal pull-up resistors. The internal pull-up resistor can only be specified for pins that use an internal pull-up resistor through the pull-up resistor selection register and the POMmn bit is "0" and set to the input mode (PMmn=1), and the internal pull-up resistor is used in bits.
Page 38: Port Input Mode Register (Pimxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.6 Port input mode register (PIMxx). This is the register that sets the input buffer in bits. When communicating serially with external devices with different voltage level, the TTL input buffer can be selected. After generating a reset signal, the value of these registers changes to "00H".
Page 39: Port Output Mode Register (Pomxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.7 Port output mode register (POMxx). This is the register that sets the output mode in bits. When communicating serially with external devices with different voltage level and simple I2C communication with external devices with the same voltage level , the SDAxx pin can be selected for an N-channel open-drain output mode.
Page 40: Port Mode Control Register (Pmcxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.8 Port Mode Control Register (PMCxx). The PMC registers configure digital inputs/outputs or analog inputs setting in bits. After generating a reset signal, the values of these registers become "FFH". Register address = base address + offset address; The base address of the PMC register is 0x40040000, and the offset address is shown in the figure below.
Page 41: Port Read-Back Register (Preadxx)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.9 Port read-back register (PREADxx). This is a read-only register that can be read to get the port level when the port is an ordinary digital GPIO. Register address = base address + offset address; The base address of the port register is 0x40040000, and the offset address is shown in the figure below.
Page 42: Peripheral I/O Redirect Register 0 (Pior0)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.10 Peripheral I/O redirect register 0 (PIOR0). This is register 0 that is set to allow or disable peripheral I/O redirection. The peripheral I/O redirection feature switches ports that are assigned a multiplexing function. After generating a reset signal, the value of this register changes to "00H".
Page 43: Peripheral I/O Redirect Register 1 (Pior1)
BAT32A2x9 user manual | Chapter 2 Pin function INTP1 INTP2 INTP3 bit0 (PIOR00) must be set to 0 (initial value) INTP4 INTP8 INTP9 2.3.11 Peripheral I/O redirect register 1 (PIOR1) This is set to allow or disable peripheral I/O redirection function register 1. The peripheral I/O redirection feature switches ports that are assigned a multiplexing function.
Page 44: Peripheral I/O Redirect Register 2 (Pior2)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.12 Peripheral I/O redirect register 2 (PIOR2) This is set to allow or disable peripheral I/O redirection function register 2. The peripheral I/O redirection feature switches ports that are assigned a multiplexing function. After generating a reset signal, the value of this register changes to "00H".
Page 45: Peripheral I/O Redirect Register 3 (Pior3)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.13 Peripheral I/O redirect register 3 (PIOR3) This is set to allow or disable peripheral I/O redirection function register 3. The peripheral I/O redirection feature switches ports that are assigned a multiplexing function. After generating a reset signal, the value of this register changes to "00H".
Page 46: Peripheral I/O Redirect Register 4 (Pior4)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.14 Peripheral I/O redirect register 4 (PIOR4) This is set to allow or disable peripheral I/O redirection function register 4. The peripheral I/O redirection feature switches ports that are assigned a multiplexing function. PIOR4 is only used for port redirection switching for 100pin products.
Page 47: Global Digital Input Disable Register (Gdidis)
BAT32A2x9 user manual | Chapter 2 Pin function 2.3.15 Global Digital Input Disable Register (GDIDIS) When powering off the EV , this register prevents the input buffer from leakage current for the input port that is powered from the EV .
Page 48: Unused Pin Handling
BAT32A2x9 user manual | Chapter 2 Pin function 2.4 Unused pin handling The handling of each unused pin is shown in the following table. Table2-2 Handling of each unused pin Pin name Input/Output The recommended connection method when not in use P00～P06 Input : Separately connect the EV or EV...
Page 49: Register Settings When Using The Multiplexing Function
BAT32A2x9 user manual | Chapter 2 Pin function 2.5 Register settings when using the multiplexing function 2.5.1 Basic principle when using the multiplexing feature First, pins that are multiplexed with analog functions must be set via the Port Mode Control Register (PMCxx) whether they will be used as analog functions or as digital inputs/outputs.
Page 50: Examples Of Register Settings Using The Port Function And The Multiplexing Function
BAT32A2x9 user manual | Chapter 2 Pin function 2.5.2 Examples of register settings using the port function and the multiplexing function Examples of register settings (100-pin articles) used for the port function and multiplexing function are shown in the following table. Table2-4 function register settings example The output of the multiplexing Features used...
Page 51 BAT32A2x9 user manual | Chapter 2 Pin function ― ― ― output DBRDB=1 TO17=0 PIOR01=1, PIOR41=0 ― ― ― ― (INTP10) input × PIOR07=0 ― ― ― ― TI17 input PIOR47=0 × ― ― ― output TO17 PIOR47=0 DBRDB=1 ― ―...
Page 52 BAT32A2x9 user manual | Chapter 2 Pin function Features used The output of the multiplexing function PIORx POMxx PMCxx PMxx The output function name Feature Outside of SCI/CAN Input/Output of SCI/CAN name ― ― ― ― ― input × ― ―...
Page 53 BAT32A2x9 user manual | Chapter 2 Pin function ― ― ― ― (INTP5) input PIOR04=1 × The output of the multiplexing Features used function The output name PIORx POMxx PMCxx PMxx Feature Outside of function of Input/Output name SCI/CAN SCI/CAN ―...
Page 54 BAT32A2x9 user manual | Chapter 2 Pin function The output of the multiplexing Features used function The output function of name PIORx POMxx PMCxx PMxx Feature Outside of Input/Output SCI/CAN name SCI/CAN ― ― ― ― ― input × TO01=0, ―...
Page 55 BAT32A2x9 user manual | Chapter 2 Pin function Features used Pins PMCxx PMxx name PIORx Feature Input/Output name ― input × ― output ― ANI0 Analog input × ― Reference input × REFP ― Analog input × VCIN12 (INTP11) input PIOR07=1, PIOR41=0 ―...
Page 56 BAT32A2x9 user manual | Chapter 2 Pin function Features used The output of the multiplexing function name Feature PIORx POMxx PMCxx PMxx The output function of Input/Output Outside of SCI/CAN name SCI/CAN ― ― ― ― input × × ― output RTC1HZ=0, ―...
Page 57 BAT32A2x9 user manual | Chapter 2 Pin function The output of the multiplexing Features used function name PIORx POMxx PMCxx PMxx Feature The output function of Input/Output Outside of SCI/CAN name SCI/CAN ― ― ― ― ― input × (TxD0)=1 ―...
Page 58 BAT32A2x9 user manual | Chapter 2 Pin function The output of the multiplexing Features used function Pin name PIORx POMxx PMCxx PMxx Feature The output function of Outside of Input/Output name SCI/CAN SCI/CAN ― ― ― ― input × × ―...
Page 59 BAT32A2x9 user manual | Chapter 2 Pin function ― ― ― output PIOR46=1 ― ― ― output (SCL31) PIOR46=1 The output of the multiplexing Features used function PIORx name POMxx PMCxx PMxx The output function of Outside of Feature name Input/Output SCI/CAN SCI/CAN ―...
Page 60 BAT32A2x9 user manual | Chapter 2 Pin function The output of the multiplexing Features used function name The output function of Outside of PIORx POMxx PMCxx PMxx Feature Input/Output SCI/CAN SCI/CAN name ― ― ― ― ― input × N-channel open-drain ―...
Page 61 BAT32A2x9 user manual | Chapter 2 Pin function Features used The output of the multiplexing function PIORx POMxx PMCxx PMxx name Feature The output function of Input/Output Outside of SCI/CAN name SCI/CAN ― ― ― ― ― input × ― ―...
Page 62 BAT32A2x9 user manual | Chapter 2 Pin function ― ― ― ― ― input × PIOR01=0, ― ― ― ― input PIOR07=0 × INTP11 PIOR41=0 ― ― ― ― output (TxD2/IrTxd) PIOR01=1 62 / 1149 Rev.1.00 www.mcu.com.cn...
Page 63 BAT32A2x9 user manual | Chapter 2 Pin function Features used The output of the multiplexing function name Feature PIORx POMxx PMCxx PMxx The output function of Input/Output Outside of SCI/CAN name SCI/CAN ― ― ― ― input × × ― output ―...
Page 64 BAT32A2x9 user manual | Chapter 2 Pin function The output of the multiplexing Features used function name PIORx POMxx PMCxx PMxx Feature The output function of Outside of Input/Output name SCI/CAN SCI/CAN ― ― ― ― input × P100 ― ―...
Page 65 BAT32A2x9 user manual | Chapter 2 Pin function Features used Pin name Feature Input/Output (EXCLK, OSCSEL, EXCLKS, OSCSELS) name P121 input 00xx/10xx/11xx × P121 ― ― 01xx input × P122 00xx/10xx/11xx ― ― P122 01xx ― input EXCLK 11xx input ×...
Page 66 BAT32A2x9 user manual | Chapter 2 Pin function Features used The output of the multiplexing function name PIORx POMxx PMCxx PMxx Feature Input/Outpu The output function of Outside of SCI/CAN name SCI/CAN ― ― ― ― ― input × P140 ―...
Page 67 BAT32A2x9 user manual | Chapter 2 Pin function ― ― ― ― output Analog ― ― ― ― × ANI12 input Analog ― ― ― ― × VREF0 input 67 / 1149 Rev.1.00 www.mcu.com.cn...
Page 68 BAT32A2x9 user manual | Chapter 2 Pin function Features used Pin name PIORx PMCxx PMxx Feature Input/Output name ― input × P150 ― output P150 ― Analog input × ANI17 ― input × P151 ― P151 output ― ANI18 Analog input ×...
Page 69: Chapter 3 System Structure
BAT32A2x9 user manual | Chapter 3 System structure Chapter 3 System structure 3.1 overview This product system consists of the following parts: 2 AHB bus Master: ⚫ - Cortex-M0+ - Enhanced DMA 4 AHB Bus Slaves: ⚫ - FLASH memory - SRAM memory 0 - SRAM memory 1 - AHB to APB Bridge, which contains all APB interface peripherals...
Page 70: System Address Partition
BAT32A2x9 user manual | Chapter 3 System structure 3.2 System address partition Figure 3-2 Schematic diagram of address area partition (BAT32A239). FFFF_FFFFH reserve E00F_FFFFH Cortex-M0+ specific resource region for peripherals E000_0000H reserve 4005_FFFFH resource region for peripherals 4000_0000H reserve 2000_7FFFH SRAM 32KB 2000_0000H...
Page 71 BAT32A2x9 user manual | Chapter 3 System structure Figure 3-3 Schematic diagram of address area partition (BAT32A279). FFFF_FFFFH reserve E00F_FFFFH Cortex-M0+ specific resource region for peripherals E000_0000H reserve 4005_FFFFH resource region for peripherals 4000_0000H reserve 2000_FFFFH SRAM 64KB 2000_0000H reserve 0050_4FFFH data flash 20KB...
Page 72: Peripheral Address Assignment
BAT32A2x9 user manual | Chapter 3 System structure 3.3 Peripheral address assignment Register group start addresses for peripherals Table 3-1 The start address peripheral remark 0x4000_5000-0x4000_5FFF 0x4000_6000-0x4000_6FFF Interrupt control 0x4001_8000-0x4001_9FFF SRAM 0x4001_A000-0x4001_AFFF 0x4001_B000-0x4001_BFFF DBGREG 0x4002_0000-0x4002_03FF FLASH control 0x4002_0400-0x4002_0FFF Clock control 0x4002_1000-0x4002_1001 Watchdog timer 0x4002_1002-0x4002_1800...
Page 73: Chapter 4 Clock Generation Circuit
BAT32A2x9 user manual | Chapter 4 Clock generation circuit Chapter 4 Clock generation circuit 4.1 Function of the clock generation circuit A clock generation circuit is a circuit that generates a clock to the CPU and peripheral hardware. There are three types of system clock and clock oscillation circuits.
Page 74 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Subsystem clock • XT1 oscillation circuit The clock oscillation of f =32.768kHz can be made by connecting a 32.768kHz resonator to the XT1 pin and the XT2 pin, and it can be set by XTSTOP bit (bit6 of the clock operating state control register (CSC)) to stop the oscillation.
Page 75: Structure Of The Clock Generation Circuit
BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.2 Structure of the clock generation circuit The clock generation circuit consists of the following hardware. Table 4-1 Structure of the clock generation circuit project structure Clock operating mode control register (CMC). System Clock Control Register (CKC).
Page 76 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-1 diagram of the clock generation circuit 76 / 1149 Rev.1.00 www.mcu.com.cn...
Page 77 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Remark: : X1 clock oscillation frequency HOCO : Clock frequency of high-speed internal oscillator (max. 64MHz). : Clock frequency of high-speed internal oscillator (max. 64MHz). : External master system clock frequency : High speed system clock frequency : The master system clock frequency MAIN...
Page 78 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3 Control Registers of the clock generation circuit The clock generation circuit is controlled by the following registers. • Clock Run Mode Control Register (CMC). • System Clock Control Register (CKC). •...
Page 79 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-2 Format of Clock operating mode control register (CMC) Address: 40020400H after reset: 00HR/W SYMBOL EXCLK OSCSEL EXCLKS Note OSCSELS Note AMPHS1 Note AMPHS0Note AMPH Operating mode of the high- X1/P121 pin X2/EXCLK/P122 pins EXCLK...
Page 80 BAT32A2x9 user manual | Chapter 4 Clock generation circuit (CKC). 4.3.2 System Clock Control Register This is the register that selects the CPU/peripheral hardware clock and the master system clock. The CKC register is set by the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H".
Page 81 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.3 Clock Operating State Control Register (CSC). This is the register that controls the operation of the high-speed system clock, the high-speed internal oscillator clock, and the sub-system clock (except for the low-speed internal oscillator clock). Set the CSC registers via the 8-bit memory operation instructions.
Page 82 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.4 PLL Control Register (PLLCR) for System Clock This is the register that the control system clock runs with the PLL. Set the PLLCR registers via the 8-bit memory operation instructions. After the reset signal is generated, the value of this register becomes "00H".
Page 83 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.5 The state register (OSTC) of the oscillation settling time counter This is a register that represents the oscillation settling time counter count state of the X1 clock. The oscillation settling time of the X1 clock can be confirmed in the following cases: •...
Page 84 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-7 The format of the state register (OSTC) of the oscillation settling time counter Address: 40020402H after reset: 00H SYMBOL OSTC MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 Oscillation steady time state MOST MOST MOST...
Page 85 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.6 Oscillation settling time selection register (OSTS). This is the register that selects the oscillation settling time of the X1 clock. If the X1 clock oscillates, the time to automatically wait for the OSTS register to be set just after the X1 oscillation circuit runs (MSTOP=0).
Page 86 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.7 Peripheral enable registers 0, 1, 2, 3 (PER0, PER1, PER2, P ER2 PER3) This is the register that the setting enable or disables the provision of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use.
Page 87 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-9 The format of Peripheral enable register 0 (PER0) (2/3). Address: 40020420H After reset: 00H R/W SYMBOL PER0 IICA0ANDN BTIIN ADCIN SCI1IN SCI0EN CAN0EN TM40In Provides control of the input clock of the A/D converter ADCEN Stop providing the input clock.
Page 88 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-9 The format of Peripheral enable register 0 (PER0) (3/3). Address: 40020420H After reset: 00H R/W Symbol PER0 IICA0EN RTCEN ADCIN SCI1IN SCI0EN CAN0EN TM40EN Provides control of the input clock of the CAN module CAN0EN Stop providing the input clock.
Page 89 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Provides control of the input clock of timer M TMMEN Stop providing the input clock. • SFR cannot be written to timer M. • Timer M is in reset state. An input clock is provided. •...
Page 90 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-11 The format of Peripheral enable register 2 (PER2) (1/2). Address: 4002081BH reset: 00H R/W symbol PER2 OSDCIN SPIHS1EN SPIHS0EN CAN2EN SCI2EN IICA1 CAN1IN TM81EN OSDCIN Control of the input clock that provides a clock stop detection function Stop providing the input clock.
Page 91 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-11 The format of Peripheral enable register 2 (PER2) (2/2). Address: 4002081BH reset: 00H R/W Symbol PER2 OSDCIN SPIHS1EN SPIHS0EN CAN2EN SCI2EN IICA1 CAN1IN TM81EN Provides control of the input clock of the CAN2 module CAN2EN Stop providing the input clock.
Page 92 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.8 Subsystem clock supply mode control register (OSMC). OSMC registers are registers that reduce power consumption by stopping unwanted clock functions. If the RTCLP position is "1", the clock is stopped in deep sleep mode or the CPU running in a sleep mode with a sub-system clock for peripheral functions other than the real-time clock and the 15-bit interval timer, thus reducing power consumption.
Page 93 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.9 Frequency Selection Register (HOCODIV) for high-speed internal oscillators This is the register for changing the high-speed internal oscillator frequency set by option byte (000C2H). However, the frequency that can be selected varies depending on the value of the FRQSEL4 bit and FRQSEL3 bit of the option byte (000C2H).
Page 94 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.10 Trimming Register (HIOTRM) for high-speed internal oscillator This is a register that corrects for the accuracy of the high-speed internal oscillator. Self-measurement and accuracy correction of high-speed internal oscillator frequency can be performed using a timer with a high-precision external clock input, etc.
Page 95 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.11 Subsystem Clock Select Register (SUBCKSEL) The SUBCKSEL register is a register that selects the subsystem clock f and the low-speed internal oscillator clock , as well as the low-speed internal oscillator clock frequency. Set the SUBCKSEL registers with 8-bit memory operation instructions.
Page 96 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.3.12 Master System Clock Control Register (MCKC). MCKC registers are registers used to control the clock of the main system. The MCKC register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H".
Page 97 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.4 System clock oscillation circuit 4.4.1 X1 oscillation circuit The X1 oscillation circuit oscillates by connecting a crystal resonator or ceramic resonator (1 to 20 MHz) connected to pins X1 and X2. An external clock can also be input, in which case a clock signal must be input to the EXCLK pin.
Page 98 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Fig. 4-19 XT1 oscillation circuit external circuit example (a) Crystal oscillation (b) external clock 32.768 External clock EXCLKS Note that when using the X1 oscillation circuit and the XT1 oscillation circuit, in order to avoid the influence of the wiring capacitance, etc., the Fig.
Page 99 BAT32A2x9 user manual | Chapter 4 Clock generation circuit An example of an incorrect resonator connection is shown in Figure Figure 4-20. Figure 4-20 Example of incorrect resonator connection (1/2). (a) The wiring connecting the circuit is too long (b) the signal line crosses PORT (c) Signal lines X1 and X2 cross-routing...
Page 100 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-15 Example of incorrect resonator connection (2/2). (f) Current flows along grounding of oscilation circuit (e) varying high current source close to singal lines (Point A, B, C has difference in electric potential) high current (g) extracted signal Note that when the X2 and XT1 are routed in parallel, the crosstalk noise of the X2 will be superimposed on the XT1 and...
Page 101 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.4.3 High-speed internal oscillator The BAT32A279 has a built-in high-speed internal oscillator. Can choose the frequency from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, 2MHz and 1MHz via option byte ( 000C2H). Oscillation can be controlled by bit0 (HIOSTOP) of the clock operating state control register (CSC).
Page 102 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.5 Clock generation circuit operation The clock generation circuit generates the various clocks shown below and controls the operating mode of the CPU such as standby mode (see Figure Figure 4-1). ...
Page 103 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Figure 4-21 The clock generation circuit is running when the power is turned on at least 10us low limit of working voltage range voltage of power source (V power on reset signal RESETB pin switching via reset...
Page 104 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.6 Clock control 4.6.1 Example of setting up a high-speed internal oscillator After the reset is released, the CPU/Peripheral Hardware Clock (f ) must be running at a high-speed internal oscillator clock. It can pass the FRQSEL0~FRQSEL4 bits of the option byte (000C2H) from 64MHz, 48MHz, and 32MHz , 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz , 3MHz, 2MHz, and 1MHz to select the frequency of the high-speed internal oscillator.
Page 105 BAT32A2x9 user manual | Chapter 4 Clock generation circuit [Setting of the Frequency Selection Register (HOCODIV) of the high-speed internal oscillator]. Address: 0x40021C20 SYMBOL HOCODIV HOCODIV2 HOCODIV1 HOCODIV0 Selection of high-speed internal oscillator clock frequency FRQSEL4=0 FRQSEL4=1 HOCODIV2 HOCODIV1 HOCODIV0 FRQSEL3=0 FRQSEL3=1 FRQSEL3=0...
Page 106 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.6.2 Example of setting up the X1 oscillation circuit After the reset is released, the CPU/Peripheral Hardware Clock (f ) must be running at a high-speed internal oscillator clock. Thereafter, if the oscillation clock is changed to X1, the oscillation circuit is set and the oscillation start is controlled by the oscillation settling time selection register (OSTS), the clock operation mode control register (CMC), and the clock operating state control register (CSC).
Page 107 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.6.3 Example of setting up the XT1 oscillation circuit After the reset is released, the CPU/Peripheral Hardware Clock (f ) must be running at a high-speed internal oscillator clock. Thereafter, if the XT1 oscillation clock is changed, the mode control register (OSMC), clock operating mode control register (CMC), and clock operating state control register (CSC) are provided through the sub-system clock The oscillation circuit is set up and the oscillation start is controlled, and the XT1 oscillation clock is set to f...
Page 108 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.6.4 State transition graph of the CPU clock The CPU clock state transition diagram of this product is shown in Figure 4-22. Figure 4-22 State transition diagram of the CPU clock Power on X1 oscilation / EXCLK input: stop (input port mode) XT1 oscilation / EXCLKS input: stop (input port mode)
Page 109 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Examples of CPU clock transfers and SFR register settings are shown in Table 4-3. Table 4-3 Example of CPU clock transfer and SFR register setting (1/5). (1) After reset released (A), the CPU moves to high-speed internal oscillator clock operation (B). State transition Settings for the SFR registers (A) (B)
Page 110 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Table 4-3 Example of CPU clock transfer and SFR register setting (2/5). (4) The CPU shifts from high-speed internal oscillator clock operation (B) to high-speed system clock operation (C). (SFR registers are set in order). Setting flag for the SFR register Note 1 CMC register...
Page 111 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Table 4-3 Example of CPU clock transfer and SFR register setting (3/5). (6) The CPU is transferred from high-speed system clock operation (C) to high-speed internal oscillator clock operation (B). (SFR registers are set in order). CSC registers CKC registers SFR register...
Page 112 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Table 4-3 Example of CPU clock transfer and SFR register setting (4/5). (9) The CPU shifts from subsystem clock operation (D) to high-speed system clock operation (C). (SFR registers are set in order). CSC registers CKC registers Setting flag for the SFR...
Page 113 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Table 4-3: CPU Clock Transfer and SFR Register Setting Example (5/5). (11) • The CPU is transferred to deep sleep mode (H) during high-speed internal oscillator clock operation (B). • The CPU is transferred to deep sleep mode (I) during high-speed system clock operation (C). (Set Order) State transition Content of configuration...
Page 114 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.6.5 Conditions before CPU clock transfer and processing after transfer The conditions before the CPU clock shift and the processing after the transfer are as follows. Table 4-4 the transfer of CPU clocks (1/2). CPU clock Conditions before transfer Treatment after transfer...
Page 115 BAT32A2x9 user manual | Chapter 4 Clock generation circuit Table 4-4 on the transfer of CPU clocks (2/2). CPU clock Treatment after Before After Conditions before transfer transfer transfer transfer High-speed The high-speed internal oscillator is oscillating internal and selects high-speed internal oscillator The oscillator clock acts as the main system clock.
Page 116 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.6.6 Time required to switch between the CPU clock and the master system clock The CPU clock can be switched by setting bit6 and bit4 (CSS, MCM0) of the system clock control register (CKC)(Master system clock) Subsystem Clock) and switching of the main system clock (High Speed Internal Oscillator Clock...
Page 117 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.6.7 Conditions before clock oscillation stops The register flag settings used to stop clock oscillation (invalid external clock input) and the conditions before stopping are as follows. Table 4-8 Conditions and flag settings before clock oscillation stops Condition before clock stop (external clock input is Flag setting for SFR clock...
Page 118 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.7 High-speed internal vibration correction function 4.7.1 High-speed internal vibration self-adjustment function This function measures the frequency of the high-speed internal oscillator using the sub-system clock fSUB (32.768KHz) as the reference and corrects the frequency accuracy of the high-speed internal oscillator fHOCO in real time.
Page 119 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.7.2 Register description Table 4-10shows a list of registers used for the high-speed internal oscillation frequency correction function. Table 4-10 High-speed internal oscillation frequency correction function registers at a glance project structure Control registers High Speed Internal Vibration Frequency Correction Control Register (HOCOFC)
Page 120 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.7.3 Description of the operation 4.7.3.1 Operation summary The high-speed internal oscillation frequency correction function uses the sub-system clock (fSUB) as the reference to generate a correction period, measures the frequency of the high-speed internal oscillation, and corrects the frequency accuracy of the high-speed internal oscillation in real time.
Page 121 BAT32A2x9 user manual | Chapter 4 Clock generation circuit （1） Continuous operation mode In continuous operation mode, the high-speed internal oscillating clock frequency correction action is carried out all the time. The FCMD bit of the HOCOFC register is set to 0, which is a continuous operation mode.
Page 122 BAT32A2x9 user manual | Chapter 4 Clock generation circuit （2） Interval operation mode In interval mode, the high-speed internal oscillation clock frequency correction is performed intermittently using timer interrupts, etc. The FCMD bit of the HOCOFC register is set to 1, which is the interval operation mode.
Page 123 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.7.3.2 Operation setup process The Operation mode start/stop process is shown in the following figure when the high-speed internal oscillating clock frequency correction function is used. Figure 4-28 Operation mode setting process (example). ＜Continuous action mode＞...
Page 124 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.8 Vibration stop detection circuit 4.8.1 Vibration stops the function of the detection circuit Vibration stop detection function is to use the internal low-speed oscillation clock (fIL) to monitor the operation state of the main system clock (fmx) or the secondary system clock (fsx), in a period of time, when the action stop is detected, it is judged that the X1 vibration circuit or XT1 vibration circuit is abnormal, and the output vibration stop detection signal can be used as an interrupt signal or a reset signal.
Page 125 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.8.3 The register used by the oscillator stops detection circuit 4.8.3.1 Peripheral Enable Register 2 (PER2) When using the vibration-stop detection circuit, the BIT4 (OSDCEN) of PER2 must be set to 1. Registers are described in detail in "4.3.7Peripheral enable registers 0, 1, 2, 3 (PER0, PER1, PER2, P ER2 ”.
Page 126 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.8.3.3 Vibration Stop Detection Mode Register (SCMMD) The Oscillation Stop Detection Mode Register (SCMMD) is a register that selects the object of vibration stop detection as the primary system clock (fmx) or the secondary system clock (fsx), and whether the action after the vibration stop is detected is to generate a reset or an interrupt.
Page 127 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.8.4 The operation of the vibration stop detection circuit 4.8.4.1 The operation method of the vibration stop detection circuit 1. After the external reset is released, the master system clock (fmx)/secondary system clock (fsx) begins to vibrate.
Page 128 BAT32A2x9 user manual | Chapter 4 Clock generation circuit 4.8.5 Precautions for vibration stop detection function Vibration-stop detection circuit, used with a watchdog timer. Vibration stop detection, which can be used under any of the following conditions: When bit0 (WDSTBYON) of the option byte (00C0H), bit4 (WDTON) is 1, and bit4 (WUTMMCK0) of the OSMC register is 0;...
Page 129 BAT32A2x9 user manual | Chapter 5 Hardware divider Chapter 5 Hardware divider Hardware dividers are specific-built hardware to support high-performance computing. The hardware divider is a 32-bit signed integer divider that outputs a 32-bit signed quotient and remainder result. 5.1 Features ⚫...
Page 130 BAT32A2x9 user manual | Chapter 5 Hardware divider 5.3.1 DIVIDEND register is a register that holds the , whose value participates in division operations as a 32-bit Dividend Dividend signed integer. DIVIDEND[31:24] DIVIDEND[23:16] DIVIDEND[15:8] DIVIDEND[7:0] 5.3.2 Divider (DIVISAR) A divisor register is a register that holds a divisor whose value participates in division as a 32-bit signed integer.
Page 131 BAT32A2x9 user manual | Chapter 5 Hardware divider 5.3.5 Status register (STATUS) The status of the hardware divider can be queried through the status register, including the divide-zero flag and the BUSY flag. reserved reserved reserved DIVBYZE BUSY reserved DIVBYZERO Used to indicate the case of division by zero, updated each time the divisor register is written.
Page 132 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Chapter 6 Universal timer unit Timer4/8 This product is equipped with two universal timer units, including Timer4, containing 4 channels. Timer8, with 8 channels. The number of channels for a universal timer unit varies by product. Note: The label "m"...
Page 133 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 For details of each function, please refer to the following table. Stand-alone channel operation function Multi-channel linkage operation function • Interval timer (→reference 6.8.1). Single-trigger pulse output (→reference 6.9.1). • •...
Page 134 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.1 Functions of the universal timer unit The universal timer unit has the following functions: 6.1.1 Stand-alone channel operation function The stand-alone channel operation function is a function that can use any channel independently without being affected by the operating modes of other channels.
Page 135 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Measurement of the high and low level width of the input signal The input signal starts counting on one edge of the timer input pin (TImn) and captures the count value on the other edge, measuring the high and low level width of the input signal.
Page 136 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.1.2 Multi-channel linkage operation function The multi-channel linkage operation function is a function that combines the master channel (the reference timer of the main control period) and the slave channel (the timer that follows the operation of the master channel). The multi-channel linkage operation function can be used as the following modes.
Page 137 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Note: m: unit number (m=0,1) n: channel number (when m=0: n=0~3, m=1: n=0~7). p, q: Slave channel number (m=0Time:n＜p＜q≤ 3) (m=1Time:n＜p＜q≤7) 6.1.3 8-bit timer operation function (channel 1 and channel 3 of unit 0 only). The 8-bit timer operation function is the function of using a 16-bit timer channel as two 8-bit timer channels.
Page 138 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.2 Structure of a universal timer unit The universal timer unit consists of the following hardware. Table 6-1 Structure of the Universal Timer Unit Item structure counter Timer count register mn (TCRmn). register Timer data register mn (TDRmn).
Page 139 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 The availability of timer input/output pins for each channel of the universal timer unit varies by product. Table 6-2 Timer Input /Output Pins for Each Product The presence or absence of input/output pins for each product Channel of the timer array unit 64 pins...
Page 140 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 A block diagram of the universal timer unit is shown in Figure 6-1. Figure 6-1 Overall block diagram of universal timer unit 0 Timer clock selection register0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Timer input selection register0 (TIOS0) TIS07 TIS06 TIS05 TIS04 TOS03 TIS02 TIS01 TIS00 ）...
Page 141 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.2.1 List of general-purpose timer unit registers Unit 0 (Timer4) register base address: 0x40041C00 Offset address Register name Read-write properties Bit width Reset value 0x180 TCR00 FFFFH 0x182 TCR01 FFFFH 0x184 TCR02 FFFFH...
Page 142 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Unit 1 (Timer8) register base address: 0x40042000 Offset address Register name Read-write properties Bit width Reset value 0x180 TCR10 FFFFH 0x182 TCR11 FFFFH 0x184 TCR12 FFFFH 0x186 TCR13 FFFFH 0x188 TCR14 FFFFH 0x18A...
Page 143 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Offset address Register name Read-write properties Bit width Reset value 0x1B0 0000H 0x1B0 TE1L 0x1B2 0000H 0x1B2 TS1L 0x1B4 0000H 0x1B4 TT1L 0x1B6 TPS1 0000H 0x1B8 0000H 0x1B8 TO1L 0x1BA TOE1 0000H 0x1BA...
Page 144 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.2.2 Timer count register mn (TCRmn). The TCRmn register is a 16-bit read-only register that counts the counting clock. Increments or decrements synchronously with the rising edge of the counting clock. The operating mode is selected by the MDmn3 to MDmn0 bits of the timer mode register mn (TMRmn), and the increment and decrement counts are switched (see "6.3.3 Timer Mode Registers").
Page 145 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 As shown below, the read value of the TCRmn register varies depending on the operating mode and operating state. Table 6-3 The timer count register mn (TCRmn) read value in each operating mode The timer counts the read value of the register mn (TCRmn The value at The value at...
Page 146 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.2.3 Timer data register mn (TDRmn). This is a 16-bit register that can be used to switch between the capture function and the compare function. The operating mode is selected by the MDmn3 to MDmn0 bits of the timer mode register mn (TMRmn), and the capture function and the comparison function are switched.
Page 147 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3 Control registers of the universal timer unit The registers that control the universal timer unit are as follows: • Peripheral Enable register 0 (PER0). • Timer clock selection register m (TPSm). •...
Page 148 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.1 Peripheral enable register 0 (PER0). The PER0 register is a register that is set to enable or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use universal timer unit 0, bit0 (TM4EN) must be placed at "1".
Page 149 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.2 Timer clock selection register m (TPSm). The TPSm registers are 16-bit registers that can be supplied to each channel with 2 or 4 common operating clocks (CKm0, CKm1, CKm2,CKm3). Select CKm0 by bit3~0 of the TPSm register and CKm1 by bit7~4 of the TPSm register.
Page 150 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-6 timer clock selection register m (TPSm) (1/2). symbol TPSm Select the operating clock (CKmk) (k=0, 1). =2MHz =4MHz =8MHz =20MHz f =32MHz 2MHz 4MHz 8MHz 20MHz 32MHz 1MHz 2MHz 4MHz 10MHz...
Page 151 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-7 timer clock selection register m (TPSm) (2/2). symbol TPSm note Select for the running clock (CKm2). PRSm21 PRSm20 =2MHz =4MHz =8MHz =20MHz f =32MHz 1MHz 2MHz 4MHz 10MHz 16MHz 500kHz 1MHz...
Page 152 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.3 Timer mode register mn (TMRmn). The TMRmn register is a register that sets the operating mode of channel n, and performs the selection of the operating clock (fMCK), the selection of the counting clock, the selection of the master/slave, the selection of 16 bits/ Selection of 8-bit timers (channels 1 and 3 only), setting of start and capture triggers, selection of effective edges of timer inputs, and operating modes (Interval, Capture, Event Counter, Single Count, Capture &...
Page 153 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Note: 1. Bit11 is a read-only bit, fixed to "0", ignoring write operations. Remark: 1. Bit13, 5, 4 must be placed with "0". 2. To change the clock selected as f (change the value of the System Clock Control Register (CKC)), even if the CKSmn0 bit and CKSmn1 bits are selected, the specified operating clock (f ) or the effective edge of the input...
Page 154 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-10 timer mode register mn(TMRmn) (3/4). symbol MASTER CKSmn CKSmn CCSmn STSm STSm STSm CISm CISm RMRMN n=2,4,6 symbol CKSmn CKSmn CCSmn SPLITmn STSm STSm STSm CISm CISm RMRMN (n=1.3) symbol CKSmn...
Page 155 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-11 timer mode register mn(TMRmn) (4/4). symbol MASTER CKSmn CKSmn CCSmn STSm STSm STSm CISm CISm RMRMN n=2,4,6 symbol CKSmn CKSmn CCSmn SPLITmn STSm STSm STSm CISm CISm RMRMN (n=1.3) symbol CKSmn...
Page 156 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.4 Timer status register mn (TSRmn). The TSRmn register is a register that represents the overflow status of the channel n counter. The TSRmn register is only valid in capture mode (MDmn3~MDmn1=010B) and capture single counting mode (MDmn3~MDmn1=110B).
Page 157 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.5 Timer channel enable status register m (TEm). TEm registers are registers that indicate the Enabled or stopped states in which each channel timer operates. Each of the TEm registers corresponds to the timer channel start register m(TSm) and the timer channel stop register m(TTm).
Page 158 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.6 Timer channel start register m(TSm). The TSm register is a trigger register that initializes the timer count register mn (TCRmn) and sets the start of each channel count run. If each position is "1", the corresponding bit of the Enabled status register m (TEm) of the timer channel is placed "1".
Page 159 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.7 Timer channel stop register m(TTm). The TTm register is the trigger register that sets the stop of each channel count. If each position is "1", the corresponding bit of the Enabled status register m (TEm) of the timer channel is cleared "0".
Page 160 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.8 Timer input and output selection register (TIOS0). The TIOS0 register selects the timer inputs for Channel 0 and Channel 1 for Unit 0 and the timer output for Channel 2. The TIOS0 register is set via the 8-bit memory operation instruction. After generating the reset signal, the value of the TIOS0 register changes to "00H".
Page 161 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.9 Timer output enable register m (TOEm). ToEm registers are registers that are set to enable or disable the output of each channel timer. For channel n that enable the timer output, the value of the TOmn bit of the timer output register m(TOm) described below cannot be overridden by software, and the value reflected by the timer output function of the counting operation is from the output pin of the timer (TOmn) output.
Page 162 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.10 Timer output register m (TOm). The TOm register is a buffer register for the output of each channel timer. The values of this register are output from the output pin (TOmn) of each channel timer. The TOmn bit of this register can only be rewritten by software when the timer output (TOEmn=0) is disabled.
Page 163 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.11 Timer output level register m(TOLm). The TOLm register is the register that controls the output level of each channel timer. When the timer output (TOEmn=1) is Enabled and the multi-channel linkage operation function (TOMmn=1) is used, the timing of the setting and reset of the timer output signal reflects the inverting setting of each channel n made by this register.
Page 164 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.12 Timer output mode register m (TOMm). The TOMm register is the register that controls the output mode of each channel timer. When used as a stand- alone channel operation function, the corresponding position of the channel used is "0". When used as a multi-channel linkage operation function (PWM output, single trigger pulse output, and multiple PWM output), the corresponding position of the master channel is "0"...
Page 165 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.13 Input Select Control Register (ISC). The ISC1 bits and ISC0 bits of the ISC registers are used for the coordination of Channel 3 and the Universal Serial Communication Unit to achieve LIN-bus communication. If the ISC1 position is "1", the input signal of the serial data input pin (RxD0) is selected as the input to the timer.
Page 166 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.14 Noise filter enable registers (NFEN1/NFEN2). The NFEN1/NFEN2 registers set whether the noise filter is used for the input signal of each channel timer input pin. For pins that need to be noise-cancelling, the corresponding position "1" must be placed to make the noise filter effective.
Page 167 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.3.15 Registers that control the function of the timer input/output pin ports When using a general-purpose timer unit, control registers for port functions that are multiplexed with the target channel (port mode register (PMxx), port register (Pxx), and port mode control register (PMCxx)) must be set.
Page 168 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.4 The basic rules of the universal timer unit 6.4.1 The basic rules of the multi-channel linkage operation function The multi-channel linkage operation function is a function that combines the master channel (the reference timer that mainly counts the cycles) and the slave channel (the timer that follows the operation of the master channel), and several rules need to be observed when using it.
Page 169 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Example 1 Timer4 Channel Group 1 (multi-channel linked operation function) CK00 Channel 0: Master control Channel 1: Slave Channel Group 2 (multi-channel linked operation function) CK01 Channel 2: Master control Channel 3: Slave Example 2 Timer4...
Page 170 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.4.2 Timer channel start register m(TSm). The TSm register is a trigger register that initializes the timer count register mn (TCRmn) and sets the start of each channel count run. If each position is "1", the corresponding bit of the Enabled status register m (TEm) of the timer channel is placed "1".
Page 171 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.4.3 The basic rules for the 8-bit timer to operate the function (limited to Channel 1 and Channel 3 of Unit 0). The 8-bit timer operation function is the function of using the channel of a 16-bit timer as the channel of two 8- bit timers.
Page 172 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.5 The operation of the counter 6.5.1 Count clock (f TCLK The general-purpose timer unit's counting clock (f ) selects any of the following clocks by the CCSmn TCLK bit of the timer mode register mn (TMRmn). •...
Page 173 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Select the case where the effective edge of the input signal of the TImn pin is selected (CCSmn=1). The counting clock (fTCLK) is a signal that detects the effective edge of the input signal of the TImn pin and synchronizes with the rising edge of the next fMCK.
Page 174 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.5.2 The start timing of the counter By placing the timer channel starting the TSmn position bit of register m(TSm), the timer count register mn (TCRmn) enters the run Enabled state. The operation from the count Enabled state to the timer count register mn (TCRmn) begins to count as shown in Table 6-6.
Page 175 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.5.3 The operation of the counter The counter operation for each mode is described below. Operation of interval timer mode (1) By writing "1" to the TSmn bit, enter the run Enabled state (TEmn=1). The timer count register mn (TCRmn) remains at its initial value until a count clock is generated.
Page 176 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Note: , start trigger heartbeat, and INTMmn are synchronized to f are valid within 1 clock. The operation of the event counter pattern (1) During the run stop state (TEmn=0), the timer count register mn (TCRmn) maintains the initial value. (2) By writing "1"...
Page 177 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Operation of capture mode (interval measurement of input pulses). (1) By writing "1" to the TSmn bit, enter the run Enabled state (TEmn=1). (2) The timer count register mn (TCRmn) maintains the initial value until the count clock is generated. (3) Generate a start trigger signal by allowing the first counting clock (fMCK) after running.
Page 178 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 counting. Note: This is the timing when no noise filter is used. If a noise filter is used, edge detection is ) from the input input delayed cycles 3 to 4 cycles in total TImn .
Page 179 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Capture & Run of Single Count mode (measurement of high level width). (1) Write "1" in the TSmn bit of register m(TSm) through the given timer channel and enter the run Enabled state (TEmn=1).
Page 180 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.6 Control of the channel output (TOmn pin). 6.6.1 Structure of the TOmn pin output circuit Figure 6-31 Output circuit structure TOmn register Interrupt signal of master channel （INTTMmn） interrupt singal of slave Tomn pin channel （INTTMmp）...
Page 181 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.6.2 Output setting of the TOmn pin The steps and state changes from the initial setting of the TOmn output pin to the start of the timer run are shown below. Figure 6-32 The state change from setting the output of the timer to starting operation TCRmn Random value ( "FFFFH"...
Page 182 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.6.3 Considerations for channel output operation About the configuration changes of the TOm, TOEm, TOLm, and TOMm registers in the operation of the timer The operation of the timer (the operation of the timer count register mn (TCRmn) and the timer data register mn (TDRmn)) and the TOmn output circuit are independent of each other.
Page 183 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-34 TOmn pin at PWM output (TOMmn=1). valid voltage level valid voltage level valid voltage level initial state (initial State: low voltage level) (valid high voltage level) (initial State: high voltage level) TOmP (output)
Page 184 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Set/reset timing To achieve 0% and 100% output at PWM output, the TOmn pin/TOmn at the master channel timer interrupt (INTTMmn) will be generated through the slave channel The set timing of the bits delays by 1 count clock. When a placement condition and a reset condition occur at the same time, the reset condition takes precedence.
Page 185 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 0% runtime order of duty cycle TCLK INTTMmn master control channel internal reset signal Tomn Pin/TOmn swap swap internal reset signal delay 1 clock cycle TCRmp slave channel INTTMmp reset internal reset signal reset reset...
Page 186 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.6.4 one-time operation of the TOmn bit Like the timer channel start register m (TSm), the timer output register m (TOm) has all channel set bits (TOmn). This allows the TOmn bits of all channels to be manipulated at once. Figure 6-37 Example of one-time operation of the TO0n bit Before writing TO03...
Page 187 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.6.5 About the timer interrupt and TOmn pin output when starting to count In interval timer mode or capture mode, the MDmn0 bit of the timer mode register mn (TMRmn) is the bit that sets whether a timer interrupt occurs at the start of counting.
Page 188 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.7 Control of the timer input (TImn). 6.7.1 Structure of the TImn pin input circuit Signals from the timer input pins are fed into the timer control circuitry through a noise filter and edge detection circuitry.
Page 189 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.7.3 Considerations when operating channel input When set to not use the timer input pin, the noise filter circuit is not provided with an operating clock. Therefore, the following waiting times are required from the channel operation set to use the timer input pin to the corresponding channel operation of the set timer input pin to enable triggering.
Page 190 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.8 Stand-alone channel operation of the universal timer unit 6.8.1 Operation as an interval timer/square wave output Interval timer It can be used as a reference timer for generating INTMmn (timer interrupts) at regular intervals. The interrupt generation period can be calculated using the following calculation: The production cycle of INTTMmn (Hours interrupt) = counting clock circumference Period x (setpoint +1 for T DRmn).
Page 191 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-41 basic timing example of operation as an interval timer/square wave output (MDmn0=1). note operational clock Timer count register mn output Tomn Pin (TCRmn) control circuit Timer data register mn interrupt interrupt singal (TDRmn)
Page 192 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-43 Example of register setting content for interval timer/square wave output Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 note MDmn3 MDmn2 MDmn1 TMRmn operation mode of Channel N 000B: Interval Timer...
Page 193 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-44 the interval timer / square wave output function is in place software operation Hardware Status The input clock of the timer unit m is in a stopped supply state. (stop providing clock, cannot write registers) TAU initial The input clock of the timer unit m is in a supplied...
Page 194 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.8.2 Run as an external event counter It can be used as an event counter to count the effective edges (external events) of the detected TImn pin input and generate an interrupt if the specified count value is reached. The specified count value can be calculated using the following calculation: The specified count value = TD Rmn's value +1...
Page 195 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-46 register setting content in external event counter mode Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 note MDmn3 MDmn2 MDmn1 TMRmn operation mode of Channel N 000B: Interval Timer operation configuration when start counting 0: when start counting, not to generate INTTMmn and do not...
Page 196 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-47 The operation steps when the external event counter function is performed software operation Hardware Status The input clock of the timer unit m is in a state where supply is stopped. (stop providing clock, cannot write registers) Place the TM4 mEN location "1"...
Page 197 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.8.3 Operation as a divider It can divide the clock of the TI mn pin input and serve as a divider for the output of the TO mn pin. The divider clock frequency of the TO mn output can be calculated using the following calculation equation: •...
Page 198 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 TCRmn: Timer count register (TCRmn). TDRmn: Timer data register (TDRmn). TOmn: The TOmn pin output signal m: unit number (m=0,1) n: channel number (when m=0: n=0~3, m=1: n=0~7). Figure 6-49 an example of register settings when the divider is running (channel 0 of unit 0). (a) Timer mode register 00 (TMR00).
Page 199 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-50 Operational Steps for Frequency Divider (take channel 0 of unit 0 as an example) software operation hardware state Timer Unit 0 input clock is in stopped state (stop providing clock, not able to write into registers) Timer 4 initial set TM4mEN bit of peripheral enable register 0...
Page 200 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.8.4 Operation as input pulse interval measurements The count value can be captured at the effective edge of TImn and the interval between TImn input pulses can be measured. During the period when the TEmn bit is "1", the software operation (TSmn=1) can also be set to capture trigger, and the capture count value can also be set.
Page 201 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 TImn : The TImn pin input signal TCRmn: Timer count register mn (TCRmn). TDRmn: Timer data register mn (TDRmn). OVF: Bit 0 of the timer status register mn (TSRmn Fig. 6-52 Example of register setting value at the measurement input pulse interval (a) Timer mode register mn (TMRmn).
Page 202 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-53 Operation steps when the pulse interval measurement function is input software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers) set TM4mEN bit of peripheral enable register 0 Timer Unit m input clock is in active state, all channels Timer 4 initial...
Page 203 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.8.5 Operation as input signal high and low level width measurements support feature, ) must be Note: When used as a LIN-bus the bit1 ISC1) of the input switching control register (ISC set to "1", and in the instructions below, use RxD0 Instead of TImn.
Page 204 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-54 an example of running basic timing for input signal high and low level width measurements TSmn TEmn TImn TCRmn TDRmn 0000H INTTMmn Note: 1.m: unit number (m=0,1) n: channel number (m=0: n=0~3, m=1: n=0~7). TSmn : Bitn of the timer channel start register m(TSm Temn : The bit n of the timer channel enable the status register m(TEm...
Page 205 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-55 Example of register setting content when measuring the high and low level width of the input signal Timer mode register mn (TMRmn). CKSmn1 CKSmn0 注 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0...
Page 206 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-56 input signal when measuring the high and low level width function software operation hardware state Timer Unit 0 input clock is in stopped state (stop providing clock, not able to write into registers) Timer 4 initial set TM4mEN bit of peripheral enable register 0 (PER0) to '1' Timer Unit m input clock is in active state, all channels in configuration...
Page 207 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.8.6 Runs as a delay counter The count can be decremented by the effective edge detection (external event) of the TImn pin input and intTMmn is generated at arbitrary set intervals (Timer interrupt).
Page 208 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-58 Example of register setting value during the 58 delay counter function (a) Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn 注 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2 MDmn1 TMRmn...
Page 209 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-59 The operation steps when the delay counter function is performed software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers) set TM4mEN bit of peripheral enable register 0 Timer Unit m input clock is in active state, all channels in Timer 4 initial...
Page 210 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.9 Multi-channel linkage operation function of the universal timer unit 6.9.1 Operation as a single-trigger pulse output function Pairing the two channels enable a single-trigger pulse of any delay pulse width to be generated via the input of the TImn pin.
Page 211 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig6-60 operating as a single-trigger pulse output function master control channel (single counting mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register mn control interrupt signal (TDRmn) Noise circuit edge...
Page 212 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig6-61 an example of the basic timing of the operation of the single-trigger pulse output function TSmn TEmn TImn master FFFFH control channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp slave...
Page 213 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6-62 Example of register setting content when the single trigger pulse output function (master channel) is used (a) Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
Page 214 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6-63 Example of register settings when the pulse output function is triggered alone (slave channel). (a) Timer mode register mp (TMRmp). CKSmp1 CKSmp0 CCSmp 注 STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp0 MDmp3 MDmp2...
Page 215 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig6-64 Operating steps for single trigger pulse output function (1/2). software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers) Timer 4 initial set TM4mEN bit of peripheral enable register 0...
Page 216 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig6-65 Operating steps when the pulse output function is triggered single (2/2). set TOEmp bit (slave) to '1' (only limit to restart operation). Set TSmn bit)(master control) and TSmp bit(slave) of timer TEmn bit and Temp bit turn into '1' and master channel enter into start channel start register m(TSm) both to '1'.
Page 217 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.9.2 Operates as a PWM function Pairing 2 channels generates pulses of any period and duty cycle. The period and duty cycle of the output pulse can be calculated using the following calculation equation: Pulse period = {TDRmn (master control) of the set value + 1} ×counting time Clock cycle Duty cycle[%] = {TDRmp (dependent) of the set value}/{ The setting of TDRmn (master) is +1}×100 0% output...
Page 218 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-66 operating as a PWM function master control channel (interval Timer mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register mn control interrupt signal (TDRmn) circuit (INTTMmn) slave channel (single counting mode)
Page 219 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure6-67 an example of the basic timing of the operation of the PWM function TSmn TEmn FFFFH TCRmn 0000H master control channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp slave 0000H channel TDRmp...
Page 220 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig6-68 Example of register setting content during PWM function (master channel). (a) Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn TERmn注...
Page 221 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig 6-69 Example of register setting content during PWM function (slave channel). (a) Timer mode register mp (TMRmp). CKSmp1 CKSmp0 注 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0 TMRmp operation mode of Channel p...
Page 222 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-70 Operating steps when the PWM function is performed (1/2). Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers) Timer 4 initial set TM4mEN bit of peripheral enable register 0 (PER0) to '1' Timer Unit m input clock is in active state, all channels in configuration...
Page 223 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-71 Operation steps while the PWM function is performed (2/2). set TOEmp bit (slave) to '1' (only limit to restart operation). Set TSmn bit)(master control) and TSmp bit(slave) of timer TEmn bit and TEmp bit both turns into '1'.
Page 224 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.9.3 Operation as a multi-PWM output function This is the function of extending the PWM function and using multiple slave channels for multiple PWM outputs with different duty cycles. For example, when 2 slave channels are used in pairs, the period and duty cycle of the output pulse can be calculated using the following equation: Pulse period = {TDRmn (master control) of the set value + 1}×...
Page 225 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-72 Block diagram of operation as a multi-PWM output function (in the case of outputting two types of PWM). master control channel (interval Timer mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register...
Page 226 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Figure 6-73 an example of running a basic timing function for multiple PWM output functions (in the case of outputting two PWMs). TSmn TEmn FFFFH TCRmn 0000H master control channel TDRmn TOmn INTTMmn...
Page 227 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 p: Slave channel number q: Slave channel number m=0Time:n＜p＜q≤3 (p和qis greater thanninteger) m=1Time:n＜p＜q≤7 (p和qis greater thanninteger) 2, TSmn, TSmp, TSmq: timer channel start register m (TSm) of bitn, p, q the status register TEmn, TEmp, TEmq: Timer channels enable bitn, p and bitn of...
Page 228 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-74 multi-PWM output function (master channel). (a) Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn TERmn注 operation mode of Channel N 000B: Interval Timer operation configuration when start counting 1: when start counting, generate INTTMmn...
Page 229 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-75 multiple PWM output function (slave channel) (in the case of outputting two PWMs). (a) Timer mode registers mp, mq (TMRmp, TMRmq). CKSmp1 注 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3...
Page 230 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-76 the multiple PWM output function (in the case of outputting 2 PWMs) (1/2). software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers) Timer 4 initial set TM4mEN bit of peripheral enable register 0 (PER0) to '1' Timer Unit m input clock is in active state, all channels...
Page 231 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 Fig. 6-77 multiple PWM output functions (in the case of outputting two kinds of PWM) (2/2). (only during restart operation, TOEmp bit and TOEmq bit (slave) will set to '1'). Set TSmn bit(master), TSmp bit and TSmq bit (slave) of timer Start operation channel start register m(TSm) all set to '1' at the same time.
Page 232 BAT32A2x9 user manual | Chapter 6 Universal timer unit Timer4/8 6.10 Considerations when using a universal timer unit 6.10.1 Considerations when using timer outputs Depending on the product, pins assigned the timer output function may also be assigned to the output of other multiplexing functions.
Page 233 BAT32A2x9 user manual | Chapter 7 Timer A Chapter 7 Timer A 7.1 Function of timer A Timer A is a 16-bit timer capable of measuring pulse outputs, pulse widths and cycles of external inputs, and counting external events. The 16-bit timer consists of a reload register and a decrement counter, which are assigned to the same address.
Page 234 BAT32A2x9 user manual | Chapter 7 Timer A 7.2 Structure of timer A The block diagram and pin structure of Timer A are shown in Figure 7-1 and Table 7-2, respectively. Figure 7-1 Block diagram of Timer A TCK2~TCK0 =000B =001B =011B =100B...
Page 235 BAT32A2x9 user manual | Chapter 7 Timer A 7.3 Controls the registers of timer A The registers that control timer A are shown in Table 7-3. Table 7-3 control registers of timer A Register name symbol Peripheral I/O redirect register 1 PIOR1 Peripheral enable register 1 PER1...
Page 236 BAT32A2x9 user manual | Chapter 7 Timer A 7.3.1 Peripheral enable register 1 (PER1). The PER1 register is a register that is set to allow or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use timer A, bit0 (TMAEN) must be set to "1".
Page 237 BAT32A2x9 user manual | Chapter 7 Timer A 7.3.2 The subsystem clock provides a mode control register (OSMC). The operating clock of timer A can be selected by WUTMMCK0 bits. The RTCLPC bit is a bit that reduces power consumption by stopping unwanted clock functions. For the setting of the RTCLPC bit, refer to "Chapter 4 Clock Generation Circuit".
Page 238 BAT32A2x9 user manual | Chapter 7 Timer A 7.3.3 Timer A counts register 0 (TA0). This is the 16-bit register. If you write this register, you write the data to the reload register. If you read this register, you read the count value. The state of reloading registers and counters varies depending on the value of the TSTART bit of the TARR0 register.
Page 239 BAT32A2x9 user manual | Chapter 7 Timer A 7.3.4 Timer A controls register 0 (TACR0). The TACR0 register is the register that controls the count and stop of register A and the state of timer A. Set the TARR0 register via the 8-bit memory operation instruction. After generating a reset signal, the value of the TACR0 register changes to "00H".
Page 240 BAT32A2x9 user manual | Chapter 7 Timer A 7.3.5 Timer AI/O control register 0 (TAIOC0). The TAIOC0 register is the register that sets the input/output of timer A. The TAIOC0 register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of the TAIOC0 register changes to "00H". Figure 7-6 Format of timer AI/O control register 0 (TAIOC0).
Page 241 BAT32A2x9 user manual | Chapter 7 Timer A Table 7-4 Edge and polarity switching of TAIO input/output Operating mode function Timer mode Not used (input/output ports). 0: Output from the "H" level (initial level: "H"). Pulse output mode 1: Output from the "L" level (initial level: "L"). 0: Count on the rising edge Event counter pattern 1: Count on the falling edge...
Page 242 BAT32A2x9 user manual | Chapter 7 Timer A 7.3.6 Timer A controls register 0 (TAMR0). The TAMR0 register is the register that sets the operating mode of register A. The TAMR0 register is set via the 8-bit memory operation instruction. After generating the reset signal, the value of the TAMR0 register changes to "00H".
Page 243 BAT32A2x9 user manual | Chapter 7 Timer A 7.3.7 Timer A event pin select register 0 (TAISR0). The TAISR0 register is a register that selects the timer that controls the event count in event counter mode and sets the polarity. The TAISR0 register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of the TAISR0 register changes to "00H".
Page 244 BAT32A2x9 user manual | Chapter 7 Timer A 7.3.8 Port mode register x (PMx). This is the register that sets the port input/output. To use the multiplex port of the timer output pin (TAIO, TAO, etc.) as the output of the timer, the bit of the port mode register (PMxx) corresponding to each port and the position of the port register (Pxx) must be "0".
Page 245 BAT32A2x9 user manual | Chapter 7 Timer A 7.4 Operation of timer A 7.4.1 Overrides to reload registers and counters Independent of the operating mode, the rewriting timing of reload registers and counters varies depending on the value of the TSTART bit of the TARR0 register. When the TSTART bit is "0" (stop count), the registers and counters are reloaded directly;...
Page 246 BAT32A2x9 user manual | Chapter 7 Timer A 7.4.2 Timer mode This is the mode of counting down by selecting a count source from TCK0 to TCK2 bits of the TAMR0 register. In timer mode, the count value is decremented by 1 whenever a count source is entered, and if the count value becomes "0000H"...
Page 247 BAT32A2x9 user manual | Chapter 7 Timer A 7.4.3 Pulse output mode In this mode, the count is decremented through the TCK0~TCK2 bit selected count source of the TAMR0 register, and whenever an underflow occurs, the output level of the TAIO pin and the TAO pin is inverted. In pulse output mode, the count value is decremented by 1 whenever the count source is entered, and if the count value becomes "0000H"...
Page 248 BAT32A2x9 user manual | Chapter 7 Timer A 7.4.4 Event counter pattern This is a mode of decrementing counting via an external event signal (count source) input by the TAIO pin. I can pass tiPF0 of the TAIOC0 register through the TIOGT0 to TIOGT1 bit and TAISR0 registers for various settings during event counting and can pass the TIPF0 of the TAIOC0 register The ~TIPF1 bit specifies the filter function of the TAIO input.
Page 249 BAT32A2x9 user manual | Chapter 7 Timer A Figure 7-13 Example of operation of the event counter pattern 2 example of timing sequence to configure operational mode to following scenario. TAMR0 register: TMOD2, 1, 0=010B (Event counter mode) TAIOC0 register: TIOGT1,0=01B(event count during external interrupt pin defined period) TIPF1, 0=00B (no filter) TEDGSEL=0 (counting at rising edge) TAISR0 register: RCCPSEL2=1(counting during H period)
Page 250 BAT32A2x9 user manual | Chapter 7 Timer A 7.4.5 Pulse width measurement mode This is the mode for measuring the width of the external signal pulse at the input of the TAIO pin. In pulse width measurement mode, if the level specified by the TEDGSEL bit of the TAIOC0 register is input to the TAIO pin, the count is decremented by the selected counting source.
Page 251 BAT32A2x9 user manual | Chapter 7 Timer A 7.4.6 Pulse period measurement mode This is the mode for measuring the pulse period of the external signal at the input of the TAIO pin. The counter counts down by selecting the count source from TCK0 to TCK2 bits of the TAMR0 register. If the TAIO pin is given a pulse for the specified period of the TEDGSEL bit of the TAIOC0 register, the count value is transmitted to the read buffer on the rising edge of the counting source, and the value of the reload register is loaded to the counter on the next rising edge, while TACR0 The TEDGF bit of the register becomes "1"...
Page 252 BAT32A2x9 user manual | Chapter 7 Timer A 7.4.7 Collaboration with EVENTC By working with EVENTC, events entered by EVENTC can be set as the count source. Through the TCK0~TCK2 bits of the TAMR0 register, the count is made on the rising edge of the event at the ELC input.
Page 253 BAT32A2x9 user manual | Chapter 7 Timer A 7.5 Considerations when using Timer A 7.5.1 Start and stop control of counting • Event counting mode or when the counting source is set to a non-EVENTC If you write "1" (start counting) to the TSTART bit of the TACR0 register during the counting stop, the TCSTF of the TARCR0 register is counted within 3 source cycles The bit is "0"...
Page 254 BAT32A2x9 user manual | Chapter 7 Timer A 7.5.4 Change in Operational mode The operating mode correlation register (TAIOC0) of timer A can only be changed if the stop count (both the TSTART bit and the TSTF bit of the TACR0 register are "0" (stop count)). , TAMR0, TAISR0), cannot be changed during the counting process.
Page 255 BAT32A2x9 user manual | Chapter 7 Timer A 7.5.5 Setup steps for TAO pins and TAIO pins After reset, the multiplexed I/O ports of the TAO pin and the TAIO pin are input ports. When you want to output from the TAO pin and the TAIO pin, you must follow the steps below to set it. Change the step (1) Set the mode.
Page 256 BAT32A2x9 user manual | Chapter 7 Timer A 7.5.8 Setup steps for deep sleep mode (event counter mode). To make event counter mode run in deep sleep mode, you must follow the steps below to move to deep sleep mode after providing the clock for Timer A Setup steps (1) Set the operating mode.
Page 257 BAT32A2x9 user manual | Chapter 8 Timer B Chapter 8 Timer B Function of timer B Timer B has the following 3 modes: • Timer Mode: The input capturing function counts on the bilateral edges of the rising, falling, or rising/falling edges. Output comparison function "L"...
Page 258 BAT32A2x9 user manual | Chapter 8 Timer B Structure of timer B The block diagram and pin structure of timer B are shown in Figure 8-1 and Table 8-1, respectively. Figure 8-1 Block diagram of Timer B fCLK、fCLK/2、fCLK/4、fCLK/8、 fCLK/32 TB register TBGRA register comparator counter...
Page 259 BAT32A2x9 user manual | Chapter 8 Timer B Control registers of timer B The registers that control timer B are shown in Table 8-2. Table 8-2 control registers of timer B Register name symbol Peripheral enable register 1 PER1 Timer B mode register TBMR Timer B counts control registers TBCNTC...
Page 260 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.1 Peripheral enables register 1 (PER1). The PER1 register is a register that is set to enable or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use timer B, bit6 (TMBEN) must be set to "1".
Page 261 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.2 Timer B mode register (TBMR). Figure 8-3 Format of the timer B mode register (TBMR). Address: 40042650H After reset: 00H R/W symbol TBMR TBDFB TBDFA TBMDF TBPINM TBSTART The beginning of the TB count Stop counting, and initialize the PWM output signal (TBIO0 pin) (PWM mode).
Page 262 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.3 Timer B counts the control register (TBCNTC). Use the TBCNTC register in phase count mode to set the counting conditions for phase count mode. Figure 8-4 Format of timer B count control register (TBCNTC). Address: 40042651H after reset: 00H R/W symbol...
Page 263 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.4 Timer B Control Register (TBCR). The TBCR register must be written in a state where the TBSTART bit of the TBMR register is "0" (stop count). Figure 8-5 Format of timer B control register (TBCR). Address: 40042652H after reset: 00H R/W symbol...
Page 264 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.5 Timer B interrupt enable register (TBIER). Figure 8-6 Timer B interrupt enable the format of the register (TBIER). Address: 40042653H after reset: 00H symbol TBIER TBUDIE TBIMIEB TBIMIEA Overflow interrupt Enable TBOVIE Interrupts due to TBOVF bits are prohibited.
Page 265 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.6 Timer B status register (TBSR). Figure 8-7 Format of the timer B status register (TBSR). Address: 40042654H after reset: 00H symbol TBSR TBDIRF TBOVF TBUDF TBIMFB TBIMFA Count direction flags TBDIRF The TB register counts down.
Page 266 BAT32A2x9 user manual | Chapter 8 Timer B (a) The object status flag must be written "0" after setting the timer B interrupt enable register (TBIER) to "00H" (disable all interrupts). (b) When the timer B interrupt enable register (TBIER) has a bit of "1" (Enable) set and the bit Enable interrupt source status is flagged as "0"...
Page 267 BAT32A2x9 user manual | Chapter 8 Timer B Table 8-3 condition for flag to be marked "1" Note 1 Timer mode Bit symbol PWM mode Enter the capture function Output comparison function When tb overflows occur TBOVF When a TB underflow occurs (limited to phase count mode only). TBUDF to the input edge of the TBIO1 pin When the values of TB and TBGRB are the same TBIMFB...
Page 268 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.7 Timer BI/O Control Register (TBIOR). Figure 8-8 Format of the timer BI/O Control Register (TBIOR). Address: 40042655H After reset: 00H R/W After reset: 00H R TBIOR TBBUFB TBIOB2 TBIOB1 TBIOB0 TBBUFA TBIOA2 TBIOA1 TBIOA0...
Page 269 BAT32A2x9 user manual | Chapter 8 Timer B TBGRA control TBIOA1 TBIOA0 Disables comparison of matching pin outputs. Output "L" level. Outputs the "H" level. Alternate outputs. The output of the TB register and TBGRA registers is compared and matched by the output comparison function.
Page 270 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.8 Timer B counter (TB). Tb registers are connected via a 16-bit internal bus and CPU, so they must be accessed in 16-bit units. TB registers can be incremented, free-running, cycle counting, or external event counting. Tb can be captured by matching with the corresponding TBGRA registers, TBGRB registers, or inputs to TBGRA registers and TBGRB registers Register clear "0000H"...
Page 271 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.9 (TBGRA, TBGRB, TBGRC, TBGRD) Timer B universal registers A, B, C, D The TBGRA registers and TBGRB registers are 16-bit read-write registers with the function of output comparison registers and input capture registers. Function conversion via TBIOR registers. When used as output comparison registers, the values of tbGRA registers and TBGRB registers are always compared to the values of TB registers.
Page 272 BAT32A2x9 user manual | Chapter 8 Timer B Table 8-4TBGRA, TBGRB, TBGRC, TBGRD register functions Modes and register Set up function features TBIOR (TBIOA2=1) Enter the capture register (which holds the value of the TB TBGRA TBMR (TBPWM=0) register). Input capture TBIOR (TBIOB2=1) Enter the capture register (which holds the value of the TB TBGRB...
Page 273 BAT32A2x9 user manual | Chapter 8 Timer B 8.3.10 Port registers and port mode registers When using the multiplex port of the timer output pin as the output of the timer, the bit of the corresponding port mode register (PMxx) and the position of the port register (Pxx) of each port must be "0". (Example) The P50/TBIO0 is used as a timer output in the case of the PM50 position "0"...
Page 274 BAT32A2x9 user manual | Chapter 8 Timer B Operation of timer B 8.4.1 Common things about multiple patterns and features Count the sources The selection of the counting source and the block diagram are shown in Table 8-5 and Figure 8-12, respectively.
Page 275 BAT32A2x9 user manual | Chapter 8 Timer B The buffer runs The TBGRC register and tbGRD register can be set to the TBGRA register and the TBGRA register and the TBGRD register respectively through the TBBUFA bit and TBBUFB bit of the TBIBOR register Buffer registers for TBGRB registers.
Page 276 BAT32A2x9 user manual | Chapter 8 Timer B Figure 8-14 The buffer of the output comparison function is running compare matching signal TBGRC TBGRA comparator register register register TB register TBGRA register transmit TBGRC register (buffer) TBIO0 output above diagram condition as following: ・TBBUFA bit of TBIOR register is 1 (TBGRC register is the buffer register of TBGRA) ・TBIOA2~TBIOA0 bit of TBIOR register as "001B"...
Page 277 BAT32A2x9 user manual | Chapter 8 Timer B Digital filters The TBIOj input (j=0, 1) is sampled and if the signals are the same three times, the level is considered determined. The function and sample clock of the digital filter must be selected through the TBMR registers. The block diagram of the digital filter is shown in Figure 8-15.
Page 278 BAT32A2x9 user manual | Chapter 8 Timer B Enter events from EVENTC Over event events entered by EVENTC, Timer B performs an input capture run B. At this point, the TBSR register has a TBIMFB bit of "1". To use this function, the input capture function of timer mode/phase count mode must be selected, and the TBELCICE position of the TBMR register must be "1".
Page 279 BAT32A2x9 user manual | Chapter 8 Timer B 8.4.2 Timer mode (input capture function) Capable of passing the value of tb registers to TBGRA registers and TBGRBs after detecting the input edge of the input capture/output comparison pins (TBIO0, TBIO1). Register. Detection edges can be selected from rising, falling, and bilateral edges.
Page 280 BAT32A2x9 user manual | Chapter 8 Timer B Enter an example of a setup step for the capture run An example of the setup steps for entering a capture run is shown in Figure 8-16. Figure 8-16 Example of setup steps for input capture runs Enter the timing of the capture signal Input capture inputs can be selected by setting the TBIOR registers on the rising, falling, or bilateral edges.
Page 281 BAT32A2x9 user manual | Chapter 8 Timer B Run the example An example of an input capture operation is shown in Figure 8-18. In this example, select the double edge of the rising/falling edge as the input edge of the input snap of the TBIO0 pin, select the falling edge as the input edge of the input capture of the TBIO1 pin, and clear the TB when the input snap of the TBGRB register Counters for registers.
Page 282 BAT32A2x9 user manual | Chapter 8 Timer B 8.4.3 Timer mode (output comparison function) This is the mode that detects (relatively matches) whether the contents of the TB register and the contents of the TBGRA register or TBGRB register are the same. If the content is the same, output any level from the TBIO0 pin or the TBIO1 pin.
Page 283 BAT32A2x9 user manual | Chapter 8 Timer B Example of setup steps to compare matching waveform outputs The setup steps for comparing the matching waveform outputs are shown in Figure 8-19. Figure 8-19 compares the setup steps for matching waveform outputs output selection must select compare matching output via TBIOR register between "L"...
Page 284 BAT32A2x9 user manual | Chapter 8 Timer B Run the example An example of the operation of the "L" level output and the "H" level output is shown in Figure 8-21. In this example, the TB register is set to run freely and outputs the "L" level when comparing match A and the "H"...
Page 285 BAT32A2x9 user manual | Chapter 8 Timer B An example of alternating outputs is shown in Figure 8-22. In this example, the TB register is set to cycle count operation (the counter is cleared when the comparison matches B) and alternate outputs occur when either match A or match B is compared.
Page 286 BAT32A2x9 user manual | Chapter 8 Timer B 8.4.4 PWM mode PWM mode pairing uses TBGRA registers and TBGRB registers to output the PWM waveform from the TBIO0 output pin. For output pins set to PWM mode, the output setting of the TBIOR register is invalid. Set the "H"...
Page 287 BAT32A2x9 user manual | Chapter 8 Timer B Example of setup steps for PWM mode An example of the setup steps for the PWM mode is shown in Figure 8-23. Figure 8-23 Example of setup steps for PWM mode (1) must select counting source via TBTCK0~TBTCK2 bit of TBCR register. PWM mode When select external clock, must select external clock edge via TBCKEG0 bit and TBCDEG1 bit of TBCR register.
Page 288 BAT32A2x9 user manual | Chapter 8 Timer B Figure 8-24 Operation example of PWM mode (1). Value of TB register clear counter while compare matching A. TBGRA register TBGRB register 0000H Time TBIO0 output (a) clear counter while TBGRA register compare matching Value of TB register clear counter while compare matching B.
Page 289 BAT32A2x9 user manual | Chapter 8 Timer B Figure 8-25 Example of operation of PWM mode (2). Value of TRG register clear counter while compare matching B. TBGRB register TBGRA register 0000H Time TBIO0 output write configuration value write configuration value into TBGRA register into TBGRA register (a)Duty cycle 0%.
Page 290 BAT32A2x9 user manual | Chapter 8 Timer B 8.4.5 Phase count mode The phase count mode detects the phase difference between the external input signals of the two TBBCLK0 pins and the TBKK1 pin, and the TB registers increment/decrement count. When the PM xx bit of the PM register is "1", if set to phase count mode, the TBCLK0 pin and the TBBCLK1 pin are automatically used as external clock input pins, and Tb registers are added and subtracted according to the setting of CNTEN0 to CNTEN7 bits of the TBCNTC registers, and the TB REGISTER is counted The settings of...
Page 291 BAT32A2x9 user manual | Chapter 8 Timer B Example of a step setup step for the phase count mode An example of the setup steps for the phase count mode is shown in Figure 8-26. Figure 8-26 Example of the setup steps of the phase count mode phase counting mode (1)must set TBMDF bit of TBMR register to 1, select phase counting mode...
Page 292 BAT32A2x9 user manual | Chapter 8 Timer B Figure 8-28 Example of the phase count mode 2 ・whlie TBCNTC register value as "24H" TBCLK1 input TBCLK0 input Value of TB register increment decrement Time Figure 8-29 Example of the phase count mode 3 ・while TBCNTC register value as "28H"...
Page 293 BAT32A2x9 user manual | Chapter 8 Timer B Timer B interrupt Timer B generates timer B interrupt requests from 4 interrupt sources. The associated registers for the timer B interrupt are shown in Table 8-16, and the block diagram of the timer B interrupt is shown in Figure 8-31. Table 8-16 Timer B interrupt related registers Status...
Page 294 BAT32A2x9 user manual | Chapter 8 Timer B • Timer B interrupt enables the state of the register (TBIER). Interrupts are allowed — — — — TBOVIE TBIMIEB TBIEA TBUDIE TBIER Ban Suspend • The status of the timer B status register (TBSR). The bits to clear the request —...
Page 295 BAT32A2x9 user manual | Chapter 8 Timer B Considerations when using timer B 8.6.1 Phase difference, overlap, and pulse width in phase count mode The phase difference and overlap of the external input signals on the TBCLK0 pin and TBCLK1 pin must be at least 1.5 f and a pulse width of at least 2.5 f , respectively.
Page 296 BAT32A2x9 user manual | Chapter 8 Timer B 8.6.4 Setup steps for TBIO0 pins and TBIO1 pins After reset, the multiplexed I/O ports on the TBIO0 pin and TBIO1 pins are used as input ports. • When you want to output from the TBIO0 pin and TBIO1 pins, you must follow the steps below to set it up.
Page 297 BAT32A2x9 user manual | Chapter 8 Timer B 8.6.7 Stop counting when the input snap runs In input capture mode, input is given to the TBIO0/TBIO1 pin if the TBSTART bit of the TBBR register is "0" (stop count). The TBIOj0 bit and TBIOj1 bits of the TBIOR registers are selected at the edges that generate an input capture interrupt request at the effective edge of the TBIO0/TBIO1 input (j=A, B) 。...
Page 298 BAT32A2x9 user manual | Chapter 9 Timer C Chapter 9 Timer C 9.1 Function of timer C Timer C is a timer that can trigger the input capture function via software, comparator 1, and timer M. The actions are as follows: Count Start: The count action is triggered by software or timer M Count Stop: The count stop is triggered by the software or the output of Comparator 1 Input capture: When an interrupt from comparator 1 occurs, the count value is transferred to the buffer...
Page 299 BAT32A2x9 user manual | Chapter 9 Timer C 9.2 Structure of timer C The block diagram of timer C is shown in Figure 9-1. Figure 9-1 Block diagram of timer C Timer C counter source selection Timer control Trigger event from Timer M Trigger event from Comparator 1 299 / 1149 Rev.1.00...
Page 300 BAT32A2x9 user manual | Chapter 9 Timer C 9.3 Control registers of timer C The registers that control timer C are shown in Table 9-1. Table 9-1 control registers of timer C Register name symbol Peripheral enable register 1 PER1 Timer C count register Timer C counts buffer registers TCBUF0...
Page 301 BAT32A2x9 user manual | Chapter 9 Timer C 9.3.2 Timer C count register (TC). This is the 16-bit register. If you write this register, you write the data to the reload register. If you read this register, you read the count value. Figure 9-3 Format of the timer C count register (TC).
Page 302 BAT32A2x9 user manual | Chapter 9 Timer C 9.3.4 Timer C controls register 1 (TCCR1). Figure 9-5 Timer C controls the format of register 1 (TCCR1). Address: 0x40042C54 After reset: 00H R/W Symbol TRIG_MD_S TRIG_MD_H TCCR1 TCK2 TCK1 TCK0 START_MD TM_TRIG OVIE TCK2...
Page 303 BAT32A2x9 user manual | Chapter 9 Timer C 9.3.5 Timer C controls register 1 (TCCR2). Figure 9-6 Timer C controls the format of register 1 (TCCR2). Address: 0x40042C55 After reset: 00H R/W Symbol TCCR2 CMP_TCR1 CMP_TCR0 TSART The action selection when Timer C is triggered by the CMP1_TCR1 CMP1_TCR0 output of comparator 1...
Page 304 BAT32A2x9 user manual | Chapter 9 Timer C (TCSR). 9.3.6 Timer C status register Figure 9-7 Format of timer C control register 1 (TCSR). Address: 0x40042C56 After reset: 00H R/W Symbol TCSR TCSB TCOVF TCSB Timer C counter status flag bit Note 1 Count stops Count...
Page 305 BAT32A2x9 user manual | Chapter 9 Timer C 9.4 Operation of timer C Timer C can start with the signal trigger count of timer M, and the signal trigger count of comparator 1 stops. 9.4.1 Count the sources The action clock of timer C is determined by the dividing setting of timer C. （1）...
Page 306 BAT32A2x9 user manual | Chapter 9 Timer C 9.4.2.1 Select the signal of the Timer M as the setting and action when triggered Reset and start setup steps for the Timer C count when TRIG_MD_HW=0: Select the Timer M output signal as the trigger source for counting start: TCCR1. START_MD=1 Select the trigger function of Timer C: TCCR1.
Page 307 BAT32A2x9 user manual | Chapter 9 Timer C 9.4.2.2 Select the settings and actions when the software triggers 1. Count Start Source Selection Software Trigger: TCCR1. START_MD=0 2. Timer C count start: TCCR2. TSTART=1 Fig. 9-10 Example of software triggering the start of the Timer C count TC counting source TCCR1.START_MD TCCR2.TSTART...
Page 308 BAT32A2x9 user manual | Chapter 9 Timer C 9.4.3 Timer C counts stopped actions Timer C is in the counting and can be stopped by triggering comparator 1 or by setting the software. 9.4.3.1 Select Comparator 1 as the setting and action when triggered Select Comparator 1 as the trigger: TCCR2 CMP1_TCR=00 Timer C count starts: TCCR2.
Page 309 BAT32A2x9 user manual | Chapter 9 Timer C 9.4.4 Enter the capture motion If comparator 1 produces an interrupt during the Timer C action, the Timer C action changes. （1） Case 1: TCCR2. CMP1_TCR=01, the count value of Timer C is transferred to the count buffer. TCCR2.CMP1_TCR=01 (select input capture function).
Page 310 BAT32A2x9 user manual | Chapter 9 Timer C 9.4.5 Timer C counts the reset action When the Timer C action is set to begin using the software, the output signal of Timer M and the output signal of comparator 1 can reset the counter of Timer C. TRIG_MD_SW=0, the output signal of Timer M cannot reset the count value when the software triggers the count starts.
Page 311 BAT32A2x9 user manual | Chapter 9 Timer C When TCCR2.CMP1_TCR=10, the output signal of CMP1 resets the count value. The count value is reset and the count action continues: TCCR2.CMP1_TCR=10 (input capture function cannot be used). Timer C count starts: TCCR2. TSTART=1 Fig.
Page 312 BAT32A2x9 user manual | Chapter 9 Timer C 9.4.6 Interrupt of timer C Timer C counter overflows if TCCR1 is set. OVIE=1, which produces an overflow interrupt signal. Fig. 9-17: Example of interrupt generation when the Timer C overflows TC counting source Timer M or software trigger start...
Page 313 BAT32A2x9 user manual | Chapter 9 Timer C 9.5 Precautions when using Timer C 9.5.1 Read and write registers To set the timer C, you must first place the TMCEN position "1" of P ER1. When the TMCEN bit is "0", the write operation of the control register of timer C is ignored, and the read values are the initial values.
Page 314 BAT32A2x9 user manual | Chapter 10 Timer M Chapter 10 Timer M 10.1 Function of timer M Timer M has the following 4 modes: • Timer mode The input capture function is triggered by an external signal to take the count value to the register. The output comparison function detects whether the count value and the register value are the same (the output of the pin can be changed at the time of detection).
Page 315 BAT32A2x9 user manual | Chapter 10 Timer M 10.2 Structure of timer M The block diagram and pin structure of timer M are shown in Figure 10-1 and Table 10-1, respectively. Figure 10-1 Block diagram of timer M fHOCO,fCLK,fCLK/2,fCLK/4,fCLK/8,fCLK/32 Timer Mi TMi registers INTP0 TMGRAi...
Page 316 BAT32A2x9 user manual | Chapter 10 Timer M 10.3 Control register of timer M The registers that control timer M are shown in Table 10-2. Table 10-2 control registers of timer Register name symbol Peripheral enable register 1 PER1 Timer M EVENTC register TMELC Timer M starts the register TMSTR...
Page 317 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.1 Peripheral enable register 1 (PER1). Per1 registers are registers that are set to allow or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use timer M, bit4 (TMMEN) must be set to "1".
Page 318 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.2 Timer M EVENTC register (TMELC). Figure 10-3 Format of the timer M EVENTC register (TMELC). Address: 0x40042A60 after reset: 00H R/W symbol TMELC ELCOBE1 ELCICE1 ANDLCOBE0 ELCICE0 ELCOBE1 Permissibility of EVENTC event input 1 (pulse output for forced cut-off timer Mandatory cut-off is prohibited.
Page 319 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.3 Timer M Start Register (TMSTR). The TMSTR register can be set via an 8-bit memory operation instruction. Please refer to "10.7.1(1) TMSTR Registers" for Precautions When Using Timer M. Figure 10-4 Format of the Start Register (TMSTR) for timer M Address: 0x40042A63 reset: 0CH R/W symbol...
Page 320 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.4 Timer M mode register (TMMR). Figure 10-5 Format of the mode register (TMMR) for timer M Address: 0x40042A64 reset: 00H R/W symbol TMMR TMBFD1 TMBFC1 TMBFD0 TMBFC0 TMSYNC note 1 TMBFD1 TMGRD1 register function selection General Purpose registers Buffer register for the TMGRB1 register...
Page 321 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.5 Timer M PWM function select register (TMPMR). Figure 10-6 Format of the timer M PWM function selection register (TMPMR) [Timer Mode]. Address: 0x40042A65 reset: 00HR/W symbol TMPMR TMPWMD1 TMPWMC1 TMPWMB1 TMPWMD0 TMPWMC0 TMPWMB0 TMPWMD1...
Page 322 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.6 Timer M function control register (TMFCR). Figure 10-7 Timer M function control register (TMFCR) format Address: 0x40042A66 Reset: 80H R/W symbol TMFCR HPM3 STCLK The LS1 OLS0 CMD1 CMD0 note 1 PWM3 mode selection PWM3 •...
Page 323 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.7 Timer M output master enable register 1 (TMOER1). Figure 10-8 Timer M outputs the format of the main enable register 1 (TMOER1). [Output Comparison Function, PWM Function, Reset Synchronous PWM Mode, Complementary PWM Mode, and PWM3 Mode].
Page 324 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.8 Timer M output main enable register 2 (TMOER2). Figure 10-9 Timer M outputs the format of the main enable register 2 (TMOER2). [PWM function, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode]. Address: 0x40042A68 reset: 00HR/W symbol TMOER2...
Page 325 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.9 Timer M output control register (TMOCR). The TMOCR register must be written when both the TSTART0 bit and the TSTART1 bit of the TMSTR register are "0" (stop count). Figure 10-10 Format of the M Output Control Register (TMOCR) of the timer [Output Comparison Function]. Address: 0x40042A69 reset: 00H R/W symbol TMOCR...
Page 326 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-11 : Format of the output control register (TMOCR) of the timer M [PWM function]. Address: 0x40042A69 after reset: 00H R/W symbol TMOCR TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 TOD1 Note 1 TMIOD1 Initial Output Level Selection...
Page 327 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-12 Format of the output control register (TMOCR) of the timer M [PWM3 mode]. Address: 0x40042A69 after reset: 00H R/W symbol TMOCR TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 TOD1 The choice of the initial output level of TMIOD1 Not valid in PWM3 mode.
Page 328 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.10 The timer M digital filter function selects register i (TMDFi) (i=0, 1). Fig. 10-13 Format of timer M digital filter function selection register i (TMDFi) (i=0, 1) [Input Capture Function] Address: 0x40042A6A (TMDF0), 0x40042A6B (TMDF1) after reset: 00H R/W symbol TMDFi...
Page 329 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-14 Timer M digital filter function selection register i (TMDFi) (i=0, 1) format [PWM function, reset synchronization PWM mode, complementary PWM mode, and PWM3 mode]. Address: 0x40042A6A (TMDF0), 0x40042A6B (TMDF1) after reset: 00H R/W symbol TMDFi...
Page 330 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.11 Timer M controls register i (TMCRi) (i=0, 1). The TMCR1 register is not used in reset synchronous PWM mode and PWM3 mode. Fig. 10-15 Format of timer M control register i (TMCRi) (i=0, 1) [input capture function and output comparison function] Address: 0x40042A70 (TMCR0), 0x40042A80 (TMCR1) after reset: 00H R/W...
Page 331 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-16 Format of timer M control register i (TMCRi) (i=0, 1) [PWM function]. Address: 0x40042A70 (TMCR0), 0x40042A80 (TMCR1) after reset: 00H R/W symbol TMCRi CCLR2 CcLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1...
Page 332 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-17 Format of timer M control register 0 (TMCR0) [Reset Synchronous PWM Mode]. Address: 0x40042A70 after reset: 00H R/W symbol TMCR0 CCLR2 CcLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1 CCLR0 Clear selection for the TM0 counter "001B"...
Page 333 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-18 Format of Timer M Control Register 0 (TMCR0) [Complementary PWM Mode]. Address: 0x40042A70 after reset: 00H R/W symbol TMCR0 CCLR2 CcLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1 CCLR0 Clear selection for the TM0 counter Must be set to "000B"...
Page 334 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-19 Format of timer M control register 0 (TMCR0) [PWM3 mode]. Address: 0x40042A70 after reset: 00H R/W symbol TMCR0 CCLR2 CcLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1 CCLR0 Clear selection for the TM0 counter "001B"...
Page 335 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.12 Timer M I/O control register Ai (TMIORAi) (i =0, 1). Figure 10-20 Format of the I/O control register Ai (TMIORAi) (i=0, 1) of the timer M [ Input Capture Function]. Address: 0x40042A71 (TMIORA0), 0x40042A81H (TMIORA1) After reset: 00H R/W symbol TMIORAi...
Page 336 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-21 Format of the I/O control register Ai (TMIORAi) (i=0, 1) of the timer M[ Output comparison function]. Address: 0x40042A71 (TMIORA0), 0x40042A81H (TMIORA1) After reset: 00H R/W symbol TMIORAi IOB2 IWhether IOB0 IOA2 IOA1...
Page 337 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.13 Timer M I/O control register Ci (TMIORCi) (i=0, 1). Figure 10-22 Format of the timer M I/O control register Ci (TMIORCi) (i=0, 1) [ Input Capture Function]. Address: 0x40042A72 (TMIORC0), 0x40042A82 (TMIORC1) after reset: 88H R/W symbol TMIORCi...
Page 338 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-23 Format of timer M I/O control register Ci (TMIORCi) (i=0, 1) [ Output comparison function]. Address: 0x40042A72 (TMIORC0), 0x40042A82 (TMIORC1) after reset: 88H R/W symbol TMIORCi IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0...
Page 339 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.14 Timer M status register 0 (TMSR0). Figure 10-24 Format of timer M status register 0 (TMSR0) [Input Capture Function]. Address: 0x40042A73 after reset: 00H symbol TMSR0 IMFD IMFC IMFB IMFA note 1 Overflow flag [condition for "0"].
Page 340 BAT32A2x9 user manual | Chapter 10 Timer M Note 2 Write the result as follows: • When you write "1", this bit does not change. • In the case of reading a value of "0" , it even if does not change "0"...
Page 341 BAT32A2x9 user manual | Chapter 10 Timer M • Status of timer M status register i (TMSRi). must cclear request bit — — IMFD IMFC IMFB IMFA TMSRi must write 0 to IMFB since the corresponding status flag (OVF, IMFA) of enabled interrupt are "0".
Page 342 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-25 Format of timer M status register 0 (TMSR0) [functions other than input capture]. Address: 0x40042A73 after reset: 00H R/W symbol TMSR0 IMFD IMFC IMFB IMFA note 2 Overflow flag [condition for "0"]. note 1 Read "0"...
Page 343 BAT32A2x9 user manual | Chapter 10 Timer M Note 1 Write the result as follows: • When you write "1", this bit does not change. • In the case of reading a value of "0" , it even if does not change "0"...
Page 344 BAT32A2x9 user manual | Chapter 10 Timer M • Status of timer M status register i (TMSRi). must cclear request — — IMFD IMFC IMFB IMFA TMSRi must write 0 to IMFA and IMFB since the corresponding status flag (IMFA) of enabled interrupt are "0". 2.
Page 345 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.15 Timer M status register 1 (TMSR1). Figure 10-26 Format of timer M status register 1 (TMSR1) [Input Capture Function]. Address: 0x40042A83 reset: 00H R/W symbol TMSR1 IMFD IMFC IMFB IMFA Underflow flag Not valid when using the input capture feature.
Page 346 BAT32A2x9 user manual | Chapter 10 Timer M Note 2 Write the result as follows: •When writing "1", this bit does not change. • In the case of reading a value of "0" , it even if does not change "0"...
Page 347 BAT32A2x9 user manual | Chapter 10 Timer M • Status of timer M status register i (TMSRi). must cclear request — — IMFD IMFC IMFB IMFA TMSRi Because the status flag (IMFA) corresponding to the interrupt enable bit is "1", it is necessary to write "0" to IMFA and IMFB at the same time.
Page 348 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-27 Format of timer M status register 1 (TMSR1) [functions other than input capture]. Address: 0x40042A83 reset: 00H R/W symbol TMSR1 IMFD IMFC IMFB IMFA Underflow flag Case of complementary PWM mode [condition for "0"].
Page 349 BAT32A2x9 user manual | Chapter 10 Timer M Note 1 Write the result as follows: •When writing "1", this bit does not change. • In the case of reading a value of "0" , it even if does not change "0"...
Page 350 BAT32A2x9 user manual | Chapter 10 Timer M • Status of timer M status register i (TMSRi). must cclear request — — IMFD IMFC IMFB IMFA TMSRi Because the status flag (IMFA) corresponding to the interrupt enable bit is "1", it is necessary to write "0" to IMFA and IMFB at the same time.
Page 351 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.16 Timer M interrupt enable register i (TMIERi) (i= 0, 1). Figure 10-28 the format of Timer M interrupt enable register i (TMIERi) (i=0, 1). Address: 0x40042A74 (TMIER0), 0x40042A84 (TMIER1) after reset: 00HR/W symbol TMIERi...
Page 352 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.17 The timer MPWM function outputs level control register i (TMPOCRi) (i=0, 1). The setting of the TMPOCRi register is valid only when the PWM function is used, otherwise the setting of the TMPOCRi register is invalid.
Page 353 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.18 Timer M counter i(TMi) (i=0, 1). [Timer mode]. TMi registers must be accessed in 16 bits, not 8 bits. [Reset Synchronous PWM Mode and PWM3 Mode]. The TM0 register must be accessed in 16 bits, not 8 bits. In reset synchronous PWM mode and PWM3 mode, TM1 is not used Register.
Page 354 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-32 Format of the timer M counter i(TMi) (i=0, 1) [Complementary PWM Mode ( TM0) ] Address: 0x40042A76 (TM0), 0x40042A86 (TM1) after reset: 0000H R/W 15 14 Symbol — function Configure range The dead time must be set.
Page 355 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.19 Timer M General Purpose registers Ai, Bi, Ci, Di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0, 1) [Input capture function]. The TMGRAi~TMGRDi registers must be accessed in 16 bits, not 8 bits. When using the input capture function, the following registers are invalid: TMOER1, TMOER2, TMOCR, TMPOCR0, TMPOCR1 When no digital filter is used (the DFj bit of the TMDFi register is "0"), the pulse width of the capture signal input to the TMIOji pin must be at least 3 timer M's operating clock (f CLK ) cycle.
Page 356 BAT32A2x9 user manual | Chapter 10 Timer M [PWM3 mode]. The TMGRAi~TMGRDi registers must be accessed in 16 bits, not 8 bits. In PWM3 mode, the following registers are invalid: TMPMR, TMDF0, TMDF1, TMIORA0, TMIORC0, TMPOCR0, TMIORA1, TMIORC1, TMPOCR1 In PWM3 mode, the TMGRC0, TMGRC1, TMGRD0, TMGRD1 registers are not used. However, when using these registers as buffer registers, place the TMBFC0 bits, TMBFC1 bits, TMBFD0 bits, and TMBFD1 positions "0"...
Page 357 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-35 Timer M General Purpose registers Ai, Bi, Ci, Di Format of (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0, 1) [ Output comparison function]. Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), After Reset: FFFFH R/W 0x40042B58 (TMGRC0) , 0x40042B5A (TMGRD0) , 0x40042A88 (TMGRA1) , 0x40042A8A (TMGRB1) , 0x40042B5C(TMGRC1), 0x40042B5E(TMGRD1)
Page 358 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-36 Timer M General Purpose registers Ai, Bi, Ci, Di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0, 1) format [PWM]. Function]. Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), After reset: FFFFH R/W 0x40042B58 (TMGRC0) , 0x40042B5A (TMGRD0) , 0x40042A88 (TMGRA1) , 0x40042A8A (TMGRB1) , 0x40042B5C(TMGRC1), 0x40042B5E(TMGRD1) 15 14...
Page 359 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-37 Timer M General Purpose registers Ai, Bi, Ci, Di Format of (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0, 1) [ Reset synchronous PWM mode]. Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), After reset: FFFFH R/W 0x40042B58 (TMGRC0) , 0x40042B5A (TMGRD0) , 0x40042A88 (TMGRA1) , 0x40042A8A (TMGRB1) , 0x40042B5C(TMGRC1), 0x40042B5E(TMGRD1)
Page 360 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-38 Timer M General Purpose registers Ai, Bi, Ci, Di Format of (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0, 1) [ Complementary PWM mode]. Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), After reset: FFFFH R/W 0x40042B58 (TMGRC0) , 0x40042B5A (TMGRD0) , 0x40042A88 (TMGRA1) , 0x40042A8A (TMGRB1) , 0x40042B5C(TMGRC1), 0x40042B5E(TMGRD1)
Page 361 BAT32A2x9 user manual | Chapter 10 Timer M Table 10-7 Complementary TMGRji register functions in PWM mode register Set up Register function PWM output pin A general purpose register that must set the PWM period at the time of initial setup. (TMIOC0 outputs Setting range: The setting value (initial value of the count) of the TM0 register ≤The setting value of TMGRA0 ≤...
Page 362 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-39 Timer M General Purpose registers Ai, Bi, Ci, Di Format (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0, 1) format [PWM3 Mode]. Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), After reset: FFFFH R/W 0x40042B58 (TMGRC0) , 0x40042B5A (TMGRD0) , 0x40042A88 (TMGRA1) , 0x40042A8A (TMGRB1) , 0x40042B5C(TMGRC1), 0x40042B5E(TMGRD1) 15 14...
Page 363 BAT32A2x9 user manual | Chapter 10 Timer M Table 10-8 TMGRji register functions in PWM3 mode register Set up Register function PWM output pin General Purpose registers, the PWM period must be set. Setting range: The setting value of the TMGRA1 register ≤ the TMGRA0 setting value of TMGRA0 A general purpose register where the change point of the PWM...
Page 364 BAT32A2x9 user manual | Chapter 10 Timer M 10.3.20 Port mode registers (PMxx, PMCxx). This is the register that sets the input/output of the port or the analog input. When using the multiplex port of the timer output pin (Pxx/TMIOD1, Pxx/TMIOC1, etc.) as the output of the timer, the corresponding port mode register (PMxx, P) must be used for each port MCxx) bit and port register (Pxx) position "0".
Page 365 BAT32A2x9 user manual | Chapter 10 Timer M 10.4 Common things about multiple patterns 10.4.1 Counting sources The method of selecting the counting source is the same for all patterns. However, in PWM3 mode, an external clock cannot be selected. Table 10-9 Selection of counting sources Counting source...
Page 366 BAT32A2x9 user manual | Chapter 10 Timer M 10.4.2 The buffer operation The TMBFCi (i=0, 1)bits and TMBFDi bits of the TMMR registers can be combined with the TMBRCi registers The TMGRDi registers are set as buffer registers for the TMGRAi registers and the TMGRBi registers, respectively.
Page 367 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-42 The buffer operation of the input capture function TMIOAi input (Enter capture signal). no.). TMGRAi TMGRCi registers (Buffer) register TMIOAi input TMi registers n–1 transmission TMGRAi registers transmission TMGRCi registers (Buffer) Note: i=0,1 The conditions in the above figure are as follows:...
Page 368 BAT32A2x9 user manual | Chapter 10 Timer M In timer mode (input capture function and output comparison function), the following settings must be made. Case of using the TMGRCi (i=0, 1) register as a buffer register for the TMGRAi register: •...
Page 369 BAT32A2x9 user manual | Chapter 10 Timer M 10.4.3 Synchronous Operation Synchronize the TM0 register with the TM1 register. • Sync presets If you write the TMi register when the TMSYNC bit of the TMMR register is "1" (synchronous operation), the data is written to both the TM0 register and the TM1 register. •...
Page 370 BAT32A2x9 user manual | Chapter 10 Timer M 10.4.4 Forced cutoff of the pulse output When using the PWM function or in reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, TMIOji can be cut off by the input of the INTP0 pin Pulse output of the output pins (i=0, 1, j=A, B, C, D).
Page 371 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-45 Forced cutoff of pulse output ELCOBE0 DFCK1，DFCK0 EVENTC event input 0 TMSHUTS bit TIMER M output data INTP0 input TMIOA0 multiplex I/O TMPTO port output data HI-Z selection signal ELCOBE1 EVENTC event input 1 PMxx input data...
Page 372 BAT32A2x9 user manual | Chapter 10 Timer M 10.4.5 Event inputs from the Event Linkage Controller (EVENTC). For events entered by EVENTC, timer M performs 2 operations. (a) Input capture for TMIOD0/TMIOD1 With event input from EVENTC, timer M performs input capture of TMIOD0/TMIOD1. At this point, the IMFD bit of the TMSRi register is "1".
Page 373 BAT32A2x9 user manual | Chapter 10 Timer M 10.5 Operation of timer M 10.5.1 Enter the capture function This is a function of measuring the width and period of an external signal. Triggered with the external signal of the TMIOji pins (i=0, 1, j=A, B, C, D), will be The contents of the TMi register (counter) are transferred to the TMGRji register (input capture).
Page 374 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-46 Block diagram of the input capture function 374 / 1149 Rev.1.00 www.mcu.com.cn...
Page 375 BAT32A2x9 user manual | Chapter 10 Timer M Table 10-12 Specifications for input capture function project specification /2, f /4, f /8, f Count the sources An external input signal from the TMCLK pin that procedurally selects a valid edge count Increment the count When the CCLR2~CCLR0 bits of the TMCRi register are "000B"...
Page 376 BAT32A2x9 user manual | Chapter 10 Timer M Operation example By setting the CCLR0 to CCLR2 bits of the TMCRi registers (i=0, 1), the timer M i is applied when input capture or comparison matching occurs The count value is reset. Fig. 10-47 is an example of the operation when the CCLR2~CCLR0 position "001B"...
Page 377 BAT32A2x9 user manual | Chapter 10 Timer M Digital filters Sample the TMIOji inputs (i=0, 1, j=A, B, C, D) if the signal 3 times the same, the level is considered to have been determined. The function and sample clock of the digital filter must be selected through the TMDFi registers.
Page 378 BAT32A2x9 user manual | Chapter 10 Timer M 10.5.2 Output comparison function This is the content of the detection TMi register (counter) (i=0, 1) and the TMGRji register (j=A, B, C , D) whether the content is the same (comparative match) pattern. If the content is the same, output any level from the TMIOji pin.
Page 379 BAT32A2x9 user manual | Chapter 10 Timer M Table 10-13 Specifications of the output comparison function project specification f CLK , f CLK /2, f CLK /4, f CLK /8, f CLK /32 Count the sources An external input signal from the TMCLK pin that procedurally selects a valid edge count Increment the count...
Page 380 BAT32A2x9 user manual | Chapter 10 Timer M Operation example By setting the CCLR0 to CCLR2 bits of the TMCRi registers (i=0, 1), the timer M i is applied when input capture or comparison matching occurs The count value is reset. If the comparison expectation value is "FFFFH", it changes from "FFFFH"...
Page 381 BAT32A2x9 user manual | Chapter 10 Timer M Change of output pins of the TMGRCi register and the TMGRDi register (i=0, 1). The TMGRCi register and the TMGRDi register can be used for output control of the TMIOAi pin and the TMIOBi pin, respectively.
Page 382 BAT32A2x9 user manual | Chapter 10 Timer M An example of how TBGRCi and TMGRDi are used for output control of the TMIOAi pin and TMIOBi pin, respectively, is shown in Figure 10-52. Figure 10-52 uses tMGRCi and TMGRDi for examples of operation when using output control of the TMIOAi pin and TMIOBi pin, respectively counting source value in Tmi register...
Page 383 BAT32A2x9 user manual | Chapter 10 Timer M The TMOCR registers TOAi bits and TOBi bits are "0" (the initial output "L" level is before the comparison matches). The IOA2~IOA0 bits of the TMIORAi register are "011B" (TMIOAi inverts the output when the TMGRAi comparison matches). The IOB2~IOB0 of the TMIORAi register is "011B"...
Page 384 BAT32A2x9 user manual | Chapter 10 Timer M 10.5.3 PWM function This is the function of the output PWM waveform. Up to 3 PWM waveforms of the same period can be output via the timer Mi (i=0, 1). By synchronizing timer M0 with timer M1, up to six PWM waveforms of the same period can be output.
Page 385 BAT32A2x9 user manual | Chapter 10 Timer M Table 10-14 Specifications for PWM functions project specification Count the sources /2, f /4, f /8, f An external input signal from the TMCLK pin that can programmatically select valid edges count Increment the count PWM waveform PWM period: 1/fk×(m+1) Effective level width: 1/fk×(m–n) Invalid level width: 1/fk×(n+1).
Page 386 BAT32A2x9 user manual | Chapter 10 Timer M Operation example Figure 10-54 Example of operation of the PWM function counting source value in Tmi register Time "L" voltage invalid TMIOBi output "H" voltage valid initial output "L" voltage level before compare matching TMIOCi output initial output "H"...
Page 387 BAT32A2x9 user manual | Chapter 10 Timer M Fig 10-55 PWM Example of running a feature (duty cycle 0% and 100%) TMi寄存器的值 value in TMi register Time TSTRATi bit of TMIOBi will not output "L" voltage level since TMSTR register 因为不发生TMGRBi寄存器的比较匹配，...
Page 388 BAT32A2x9 user manual | Chapter 10 Timer M 10.5.4 Reset synchronous PWM mode Outputs the same-period PWM waveforms (three-phase, sawtooth wave modulation, no dead time) of 3 normal phases and 3 inverted phases (6 in total). The block diagram and operation example of the reset synchronous PWM mode are shown in Figures 10-56 and 10-57, respectively, and the specifications of the reset synchronous PWM mode are shown in Table 10-15.
Page 389 BAT32A2x9 user manual | Chapter 10 Timer M Table 10-15 Specifications for Reset Synchronous PWM Mode specification project /2, f /4, f /8, f An external input signal from the TMCLK pin that can Count the sources programmatically select valid edges TM0 is an incremental count (TM1 is not used).
Page 390 BAT32A2x9 user manual | Chapter 10 Timer M Operation example Figure 10-57 Operation example of reset synchronous PWM mode counting source TMi寄存器的值 value in TMi register Time TSTRATi bit of TMSTR register TMIOB0 output TMIOD0 output TMIOA1 output TMIOC1 output TMIOB1 output Initial output H voltage level...
Page 391 BAT32A2x9 user manual | Chapter 10 Timer M 10.5.5 Complementary PWM mode Outputs the same-period PWM waveforms (three-phase, triangular wave modulation, dead time) of 3 normal phases and 3 inverting phases (6 in total). The block diagram of the complementary PWM mode is shown in Figure 10-58, the specifications of the complementary PWM mode are shown in Table 10-16, and the output model and running example of the complementary PWM mode are shown in Figure 10-59, respectively and Figure 10-60.
Page 392 BAT32A2x9 user manual | Chapter 10 Timer M Table 10-16 Specifications for Complementary PWM Modes project specification Count the sources /2, f /4, f /8, f An external input signal from the TMCLK pin that can programmatically select valid edges The same values must be set for the TCK0~TCK2 bits of the TKG0 register and the TCK0~TCK2 bits of the TMCR1 register (same count source).
Page 393 BAT32A2x9 user manual | Chapter 10 Timer M Operation example Fig. 10-59 Output model of complementary PWM mode TMi register The value of the The value of the TM0 register TMGRA0The value of the register The value of the TM1 register TMGRB0 register The value of the TMGRA1 register...
Page 394 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-60 operation example of complementary PWM mode counting source value in TMi register value in TM0 register value in TM1 register Time change to "FFFFH" TSTRATi bit of TMSTR register TMIOB0 output Initial output voltage level "L"...
Page 395 BAT32A2x9 user manual | Chapter 10 Timer M Data transfer timing for buffer registers TMGRD0, TMGRC1, TMGRD1 registers to TMGRB0, TMGRA1, TMGRB1 register data is transferred to TMFCR The CMD1 bits and CMD0 bits of the registers are "10B" and data transfer occurs when TM1 underflow occurs.
Page 396 BAT32A2x9 user manual | Chapter 10 Timer M Table 10-17 Specifications for PWM3 mode specification project /2, f /4, f /8, f Count the sources TM0 is an incremental count (TM1 is not used). count PWM period: 1/fk×(m+1). Effective level width for TMIOA0 output: 1/fk×(m–n). Effective level width for TMIOB0 output: 1/fk×(p–q).
Page 397 BAT32A2x9 user manual | Chapter 10 Timer M Operation example Figure 10-62 Example of operation of the PWM3 mode counting source value in TMi register Time TSTRAT0 bit of TMSTR register Stop counting set to 0 via program CSEL0 bit of TMSTR register initial output "H"...
Page 398 BAT32A2x9 user manual | Chapter 10 Timer M 10.6 Timer M interrupt Timer M generates timer M i (i=0, 1) interrupt requests from each of the six interrupt sources of timer M 0 and timer M1. The associated registers for the timer M interrupt are shown in Table 10-18, and the block diagram of the timer M interrupt is shown in Figure 10-63.
Page 399 BAT32A2x9 user manual | Chapter 10 Timer M Because timer M generates 1 interrupt request from multiple interrupt request sources (timer M interrupt), there is the following difference between timer RG interrupts and other maskable interrupts: • TMIFi of the IF2H register when the bit of the TMSRi register is "1" and the bit of the corresponding TMEEi register is "1"...
Page 400 BAT32A2x9 user manual | Chapter 10 Timer M • The status of the timer M status register i (TMSRi). must cclear request bit — — IMFD IMFC IMFB IMFA TMSRi The status flag (IMFA) corresponding to the interrupt-enable bit is "1", so both IMFA and IMFB must be written "0".
Page 401 BAT32A2x9 user manual | Chapter 10 Timer M 10.7 Considerations when using timer M 10.7.1 Read and write access to SFR To set the timer M, you must first place the TMMEN position of the PER1 register "1". When the TMMEN bit is "0", the write operation of the control register of timer M is ignored, and the read values are initial values (except for port registers and port mode registers).
Page 402 BAT32A2x9 user manual | Chapter 10 Timer M 10.7.3 Counting sources •To switch the counting source, you must switch after stopping counting. [Change Step]. (1) Place the TSTARTi bits (i=0, 1) of the TMSTR register to "0" (stop count). (2) Change the TCK0~TCK2 bit of the TMCRi register. •...
Page 403 BAT32A2x9 user manual | Chapter 10 Timer M 10.7.6 External clock TMCLK The pulse width of the external clock input to the TMCLK pin must be at least 3 timer M operating clock cycles. Reset synchronous PWM mode • When this mode is used for motor control, it must be used under the condition of OLS0=OLS1. •...
Page 404 BAT32A2x9 user manual | Chapter 10 Timer M Figure 10-64 Example of operation when the TM0 and TMGRA0 registers in the complementary PWM mode are matched TM0 register counting value configure value m of TMGRA0 register Time set to 0 via program remain unchanged IMFA bit of...
Page 405 BAT32A2x9 user manual | Chapter 10 Timer M •The data transfer timing from the buffer register to the general-purpose register must be selected by the CMD0 bit and CMD1 bit of the TMFCR register. However, in the case of 0% duty cycle and 100% duty cycle, regardless of the values of CMD0 bits and CMD1 bits, the following transmission timing is the following.
Page 406 BAT32A2x9 user manual | Chapter 10 Timer M register and the PWM waveform is output when the TM1 counter underflow occurs. After the PWM waveform is output, the value of the buffer register is transmitted to the general-purpose register via the timing set by CMD0 bits.
Page 407 BAT32A2x9 user manual | Chapter 10 Timer M waveform is output, the value of the buffer register is transmitted to the general-purpose register via the timing set by CMD0 bits. You cannot directly change from the output of 0% positive phase duty cycle and 100% inverting phase to the output of 100% duty cycle of positive phase and 0% duty cycle of inverting phase.
Page 408 BAT32A2x9 user manual | Chapter 10 Timer M 10.8 PWMOP The PWMOP the Timer M unit can implement the output forced cutoff function of . The cutoff source can be CMP0, INTP0 EVENT from timer selected from , and . This is different M's own pulse forced cutoff function.
Page 409 BAT32A2x9 user manual | Chapter 10 Timer M 10.8.1 Features of PWMOP PWMOP can implement the following functions: The output of comparator 0, the INTP0 input, and the event input of EVENTC can be selected as output force cutoff sources. When selecting the output of comparator 0 and the input of INTP0 as the source, you can select the edge checkout.
Page 410 BAT32A2x9 user manual | Chapter 10 Timer M PWMOP control register 0 (OPCTL0). Figure 10-69 Format of PWMOP control register 0 Address: 0x40043C58 after reset: 00H R/W Symbol OPCTL0 HAZAD_SET IN_EG IN_SEL1 IN_SEL0 HZ_REL HS_SEL HAZAD_SET Output forced cut-off hazard control Note 1 of hazard countermeasures Prohibition...
Page 411 BAT32A2x9 user manual | Chapter 10 Timer M HS_REL Outputs a mode selection for forced cutoff Hardware release: When using hardware to deactivate the output, the timing is different depending on the action mode of timer M. Timer M complementary PWM mode: After monitoring the release source, the edge of TMIOC0 selected according to OPEDGE is decommissioned.
Page 412 BAT32A2x9 user manual | Chapter 10 Timer M PWMOP Forced CutOff Control Register 0 (OPDF0). Figure 10-70 PWMOP Forced Cutoff Control Register 0 Format Address: 0x40043C59 after reset: 00H R/W Symbol OPDF0 DFD01 DFD00 DFC01 DFC00 DFB01 DFB00 DFA01 DFA00 DFD01 DFD00 TMIOD0 pin output forced cutoff control...
Page 413 BAT32A2x9 user manual | Chapter 10 Timer M PWMOP Forced Cutoff Control Register 1 (OPDF1). Figure 10-71 Format of PWMOP Forced Cutoff Control Register 1 Address: 0x40043C5A after reset: 00H R/W Symbol OPDF1 DFD11 DFD10 DFC11 DFC10 DFB11 DFB10 DFA11 DFA10 DFD11 DFD10...
Page 414 BAT32A2x9 user manual | Chapter 10 Timer M PWMOP edge selection register (OPEDGE). When timer M is operating in complementary PWM mode and a hardware de-output is forced to cut off, the deregistration point can be set via the OPEDGE register. Figure 10-72 the format of PWMOP edge selection register Address: 0x40043C5B after reset: 00H R/W...
Page 415 BAT32A2x9 user manual | Chapter 10 Timer M PWMOP Status Register (OPSR). Figure 10-73 Format of the PWMOP status register Address: 0x40043C5C after reset: 00H R Symbol OnSR HZOF1 HZOF0 HZIF0 HZOF1 Mandatory cut-off status Normal Timer output (TMIOA1，TMIOB1，TMIOC1，TMIOD1) Force cutoff state (TMIOA1,TMIOB1,TMIOC1,TMIOD1) HZOF0 Mandatory cut-off status Normal Timer output (TMIOA0，TMIOB0，TMIOC0，TMIOD0)
Page 416 BAT32A2x9 user manual | Chapter 10 Timer M 10.8.3 Operation of PWMOP The output of comparator 0, the INTP0 input, and the event input of EVENTC can be selected as output force cutoff sources. When selecting the output of comparator 0 and the input of INTP0 as the source, you can select the edge checkout.
Page 417 BAT32A2x9 user manual | Chapter 10 Timer M –74 Figure 10 Example of output force cutoff/hardware de-output force cutoff pin being forced to cut off (Example of TMIOB0, TMIOC0, TMIOD0 PWMOP operational clock valid timing signal when TM0 counter at 0000H.
Page 418 BAT32A2x9 user manual | Chapter 10 Timer M –75 Figure 10 Detailed timing diagram of the forced cutoff PWMOP operational clock TIMER M counter0 comparator0 output HZIF0 TMIOB0 output Note 1 from PWMOP. TMIOB0 output Note 2 from Timer M. TMIOC0 output Note 1 from PWMOP.
Page 419 BAT32A2x9 user manual | Chapter 10 Timer M –76: Figures 10 Detailed timing diagram of forced cutoff release (count source for timer M = Fclk). PWMOP operational clock TIMER M counter0 valid timing signal when TM0 counter at 0000H. comparator0 output HZIF0 TMIOB0 output Note 1...
Page 420 BAT32A2x9 user manual | Chapter 10 Timer M – Figure 10 77: Detailed timing diagram of forced cut-off release (count source of timer M = Fclk/2). PWMOP operational clock TIMER M counter0 valid timing signal when TM0 counter at 0000H. comparator0 output HZIF0 TMIOB0 output...
Page 421 BAT32A2x9 user manual | Chapter 10 Timer M （2） The occasion of complementary PWM function output After the source is detected, the edge of TMIOC0 selected according to OPEDGE is decommissioned. Figure 10-78 Example of hardware deforce cutoff (take TMIOB0, TMIOD0 as an example). PWMOP operational clock TMIOC0 output...
Page 422 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-79 Detailed timing diagram of forced cut-off release (count source of timer M = Fclk, decrement count). PWMOP operational clock TIMER M counter 1 TMIOC0 output from Timer M comparator0 output HZIF0 TMIOB0 output Note 1...
Page 423 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-80 Detailed timing diagram of forced cutoff release (count source for timer M = Fclk, counter = TMGRA0). PWMOP operational clock TIMER M counter0 TMIOC0 output from Timer M Comparator 0 output HZIF0 TMIOB0 output Note 1...
Page 424 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-81 Detailed timing diagram of forced cut-off release (count source of timer M = Fclk/2, decrement count). PWMOP operational clock TIMER M counter 1 TMIOC0 output from Timer M Comparator 0 output HZIF0 TMIOB0 output Note 1...
Page 425 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-82 Detailed timing diagram of forced cut-off release (count source of timer M = Fclk/2, counter = TMGRA0). PWMOP operational clock TIMER M counter0 TMIOC0 output from Timer M Comparator 0 output HZIF0 TMIOB0 output Note 1...
Page 426 BAT32A2x9 user manual | Chapter 10 Timer M 10.8.3.3 Software release (HS_SEL=1). The ACT settings of OPCTL0 are different, and the forced cutoff is released in different timings. （1） Immediately unblock (ACT=0) using the software If ACT=0 is set, once the H Z_REL bit of theOPCTL0 register is set to 1, the enforcement cutoff is immediately lifted.
Page 427 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-84 Detailed timing diagram of forced cutoff release PWMOP operational clock TIMER M counter0 forced cut-off release control HZ_REL TMIOB0 output Note 1 from PWMOP. TMIOB0 output Note 2 from Timer M. TMIOC0 output Note 1 from PWMOP.
Page 428 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-85 Example of software release forced cutoff (timer M, 2-channel count PWMOP operational clock TMSTR.TSTART0 TMSTR.TSTART1 valid signal when count of TM0 is 0000H. valid signal when count of TM1 is 0000H.
Page 429 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-86 Example of software release cutoff (timer M, 1 channel count PWMOP operational clock TMSTR.TSTART0 TMSTR.TSTART1 valid signal when count of TM0 is 0000H. valid signal when count of TM1 is 0000H.
Page 430 BAT32A2x9 user manual | Chapter 10 Timer M （b） Timer M operates in reset synchronous PWM mode Set the HZ_REL to 1, and at a T M0 count value of 00 000H, the output force cutoff of all T MIO pins is removed.
Page 431 BAT32A2x9 user manual | Chapter 10 Timer M （c） The timer operates in complementary PWM modes After the HZ_REL is set to 1, the edge of TMIOC0 selected by OPEDGE is lifted from the forced cutoff. Figure 10-88 Example of software release forced cutoff (take TMIOB0, TMIOD0 as an example PWMOP operational clock ACT bit of OPCTL0...
Page 432 BAT32A2x9 user manual | Chapter 10 Timer M 10.8.3.4 Hazard countermeasures If the TMIO pin switches between the multiplexing function and the PORT function in the forced cut-off state/forced cut-off state/timer M action, there is a risk of malfunction. The H AZAD_SET can be set to 1 to allow hazard countermeasures to avoid this risk.
Page 433 BAT32A2x9 user manual | Chapter 10 Timer M 10.8.3.5 Outputs force-cut source checkout and unchecked out states Whether the output forced cutoff source is checked out is selected by the cutoff source bit (OPCTL0. IN_SEL1,OPCTL0. IN_SEL0) The level of the selected signal (INTP0, CMP0) is determined. If you set OPCTL0.
Page 434 BAT32A2x9 user manual | Chapter 10 Timer M 10.8.3.6 Timing plot of the counter of timer M reaches 0000H When the hardware releases the output force cutoff, the force cutoff condition varies depending on the action mode of timer M. （1）...
Page 435 BAT32A2x9 user manual | Chapter 10 Timer M Fig. 10-91 timing sequence when count value = 0000H (Count source = Fclk/2, timer M count value reaches 0000H at the next cycle counter stop). PWMOP operational clock TIMER M counting TMSTR.TSTART0 detection signal when TIMER M count = 0000H 435 / 1149...
Page 436 BAT32A2x9 user manual | Chapter 10 Timer M 10.8.3.7 Setup steps The PWMOP may be associate with that timer M, and the setting of the PWMOP may be appended to the setting of the timer M. The steps are as follows: After Timer M's clock and mode are set Set PWMOPEN to 1 Set up OPCTL0 register...
Page 437 BAT32A2x9 user manual | Chapter 10 Timer M 10.8.4 Precautions (1) When the pulse output forced cutoff of timer M works at the same time as the output force cutoff of PWMOP, the priority is as follows: Table 10-22 Priority at the time of enforcement deadline Pin status at PWMOP forced cutoff forbid Hi-Z...
Page 438 BAT32A2x9 user manual | Chapter 11 Real-time clock Chapter 11 Real-time clock 11.1 The function of a real-time clock The real-time clock has the following functions. • Holds a counter of years, months, days, hours, minutes, and seconds that can be counted up to 99 years.
Page 439 BAT32A2x9 user manual | Chapter 11 Real-time clock Figure 11-1 Block diagram of real-time clock real time clock control register 1 real time clock control register 0 secondary system provide mode control register (OSMC) alarm week alarm hour alarm minute register regsiter register...
Page 440 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3 Control Registers the real-time clock The real-time clock is controlled by the following registers. • Peripheral enable register 0 (PER0). • Real-time clock selection register (RTCCL). • Real-time clock control register 0 (RTCC0). •...
Page 441 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.1 Peripheral enable register 0 (PER0). The PER0 register is a register that is set to allow or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use a real-time clock, bit7 (RTCEN) must be set to "1".
Page 442 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.2 Real-time clock selection register (RTCCL). The count clock (fRTC) of the real-time clock and the 15-bit interval timer can be selected via RTCCL. Figure 11-3 Format of the real-time clock selection register (RTCCL). Address: 0x4004047C after reset: 00H R/W Symbol RTCCL7...
Page 443 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.3 Real-time clock control register 0 (RTCC0). This is an 8-bit register that sets the start or stop of the real-time clock, the control of the RTC1HZ pin, the 12/24-hour system, and the fixed cycle interrupt function. The RTCC0 register is set via the 8-bit memory operation instruction.
Page 444 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.4 Real-time clock control register 1 (RTCC1). This is an 8-bit register that controls the alarm interrupt function and counter waits. The RTCC1 register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H".
Page 445 BAT32A2x9 user manual | Chapter 11 Real-time clock Figure 11-5 Format of real-time clock control register 1 (RTCC1) (2/2). Fixed-cycle interrupt status flag RIFG There are no fixed cycle interruptions. Generates a fixed cycle interrupt. This is a status flag that indicates a fixed-cycle interrupt. When a fixed-cycle interrupt is generated, this flag is "1".
Page 446 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.5 Clock Error Correction Register (SUBCUD). This is a register that can correct the clock speed with high accuracy by changing the overflow value (reference value: 7FFFH) from the internal counter (16 bits) to the second count register (SEC). Set the SUBCUD registers via 16-bit memory manipulation instructions.
Page 447 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.6 Seconds Count Register (SEC). This is an 8-bit register that represents the second count value from 0 to 59 (decimal). The count is incremented by the overflow of the internal counter (16 bits). At write time, the data is first written to the buffer and to the counter after passing through up to 2 fRTC clocks.
Page 448 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.8 Hour Count Register (HOUR). This is 8 of the hour count value expressed in 00 to 23 or 01 to 12, 21 to 32 (decimal). Bit registers. The count is incremented by the overflow of the minute counter. At write time, the data is first written to the buffer and to the counter after passing through up to 2 fRTC clocks.
Page 449 BAT32A2x9 user manual | Chapter 11 Real-time clock The relationship between the setting value of the AMPM bit, the value of the hour count register (HOUR), and the time is shown in Table 11-2. Table 11-2 Representation of time bits 24-hour representation (AMPM=1).
Page 450 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.9 Day count register (DAY). This is an 8-bit register that represents the daily count value from 1 to 31 (decimal). The count is incremented by the overflow of the hour counter. Counters make the following counts. •...
Page 451 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.10 Week Count Register (WEEK). This is an 8-bit register that represents the week count value in 0 to 6 (decimal). Increment the count synchronously with the daily counter. At write time, the data is first written to the buffer and to the counter after passing through up to 2 fRTC clocks.
Page 452 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.11 Month count register (MONTH). This is an 8-bit register that represents the monthly count value from 1 to 12 (decimal). The count is incremented by the overflow of the daily counter. At write time, the data is first written to the buffer and to the counter after passing through up to 2 f clocks.
Page 453 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.3.13 Alarm clock minute register (ALARMWM). This is the register for setting the alarm minute. The ALARMWM register is set by the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H". in the code Note that the decimal value must be set to 00~59...
Page 454 BAT32A2x9 user manual | Chapter 11 Real-time clock An example of setting the alarm time is shown below. week 12 hours indicates 24 hours indicated Monda Tuesda Wedne Thursd Saturda Sunday Friday sday Alarm setting time o'cloc o'clo minut minu o'cloc o'clo minut...
Page 455 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.4 Operation of a real-time clock 11.4.1 The operation of the real-time clock begins Figure 11-19 The start steps of the operation of the real-time clock start configure to provide Note1 RTCEN=1 input clock RTCE=0 configure to stop counting...
Page 456 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.4.2 Start the transfer of sleep mode after running To transfer to sleep (including deep sleep) mode immediately after the RTCE position "1", one of the following processes must be performed. However, after placing the RTCE position "1", these processes are not required if you want to move to sleep mode after an INTTTC interrupt occurs.
Page 457 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.4.3 Read and write to the real-time clock counter The RWAIT must first be set to "1" and then the counter must be read and written. The RWAIT position must be "0" after reading and writing the counter. Figure 11-21 The read operation procedure of the real-time clock counter start configure as SEC~Year counter...
Page 458 BAT32A2x9 user manual | Chapter 11 Real-time clock Figure 11-22: Read procedure for a real-time clock counter Start configure as SEC~Year counter RWAIT=1 stop operating, enter into read/ write mode of counter. confirm counter wait state RWST=1? 设定SEC Write SEC Write second count register Write MIN Write minute count register...
Page 459 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.4.4 Alarm settings for the real-time clock You must first place the WALL position "0" (the alarm does not run invalid) and then set the alarm time. Figure 11-23 Alarm setting steps Start WALE=0 alarm alignment operation invalid...
Page 460 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.4.5 1Hz output of the real-time clock Figure 11-24 Setup steps for the 1Hz output " must first be Note 1 RTCEN position 1" placed in the oscillation stable state of the counting clock (f output function of real-time 2.
Page 461 BAT32A2x9 user manual | Chapter 11 Real-time clock 11.4.6 An example of clock error correction for a real-time clock High-precision clock speed correction can be performed by setting the value of the clock error correction register. Example of the method of calculating the corrected value The correction value when correcting the count value of the internal counter (16 bits) can be calculated –4165.6ppm to 4165.6ppm using the following formula.
Page 462 BAT32A2x9 user manual | Chapter 11 Real-time clock Correction example Example of correction from 32767.4Hz to 32768Hz (32767.4Hz +18.3ppm). 【Measurement of oscillation frequency】 When the clock error correction register (SUBCUD) is the initial value ("0000H"), the oscillation frequency of each product is measured by outputting a signal of approximately 1Hz from the RTC1HZ pin. Note For the setup steps of the RTC1Hz output, please refer to "11 1.4.5 1Hz Output of the Real-Time Clock".
Page 463 BAT32A2x9 user manual | Chapter 12 15-bit interval timer Chapter 12 15-bit interval timer 12.1 1Function of 5-bit interval timer Generate interrupts (INTIT) at any pre-set interval that can be used for wake-up from deep sleep mode. 12.2 Structure of the 15-bit interval timer The 15-bit interval timer consists of the following hardware.
Page 464 BAT32A2x9 user manual | Chapter 12 15-bit interval timer 12.3 control Registers of the 15-bit interval timer The 15-bit interval timer is controlled by the following registers. • Peripheral enable register 0 (PER0). • Real-time clock selection register (RTCCL). • Control Register (ITMC) for 15-bit interval timers 12.3.1 Peripheral enable register 0 (PER0).
Page 465 BAT32A2x9 user manual | Chapter 12 15-bit interval timer 12.3.2 Real-time clock selection register (RTCCL). The real-time clock and the count clock (fRTC) of the 15-bit interval timer can be selected via RTCCL. Figure 12-3 Format of the Real-Time Clock Selection Register (RTCCL). Address: 0x4002047C after reset: 00H R/W Symbol...
Page 466 BAT32A2x9 user manual | Chapter 12 15-bit interval timer 12.3.3 Control Register (ITMC) for 15-bit interval timers This is the register that sets the start and stop of the run of the 15-bit interval timer and the comparison value. Set the ITMC registers with 16-bit memory operation instructions. After generating a reset signal, the value of this register becomes "7FFFH".
Page 467 BAT32A2x9 user manual | Chapter 12 15-bit interval timer 12.4 15-bit interval timer operation 12.4.1 Operation sequence of the 1 5-bit interval timer Operation as a 15-bit interval timer for repeatedly generating interrupt requests (INTIT) in intervals of the count value set by ITCMP14 ~ ITCMP0 bits. If you place the RINTE at "1", the 15-bit counter starts counting.
Page 468 BAT32A2x9 user manual | Chapter 12 15-bit interval timer 12.4.2 After returning from sleep mode, the operation of the counter begins and then transition to sleep mode again After returning from sleep mode, if you want to transfer the RINTE position "1" and to sleep mode again, you must confirm that the write value of the RINTE bit is reflected after the RINTE position "1"...
Page 469 BAT32A2x9 user manual | Chapter 13 Clock output/buzzer output control circuitry Chapter 13 Clock output/buzzer output control circuitry 13.1 the function of controls circuitry of Clock output/buzzer output The clock output is the function of outputing the clock to the peripheral IC, and the buzzer output is the function of outputting the buzzer frequency square wave.
Page 470 BAT32A2x9 user manual | Chapter 13 Clock output/buzzer output control circuitry 13.2 Structure of the clock output/buzzer output control circuit The clock output/buzzer output control circuit consists of the following hardware. Table 13-1 Structure of the clock output / buzzer output control circuit Item structure Control registers...
Page 471 BAT32A2x9 user manual | Chapter 13 Clock output/buzzer output control circuitry Figure 13-2 The clock output selects the format of register n (CKSn). Address: 0x40040FA5 (CKS0), 0x40040FA6 (CKS1) after reset: 00H R/W Symbol PCLOEn CSELn CCSn2 CCSn1 CCSn0 CKSn CLKBUZn pin output enable/disables the designation PCLOEn Disable output (default).
Page 472 BAT32A2x9 user manual | Chapter 13 Clock output/buzzer output control circuitry 13.3.2 Control Registers of the clock output/buzzer output pin port function When used as a clock output/buzzer output function, the control registers (port mode register (PMxx) and port register (Pxx)) that are reused with the port function of the object channel must be set. For details, please refer to "2.3.1 Port Mode Register (PMxx)"...
Page 473 BAT32A2x9 user manual | Chapter 13 Clock output/buzzer output control circuitry 13.4 the operation of Clock output/buzzer output controls circuitry It can be selected as a clock output or buzzer output with 1 pin. The CLKBUZ0 pin outputs a clock/buzzer selected by clock output select register 0 (CKS0). The CLKBUZ1 pin outputs a clock/buzzer selected by clock output select register 1 (CKS1).
Page 474 BAT32A2x9 user manual | Chapter 14 Watchdog timer Chapter 14 Watchdog timer 14.1 The function of the watchdog timer The watchdog timer operates with an option byte (000C0H) to set the count. The watchdog timer operates with a low-speed internal oscillator clock (f ).
Page 475 BAT32A2x9 user manual | Chapter 14 Watchdog timer Figure 14-1 Diagram of Watchdog Timer interval time control circuit option bytes (000C0H) interval time (count value overflow time x3/4 WDTINT +1/2fIL) option bytes (000C0H) WDCS2~WDCS0 interval clock overflow signal counter input selector reset control...
Page 476 BAT32A2x9 user manual | Chapter 14 Watchdog timer 14.3 Control registers of the watchdog timer The watchdog timer is controlled by the watchdog timer's Allow Register (WDTE). 14.3.1 The Watchdog Timer's enable Register (WDTE). By writing "ACH" to the WDTE register, clear the watchdog timer counter and start counting again. The WDTE register is set via the 8-bit memory operation instruction.
Page 477 BAT32A2x9 user manual | Chapter 14 Watchdog timer 14.3.2 LockUP Control Register (LOCKCTL) and its Protection Register (PRCR). The LOCKCTL register is the configuration register for whether the Cortex-M0+ LockUp function causes the watchdog timer to run, and the PRCR is its write-protect register. Set lockCTL, PRCR registers via 8-bit memory operation instructions.
Page 478 BAT32A2x9 user manual | Chapter 14 Watchdog timer 14.3.3 WDTCFG Configuration Register (WDTCFG0/1/2/3) The WDTCFG configuration register is a register that forces the watchdog timer to run. The WDTCFG register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of the WDTCFG register changes to "00H". Figure 14-4 WDTCFG configuration register (WDTCFG0/1/2/3).
Page 479 BAT32A2x9 user manual | Chapter 14 Watchdog timer 14.4 Operation of the watchdog timer 14.4.1 Operational control of the watchdog timer When using the watchdog timer, set the following by option byte (000C0H): • The bit4 (WDTON) of the option byte (000C0H) must be set to "1" to allow the watchdog timer to run count (after the reset is lifted, the counter starts to run) (see Article 33 for details).
Page 480 BAT32A2x9 user manual | Chapter 14 Watchdog timer When running on the X1 oscillating clock after deactivating deep sleep mode, the CPU starts running after the oscillation settling time has elapsed. If the time from the time from the release of deep sleep mode to the timepiece overflow of the watchdog timer is short, a return will occur during the oscillation stabilization time.
Page 481 BAT32A2x9 user manual | Chapter 14 Watchdog timer 14.4.3 The setting during which the watchdog timer window is open Set the window opening period of the watchdog timer by bit6 and bit5 (WINDOW1, WINDOW0) of the option bytes (000C0H). The window outline is as follows: •...
Page 482 BAT32A2x9 user manual | Chapter 14 Watchdog timer 14.4.4 Setting of watchdog timer interval interrupts By setting the bit7 (WDTINT) of the option byte (000C0H), an interval interrupt (INTWDTI) can be generated when the overflow time is reached at 75% +1/2fIL. Table 14-5 Watchdog timer interval interrupt settings WDTINT...
Page 483 BAT32A2x9 user manual | Chapter 15 A/D converter Chapter 15 A/D converter 15.1 Functions of the A/D converter The A/D converter is a converter that converts analog inputs to digital values and supports A/D conversion of up to 31 analog channels (28external pin input channels and 3 internal channels). The number of external analog input channels for the A/D converter is related to each product as shown in the following table.
Page 484 BAT32A2x9 user manual | Chapter 15 A/D converter Figure15-1 Block Diagram of A/D converter 484 / 1149 Rev.1.00 www.mcu.com.cn...
Page 485 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2 Control registers of the A/D converter The registers that control the A/D converter are as follows: Register base address: CSC_BASE=4002_0420H; ADC_BASE=4004_5000H; PORT_BASE=4004_0000H Reset the Register name Register description Register address value PER0 Peripheral enable register 0 CSC_BASE+20H...
Page 486 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.1 Peripheral enable register 0 (PER0). The PER0 register is a register that is set to allow or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use the A/D converter, bit5 (ADCEN) must be set to "1".
Page 487 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.2 The mode register 0 (ADM0) of the A/D converter Registers for setting the A/D conversion clock, conversion start or stop. The ADM0 register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H".
Page 488 BAT32A2x9 user manual | Chapter 15 A/D converter Table15-1 Settings for ADCS bits and ADCCE bits The A/D conversion runs ADCS ADCE The transition stopped state Transition standby Prohibit settings. Transition run status Table15-2 ADCS bits for positioning and clearing conditions Placement A/D conversion mode Clear the condition...
Page 489 BAT32A2x9 user manual | Chapter 15 A/D converter Figure15-4 Motion state Diagram while using the various modes of A/D ADCS write ADCS Auto clear to zero while A/D write conversion completes software trigger mode Note1 (ADCS) conversion stops conversion idle conversion ongoing conversion idle detected...
Page 490 BAT32A2x9 user manual | Chapter 15 A/D converter Table15-3 Selection of A/D conversion times (1/2). (1) No A/D power settling wait time (software trigger mode/hardware trigger no wait mode The mode of the The mode of the A/D 1 conversion time for 2-bit resolution A/D converter converter Converts the...
Page 491 BAT32A2x9 user manual | Chapter 15 A/D converter Selection of A/D conversion time (2/2). Note 1 (2) There is an A/D power supply settling wait time (hardware trigger wait mode The mode of the A/D The mode of the converter A/D power A/D converter frequency...
Page 492 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.3 The mode register 1 (ADM1) of the A/D converter This is the register that sets the A/D conversion mode. The ADM1 register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H". Figure15-5 mode register 1 (ADM1) of the A/D converter Reset value: 00H ADM1...
Page 493 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.4 The mode register 2 (ADM2) of the A/D converter Set the ADM2 registers via the 8-bit memory operation instructions. After generating a reset signal, the value of this register changes to "00H". Figure15-6 mode register 2 (ADM2) of A/D converters (1/3).
Page 494 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.5 The A/D converter's trigger mode register (ADTRG). This is the register that sets the A/D conversion trigger mode and the hardware trigger signal. The ADTRG register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H".
Page 495 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.6 Analog input channel specified register (ADS). This is the register that specifies the analog voltage input channel to be converted to A/D. Set the ADS registers via the 8-bit memory operation instructions. After generating a reset signal, the value of this register changes to "00H".
Page 496 BAT32A2x9 user manual | Chapter 15 A/D converter Note 1 If you select the internal reference voltage (1.45V) as the reference voltage for comparator 0 or comparator 1, the temperature sensor output cannot be selected. ○4-channel scan mode (ADM1. ADMD=1) Analog input channel ADS4 ADISS...
Page 497 BAT32A2x9 user manual | Chapter 15 A/D converter ○2 channel scan mode (ADM1. ADMD=1) Analog input channel ADISS ADS[4:0] Scan 0 Scan 1 1'b0 5'h00 ANI0 ANI1 1'b0 5'h01 ANI1 ANI2 1'b0 5'h02 ANI2 ANI3 1'b0 5'h03 ANI3 ANI4 1'b0 5'h04 ANI4 ANI5...
Page 498 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.7 12-bit A/D conversion result register (ADCR). This is the 16-bit register that holds the results of the A/D conversion, which is readable only. Whenever an A/D conversion ends, the conversion result note is loaded from the successive approximation register (SAR). The high 4 bits of this register are fixed to "0"...
Page 499 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.8 8-bit A/D conversion result register (ADCRH). note This is an 8-bit register that holds the A/D conversion results, saving a high 8-bit with 12-bit resolution. registers via Read the ADCRH the 8-bit memory operation instructions. After generating a reset signal, the value of this register changes to "00H".
Page 500 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.9 The conversion result compares the upper limit value of the set register (ADUL). This is the setting register used to check the upper limit of the A/D conversion result. Compare the A/D conversion results with the values of the ADUL registers, and the ADRCK the mode register 2 (ADM2) of the A/D converter The setting range of bits controls the generation of an interrupt signal register...
Page 501 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.11 A/D Sampling Time Control Register (ADNSMP). This register controls the A/D sampling time. The ADNSMP register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "0dH". Figure15-14A/D Sampling Time Control Register (ADNSMP).
Page 502 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.12 A/D sampling time extended register (ADSMPWAIT). This register is used to extend the A/D sampling time. The ADSMPWAIT register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H". Figure15-15 A/D Sampling Time Extension Register (ADSMPWAIT).
Page 503 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.13 A/D Test Register (ADTES). This register is used to set the test mode of the A/D converter. The ADTES register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H". Figure15-16 A/D Test Register (ADTES).
Page 504 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.14 A/D status register (ADFLG). This register represents the status of the A/D converter. Read the ADFLG registers via the 8-bit memory operation instructions. After generating a reset signal, the value of this register changes to "00H". Figure15-17 A/D Status Register (ADFLG).
Page 505 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.15 A/D Charge and Discharge Control Register (ADNDIS). This register is used to control the charge and discharge action and time of the A/D converter. Read and write ADNDIS registers via 8-bit memory manipulation instructions. After generating a reset signal, the value of this register changes to "00H".
Page 506 BAT32A2x9 user manual | Chapter 15 A/D converter 15.2.16 Registers that control the pin function of the analog input pins Control registers (PIN Mode Control Registers (PMCxx)) for pin function multiplexing with the analog inputs of the A/D converter must be set. For details, please refer to "2.3." 8-pin mode control register (PMCxx)". When using the ANIx pins as analog inputs to A/D converters, the corresponding pin-mode control register (PMCxx) must be placed at position "1".
Page 507 BAT32A2x9 user manual | Chapter 15 A/D converter 15.3 Input voltage and conversion result pin ( ) and theoretical Analog input voltage of the analog input ANIx A/D conversion result (1 2-bit A/D conversion result register (ADCR )) has the following expression relationship. INT(): A function that returns the integer portion of a numeric value in parentheses V AIN: Analog input voltage...
Page 508 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4 The operating mode of the A/D converter The operation of each mode of the A/D converter is as follows. For the setup steps for each mode, refer to "15. 5A/D Converter Setup Flowchart". 15.4.1 Software-triggered mode (selection mode, continuous conversion mode) ①...
Page 509 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.2 Software-triggered mode (select mode, single-shot conversion mode) ① In the stopped state, enter the ADCE position "1" of the A/D converter's mode register 0 (ADM0) into the A/D transition standby state. ②...
Page 510 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.3 Software trigger mode (scan mode, continuous conversion mode) ① In the stopped state, enter the ADCE position "1" of the A/D converter's mode register 0 (ADM0) into the A/D transition standby state. ②...
Page 511 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.4 Software trigger mode (scan mode, single-shot conversion mode) ① In the stopped state, enter the ADCE position "1" of the A/D converter's mode register 0 (ADM0) into the A/D transition standby state. ②...
Page 512 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.5 Hardware-triggered no-wait mode (select mode, continuous transition mode) ① In the stopped state, enter the ADCE position "1" of the A/D converter's mode register 0 (ADM0) into the A/D transition standby state. ②...
Page 513 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.6 Hardware-triggered no-wait mode (select mode, single-shot transition mode) ① In the stopped state, enter the ADCE position "1" of the A/D converter's mode register 0 (ADM0) into the A/D transition standby state. ②...
Page 514 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.7 Hardware-triggered no-wait mode (scan mode, continuous transition mode) ① In the stopped state, enter the ADCE position "1" of the A/D converter's mode register 0 (ADM0) into the A/D transition standby state. ②...
Page 515 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.8 Hardware-triggered no-wait mode (scan mode, single-shot conversion mode) ① In the stopped state, enter the ADCE position "1" of the A/D converter's mode register 0 (ADM0) into the A/D transition standby state. ②...
Page 516 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.9 Hardware-triggered wait mode (selection mode, continuous transition mode) ① In the stopped state, enter the hardware-triggered standby state by placing the ADCE position "1" of the ADM0's mode register 0 (ADM0). ②...
Page 517 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.10 Hardware-triggered wait mode (select mode, single-shot transition mode) ① In the stopped state, enter the hardware-triggered standby state by placing the ADCE position "1" of the ADM0's mode register 0 (ADM0). ②...
Page 518 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.11 Hardware-triggered wait mode (scan mode, continuous transition mode) ① In the stopped state, enter the hardware-triggered standby state by placing the ADCE position "1" of the ADM0's mode register 0 (ADM0). ②...
Page 519 BAT32A2x9 user manual | Chapter 15 A/D converter 15.4.12 Hardware-triggered wait mode (scan mode, single-shot transition mode) ① In the stopped state, enter the hardware-triggered standby state by placing the ADCE position "1" of the ADM0's mode register 0 (ADM0). ②...
Page 520 BAT32A2x9 user manual | Chapter 15 A/D converter 15.5 Setup flowchart for the converter converters for each operating mode The setup flowchart of the A/D is shown below. 15.5.1 The setting of the software trigger mode Figure15-32 software trigger mode configuration starts configure PER0 register set ADCEN bit of PER0 register to 1, start provide clock...
Page 521 BAT32A2x9 user manual | Chapter 15 A/D converter 15.5.2 The hardware triggers the setting of no wait mode Figure15-33 Hardware triggers the setup of no wait mode configuration starts configure PER0 register set ADCEN bit of PER0 register to 1, start provide clock configure PMC register configure port as analog input: configure via PMCx register ADM0 register...
Page 522 BAT32A2x9 user manual | Chapter 15 A/D converter 15.5.3 Hardware triggers the setting of wait mode Figure15-34 Hardware triggers the setup of wait mode configuration starts configuration PER0 set ADCEN bit of PER0 register to 1, start provide clock register configuration PMC register configure port as analog input: configure via PMCx register ADM0 register...
Page 523 BAT32A2x9 user manual | Chapter 15 A/D converter 15.5.4 Select the setting for the output voltage/internal reference voltage of the temperature sensor (Take software trigger mode, single conversion mode as an example) Figure15-35 Settings when selecting the output voltage/internal reference voltage of the temperature sensor configuration starts configuration PER0 set ADCEN bit of PER0 register to 1, start provide clock...
Page 524 BAT32A2x9 user manual | Chapter 15 A/D converter 15.5.5 The setting of the test mode Figure15-36 test mode (VSS/half_VDD/VDD as conversion objects). configuration starts configure PER0 register set ADCEN bit of PER0 register to 1, start provide clock ADM0 register FR2~FR0 bit: configure A/D conversion time.
Page 525 BAT32A2x9 user manual | Chapter 16 D/A converter Chapter 16 D/A converter 16.1 The functionality of the D/A converter The D/A converter is an 8-bit resolution converter that converts a digital input to an analog signal and can control the analog output of 2 channels (ANO0, ANO1). The D/A converter has the following functions: ◼...
Page 526 BAT32A2x9 user manual | Chapter 16 D/A converter 16.2 The structure of the D/A converter The block diagram of the D/A converter is shown in Figure 1 6-1. Fig. 16-1 Block diagram of the D/A converter internal bus D/A conversion value configuration register0 write DACS0 (DACS0)
Page 527 BAT32A2x9 user manual | Chapter 16 D/A converter 16.3 Registers that control the D/A converter The D/A converter is controlled by the following registers. • Peripheral enable register 1 (PER1). • Mode register (DAM) for D/A converters • D/A conversion values set registers 0, 1 (DACS0, DACS1). •...
Page 528 BAT32A2x9 user manual | Chapter 16 D/A converter 16.3.2 The mode register (DAM) of the D/A converter This is the register that controls the operation of the D/A converter. Set the DAM registers via the 8-bit memory manipulation instructions. After generating a reset signal, the value of this register changes to "00H".
Page 529 BAT32A2x9 user manual | Chapter 16 D/A converter 16.3.4 The event output target selection register n (ELSELRn), n=00~21 When using the real-time output mode of the D/A converter, the event signal of the event link controller is used as the initiation trigger, and the D/A conversion is performed. For details, please refer to "24.3.1 Event Output Destination Selection Register n(ELSELRn)(n=00~21)".
Page 530 BAT32A2x9 user manual | Chapter 16 D/A converter 16.4 Operation of the D/A converter 16.4.1 Normal mode of operation The D/A conversion is initiated using the write operation of the DACSi register as the initiation trigger. The setup method is as follows: ①...
Page 531 BAT32A2x9 user manual | Chapter 16 D/A converter 16.4.2 Operation of real-time output mode Each channel of the D/A converter is triggered by the event signal of eventC and the D/A conversion is performed. The setup method is as follows: ①...
Page 532 BAT32A2x9 user manual | Chapter 16 D/A converter 16.4.3 The output timing of the D/A conversion values The output timing of the D/A conversion values is shown in Figure 16-5. general mode real time output mode (DACEi=1) real time output mode (DACEi=0) DAMDi bit operational clock DACSi register write enable...
Page 533 BAT32A2x9 user manual | Chapter 16 D/A converter 16.5 Considerations when using D/A converters Considerations when using D/A converters are as follows. (1) When the port is set to an analog pin through the PMC register (port mode control register), the input/output function of the digital ports with the AN0 pin and anO1 pin multiplexing does not work.
Page 534 BAT32A2x9 user manual | Chapter 17 Comparator Chapter 17 Comparator This product has a built-in comparator with 2 channels. 17.1 The functionality of the comparator The comparator has the following features: • The CMP1's input pins select external ports, internal reference voltage, and built-in DAC reference voltage.
Page 535 BAT32A2x9 user manual | Chapter 17 Comparator 17.2 The structure of the comparator The block diagram of the comparator is shown in Figure 17-1. Fig. 17-1 Block diagram of comparator 0 CMP0SEL C0ENB C0FCK C0EPO C0EDG C0IE VCIN0 PGA0 A/D convertor CMP0 Edge interrupt...
Page 536 BAT32A2x9 user manual | Chapter 17 Comparator Figure 17-2 Block diagram of comparator 1 CMP1SEL C1MON C1ENB C1FCK C1EPO C1EDG C1IE VCIN10 Edge CMP1 选 detection interrupt VCIN11 择 circuit 器 VCIN12 CMP1 EVENTC event VCIN13 noise removal / Digital filter output 选...
Page 537 BAT32A2x9 user manual | Chapter 17 Comparator 17.3 Control registers of the comparator The registers that control the comparator are shown in Table 17-1. Table 17-2 controls the registers of the comparator Register name symbol Peripheral enable register 1 PER1 Comparator mode configure registers COMPMDR Comparator filter control registers...
Page 538 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.1 Peripheral enable register 1 (PER1). The PER1 register is a register that is set to enable or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use the comparator, bit5 (PGACMPEN) must be set to "1".
Page 539 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.2 Comparator Mode Setting Register (COMPMDR). The COMPMDR register is the register that sets the comparator action permission/disable and detects the comparator output. The CiENB bit is disabled to "0" when the comparator output is licensed (CiOE position "1" for compoCR registers).
Page 540 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.3 Comparator Filter Control Register (COMPFIR). The COMPFIR register is the control register for a digital filter. Set the COMFIR registers via the 8- bit memory operation instructions. After generating a reset signal, the value of this register changes to "00H". Figure 17-5 Comparator Filter Control Register (COMPFIR) format Address: 40043841H after reset: 00H R/W...
Page 541 BAT32A2x9 user manual | Chapter 17 Comparator If you change the C0FCK1~C0FCK0 bits from "00B" (comparator 0 without filter) to another value (comparator 0 After has a filter), you must pass before updating the output of the filter 4 samples, use the interrupt request of event signal output to comparator 0 or the EVENTC.
Page 542 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.4 Comparator Output Control Register (COMPOCR). COMPOCR registers are control registers that set the polarity of the comparator output, the permission/disable of the output, and the permission/disable of the interrupt output. In the following cases, it is forbidden to place the CiOE position "1" of the COMCCR register (output license).
Page 543 BAT32A2x9 user manual | Chapter 17 Comparator Note1: When comparator 1 uses TIMER WINDOW mode, the bit7 (C1EDG) of register COMPFIR must be set to "1". C1OE and C1OTWMD bits cannot be set at the same time, and the C1OTWMD bit must be set first, and then the C1OE position should be "1".
Page 544 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.5 The comparator has a built-in reference control register (CVRCTL). The CVRCTL register is the register that sets the allow/stop action of the comparator's built-in reference voltage. The CVRCTL register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H".
Page 545 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.6 The comparator has a built-in reference voltage selection register (CiRVM). The CiRVM register is the register that sets the comparator's built-in reference voltage. When the built-in reference stop action (CVREi=0), the CiRVM register is rewritten The CVRCTL register is set via the 8-bit memory operation instruction.
Page 546 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.7 The input signal of comparator 0 selects the control register (CMPSEL0). The CMPSEL0 register is the positive end of comparator 0 and the selection register for the negative end of the input signal. When the comparator 0 stops (C0ENB=0), the CMPSEL0 register is overwritten.
Page 547 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.8 The input signal of comparator 1 selects the control register (CMPSEL1). The CMPSEL1 register is the positive end of comparator 1 and the selection register for the negative input signal. When comparator 1 stops (C1ENB=0), rewrite the CMPSEL1 register. The CMPSEL1 register is set by the 8-bit memory operation instruction.
Page 548 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.9 Hysteresis control register (CMP0HY) for comparator 0 The CMP0HY register is the hysteresis function control register of comparator 0. When the comparator 0 stops (C0ENB=0), the CMP0HY register is rewritten. The CMP0HY register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H".
Page 549 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.10 Hysteresis control register (CMP1HY) for comparator 1 The CMP1HY register is the hysteresis function control register of comparator 1. When comparator 1 stops (C1ENB=0), rewrite the CMP1HY register. The CMP1HY register is set via the 8-bit memory operation instruction. After generating a reset signal, the value of this register changes to "00H".
Page 550 BAT32A2x9 user manual | Chapter 17 Comparator 17.3.11 Registers that control the function of the analog input pin port When using the VCIN0 pin, VCIN10-VCIN1 3 pin, and VREF0 pin pin as analog inputs to the comparator, the corresponding port mode register (PMxx) must be used for each port) and the position of the port control register (PMCxx) is "1".
Page 551 BAT32A2x9 user manual | Chapter 17 Comparator 17.4 Run the instructions Comparators 0 and comparator 1 can operate independently of each other. The setup method is the same as running CMP0 and PGA can be combined to link. The setup steps for the independent operation and linkage of the comparator are shown in Table 17-3. Table 17-3 Comparator-related register setup steps steps...
Page 552 BAT32A2x9 user manual | Chapter 17 Comparator An example of the operation of comparators i(i=0, 1) is shown in Figure 17-11. In basic mode, when the analog input voltage is higher than the reference input voltage, the CiMON bit of the COMPMDR register is "1";...
Page 553 BAT32A2x9 user manual | Chapter 17 Comparator 17.4.10 The digital filter of comparator i (i=0, 1). The comparator i has a built-in digital filter that selects the sample clock by the CiFCK1 to CiFCK0 bits of the COMFIR register. The output signal of comparator i is sampled by each sample clock, and the next sample clock after the level is the same 3 times, the digital filter outputs this sample value.
Page 554 BAT32A2x9 user manual | Chapter 17 Comparator 17.4.12 The event signal output to the linkage controller (EVENTC). In the same way that interrupt requests are generated, an event signal is generated to eventc by detecting the output edge of the digital filter set by the COMFIR register. However, unlike interrupt requests, it is independent of the CiIE bit of the COMCCR register and always outputs an event signal to EVENTC.
Page 555 BAT32A2x9 user manual | Chapter 17 Comparator 17.4.13 The output of comparator i (i=0, 1). The comparison results of the comparator can be output to an external pin, and the output polarity (positive or inverting output) can be set through the CiOP and CiOE bits of the COMLOCR register and whether the output is allowed.
Page 556 BAT32A2x9 user manual | Chapter 18 Programmable Gain Amplifier (PGA) Chapter 18 Programmable Gain Amplifier (PGA) 18.1 Programmable gain amplifier function This product contains two programmable gain amplifiers (PGA0 and PGA1) with the following functions: ⚫ There are 7 options for amplification gain per PGA: 4x, 8x, 10x, 12x, 14x, 16x, 32x ⚫...
Page 557 BAT32A2x9 user manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.2 Structure of a programmable gain amplifier Figure18-1 diagram of a programmable gain amplifier 557 / 1149 Rev.1.00 www.mcu.com.cn...
Page 558 BAT32A2x9 user manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.3 Register of a programmable gain amplifier Table18-1 control registers of the programmable gain amplifier 18.3.1 Peripheral enable register 1 (PER1). The PER1 register is a register that is set to enable or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use.
Page 559 BAT32A2x9 user manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.3.2 Programmable Gain Amplifier Control Register (PGAnCTL) The PGA0CTL and PGA1CTL registers are used to control the programmable gain amplifier to start, stop, and amplify. The PGA0CTL and PGA 1 CTL registers can be set via 1-bit or 8-bit memory manipulation instructions. After generating a reset signal, this register resets to a value of 00H.
Page 560 BAT32A2x9 user manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.4 Operation of a programmable gain amplifier Amplifying the analog voltage of the PGAIN pin input, there are 7 options for amplification gain: 4x, 8x, 10x, 12x, 14x, 16x, 32x. converter and The amplified voltage can be used for the analog input of the the positive input signal...
Page 561 BAT32A2x9 user manual | Chapter 18 Programmable Gain Amplifier (PGA) 18.4.2 The stop-run step of the programmable gain amplifier Taking PGA0 as an example, the setup steps are as follows: Note 1: When restarting PGA and A/D conversion or amplifier, a PGA settling time of 1 0 us is required after setting the PGAEN bit to 1.
Page 562 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Chapter 19 Universal serial communication unit Unit 0 of the Universal Serial Communication Unit has 4 serial channels, Unit 1 has 2 serial channels, and Unit 2 has 2 serial channels, each channel can achieve 3-wire serial SSPI, UART and simple C Communication features.
Page 563 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.1 Functions of the Universal Serial Communication Unit The characteristics of each serial interface supported by this product are as follows. 19.1.1 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) Data is sent and received synchronously with the serial clock (SCLK) output of the master device.
Page 564 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.1.2 UART (UART0～UART3) This is a function of asynchronous communication over two lines: Serial Data Transmission (TxD) and Serial Data Receiving (RxD). Using these two communication lines, data is sent and received asynchronously (using the internal baud rate) by data frame (consisting of start bits, data, parity bits, and stop bits).
Page 565 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.1.3 Simple I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) This is the function of clock synchronization communication with multiple devices through two lines of serial clock (SCL) and serial data (SDA). Because this simple I C is designed for single communication with devices such as EEPROM, flash memory, A/D converters, etc., it is only used as a master device.
Page 566 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.2 The structure of a universal serial communication unit The Universal Serial Communication Unit consists of the following hardware. Table 19-1 Structure of the Universal Serial Communication Unit project structure note 1 SCI0: 8 digits or 9 bits Shift register...
Page 567 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Block diagram of universal serial communication unit 0 is shown in Figure 19-1. Figure 19-1 Block diagram of the Universal Serial Communication Unit 0 noise filter enable serial output register (SO0) regsiter 0 (NFEN0) peripherial enable serial clock selection register0...
Page 568 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Block diagram of the universal serial communication unit 1 is shown in FIG 19-2. FIG 19-2 Block diagram of the universal serial communication unit 1 serial output register 1(SO1) noise filter enable regsiter 1(NFEN1) SNFEN serial channel enable status...
Page 569 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.2.1 Shift Register (SCI0) This is a 9-bit register that converts parallel and serial to and from each other. Note 1 。 Convert the input data of For UART communication at 9 bits of data length, use 9 bits (bit0 to 8) the serial input pins into parallel data when receiving data;...
Page 570 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-3 the format of Serial data register mn (SDRmn) (mn = 00, 01, 10, 11 ), After reset: 0000H 40041211H (in the case of SDR00 40041310H (in the case of SDR00). SDRmn Shift register...
Page 571 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.2.3 Shift Register (SCI1/SCI2) This is a 16-bit register that converts parallelly and serially to and from each other. Convert the input data of the serial input pins into parallel data when receiving data; When data is sent, the value that will be passed to this register is output from the serial output pin as serial data.
Page 572 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-4 Serial data register mn (SDRmn) (mn = 20, 21, 30, 31) format After reset: 0000H SDRmn Shift register , refer to Note For the high 7-bit function of the SDRmn register "19.3 Registers for Controlling Universal Serial Communication Units".
Page 573 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3 Control registers of the universal serial communication unit The registers that control the universal serial communication unit are as follows: Register base address: SCI0=4004_1100H; SCI1=4004_1400H; SCI2=4004_1600H; Register name Register description Reset value Register address PER0...
Page 574 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register base address: SCI0=4004_1100H; SCI1=4004_1400H; SCI2=4004_1600H; Reset the Register name Register description Register address value SSR20/21 Serial status register 20/21 0000H SCI2+00H/02H The serial flag clears the trigger register SIR20/21 0000H SCI2+04H/06H 20/21...
Page 575 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.1 Peripheral enable register 0/2 (PER0/PER2). Per0/2 registers are registers that are set to allow or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use Universal Serial Communication Unit 0, the bit2 (SCI0EN) of PER0 must be placed on "1".
Page 576 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.2 Serial clock selection register m (SPSm). The SPSm register is a 16-bit register that selects two common operating clocks (CKm0, CKm1) available to each channel. Select CKm1 by bit7 to 4 of the SPSm register and select from bit3 to 0 CKm0。 It is forbidden to overwrite the SPSm register during operation (SEmn=1).
Page 577 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.3 Serial mode register mn (SMRmn). The SMRmn register is a register that sets the operating mode of channel n, selects the operating clock ), specifies whether the serial clock (f ) input can be used, sets the start of triggering, and operates the SCLK mode Settings (SSPI, UART, Simple...
Page 578 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-7 Format of serial mode register mn (SMRmn) (2/2). After reset: 0020H Symbol 15 SMRmn STSm SISmn note1 note1 Note Channel n receives data in UART mode with level inversion control SISmn0 Detect the falling edge as the starting position.
Page 579 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.4 Serial communication runs the set register mn (SCRmn). The SCRmn register is the communication operation setting register of channel n, which sets the data transmission and reception modes, data and clock phases, whether to mask the error signal, parity test bits, start bits, stop bits, and data length.
Page 580 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-8 Format of serial communication operation set register mn (SCRmn) (2/3). After reset: 0087H Symbol 15 SCRmn SLCm DLSm DLSm DlSm note1 note2 note3 note3 The setting of the parity bit in UART mode PTCmn1 PTCmn0 Send...
Page 581 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-8 Serial communication runs the format of the set register mn (SCRmn) (3/3). After reset: 0087H Symbol 15 SLCm DLSm SCRmn note1 note2 Note 3 Note Serial function correspondence The setting of the data length SSPI UART...
Page 582 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.5 Serial data register mn(SDRmn) (SCI0 i.e. m=0). The SDR mn register is the data register (16-bit) that channel n sends and receives. SDR00, bit8 to 0 of SDR01 (9 bits lower) or SDR02, SDR03 Bit7 to 0 (low 8 bits) is used as a transmit and receive buffer register, bit15 to 9 (high 7 bits) is used as a crossover setting register for the operating clock (f If the CCSmn position of the serial mode register mn (SMRmn) is "0", the bit15 to 9 of the SDRmn register is used The divider clock of the operating clock (7 bits high) is used as the transmission clock.
Page 583 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.6 Serial data register mn(SDRmn) (SCI1/SCI2 i.e. m=1/2). The SDRmn register is the data register (16-bit) that channel n sends and receives. When the operation stops (SEmn=0), bit15~9 is used as a crossover setting register for the operating clock ).
Page 584 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.7 The serial flag clears the trigger register mn (SIRmn). This is the trigger register used to clear each error flag for channel n. If you set "1" for each of you (FECTmn, PECTmn, OVCTmn), the corresponding bit of the serial status register mn (SSRmn) ( FEFmn, PEFmn, OVFmn) clear "0".
Page 585 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.8 Serial status register mn (SSRmn). The SSRmn register indicates the communication status of channel n and the condition in which an error occurred. Errors represented are frame errors, parity errors, and overflow errors. Read the SSRmn registers via a 16-bit memory manipulation instruction.
Page 586 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-11 Format of serial status register mn (SSRmn) (2/2). After reset: 0000H Symbol 15 SSRmn note1 Note 1 Detection flag for channel n frame errors FEFmn No errors occurred. An error occurred (when the UART was received).
Page 587 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.9 Serial channel start register m(SSm). The SSm register is a trigger register that sets the allowed communication/start count of each channel. If you write "1" to each of you (SSmn), set the corresponding bit (SEmn) of the serial channel allowed status register m(SEm) to "1"...
Page 588 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.10 Serial channel stop register m(STm). The STm register is a trigger register that sets the allowable communication/stop count for each channel. If you write "1" to each of you (STmn), the corresponding bit (SEmn) of the serial channel allowed status register m(SEm) is cleared to "0"...
Page 589 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.11 Serial channel enable status register m (SEm). SEm registers are used to confirm the allow or stop status of serial transmits and receives for each channel. If you write "1" to each of you who allow register m (SSm) to start serially, place it at "1". If you write "1" to each of the serial channel stop register m(STm), it corresponds to bit "0".
Page 590 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.12 Serial output enable register m (SOEm). The SOEm register setting enable or stops the output of serial communication for each channel. For channel n that enable serial output, the value of the SOmn bit of the serial output register m (SOm) described below cannot be rewritten by software, but the value reflected by the communication operation is output from the serial data output pin.
Page 591 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.13 Serial output register m(SOm). SOm registers are buffer registers for the serial output of each channel. Outputs the value of the SOmn bit of this register from the serial data output pin of channel n. Outputs the value of the CKOmn bit of this register from the serial clock output pin of channel n.
Page 592 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.14 Serial output level register m(SOLm). The SOLm register is a register that sets the data output level inversion of each channel. This register can only be set in UART mode. In SSPI mode and simple mode, the corresponding position "0"...
Page 593 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit When performing a UART transmission, an example of the level reversal of the transmitted data is shown in Figure 19-18. Figure 19-18 Example of level inversion of the transmitted data (a)Non-inverting output (SOLmn=0) SOLmn=0 output TxDq...
Page 594 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.15 Input Switch Control Register (ISC). When LIN-bus communication is implemented via UART0, the ISC1 bits and ISC0 bits of the ISC registers are used for coordination of external interrupts and timer array units. If bit0 is placed at "1", the input signal of the serial data input (RxD0) pin is selected as the input to the external interrupt (INTP0), so it can pass THE INTP0 interrupt detects the wake-up signal.
Page 595 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.16 Noise filter enable register 0 (NFEN0). The NFEN0 register sets whether the noise filter is used for the input signal of each channel's serial data input pin. For pins used for SSPI or simple I C communication, the corresponding position must be "0"...
Page 596 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.3.17 Registers that control serial input/output pin port functions When using a universal serial communication unit, control registers for port functions that are multiplexed with the object channel (port mode registers (PMxx), port registers (Pxx), and port mode control registers (PMCxx)) must be set.
Page 597 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.4 Run stop mode Each serial interface of a universal serial communication unit has a stop-run mode. Serial communication is not possible in run-stop mode, so power consumption is reduced. In addition, pins for the serial interface can be used as port functions in run-stop mode.
Page 598 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.4.2 Case of stop operation by channel Stop operation by channel through each of the register settings below. Figure 19-21 Setting of each register during channel based stop operation (a) Serial channel stop register m(STm)... This is the register that sets the allowed communication/stop count for each channel. note note STm3...
Page 599 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI20, SSPI20, SSPI20, Operation of SSPI21, SSPI30, SSPI31) communication This is a clock synchronization communication function implemented by three lines of serial clock (SCLK) and serial data (SDI and SDO).
Page 600 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5.1 Master send Master transmission refers to the operation of this product output transmission clock and sending data to other devices. 3-wire SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21 SSPI30 SSPI31 serial I/O Object Channel 0...
Page 601 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Fig19-22: 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) Example of register setting content when the master sends (a) serial mode register mn (SMRmn) channel n operational clock （f ）...
Page 602 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-23 The initial setup steps of the master transmission initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 603 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-25 Restart the setup step of the master send restart configuration starts. wait till commuication target (slave (mandatory) slave device ready? device) stops or communication ends via Configure port register and port (mandatory) port operation mode register (data output and clock...
Page 604 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single send mode). Figure 19-26 Timing diagram of the master transmit (single send mode) (type 1: DAPmn= 0, CKPmn = 0). SSmn STmn SEmn transmit data1 transmit data2 transmit data3 SDRmn SCLKp pin...
Page 605 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-27 Flowchart of the master transmission (single send mode). SSPI communication starts relevant initial configuration, refer to diagram 19~26 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag (via software, any configured internal RAM reserved region, transmit data pointer, transmit data communication data count and communication completion flag).
Page 606 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (continuous send mode). Figure 19-28 Timing diagram of the master transmit (continuous send mode) (type 1: DAPmn= 0, CKPmn = 0). SSmn STmn SEmn transmit transmit data2 transmit data3 SDRmn data1 SCLKp pin...
Page 607 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-29 Flowchart of the master transmission (continuous transmission mode). SSPI communication starts relevant initial configuration, refer to diagram 19~34 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag (via software, any configured internal RAM reserved region, transmit data pointer, transmit data communication data count).
Page 608 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5.2 Master receive Master receiver refers to the operation of this product output transmission clock and receiving data from other devices. 3-Wire Serial I/O SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21 Channel 0 for Channel 1 Channel 2...
Page 609 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Fig19-30: 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) Example of register setting content when the master receives (a) serial mode register mn(SMRmn) channel n operational clock （f ）...
Page 610 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-31 Initial setup steps for master reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 611 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-33 Restarts the setup step of the master receive restart configuration starts. wait till commuication target (slave device) stops or communication ends (mandatory) slave device ready? via Configure port register and port mode register (data output and clock output of target (mandatory) port operation...
Page 612 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single receive mode). Figure 19-34 Timing diagram of the master receive (single receive mode) (type 1: DAPmn = 0, CKPmn = 0). SSmn STmn SEmn data reception2 data reception3 data reception1 SDRmn virtual data used for receiving...
Page 613 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-35 Flowchart of the master receive (single receive mode). SSPI communication starts relevant initial configuration, refer to diagram 19~34 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag (via software, any configured configure receiving data internal RAM reserved region, transmit data pointer,...
Page 614 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (continuous receive mode). Figure 19-36 the master receive (continuous receive mode) (type 1: DAPmn= 0, CKPmn = 0). SSmn STmn SEmn data reception3 SDRmn data reception2 virtual data virtual data data reception2 virtual data...
Page 615 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Fig. 19-37 Flowchart of the master receiver (continuous receive mode). SSPI communication starts relevant initial configuration, refer to diagram 19~34(select buffer empty interrupt) SCI initial configuration For the received data, set the storage area and the number of communication data (through software, configure receiving data arbitrarily set the storage area in the internal RAM, the...
Page 616 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5.3 Sending and receiving of the master The transmission and reception of the master refers to the operation of this product output transmission clock and data transmission and reception with other devices. 3-wire serial SSPI00 SSPI01...
Page 617 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Fig19-38 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) Example of register settings for master sending and receiving (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 618 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-39 Initial setup steps for master sending and receiving initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 619 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-41 Restart the setup steps of the master send and receive restart configuration starts. wait till commuication target (slave device) (mandatory) slave device ready? stops or communication ends via Configure port register and port mode (mandatory) port operation register，data output and clock output of...
Page 620 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single send and receive mode). Figure 19-42 Timing diagram of the master transmit and receive (single transmit and receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception1 data reception2 data reception3 SDRmn...
Page 621 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-43 Flowchart of the master transmit and receive (single send and receive mode). SSPI communication starts relevant initial configuration, refer to diagram 19~42 (select transmission SCI initial configuration completion interrupt) regarding transmit and receive data, configure storage region and data count (via software, any specified internal RAM storage region, transmit data pointer configure transmit and receive data...
Page 622 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (continuous send and receive mode). Fig. 19-44: Timing diagram of the master transmit and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception 3 SDRmn transmit data1 transmit data 2...
Page 623 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-45 Flowchart of the master transmit and receive (continuous transmit and receive mode). SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19~42(select buffer empty interrupt) regarding transmit data, configure storage region and configure transmit and receive data count (via software, any specified internal RAM...
Page 624 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5.4 Slave sending Slave transmission refers to the operation of the BAT32A2x9microcontroller to send data to other devices in the state of transmitting clocks from other device inputs. 3-wire serial SSPI00 SSPI01 SSPI10...
Page 625 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Fig19-46 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) Example of register settings at the time of Slave sending (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 626 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-47 Initial setup steps for Slave sending initial configuration starts release universal serial communication configure PER0 register unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 627 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-49 Restarts the setup step of the slave send restart configuration starts. wait till commuication target (master device) master device stops or communication ends (mandatory) preparation complete? via Configure port register and port mode port operation (mandatory) register, set clock output of target channel to...
Page 628 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single send mode). Figure 19-50 Timing diagram of a Slave send (single send mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 SCLKp pin transmit data1 transmit data2...
Page 629 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-51 Flowchart of Slave send (single send mode). SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19~50 (select transmission completion interrupt) regarding transmit data, configure storage region and configure transmit and receive data count (via software, any specified internal RAM data...
Page 630 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (continuous send mode). Fig. 19-52 Timing diagram of Slave send (continuous send mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1 SCLKp pin SDOP pin transmit data1 transmit data2...
Page 631 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-53 Flowchart of Slave send (continuous send mode). SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19~50 (select buffer empty interrupt) regarding transmit data, configure storage region and data count (via software, any specified internal RAM storage region, Transmit data transmit data pointer communnication data count)
Page 632 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5.5 Slave receive Slave reception refers to the operation of this product receiving data from other devices in the state of transmitting clocks from other devices. 3-wire serial SSPI00 SSPI01 SSPI10 SSPI11 SSPI20...
Page 633 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Fig19-54 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) Example of register setting content at slave receive time (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 634 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Operation steps Fig. 19-55 Initial setup step of Slave reception initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 635 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Fig. 19-57 Restart the setup step of Slave reception restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode port operation (mandatory) register, set clock output of target channel to...
Page 636 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single receive mode). Fig. 19-58 Timing diagram of Slave receive (single receive mode) (type 1: DAPmn= 0, CKPmn = 0). SSmn STmn SEmn data reception3 SDRmn data reception1 data reception2 Read Read...
Page 637 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-59 Flowchart of Slave receive (single receive mode). SSPI communication starts relevant initial configuration, refer to diagram 19-58 SCI initial configuration (select transmission completion interrupt) configure receiving data storage region, clear receiving data count (via software, any configured internal RAM receiving preparation storage region, receiving data pointer and receiving...
Page 638 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5.6 Slave sending and receiving Slave transmit and receive refers to the operation of data transmission and reception by microcontrollers and other devices of this product in the state of transmitting clocks from other device inputs. 3-wire serial SSPI00 SSPI01...
Page 639 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Fig19-60 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) Example of register settings for Slave transmit and receive (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 640 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-61 Initial setup steps for slave sending and receiving initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 641 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-62 Abort steps for slave sending and receiving termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait). set STmm bit of target channel to 1.
Page 642 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-63 restarts the setup steps for Slave sending and receiving restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode (mandatory) port operation register, set clock output of target channel to...
Page 643 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single send and receive mode). Fig. 19-64: Timing diagram of Slave transmit and receive (single transmit and receive mode) (type 1: DAPmn= 0, CKPmn = 0). SSmn STmn SEmn data reception1 data reception3...
Page 644 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-65 Flowchart of slave send and receive (single send and receive mode). SSPI communication starts relevant initial configuration, refer to diagram 19-64 SCI initial configuration (select transmission completion interrupt) regarding transmit and receive data, configure storage configure transmit and receive region and data count (via software, any specified...
Page 645 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (continuous send and receive mode). Fig. 19-66 Timing diagram of Slave send and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception 3 SDRmn transmit data1 data reception 2...
Page 646 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Fig. 19-67: Flowchart of Slave transmit and receive (continuous transmit and receive mode). SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-64(select buffer empty interrupt) regarding transmit data, configure storage region and data count (via configure transmit and receive software, any specified internal RAM storage region, transmit data pointer data...
Page 647 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5.7 Calculate the transmit clock frequency 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI20, SSPI20, SSPI20, SSPI21, SSPI30, SSPI31) communication transmission clock frequency can be calculated using the following calculation equation. Master device (Transmit clock frequency) = {Object Channel's operating clock (f ) frequency} (SDRmn[15:9]+ 1)÷2[Hz]...
Page 648 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Table 19-2 3-wire serial I/O operating clocks SMRmn Note Running Clock (f SPSm register register =32MHz runtime CKSmn 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.63kHz 7.81kHz 3.91kHz 1.95kHz...
Page 649 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.5.8 In 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20 , SSPI21, SSPI30, Processing steps when an error occurs during communication SSPI31) In 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20 , SSPI21, SSPI30, SSPI31) The processing steps when an error occurs during communication, such as Figure 19-68shows.
Page 650 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.6 The operation of the clock synchronization serial communication of the slave selection input function Channel 0 of SCI0 is a channel that supports clock synchronization serial communication with the Slave select input function.
Page 651 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit By using the slave selection input function, a master device can be connected to multiple slave devices for communication. The master device performs the output of the slave selection signal of the slave device (1) of the communication object, and each slave device determines whether it is selected as the communication object and controls the output of the SDO pin.
Page 652 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-70 Timing diagram of the Slave selection input function DAPmn=0 configure transmit data BFFmn TSFmn SSEmn SCLKmn (CKPmn=0) SDImn sample timing sequence SDOmn SSmn During periods when SSmn is high, no transmission is made even on the falling edge of THECKmn (serial clock), and no sampling of received data synchronized with the rising edge is performed.
Page 653 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.6.1 Slave sending Slave transmission refers to the operation of this product to send data to other devices in the state of transmitting clocks from other device inputs. Slave selection input SSPI00 function Object channels...
Page 654 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Figure 19-71 Slave Selection Input Function (SSPI00) Example of register setting content when slave sending (1/2). (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n 0: Transmit completion 0: SPSm register configured pre-scaler output clock CKm0 interrupt...
Page 655 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-72 Slave Selection Input Function (SSPI00) Example of Register Setting Content when Slave Sends (2/2). (f) serial channel start register m (SSm) Only set bit of target channel to 1. (g) input switch control register (ISC) This is controlled by SS00 pin of SSPI00 slave channel (channel 0 of unit 0).
Page 656 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-72 Initial setup steps for slave sending initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 657 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-73 Abort step of the slave send termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait). set STmm bit of target channel to 1.
Page 658 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-74 Restarts the setup step of the Slave send restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode (mandatory) port operation register, set clock output of target channel to...
Page 659 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single send mode). Fig. 19-75 Timing diagram of a Slave send (single send mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn SDRmn transmit data1 transmit data 2 transmit data 3 SCLKp pin transmit data1 transmit data 2...
Page 660 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-76 Flowchart of Slave send (single send mode). SSPI communication starts relevant intial configure, please refer to diagram 19-79 (select transmission SCI initial configuration completion interrupt) regarding transmit data, configure storage region and data configure transmit data count (via software, any specified internal RAM storage region, transmit data pointer communnication data count)
Page 661 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (continuous send mode). Figure 19-77 Timing diagram of Slave send (continuous send mode) (type 1: DAPmn= 0, CKPmn = 0). SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1 SCLKp pin SDOp pin...
Page 662 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-78 Flowchart of Slave send (continuous send mode). SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19-79 (select buffer empty interrupt) regarding transmit data, configure storage region and data count (via software, any specified internal configure transmit data RAM storage region, transmit data pointer...
Page 663 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.6.2 Slave receive Slave reception refers to the operation of this product receiving data from other devices in the state of transmitting clocks from other devices. Slave selection input SSPI00 function Object channels Channel 0 for SCI0...
Page 664 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Figure 19-79 Slave Selection Input Function (SSPI00) Example of register setting content when slave receives (1/2). (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n 0: SPSm register configured pre-scaler output clock CKm0 0: Transmit completion interrupt1: Buffer 1: SPSm register configured pre-scaler output clock CKm1...
Page 665 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-80 Slave Selection Input Function (SSPI00) Example of Register Setting Content when Slave Receives (2/2). (f) serial channel start register m (SSm) Only set bit of target channel to 1. (g) input switch control register (ISC) This is controlled by SS00 pin of SSPI00 slave channel (channel 0 of unit 0).
Page 666 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-81 Initial setup step of Slave reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 667 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-83 Restarts the setup step of Slave reception restart configuration starts. wait till commuication target (master device) master device stops or communication ends preparation complete? (mandatory) via Configure port register and port mode port operation register, set clock output of target channel to (mandatory)
Page 668 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single receive mode). Fig. 19-84 Timing diagram of Slave receive (single receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception 3 SDRmn transmit data1 transmit data 2 Read Read Read...
Page 669 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-85 Flowchart of Slave reception (single receive mode). SSPI communication starts relevant initial configuration, refer to diagram 19-58 SCI initial configuration (select transmission completion interrupt) configure receiving data storage region, clear receiving data count (via software, any configured internal RAM receiving preparation storage region, receiving data pointer and receiving...
Page 670 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.6.3 Slave sending and receiving Slave transmit and receive refers to the operation of data transmission and reception of this product and other devices in the state of input transmission clock from other devices. Slave selection input function SSPI00 Object channels...
Page 671 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Figure 19-86 Slave Selection Input Function (SSPI00) Example of register setting content when slave send and receive (1/2). (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n 0: SPSm register configured pre-scaler output clock CKm0 0: Transmit completion interrupt...
Page 672 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-87 Slave Selection Input Function (SSPI00) Example of register settings during slave sending and receiving (2/2). (f) serial channel start register m (SSm) Only set bit of target channel to 1. (g) input switch control register (ISC) This is controlled by SS00 pin of SSPI00 slave channel (channel 0 of unit 0).
Page 673 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-87 Initial setup steps for slave sending and receiving initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 674 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-88 Abort steps for slave sending and receiving termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait). set STmm bit of target channel to 1.
Page 675 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-89 Restarts the setup steps for Slave sending and receiving restart configuration starts. wait till commuication target (master device) master device preparation (mandatory) stops or communication ends complete? via Configure port register and port mode (mandatory) port operation register, set clock output of target channel to...
Page 676 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single send and receive mode). Fig. 19-90 Timing diagram of Slave transmit and receive (single send and receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception1 data reception2 data reception3 transmit data 2...
Page 677 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Fig. 19-91 Flowchart of Slave transmit and receive (single send and receive mode). SSPI communication starts relevant initial configuration, refer to diagram 19-93 SCI initial configuration (select transmission completion interrupt) regarding transmit and receive data, configure storage configure transmit and receive region and data count (via software, any specified...
Page 678 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (continuous send and receive mode). Fig. 19-92 Timing diagram of Slave send and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception 3 SDRmn transmit data1 data reception 2...
Page 679 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Fig. 19-93 Flowchart of Slave send and receive (continuous transmit and receive mode). SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-93(select buffer empty interrupt) regarding transmit data, configure storage region and configure transmit and receive data count (via software, any specified internal RAM data...
Page 680 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.6.4 Calculate the transmit clock frequency The transmit clock frequency of the slave select input function (SSPI00) communication can be calculated using the following calculation equation. Slaves Note Serial Clock ( Device (Transmit Clock Frequency) = { SCLK) Frequency Rate Provided by the Master...
Page 681 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.6.5 The processing step when an error occurs during clock synchronization serial communication with the slave selection input function The processing steps for errors that occur during clock synchronization serial communication with the slave select input function are shown in Figure 19-94.
Page 682 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.7 Operation of UART (UART0~UART3) communication This is a function of asynchronous communication over two lines: Serial Data Transmission (TxD) and Serial Data Receiving (RxD). Using these two communication lines, data is sent and received asynchronously (using the internal baud rate) data frame (consisting of start bits, data, parity bits, and stop bits) with other communicators.
Page 683 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.7.1 UART sends UART sending is the operation of this product microcontroller to asynchronously send data to other devices. An even number of the 2 channels used by UART is used for UART transmission. UART UART0 UART1...
Page 684 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Fig. 19-95 register setting content when UART is transmitted by UART (UART0~UART3) (1/2). (a) serial mode register mn (SMRmn) channel n operational clock (fMCK) channel n interrupt source 0: SPSm register configured pre-scaler output clock CKm0 0: Transmit completion interrupt 1: SPSm register configured pre-scaler output clock CKm1...
Page 685 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Fig19-96 register setting content when UART is transmitted by UART (UART0 to UART 3) (2/2). (e) serial output register m (SOm) Only configure bit of target channel Note Note 0: serial data output value as "0" 1: serial data output value as "1"...
Page 686 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-96 UART transmission initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc. configure SMRmn register configure communication format configure SCRmn register...
Page 687 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-98 Reset the setup steps for the new start UART transmission restart configuration starts. wait till commuication target (slave device) stops or (mandatory) Ready to communicate? communication ends The data output of the target channel is disabled by (mandatory) port operation setting the port register and port mode register.
Page 688 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (single send mode). Figure 19-99 UART send (single send mode). SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2 transmit data3 shift register mn shift operation shift operation...
Page 689 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-100 UART transmit (single-pass mode). UART communication starts relevant initial configuration, refer to diagram 19-102 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag (via software, any configured internal RAM reserved region, transmit data pointer, transmit data communication data count and communication completion flag).
Page 690 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow (continuous send mode). Figure 19-101 UART transmission (continuous send mode). SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2 transmit data3 shift register mn shift operation shift operation...
Page 691 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-102 Flowchart of UART sending (continuous send mode). UART communication starts relevant initial configuration, refer to diagram 19-102 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag (via software, any configured internal RAM reserved region, transmit data pointer, communication data count and Configure transmit data...
Page 692 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.7.2 UART receives UART receive is the operation of this product microcontroller asynchronously receiving data from other devices. The odd number of the 2 channels used by the UART is used for UART reception. However, the SMR registers for odd and even channels need to be set.
Page 693 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings 19-103 Example of register setting content when UART receives 103 UART (UART0~UART 3) (1/2). (a) serial mode register mn (SMRmn) 0: normal receiving channel n operational clock (fMCK) channel N operational mode: 1: inverted phase receiving 0: SPSm register configured pre-scaler output clock CKm0...
Page 694 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Fig. 19-104: Example of UART (UART0~UART 2) of UART (UART0~UART 2) (2/2). (e) serial output register m (SOm) Not used in this mode. (f) serial output enable register m (SOEm) Not used in this mode.
Page 695 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-104 UART reception initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure SMRmn register configure operational mode..etc.
Page 696 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-106 Reset the setup steps for restarting UART reception restart configuration starts. wait till commuication target stops or commuication target (mandatory) communication ends ready？ re-configure when modifing operational clock modify SPSm register (selection) configuration...
Page 697 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow Figure 19-107 UART reception SSmn STmn SEmn transmit data 3 SDRmn transmit data1 transmit data 2 RxDq pin data reception 1 data reception 2 data reception 3 shift register mn shift operation shift operation shift operation...
Page 698 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-108 Flowchart of UART reception UART communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-110 (select transmission completion interrupt) configure reciving data storage region and communication data count (via software, any configured internal RAM storage configure receiving data region, receiving data pointer and communication data count).
Page 699 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.7.3 Calculation of baud rate Equation for calculating baud rate The baud rate of UART (UART0~UART3) communication can be calculated using the following calculation equation: of the object channel (baud rate) = {Operating clock (f ) frequency } (SDRmn[15:9]+ 1)÷2[bps] the serial data register...
Page 700 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Table 19-4 UART operating clocks SMRmn Note SPSm register Running Clock (f register CKSmn =32MHz runtime 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.63kHz 7.81kHz 3.91kHz 1.95kHz 977Hz 32MHz...
Page 701 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Baud rate error when sending The baud rate error during UART (UART0~UART3) communication transmission can be calculated using the following calculation equation, and the baud rate of the sender must be set within the allowable baud rate of the receiver.
Page 702 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit The allowable range of baud rate at the time of reception The baud rate tolerance range for UART (UART0~UART2) communication reception can be calculated using the following equation, and the baud rate of the sender must be set within the baud rate tolerance range of the receiver. 2×K×Nfr ×Brate (Maximum baud rate that can be received)
Page 703 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.7.4 The processing step when an error occurs during UART (UART0~UART3) communication The processing steps for errors that occur during UART (UART0~UART 3) communication are shown in Figure 19-110andFigure 19-111. Figure 19-110: The processing steps when a parity error or overflow error occurs Software operation Hardware status...
Page 704 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.8 Operation of LIN communications 19.8.1 LIN sends In UART transmission, UART0 supports LIN communication. LIN sends channel 0 using unit 0. UART UART0 UART1 UART2 UART3 Support for LIN communication Channel 0 for —...
Page 705 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit LIN, short for Local Interconnect Network, is a low-speed (1 to 20kbps) serial communication protocol for reducing the cost of automotive networks. LIN communication is a single master communication, and a master device can connect up to 15 slave devices.
Page 706 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-113 Flowchart sent by LIN hardware operation(reference) LIN transmit start Transmit wakeup signal frame (80H->TxD0) generate wakeup signal frame 8 bit Transmit wakeup TxD0 TSF00=0? Note signal frame transmit data wait for transmit result stop UART0(1->ST00 bit) modify UART0 Baud rate...
Page 707 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.8.2 LIN receives In UART reception, UART0 supports LIN communication. LIN receives channel 1 using unit 0. UART UART0 UART1 UART2 UART3 Support for LIN communication — — — Object channels Channel 1 of SCI0 —...
Page 708 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit A summary of the receive operation of LIN is shown in Figure 19-114. Figure 19-114 The receive operation of LIN wake up signal frame interval field sync field identifier data field data field checksum information...
Page 709 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-115 Flowchart of LIN reception LIN Bus signal state and hardware operation. LIN communication starts wake up signal frame wait for wake up signal INTTM03 occurs? NOTE. RxD0 pin frame.
Page 710 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit The port structure diagram for THE LIN receive operation is shown in Figure 19-116. The wake-up signal sent by the LIN master is received through edge detection of the external interrupt (INTP0).
Page 711 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit The peripheral functions for LIN communication operation are summarized as follows: The peripheral functions that < use > • External Interrupt (INTP0): Detection of wake-up signals Uses: Detects the edge of the wake signal and the start of communication. Channel 3 of the universal timer unit: detection of baud rate error, detection of interval segment (BF).
Page 712 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.9 Simple I C (IIC00, IIC01, IIC10, IIC11, IIC20, Operation of IIC21, IIC30, IIC31) communication This is the function of clock synchronization communication with multiple devices through two lines of serial clock (SCL) and serial data (SDA).
Page 713 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.9.1 The address segment is sent The address segment transmission is the first transmission operation when communicating in I for the purpose of specifically specifying the transmitting object (the slave). After the start condition is generated, the address (7 bits) and the transmission direction (1 bit) are sent as 1 frame.
Page 714 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Figure 19-117 Simple I C (IIC00, IIC01, IIC10, IIC10 IIC11, IIC20, IIC21, IIC30, IIC31 ) when the address segment is sent Example of register setting content (a) serial mode register mn (SMRmn) Note1 Note1 channel n operational clock （fMCK）...
Page 715 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Procedure Figure 19-118 The initial setup steps for the transmission of the address segment initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 716 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow Figure 19-119 Timing diagram of the address segment sent address field transmit SDLr output bit operation SDAr output Somn bit operation address SDAr input shift operation shift register mn Remark m: unit number(m=0~2) n:channel number(n=0~3)r:IIC number(r=00, 01, 10, 11, 20, 21, 30, 31) mn=00～03, 10～11, 20～21 716 / 1149...
Page 717 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Figure 19-120: Flowchart of the address segment sent address field transmit relevant initial configuration, refer to initial configuration diagram 19-129 set SOmn bit to '0'. set SOmn bit to '0'. generate start condition wait ensure SCL signal hold time...
Page 718 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.9.2 Data sending Data sending is the operation of sending data to the transmitting object (slave) after sending an address segment. A stop condition is generated and the bus is released after all data is sent to the object slave. Simple I IIC00 IIC01...
Page 719 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Figure 19-121 Simple I C (IIC00, IIC01, IIC10, IIC11 , IIC20, IIC21, IIC30, IIC31 ) when the data is sent Example of register setting content (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 720 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow Figure 19-122 Timing diagram of data transmission transmit data 1 SDLr output SDAr output SDAr input shift register mn shift operation Figure 19-123 Flowchart of data transmission address field transmit completes.
Page 721 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.9.3 Data reception Data ingestion is the operation of receiving data from a transmitting object (slave) after sending an address segment.Generates a stop condition and releases the bus after the slave slave receives all the data. Simple IIC00 IIC01...
Page 722 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Register settings Figure 19-124 Simple I C (IIC00, IIC01, IIC10, IIC11 , IIC20, IIC21, IIC30, IIC31 ) when the data is received Example of register setting content (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 723 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Process flow Figure 19-125 Timing diagram of data reception (a) The case when you start receiving data virtual data(FFH) receiving data SCLr output SDAr output SDAr input shift register mn shift operation (b) The case of receiving the last data stop serial commnication output...
Page 724 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Fig. 19-126 Flowchart of data reception address field transmit completes. data reception stop operation in order to modify set STmn bit to 1. SCRmn register cofigure channel operation mode to write "0"...
Page 725 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.9.4 Stop conditions generation After all data has been sent and received with the object slave, a stop condition is generated and the bus is released. Process flow Figure 19-127: A timing diagram of the generation stop condition STmn SEmn note...
Page 726 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit 19.9.5 Calculation of the transfer rate Simple I C (IIC00, IIC01, IIC10, IIC11, IIC20, The transmission rate of IIC21, IIC30, IIC31) communication can be calculated using the following calculation equation. (Transfer Rate)={Runtime Clock ( ) Frequency} (SDRmn÷[15:9]+1)÷2 fMCK...
Page 727 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Table 19-5 Selection of simple I operating clocks SMRmn Running Clock (f MCK ) Note SPSm register register f CLK =32MHz runtime CKSmn f CLK 32MHz f CLK /2 16MHz f CLK /2 2 8MHz f CLK /2 3...
Page 728 BAT32A2x9 user manual | Chapter 19 Universal serial communication unit Processing steps 19.9.6 In simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) when an error occurs during communication In simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, The processing steps for errors that occur during IIC21, IIC 3 0, IIC31) are Figure 19-129and Figure 19-130shown.
Page 729 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Chapter 20 Serial interface IICA 20.1 The serial interface IICA functions This product is equipped with two serial interfaces IICA0, IICA1, and has the following three modes. 20.1.1 Run stop mode This is a mode used when serial transfer is not in progress and reduces power consumption.
Page 730 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-1 diagram of the serial interface IICA 730 / 1149 Rev.1.00 www.mcu.com.cn...
Page 731 BAT32A2x9 user manual | Chapter 20 Serial interface IICA An example of the structure of a serial bus is shown in Figure 20-2. Figure 20-2 example of a serial bus structure for I2C-bus serial data bus master control CPU2 master control CPU1 SDAAn SDAAn slave CPU2...
Page 732 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.2 Structure of the serial interface IICA The serial interface IICA consists of the following hardware. Table 20-1 Structure of the serial interface IICA item structure IICA shift register n (IICAn) slave address register n register (SVAn).
Page 733 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.2.1 IICA shift register n (IICAn). IICAn registers are registers that convert 8-bit serial data and 8-bit parallel data to and from a serial clock for sending and receiving. Actual sending and receiving can be controlled by reading and writing IICAn registers. During the wait, the wait is lifted by writing the IICAn register and the data is transferred.
Page 734 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.2.2 Slave address register n(SVAn). This is the register that holds the 7-bit local station address {A6, A5, A4, A3, A2, A1, A0} when used as a slave. The SVAn register is set by the 8-bit memory operation instruction. However, when the STDn bit is "1" (start condition detected), it is forbidden to overwrite this register.
Page 735 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Remarks: 1. STTn bit: bit1 of IICA control register n0 (IICCTLn0 SPTn bit: bit0 of IICA control register n0 (IICCTLn0 IICRSVn bit: bit0 of IICA flag register n (IICFn IICBSYn bit: bit6 of IICA flag register n (IICFn STCFn bit: bit7 of IICA flag register n (IICFn STCENn bit: bit1 of IICA flag register n (IICFn...
Page 736 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.3 Controls registers of the serial interface IICA The serial interface IICA is controlled by the following registers. • Peripheral enable register 0 (PER0). • IICA control register n0 (IICCTLn0). • IICA flag register n (IICFn).
Page 737 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.3.1 Peripheral enable register 0/1 (PER0/1). Per0/1 registers are registers that are set to enable or disable clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use the serial interface IICA0, you must replace PER0 Bit5 (IICA0EN) is set to "1".
Page 738 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-5 Format of IICA control register n0 (IICCTLn0) (1/4). After reset: 00HR/W symbol IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn IICCTLn0 IICEn runs allowed note 1 Stop running. Reset to IICA status register n (IICSn) and stop internal operation.
Page 739 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (2/4). Note 1 SPIEn Allow or disallow interrupt requests resulting from stop condition detection forbid allow When the WUPn bit of IICA control register n1 (IICCTLn1) is "1", even if the SPIEN position is "1" There is also no stop condition interrupt.
Page 740 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (3/4). note1, 2 The triggering of the start condition STTn No start conditions are generated. When the bus is released (standby, IICBSYn bit is "0"): If this position is "1", a start condition (boot as the master device) is generated.
Page 741 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (4/4). The trigger of the stop condition Note SPTn No stop conditions are generated. Generate a stop condition (end of transfer as master). Notes on position timing: •...
Page 742 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.3.3 IICA status register n (IICSn). This is the register that represents the state. The IICSn register can only be read by the 8-bit memory operation instruction during the STTn bit "1" and waiting.
Page 743 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-7 Format of IICA status register n (IICSn) (2/3). Receive detection of extension codes EXCn The extension code was not received. Extended code received. Clear condition (EXCn=0,1). Position condition (EXCn=1). •When a start condition is detected •...
Page 744 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Note: 1. LRELn: Bit6 of IICA control register n0 (IICCTLn0 IICEn: Bit7 of IICA control register n0 (IICCTLn0 2.n=0,1 Figure 20-7 Format of IICA status register n (IICSn) (3/3). Detection of the Ack (ACK). ACKDn No Ack was detected.
Page 745 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.3.4 IICA flag register n (IICFn). This is the register that sets the operating mode and indicates the status of the I2 C-bus. The IICFn register is set by the 8-bit memory operation instruction. However, only the STTn clear flag (STCFn) and the I2 C-bus status flag (IICBSYn) can be read.
Page 746 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-7 Format of the IICA flag register n (IICFn). Note After reset: 00HR/W symbol IICFn STCFn IICBSYn STCENn IICRSVn STTn clear flag STCFn Release Start Conditions. The STTn flag cannot be cleared while the start condition cannot be issued. Clear condition (STCFn=0,1).
Page 747 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.3.5 IICA control register n1 (IICCTLn1). This is a register used to set the operating mode and to detect the status of the SCLAn pin and SDAAn pins. The IICCTLn1 register is set by the 8-bit memory operation instruction. However, only CLDn bits and DADn bits can be read.
Page 748 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-9 Format of IICA control register n1 (IICCTLn1) (2/2). Level detection of the SCLAn pin (valid only when the IICEn bit is "1"). CLDn The SCLAn pin was detected low. The SCLAn pin was detected high.
Page 749 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.3.6 IICA low-level width setting register n (IICWLn). This register controls the SCLAn pin signal low level width (t ) and SDAAn pin signal from the serial interface IICA output. The IICWLn register is set by the 8-bit memory operation instruction. Must be disabled in bit7 (IICEn) where is disabled to run (IICA control register n0 (IICCTLn0).)=0) when setting the IICWLn register.
Page 750 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.3.8 Port mode register x (PMx). This register sets the input/output of the port. When using the Pxx/SCLAn pin as the clock input/output and the Pxx/SDAAn pin as the serial data input/output, The port mode register PMx and the port output latch Px must be placed at "0".
Page 751 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.4 The functionality of C-bus mode 20.4.1 Pin structure The serial clock pin (SCLAn) and serial data bus pin (SDAAn) are structured as follows. SCLAn..Input/output pins of the serial clock The outputs of both the master and slave devices are N-channel open-drain outputs, and the inputs are Schmidt inputs.
Page 752 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.4.2 The method of transmitting the clock is set by the IICWLn register and the IICWHn register The method by which the master transmits the clock Transmission clock= IICWL+IICWH+f At this point, the optimal setpoints for the IICWLn register and the IICWHn register are as follows: (All setpoints are rounded to decimals) •...
Page 753 BAT32A2x9 user manual | Chapter 20 Serial interface IICA signal : The rise time of the SDAAn signal and SCLAn : IICA operating clock frequency 3. n=0.1 20.5 Definition and control method of the C-bus The following describes the serial data communication format and the signals used for the I2 C-bus. The Start Condition, Address, Data generated on the serial data bus of the C-bus The respective transmission timings for and "Stop Condition"...
Page 754 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.1 Start conditions When the SCLAn pin is high, a start condition is generated if the SDAAn pin changes from high to low. The starting conditions for the SCLAn pin and the SDAAn pin are the signals generated when the master device starts serially transmitting to the slave.
Page 755 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.2 address The next 7 bits of data for the start condition are defined as addresses. The address is 7 bits of data output by the master device in order to select a particular slave device from a plurality of slave devices connected to the bus.
Page 756 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.4 Ack (ACK). The serial data status of the sender and receiver can be acknowledged by answer (ACK). The receiver returns a reply each time it receives 8 bits of data. Typically, the sender receives a reply after sending 8 bits of data.
Page 757 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.5 Stop Conditions When the SCLAn pin is high, a stop condition is generated if the SDAAn pin changes from low to high. The stop condition is the signal generated when the master ends serial transmission to the slave. When used as a slave, a stop condition is detected.
Page 758 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.6 await Notify the other master or slave that the other master or slave is preparing to send/receive data by waiting (waiting status). Notify the other party that it is in a waiting state by setting the SCLAn pin low. If both the master and slave wait states are lifted, the next transfer can begin.
Page 759 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-19 Wait (2/2). (2) A situation where both the master and slave devices are waiting for 9 clocks (Master: Transmit, Slave: Receive, ACKEn=1). master device and master slave device all enter device into wait state after output 9th clock.
Page 760 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.7 method of release from wait state In general, can be relieved of waiting by the following processing. • Write data to IICA shift register n (IICAn). • Set the bit5 (WRELn) of the IICA control register n0 (IICCTLn0) (de-wait). •...
Page 761 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.8 Generation timing and waiting control of interrupt requests (INTIICAn). By setting the IICA control register n0 (IICCTLn0) bit3 (WTIMn), in Table 20-2 The timing shown generates INTIICAn and is subject to wait control. Table 20-2: Generation timing and waiting control of INTIICAns Slave run The master runs...
Page 762 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Wait for the method of release There are 4 ways to release from waiting: • Write data to IICA shift register n (IICAn). • Set the bit5 (WRELn) of the IICA control register n0 (IICCTLn0) (de-wait). •...
Page 763 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.11 Extension code (1) When the high 4 bits of the receiving address are "0000" or "1111", as the received extension code, the extended code receive flag (EXCn) is set to "1", and in the 8th The falling edge of the clock generates an interrupt request (INTIICAn).
Page 764 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.12 arbitration When multiple master devices generate start conditions at the same time (in the case of STTn position "1" before the STDn bit becomes "1"), the communication of the master device is carried out while adjusting the clock until the data is different.
Page 765 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Table 20-4 Status at the time of arbitration and timing of generation of interrupt requests The state in which the arbitration occurred Timing of the generation of interrupt requests Address during sending Read and write information after sending the address The extension code is being sent during process The descending edge of the 8th or 9th clock after the byte...
Page 766 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.13 Wake-up function This is a subordinate function of I C, which is the function of generating an interrupt request signal (INTIICAn) when the local station address and extension code are received. The processing efficiency is improved by not generating unwanted INTIICAn signals under different addresses.
Page 767 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-21 flow (including receiving the extension code) when the WUPn position "0" is matched by address matching deep sleep mode state INTIICAn=1？ WUPn=0 wait wait for 5 fMCK clock. Read IICSn after confirming serial interface IICA operation status, process accordingly.
Page 768 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-22: deep sleep mode is lifted by interrupts other than INTIICAn as the master device START SPIEn=1 WUPn=1 wait deep sleep instruction deep sleep mode state release deep sleep mode using other interrupt release deep sleep mode than INTIICAn.
Page 769 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.14 Communication appointments (1) Cases where the communication appointment function is allowed (bit0 (IICRSVn) = 0 of the IICA flag register n (IICFn)) To perform the next master communication without joining the bus, you can send a start condition when the bus is released through a communication appointment.
Page 770 BAT32A2x9 user manual | Chapter 20 Serial interface IICA The timing of the communication appointment is shown in the following figure. Figure 20-23 Timing of communication appointments program 写IICAn STTn=1 processing. hardware SPDn and communi STDnset INTIICAn cation processing. to '1' preserve set to '1' SCLAn...
Page 771 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-25: Communication appointment steps stop interrupt request set STTn flag to '1' STTn=1 (communication preserve) define communication define as in communication preserve state. preservation ( to configure and set user flag of any RAM) Note 1 Wait ensure wait time via software.
Page 772 BAT32A2x9 user manual | Chapter 20 Serial interface IICA STCFn (bit7 of the IICFn register) can be used to confirm whether a start condition was generated or the request was rejected. Because it takes 5 fMCKs from the STTn bit "1" to the STCFn position "1" The time of the clock, so this time must be ensured by the software.
Page 773 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.16 Communication operation Here, the following three running steps are represented by a flowchart. (1) The master operation of a single-master system The flowchart used as a master device in a single master system is shown below. This process is broadly divided into "initial setup"...
Page 774 BAT32A2x9 user manual | Chapter 20 Serial interface IICA The master operation of a single-master system Figure 20-26 The master operation of the single master control system START release serial interface IICA from reset state, configure PER0 register start providing clock. I2C bus initialization.
Page 775 BAT32A2x9 user manual | Chapter 20 Serial interface IICA conform to the specifications of the products in the communication. 2.n=0,1 Master operation of multi-master system Figure 20-27 operation of a multi-master system (1/3). START release serial interface IICA from reset state, configure PER0 register start providing clock.
Page 776 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-28 Master operation of a multi-master system (2/3). allow communication preservation prepare starting STTn=1 communication. (generate stop condition) ensure wait time via Wait Note. software. MSTSn=0？ does INTIICAn interrupt occur? wait to release bus.
Page 777 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-28: Master operation of a multi-master system (3/3). Start communication. Write IICAn (Specify address and transfer direction) does INTIICAn interrupt wait for detecing occur? acknowledgement MSTSn=1？ ACKDn=1？ TRCn=1？ ACKEn=1 WTIMn=0 WTIMn=1 start WRELn=1...
Page 778 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Slave run The processing steps for a slave run are as follows. Slave operations are basically event-driven, so they need to be handled through INTIICAn interrupts (large changes to the operating state such as stop condition detection in communications) need to be handled). In this description, it is assumed that the data communication does not support extension codes, THATICAn interrupt processing only performs state transition processing, and that the actual data communication is carried out by the main processing department.
Page 779 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Figure 20-28: Slave run step (1). START release serial interface IICA from reset state, configure PER0 register start providing clock. configure pins and multiplexed ports to be used. Configure Port First port configured to be input mode and output latch set to "0“...
Page 780 BAT32A2x9 user manual | Chapter 20 Serial interface IICA An example of the steps for a slave to process via an INTIICAn interrupt is shown below (assuming no extension code is used here). Confirm the status by interrupting THROUGH INTIICAn and perform the following processing.
Page 781 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.5.17 Timing of the generation of I2C interrupt requests (INTIICAn). The values of the data send and receive timing, the timing of the generation of the INTIICAn interrupt request signal, and the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below. Remarks: 1.
Page 782 BAT32A2x9 user manual | Chapter 20 Serial interface IICA The master runs Start~Address~Data~Data~Stop In the case of WTIMn=0,1 SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B Note 3:IICSn=1000X000B(set WTIMn bit to 4:IICSn=1000XX00B(set SPTn bit to 1 ) 5:IICSn=00000001B Note: to generate stop condition, must set WTIMn bit to '1' and modify INTIICAn interrupt requet signal generation timing sequenc e. Remark must generate only generate while SPIEn bit is '1'...
Page 783 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Start～Address～Data～Start～Address～Data～Stop (Start Over) In the case of WTIMn=0,1 STTn=1 SPTn=1 ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=1000X110B Note1 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000XX00B(set WTIMn bit to Note 2 and set STTn bit to 4:IICSn=1000X110B Note3 5:IICSn=1000X000B(set WTIMn bit to...
Page 784 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Start ~Code~Data Data~Stop In the case of WTIMn=0,1 SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1010X110B 2:IICSn=1010X000B Note 3:IICSn=1010X000B(set WTIMn bit to 4:IICSn=1010XX00B(set SPTn bit to 1 ) 5:IICSn=00000001B Note： to generate stop condition, must set WITIMn bit to '1' and modify INTIICAn interrupt request signal generation timing sequence.
Page 785 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Slave operation (the case of receiving a slave address). Start～Address～Data～Data～Stop In the case of WTIMn=0,1 ST AD6~AD0 D7~D0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X000B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) In the case of WTIMn=1 ST AD6~AD0 D7~D0...
Page 786 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Start～Address～Data～Start～Address～Data～Stop (i) The case where WTIMn = 0,1 (same for SVAn after restart). ST AD6~AD0 R/W ACK D7~D0 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) The case of WTIMn=1 (same SVAn after restart).
Page 787 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Start～Address～Data～Start～Code～Data～Stop (i) The case of WTIMn= 0,1 (the address is different after restart (extension code)). ST AD6~AD0 R/W ACK D7~D0 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) The case of WTIMn=1 (address is different after restart (extension code)).
Page 788 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Start～Address～Data～Start～Address～Data～Stop (i) The case of WTIMn=0,1 (the addresses are different after restart (non-extension code)). ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=00000110B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) The case of WTIMn=1 (different addresses after restart (non-extension code)).
Page 789 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Slave run (in the case of receiving an extension code). Always participate in the communication when receiving an extension code. Start～Code～Data～Data～Stop In the case of WTIMn=0,1 ST AD6~AD0 D7~D0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X000B 4:IICSn=00000001B...
Page 790 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Start～Code～Data～Start～Address～Data～Stop (i) The case where WTIMn = 0,1 (same for SVAn after restart). ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) The case of WTIMn=1 (same SVAn after restart).
Page 791 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Start～Code～Data～Start～Code～Data～Stop (i) The case of WTIMn=0,1 (receiving the extension code after restarting). ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) The case of WTIMn=1 (receiving the extension code after restarting).
Page 792 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Start～Code～Data～Start～Address～Data～Stop (i) The case of WTIMn=0,1 (the addresses are different after restart (non-extension code)). ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=00000X10B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) The case of WTIMn=1 (different addresses after restart (non-extension code)).
Page 793 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Do not participate in the operation of the communication Start～Code～Data～Data～Stop The operation of the arbitration failure (running as a slave after the arbitration fails). When used as a master device in a multi-master system, the MSTSn bit must be read each time an INTIICAn interrupt request signal is generated to confirm the arbitration result.
Page 794 BAT32A2x9 user manual | Chapter 20 Serial interface IICA In the case of WTIMn=1 (ii) ST AD6~AD0 D7~D0 D7~D0 1:IICSn=0101X110B 2:IICSn=0001X100B 3:IICSn=0001XX00B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' A condition in which arbitration fails during the sending of an extension code In the case of WTIMn=0,1 ST AD6~AD0 D7~D0...
Page 795 BAT32A2x9 user manual | Chapter 20 Serial interface IICA In the case of WTIMn=1 (ii) ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=0110X010B 2:IICSn=0010X110B 3:IICSn=0010X100B 4:IICSn=0010XX00B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' The operation of the arbitration failure (not participating in the communication after the arbitration failed). When used as a master device in a multi-master system, the MSTSn bit must be read each time an INTIICAn interrupt request signal is generated to confirm the arbitration result.
Page 796 BAT32A2x9 user manual | Chapter 20 Serial interface IICA A condition in which arbitration fails during the sending of an extension code ST AD6~AD0 D7~D0 D7~D0 1:IICSn=01000110B set LRELn bit to '1' via software 2:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' A condition in which the arbitration fails while transferring data In the case of WTIMn=0,1 ST AD6~AD0...
Page 797 BAT32A2x9 user manual | Chapter 20 Serial interface IICA In the case of WTIMn=1 (ii) ST AD6~AD0 D7~D0 D7~D0 1:IICSn=10001110B 2:IICSn=01000100B 3:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' A situation where arbitration fails due to restart conditions when transferring data Non-extended codes (for example, SVAns are different).
Page 798 BAT32A2x9 user manual | Chapter 20 Serial interface IICA (ii) Extension code ST AD6~AD0 D7~Dm ST AD6~AD0 D7~D0 1:IICSn=1000X110B 2:IICSn=01000010B set LRELn bit to '1' via software 3:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' m=0~6 A situation in which arbitration fails due to a stop condition when transferring data ST AD6~AD0 D7~Dm 1:IICSn=10000110B...
Page 799 BAT32A2x9 user manual | Chapter 20 Serial interface IICA A situation where the arbitration fails because the data is low when you want to generate a restart condition In the case of WTIMn=0,1 STTn=1 ST AD6~AD0 D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000X100B(set WTIMn bit to 0 ) 4:IICSn=01000000B...
Page 800 BAT32A2x9 user manual | Chapter 20 Serial interface IICA A case where the arbitration fails because of the stop condition when the restart condition is wanted to be generated In the case of WTIMn=0,1 STTn=1 ST AD6~AD0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000XX00B(set STTn bit to 1 ) 4:IICSn=01000001B Remark...
Page 801 BAT32A2x9 user manual | Chapter 20 Serial interface IICA A situation where the arbitration fails because the data is low when you want to generate a stop condition In the case of WTIMn=0,1 SPTn=1 ST AD6~AD0 D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000X100B(set WTIMn bit to 0 ) 4:IICSn=01000100B...
Page 802 BAT32A2x9 user manual | Chapter 20 Serial interface IICA 20.6 Timing diagram In I2C-bus mode, the master device selects a slave device for a communication object from multiple slave devices by outputting an address to the serial bus. The master device sends a TRCn bit (bit3 of the IICA status register n (IICSn)) that indicates the direction of data transmission after the slave address Begin serial communication with the slave.
Page 803 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-30 example of a slave device → the master device (Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait) (1/4). Start Condition ~ Address ~ Data master control Note IICAn ACKDn...
Page 804 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-30(1) start condition ~ address ~ data" of FIG-.20-30 is as follows: ① If the master sets the start condition trigger set (STTn=1), the bus data line (SDAAn) drops and the start condition is generated (SDAAn is changed from "1"...
Page 805 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-31 Communication example of a master device → slave device (Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait) (2/4). Address ~ data ~ data master control note note 1 IICAn...
Page 806 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-30of "(2) address ~ data ~ data" of (3) ~ (10) is described as follows: (3) On the slave, if the receiving address and the local station address (the value of the SVAn) are the note same , the ACK is sent to the master through the hardware.
Page 807 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-31 Communication example of a master device → slave device (Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait) (3/4). Data ~ data ~ stop condition master control IICAn note1 ACKDn...
Page 808 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-30 of "(3) data ~ data ~ stop condition" of (7) ~ (15) description is as follows: ⑦ At the end of the data transfer, because the ACKEn bit of the slave is "1", the ACK is sent to the master through the hardware.
Page 809 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-31 Communication example of a master device → slave device (Master: Select 9 clocks to wait, Slave: Choose 9 clocks to wait) (4/4). Data ~ restart condition ~ address master control IICAn <3>...
Page 810 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-30(4) data ~ restart condition ~ address" of Fig.20-30 are as follows. After performing steps (7) and (8), perform <1> to <3 >, and return to the data sending step of step (3). (7) After the data transfer is completed, because the ACKEn bit of the slave is "1", the ACK is sent to the master control through hardware.
Page 811 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-31 A communication example of a slave device → a master device (Master: Select 8 clocks to wait, Slave: Choose 9 clocks to wait) (1/3). Start Condition ~ Address ~ Data master control IICAn ACKDn...
Page 812 BAT32A2x9 user manual | Chapter 20 Serial interface IICA written to 3. To undo the wait during the slave send, the data must be the IICAn instead of the WRELn position bit. FIG 20-31 of the "(1) start condition ~ address ~ data" of (1) ~ (7) description is as follows: ①...
Page 813 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Fig. 20-32 Example of communication between the slave device → the master device (Master: Select 8 clocks to wait, Slave: Choose 9 clocks to wait) (2/3). Address ~ data ~ data master control IICAn ACKDn...
Page 814 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-31of the "(2) address ~ data ~ data" of (3) ~ is described as follows: (12) (3) On the slave, if the receiving address and the local station address (the value of the SVAn) are the note same , the ACK is sent to the master through the hardware.
Page 815 BAT32A2x9 user manual | Chapter 20 Serial interface IICA FIG 20-32 Example of communication between the slave device → the master device (Master: Select 8 → 9 clocks to wait, Slave: Select 9 clocks to wait) (3/3). Data ~ data ~ stop condition master control IICAn ACKDn...
Page 816 BAT32A2x9 user manual | Chapter 20 Serial interface IICA Note: 1 To lift the wait, the IICAn must be placed in the "FFH" position or the WRELn position must be placed. 2. After the release of the stop condition, the time from the SCLAn pin signal to generate the stop condition is at least 4.0us when set to standard mode and at least 0.6us when set to fast mode.
Page 817 BAT32A2x9 user manual | Chapter 21 Serial interface SPI Chapter 21 Serial interface SPI The serial interface SPI function is a proprietary function of the BAT32A279. 21.1 The serial interface SPI functions This product is equipped with two serial interfaces SPI0, SPI1, and has the following two modes. Run stop mode This is a mode used when serial transfer is not in progress and reduces power consumption.
Page 818 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.3 Registers that control the serial interface SPI The serial interface SPI is controlled by the following registers. • Peripheral enable register 2 (PER2). • Serial operating mode register (SPIMn). • Serial clock selection register (n).
Page 819 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.3.1 Peripheral enable register 2 (PER2). PER2 registers are registers that are set to allow or disable clocking to each peripheral hardware. Reduce power consumption and noise by stopping clocking hardware that is not in use. To use the SPI function, SPInEN must be set to "1".
Page 820 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.3.2 SPI Operating Mode Register (SPIMn). SPIM is used to select the mode of operation and control the allow or disallow of the operation. SPIM n can be set by 8-bit memory operation instructions. A reset signal is generated to clear the register to 00H.
Page 821 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.3.3 SPI clock selection register (n). This register specifies the timing of data send/receive and sets the serial clock. can be set by 8-bit storage operation instructions. A reset signal is generated to clear the register to 01H. Figure 21-3 Format of the clock selection register (n).
Page 822 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.3.4 SPI status register (SPISn). The SPIS register is used to confirm the communication status of the SPI. SPISn can be read by 8-bit storage operation instructions. A reset signal is generated to clear the register to 00H. Figure 21-4 status register (SPISn).
Page 823 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.3.5 Transmit buffer register (SDROn). The register is set to send data. When setting bits 7 (SPIE n) and bit 6 (TRMDn) of the serial operating mode register (SPIMn) to 1 When sending/receiving starts by writing data to SDROn.
Page 824 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.3.7 The SPI pin functions the control register When using SPI, the control registers (PMxx, P MCxx) must be set for port functions that are multiplexed with the SPI input and output pins. For details, please refer to "2.3.1 Port Mode Register (PMxx)". When using the multiplex port of the SPI pin as the output of S CK/SO/MO, the position of the port mode register (PMxx, PMCxx) corresponding to each port must be "0".
Page 825 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.4 Serial interface for operation of the SPI In 3-wire serial I/O mode, data is sent or received in 8-bit or 16-bit units. The data is sent or received synchronously with the serial clock. After communication begins, bit 0 (SPTF n) of SPISn is set to 1.
Page 826 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.4.1 The sending and receiving of the master If the serial operating mode register (SPIMn) has bit 6 (TRMDn) of 1, data can be sent or received. When a value is written to the transmit buffer register (SDROn), send/receive starts. （1）...
Page 827 BAT32A2x9 user manual | Chapter 21 Serial interface SPI Figure 21-8 Abort step of the master transmit/receive Start of abort setting i If there is data being SPTFn=0? transferred, wait for the transfer to end Place the SPIEn at the position "0"...
Page 828 BAT32A2x9 user manual | Chapter 21 Serial interface SPI (2) Processing process Fig. 21-9 diagram of transmit single transmit mode) (INTMD=0, CPHA=1, CPOL=1). Timing /receive timing ( SPIE 写SDRO Write SDRO 发送数据1 发送数据2 transmit data1 transmit data2 SDRO 移位运行移位运行 shift register 移位寄存器...
Page 829 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.4.2 The reception of the master If bit 6 (TRMDn) of the serial operating mode register (SPIMn) is 0, only data can be received. When data is read from the receive buffer register (SDRIn), the reception begins. （1）...
Page 830 BAT32A2x9 user manual | Chapter 21 Serial interface SPI Figure 21-12 The abort step of the master receive Start of abort setting i Note 1 The penultimate (m- 1) reads out the data Place the SPIEn at the position "0" to Write the SPIMn stop the operation of the SPI register...
Page 831 BAT32A2x9 user manual | Chapter 21 Serial interface SPI (2) Processing process Fig. 21-13: diagram of the receiving timing (CPHA=1, CPOL=1). Timing SPIE 读SDRI Read SDRI Receiving& Receiving& 接收&移位运行接收&移位运行移位寄存器 shift register shift operation shift operation receiving data1 接收数据1 receiving data2 接收数据2 SDRI...
Page 832 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.4.3 Slave sending and receiving If bits CKS2-0 of the serial clock selection register (n) select slave mode, bit 6 (TRMDn) of the serial operation mode register (SPIMn) is 1, you enter slave send/receive mode. When a value is written to the transmit buffer register (SDROn), wait for the clock of the master device to start sending/receiving.
Page 833 BAT32A2x9 user manual | Chapter 21 Serial interface SPI Figure 21-15 Abort step of Slave send/receive Start of abort setting i If there is data being SPTFn=0? transferred, wait for the transfer to end Place the SPIEn at the position "0" to stop the Write the SPIMn register operation of the SPI To use deep sleep mode, stop...
Page 834 BAT32A2x9 user manual | Chapter 21 Serial interface SPI (2) Processing process Figure 21-16 Timing diagram of send/receive timing (single-send mode) (INTMD= 0, CPHA= 1, CPOL = 1). SPIE 发送数据1 发送数据2 transmit data1 transmit data2 SDRO shift register shift operation 移位运行...
Page 835 BAT32A2x9 user manual | Chapter 21 Serial interface SPI 21.4.4 Slave reception If bits C KS 2-0n of the serial clock selection register (n) select slave mode and bit 6 (TRMDn) of the serial operation mode register (SPIM n) is 0, slave receive mode is entered. When reading data from the receive buffer register (SDRIn), wait for the clock of the master device to start receiving.
Page 836 BAT32A2x9 user manual | Chapter 21 Serial interface SPI Figure 21-19 Abort step of Slave reception Start of abort setting i Note 1 The penultimate (m-1) reads out the data Place the SPIEn at the position "0" to stop the Write the SPIMn register operation of the SPI If there is data being...
Page 837 BAT32A2x9 user manual | Chapter 21 Serial interface SPI (2) Processing process Figure 21-20 diagram of the receiving timing (CPHA=1, CPOL=1). SPIE 读SDRI Read SDRI Receiving& Receiving& 接收&移位运行接收&移位运行 shift register 移位寄存器 shift operation shift operation 接收数据1 接收数据2 receiving data1 receiving data2 SDRI SPTF...
Page 838 BAT32A2x9 user manual | Chapter 22 CAN control Chapter 22 CAN control The BAT32A239 is equipped with two CAN controllers, and the BAT32A279 product is equipped with three CAN controllers. 22.1 Summary description The chip has on-chip CAN controller (Controller Area Network) capability and complies with the CAN protocol of the ISO 11898 standard 22.1.1 features...
Page 839 BAT32A2x9 user manual | Chapter 22 CAN control 22.1.2 Feature overview Table22-1lists the functions of the CAN controller. Table22-1: Function Overview function detail agreement ISO 11898 CAN Protocol (Standard and Extended Frame Send/Receive). baud rate Maximum: 1Mbps (CAN input clock 8MHz).
Page 840 BAT32A2x9 user manual | Chapter 22 CAN control 22.1.3 Configuration The CAN controller consists of the following four modules interface This module provides an internal bus interface to send and receive signals between the CAN module and the host Memory Control Module (MCM). This function block controls access to the CAN protocol layer and CANRAM in the CAN module.
Page 841 BAT32A2x9 user manual | Chapter 22 CAN control 22.2 CAN protocol CAN (Controller Area Network) is a high-speed multiplexed communication protocol for real-time communication in automotive applications (Class C). CAN is regulated by ISO 11898. For more information, see the ISO 11898 specification. The CAN specification is usually divided into two layers: the physical layer and the data link layer, which in turn contains logical links and media access control.
Page 842 BAT32A2x9 user manual | Chapter 22 CAN control 22.2.2 Frame type The four frame types in the following table are used in the CAN protocol. Table22-2. Frame Type The frame type description Data frames The frame used to transmit the data Remote frames Go to the signal that requests the data frame Error frame...
Page 843 BAT32A2x9 user manual | Chapter 22 CAN control (5) Remote frames The remote frame consists of 6 bits of field master Figure 22-4. Remote frames Remote frames <1> <2> <3> <5> <6><7> <8> Inter-frame space End of Frame (EOF) ACK field CRC field Control the field Arbitration...
Page 844 BAT32A2x9 user manual | Chapter 22 CAN control < 2 > arbitration venue The arbitral field is used to set priorities, data frames/remote frames, and frame formats Figure 22-6. Arbitration field (in standard format). arbitration fields (control fields) identifier (11 bit) (1 bit) (1 bit) Note 1.
Page 845 BAT32A2x9 user manual | Chapter 22 CAN control < 3 > control field The control field is set "DLC" as the number of bytes of data in the data field (DLC=0 to 8). Figure 22-8 Control the field (arbitration fields) control fields (Data fields) Note D: Dominant = 0...
Page 846 BAT32A2x9 user manual | Chapter 22 CAN control < 4> data farm The data farm contains the amount of data, in bytes, that controls the field settings. Up to 8 data units can be set. Figure 22-9. Data farm Note D: Dominant =0 R: Recessive = 1 <5>CRCfield A CRC field is a 16-bit field that detects errors in data transmission.
Page 847 BAT32A2x9 user manual | Chapter 22 CAN control < 6> Ack field The Ack field is mainly a response to normal reception Figure 22-11. Ack field Note D: Dominant = 0 R: Recessive = 1 - If no CRC error is detected, the receiving node sets the Ack to the dominant bit - The sending node outputs two recessive bits <7>...
Page 848 BAT32A2x9 user manual | Chapter 22 CAN control Passive error node Interframe space contains a gap field, a suspend field, and a bus idle field. Figure 22-14: Inter-frame space (passive error node). (frame) Frame interva (frame) suspend interval Bus idle transmission (3bit) (0 to bit）...
Page 849 BAT32A2x9 user manual | Chapter 22 CAN control 22.2.4 Error frame If an error is detected, an error frame is sent at the next node. Figure 22-15: error frame Note D: Dominant = 0 R: Recessive = 1 Table22-7: Error Frame Definition name Number of digits definition...
Page 850 BAT32A2x9 user manual | Chapter 22 CAN control 22.2.5 Overload frames Overload frames are emitted in the following situations. - When the receive node does not complete the receive operation - During the gap, if the first two bits are detected dominant bits - If the dominant bit is at the last bit of the end frame (bit 7) or the last bit of the error delimiter/overload delimiter (bit 8) 1: CAN is fast enough to process all received frames so that no overload frames are generated.
Page 851 BAT32A2x9 user manual | Chapter 22 CAN control 22.3 function 22.3.1 Bus prioritization (1) When a node starts transmitting: - When the bus is idle, the sending node sends the data first (2) When multiple nodes start transmitting: - The node that continuously outputs the longest dominant bit starting from the first bit of the arbitral field gets the bus priority (if the dominant and recessive bits are transmitted at the same time, the dominant bit is used as the bus value).
Page 852 BAT32A2x9 user manual | Chapter 22 CAN control 22.3.6 Error control function (4) The type of error Table22-11. Error Type Error description Detection status type Detection conditions Send/Receive Detection method Field/frame Data bits on the bus between frame Compare output levels to bus Mismatched level Send/Receive nodes start and end frames, error frames, Bit error...
Page 853 BAT32A2x9 user manual | Chapter 22 CAN control (7) Error status (a) The type of error status The next three error states are defined by the CAN specification - Proactive error - Passive error - Bus shutdown The error type is determined by the values of the CAN Error Count Register (CnERC) of TEC0 to TEC7 (Transmit Error Count Bit) and REC0 to REC6 (Receive Error Count Bit), as shown in Table22-13.
Page 854 BAT32A2x9 user manual | Chapter 22 CAN control 1: When the value of the BOFF bit is 1, the value of the Transmission Error Counter (TEC) is invalid if an error increases the value of the Error Transmission Counter by 8 when the value of the counter is in In the range of 248 to 255, the counter does not increase any more and is in the bus off state.
Page 855 BAT32A2x9 user manual | Chapter 22 CAN control (8) Bus shutdown resume When the CAN module is in the bus off state, the CAN module permanently sets its output signal (CTxD) to the recessive bit The CAN module recovers from the bus shutdown state in the following bus shutdown recovery sequence <1>...
Page 856 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-17. Resumes an operation from a bus shutdown state through a normal recovery sequence TEC>FFH »passive error« »bus turns off « »bus recovery sequence« »actively (generated) error« BOFFbit of C0INFO C0CTRL 中OPMODE[2:0] （user write）...
Page 857 BAT32A2x9 user manual | Chapter 22 CAN control 22.3.7 Baud rate control function (10) Prescale The CAN controller has a prescaled clock (fCAN) that is supplied to the CAN. This prescale generates a CAN Protocol Layer Base Clock (fTQ) derived from the CAN Module System Clock (fCANMOD), divided by frequencies from 1 to 256 (see 22.7.13CAN Bit Rate Prescaler Register (CnBRP)).
Page 858 BAT32A2x9 user manual | Chapter 22 CAN control Reference: The CAN standard ISO 11898 specification defines the segments that make up the data bit time, as shown Figure 22-19 Figure 22-19. Reference: Data bit time configuration as defined by the CAN specification Data Bit Time (DBT Synchronize Propagate...
Page 859 BAT32A2x9 user manual | Chapter 22 CAN control (12) Synchronize data bits - The receive node establishes synchronization by changing the level on the bus because it has no asynchronous signal - The transport node transmits data synchronously at the bit time of the transport node (a) Hardware synchronization This synchronization is established when the receiving node detects the start of a frame in the inter-frame space...
Page 860 BAT32A2x9 user manual | Chapter 22 CAN control (b) Resynchronize If a level change is detected on the bus during the receive, synchronization is established again (only if the recessive level was previously sampled). The phase error of the edge is given by the relative position of the detected edge and the synchronization segment <...
Page 861 BAT32A2x9 user manual | Chapter 22 CAN control 22.4 The connection to the target system The microcontroller that integrates CAN must be connected to the CAN bus using an external transceiver Figure22-22. Connect to the CAN bus CTxD CAN_L Microcontroller transceiver with CRxD...
Page 862 BAT32A2x9 user manual | Chapter 22 CAN control 22.5 Internal registers of the CAN controller 22.5.1 CAN controller configuration Table22-15. CAN Control Register List(1/2) item Register name Peripheral enable register 0/2 (PER0/2). Serial communication pin selection register (PIOR3). Control registers Port registers 0, 4, 5, 6 (P0, P4, P5, P6).
Page 863 BAT32A2x9 user manual | Chapter 22 CAN control Table22-15. CAN Control register list(2/2) item Register name CAN message data byte 01 register m (CnMDB01m). CAN message data byte 0 register m (CnMDB0m). CAN message data byte 1 register m (CnMDB1m). CAN message data byte 23 register m (CnMDB23m).
Page 864 BAT32A2x9 user manual | Chapter 22 CAN control 22.5.2 Register access type The access types of the control registers of the CAN controller are shown in the following table where the base address is: CAN0 0x40045400; CAN1 0x40045800； CAN2 0x40046400 BAT32A239: n=0.1 BAT32A279: n=0.1.2 Table22-16.
Page 865 BAT32A2x9 user manual | Chapter 22 CAN control Table22-16. Register Access Type (2/9) Bit operating unit Read/ The default Offset address Register name Symbol write value There is no – – 0x100H CAN message data byte 01 register 00 CnMDB0100 definition There is no –...
Page 866 BAT32A2x9 user manual | Chapter 22 CAN control definition There is no – – 0x11CH CnMIDH01 definition 00x00000 – – 0x11EH CAN message control register 01 CnMCTRL01 000xx000B 866 / 1149 Rev.1.00 www.mcu.com.cn...
Page 867 BAT32A2x9 user manual | Chapter 22 CAN control Table22-16. Register Access Type (3/9) Bit operating unit Read/ The default Offset address Register name Symbol write value There is no – – 0x120H CAN message data byte 01 register 02 CnMDB0102 definition There is no –...
Page 868 BAT32A2x9 user manual | Chapter 22 CAN control definition There is no – – 0x13CH CnMIDH03 definition 00x00000 – – 0x13EH CAN message control register 03 CnMCTRL03 000xx000B 868 / 1149 Rev.1.00 www.mcu.com.cn...
Page 869 BAT32A2x9 user manual | Chapter 22 CAN control Table22-16. Register Access Type (4/9) Bit operating unit Read/ The default Offset address Register name Symbol write value There is no – – 0x140H CAN message data byte 01 register 04 CnMDB0104 definition There is no –...
Page 870 BAT32A2x9 user manual | Chapter 22 CAN control definition There is no – – 0x15CH CnMIDH05 definition 00x00000 – – 0x15EH CAN message control register 05 CnMCTRL05 000xx000B 870 / 1149 Rev.1.00 www.mcu.com.cn...
Page 871 BAT32A2x9 user manual | Chapter 22 CAN control Table22-16. Register Access Type (5/9) Bit operating unit Read/ The default Offset address Register name Symbol write value There is no – – 0x160H CAN message data byte 01 register 06 CnMDB0106 definition There is no –...
Page 872 BAT32A2x9 user manual | Chapter 22 CAN control definition There is no – – 0x17CH CnMIDH07 definition 00x00000 – – 0x17EH CAN message control register 07 CnMCTRL07 000xx000B 872 / 1149 Rev.1.00 www.mcu.com.cn...
Page 873 BAT32A2x9 user manual | Chapter 22 CAN control Table22-16. Register Access Type (6/9) Offset address Register name Symbol Read/ Bit operating unit The default write value – – 0x180H CAN message data byte 01 register 08 CnMDB0108 Read/ There is no write definition –...
Page 874 BAT32A2x9 user manual | Chapter 22 CAN control Table22-16. Register Access Type (7/9) Bit operating unit Offset Read/ The default Register name Symbol address write value There is no – – 0x1A0H CAN message data byte 01 register 10 CnMDB0110 definition There is no –...
Page 875 BAT32A2x9 user manual | Chapter 22 CAN control definition There is no – – 0x1BCH CnMIDH11 definition 00x00000 – – 0x1BEH CAN message control register 11 CnMCTRL11 000xx000B 875 / 1149 Rev.1.00 www.mcu.com.cn...
Page 876 BAT32A2x9 user manual | Chapter 22 CAN control Table 22-16. Register Access Type (8/9) Bit operating unit Read/ The default Offset address Register name Symbol write value There is no – – 0x1C0H CAN message data byte 01 register 12 CnMDB0112 definition There is no...
Page 877 BAT32A2x9 user manual | Chapter 22 CAN control definition There is no – – 0x1DCH CnMIDH13 definition 00x00000 – – 0x1DEH CAN message control register 13 CnMCTRL13 000xx000B 877 / 1149 Rev.1.00 www.mcu.com.cn...
Page 878 BAT32A2x9 user manual | Chapter 22 CAN control Table 22-16. Register Access Type (9/9) Bit operating unit Read/ The default Offset address Register name Symbol write value There is no – – 0x1E0H CAN message data byte 01 register 14 CnMDB0114 definition There is no...
Page 879 BAT32A2x9 user manual | Chapter 22 CAN control definition There is no – – 0x1FCH CnMIDH15 definition 00x00000 – – 0x1FEH CAN message control register 15 CnMCTRL15 000xx000B 879 / 1149 Rev.1.00 www.mcu.com.cn...
Page 880 BAT32A2x9 user manual | Chapter 22 CAN control 22.5.3 Register bit configuration Table22-17. CAN Global Register Bit configuration Offset address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 0x000H ClearGOM CnGMCTRL(W) 0x001H SET EFSD SetGOM...
Page 881 BAT32A2x9 user manual | Chapter 22 CAN control Table 22-18. CAN Module Registers Bit configuration (1/2) Offset address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 0x040H CM1ID[7:0] CnMASK1L 0x041H CM1ID[15:8] 0x042H CM1ID[23:16] CnMASK1H...
Page 882 BAT32A2x9 user manual | Chapter 22 CAN control Table 22-18: CAN Module Registers Bit configuration (2/2) Offset address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 0x058H CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 CnINTS(R)
Page 883 BAT32A2x9 user manual | Chapter 22 CAN control Table 22-19. Bit configuration of the message buffer registers Offset Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 address 0x1x0H Message data (byte 0). CnMDB01m 0x1x1H Message data (byte 1).
Page 884 BAT32A2x9 user manual | Chapter 22 CAN control 22.6 Bit setting/clear function CAN control registers include registers whose bits can be set or cleared through the CPU and CAN interfaces. If the following registers are written directly, an operation error occurs. Do not write any value directly through bitwise operations, read/modify/write, or directly write to the target value.
Page 885 BAT32A2x9 user manual | Chapter 22 CAN control Figure22-24. Write 16-bit data in operations Set7 Set6 Set5 Set4 Set3 Set2 Set1 Set0 Clear7 Clear6 Clear5 Clear4 Clear3 Clear2 Clear1 Clear0 Setn Clearn n status after setting/clearing No changes No changes Note n = 0 to 7 22.7 Control registers Note m=0 to 15...
Page 886 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.2 CAN Global Module Control Register (CnGMCTRL). The CnGMCTRL register is used to control the operation of the CAN module. Figure22-25. CAN Global Module Control Register Format (CnGMCTRL) (1/2 (a) read (a) write (a) read MBON Message cache registers, transmit/receive bits...
Page 887 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-26. CAN Global Module Control Register Format (CnGMCTRL) (2/2 EFSD Bit enables force shutdown It is forbidden to turn off by writing GOM=0 Enables to be turned off by writing GOM=0 Note To request a force shutdown, you must clear the GOM bit to 0 in subsequent operations and write immediately after the EFSD bit is set to 1.
Page 888 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.3 CAN Global Module Clock Selection Register (CnGMCS). CnGMCS is used to select the system clock of the CAN module. Figure 22-26: CAN Global Module Clock Selection Register Format (CnGMCS CnGMCS CCP3 CCP2 CCP1 CCP0...
Page 889 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.4 CAN Global Automatic Block Transfer Control Register (CnGMABT). The CnGMABT register is used to control automatic block transfer (ABT) operation Figure 22-27 Format of the CAN Global Automatic Block Transfer Control Register (CnGMABT) (1/2 (a) read CnGMABT ABTCLR...
Page 890 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-28. Format of the CAN Global Automatic Block Transfer Control Register (CnGMABT) (2/2 ABTTRG Automatic block transfer status bits Automatic block transfer was stopped Automatic block transfer is being performed Note Do not set the ABTTRG bit (ABTTRG=1) in initialization mode. If the ABTTRG bit is set in initialization mode, operation cannot be guaranteed after the CAN module enters normal operation mode using ABT.
Page 891 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.5 CAN Global Automatic Block Delay Setting Register (CnGMABTD). The CnGMABTD register is used to set the time interval at which packet buffer data is allocated to ABT and transmitted in ABT normal operating mode. Figure 22-28 CAN Global Automatic Block Propagation Delay Setting Register Format (CnGMABTD).
Page 892 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.6 CAN module mask registers (CnMASKaL, CnMASKaH) (a=1, 2, 3, or4). The CnMASKaL and CnMASKaH registers expand the number of message caches that enter the same packet cache by comparing the masked portion of the packet ID and invalidating the ID of the masked portion.
Page 893 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-29. Format of the CAN module mask register(CnMASKaL,CnMASKaH)(a=1,2,3,or4)(2/2) CAN module shield 3 registers (CnMASK3L, CnMASK3H). CAN module shield 4 registers (CnMASK4L, CnMASK4H). CMID0 to CMID28 Sets the masking mode for the ID bit The ID bits of the packet buffer set by CMID0 through CMID28 are compared to the ID bits of the received packet frames.
Page 894 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.7 CAN Module Control Register (CnCTRL). The CnCTRL registers are used to control the operating mode of the CAN module. Figure 22-30 CAN Module Control Registers (CnCTRL) (1/4). (a) read (b) write (a) read RSTAT Receive status bits...
Page 895 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-30. Format of the CAN Module Control Register (CnCTRL) (2/4 TSTAT Transfer status bits The transfer is stopped The transfer is in progress Note - The RSTAT bit is set to 1 under the following conditions (timing). The SOF bit of the sending frame is detected The RSTAT bit is cleared to 0 under the following conditions (timing).
Page 896 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-30 Format of CAN Module Control Register (C0CTRL) (3/4) PSMODE1 PSMODE0 Power-saving mode No power saving mode is selected CAN sleep mode Set Prohibited CAN stop mode Note 1 Transitions to or wake up from CAN stop mode are required through CAN sleep mode. Requests to go in and out of the CAN stop mode directly are ignored.
Page 897 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-30. Format of can module control registers (CnCTRL) (4/4 ClearVALID Sets the VALID bit VALID remains VALID is cleared 0. SetPSMODE0 ClearPSMODE0 Set the PSMODE0 bit PSMODE0 is cleared 0 PSMODE0 is set to 1 Other values PSMODE0 does not change SetPSMODE1...
Page 898 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.8 CAN Module Last Error Code Register (CnLEC). The CnLEC register provides error messages for the CAN protocol. Figure22-31. Format of the LAST Error Code Register for can modules (CnLEC Note 1 When CAN switches from operating mode to initialization mode, the contents of the CnLEC register are not cleared 2.
Page 899 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.9 CAN Module Information Register (CnINFO). The CnINFO register indicates the status of the CAN module Figure22-32. Format of the CAN Module Information Register (CnINFO BOFF Bus shutdown status bit Non-bus shutdown state (transmission error counter less than 255) (transmission counter value less than 256).
Page 900 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.10 CAN Module Error Counter Register (CnERC). The CnERC register records the count value of the transmit/receive error counter Figure 22-33. CAN Module Error Counter Register Format (CnERC REPS Receives passive error status bits The Receive Error counter is not a passive error (<128).
Page 901 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.11 CAN Module Interrupt Enable Register (CnIE). CnIE registers are used to enable or disable interrupts to the CAN module. Figure 22-34. CAN Module Interrupt Enable Register Format (CnIE) (1/2 (a) read (b) write (a) read CIE5-CIE0...
Page 902 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-35. CAN Module Interrupt Enable Register Format (CnIE) (2/2 SetCIE3 ClearCIE3 Set the CIE3 bit CIE3 clear 0 CIE3 set 1 Other values CIE3 has not changed SetCIE2 ClearCIE2 Set the CIE2 bit CIE2 clear 0 CIE2 set 1 Other values...
Page 903 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.12 CAN Module Interrupt Status Register (CnINTS). The CnINTS register indicates the CAN module interrupt status Figure 22-35. CAN Module Interrupt Status Register Format (CnINTS (a) read (b) write (a) read CINTS5-CINTS0 CAN interrupt status bit No related interrupt source events are pending A related interrupt source event is pending...
Page 904 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.13 CAN Module Bit Rate Scaling Register (CnBRP). The CnBRP register is used to select the CAN protocol layer base clock (fTQ). The baud rate is set to the CnBTR register Figure 22-36. CAN Module Bit Rate Scaling Register Format (CnBRP TQPRS7-TQPRS0 CAN protocol layer basic system clock (f CANMOD...
Page 905 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.14 CAN Module Bit Rate Register (CnBTR). The CnBTR register is used to control the data bit time of the baud rate. Figure 22-38. CAN Module Bit Rate Register Format (CnBTR) (1/2 SJW1 SJW0 Synchronize the length of the jump width...
Page 906 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-38. CAN module bit rate register format(CnBTR)(2/2) TSEG13 TSEG12 TSEG11 TSEG10 The length of the time period 1 Prohibit settings 10TQ 11TQ 12TQ 13TQ 14TQ 15TQ 16TQ (default). 1 These settings must be performed when the CnBRP register is 00H Note TQ=1/f : CAN protocol layer base system clock).
Page 907 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.15 CAN module last entered the pointer register (CnLIPT). The CnLIPT register indicates the number of message buffers that last stored a data frame or remote frame. Figure 22-40. CAN module last entered the pointer register format (CnLIPT LIPT7-LIPT0 Last Input Pointer Register (CnLIPT 0 to 15...
Page 908 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.16 CAN module receive History List Register (CnRGPT). The CnRGPT register is used to read the received history list. Figure 22-41. CAN module receives the History List Register Format (CnRGPT) (1/2 (a) read (b) write (a) read RGPT7-RGPT0...
Page 909 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.17 CAN module last output pointer register (CnLOPT). The CnLOPT register indicates the number of message buffers to which a data frame or remote frame was last transmitted. Figure 22-42. CAN module last outputs pointer register format (CnLOPT LOPT7-LOPT0 Send History List Last Output Pointer (LOPT 0 to 15...
Page 910 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.18 CAN module send History List Register (CnTGPT). The CnTGPT register is used to read out the list of transmission histories. Figure 22-43. CAN module sends history list register format (CnTGPT) (1/2). (a) read (b) write (a) read...
Page 911 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.19 CAN Module Timestamp Register (CnTS). CnTS registers are used to control the timestamp function Figure22-44. CAN Module Timestamp Register Format (CnTS) (1/2). (a) read (b) write Note: When the CAN module is in normal operating mode with ABT, the lock function of the timestamp function must not be used.
Page 912 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-44. CAN module timestamp register format(CnTS)(2/2) TSSEL The timestamp capture event selects the bit Timestamp capture events in SOF The timestamp captures the last bit of the event in the EOF TSEN TSOUT signal operation setting bit TSOUT signal flipping operation is prohibited TSOUT signal flip operation enables...
Page 913 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.20 CAN message data byte register (CnMDBxm) (x=0 to 7), (CnMDBzm) (z=01, 23, 45, 67). CnMDBxm, CnMDBzm registers are used to store data for sending/receiving messages. The CnMDBxm register can be accessed in 8-bit units. The CnMDBzm registers provide access to the CnMDBxm registers of the 16-bit cell Figure 22-45.
Page 914 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-46. CAN message data byte register format (CnMDBxm) (x = 0 to 7), (CnMDBzm) (z = 01, 23, 45, 67) (2/2) register -CnMDBzm CnMDB01m MDATA MDATA MDATA MDATA MDATA MDATA MDATA MDATA 0115 0114...
Page 915 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.21 CAN message data length register m (CnMDLCm). The CnMDLCm register is used to set the number of bytes of the data segment of the message buffer Figure 22-46 CAN message data length register m format (CnMDLCm Reset value: 0000xxxxB CnMDLCm MDLC3...
Page 916 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.22 CAN Message Configuration Register (CnMCONFm). The CnMCONFm register is used to specify the type of message buffer and set the mask. Figure 22-47. CAN Message Configuration Register Format (CnMCONFm) (1/2 Reset value: No R/W is defined CnMCONFm Override the control bit The packet buffer for received data frame 1 is not overwritten by the newly received data...
Page 917 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-47. CAN Frame configuration register format(CnMCONFm)(2/2) Message cache allocation bits Message caching is not used Use message caching Note: Be sure to write bits 1 and 2 to 0 Note m = 0 to 15 22.7.23 CAN message ID register m (CnMIDLm and CnMIDHm).
Page 918 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.24 CAN message control register m (CnMCTRLm). The CnMCTRLm register is used to control the operation of the packet buffer. Figure 22-49. CAN message control register m format (CnMCTRLm) (1/3). Reset Value:000xx000B (a) read CnMCTRLm (c) write...
Page 919 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-49. CAN Frame control register m format (CnMCTRLm)(2/3) Message cache data update bits Data frames or remote frames are not stored in the message buffer Data frames or remote frames are stored in a message buffer Packet caching sends request bits There are no pending or transmitting packet frame transfer requests in the packet buffer.
Page 920 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-49. CAN frame control register m format (CnMCTRLm)(3/3) SetTRQ ClearTRQ TRQ set bit TRQ clear 0 TRQ set to 1 Other values There is no change in the TRQ Note: When receiving packets from other nodes or transmitting dissipative packets, even if the TRQ bit is set to 1, the transmission may not start immediately.
Page 921 BAT32A2x9 user manual | Chapter 22 CAN control 22.7.25 Serial communication pin select register 1 (PIOR3). The PIOR3 register is used to switch the input source to the timer array unit and the CAN0 communication pin. This register can be read or written in 8-bit form. The PIOR3 registers can be used to select the CTxD0 and CRxD 0 pins on two different ports.
Page 922 BAT32A2x9 user manual | Chapter 22 CAN control 22.8 CAN controller initialization 22.8.1 CAN module initialization Before enabling CAN module operation, the system clock of the CAN module needs to be determined by setting the CCP [3:0] bit of the CnGMCS register by software. After the CAN module is working, do not change the setting of the CAN module system clock.
Page 923 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-51. After redefining the send request to the send message cache settings(TRQ) The redefinition is complete Send? Wait for 1 bit of CAN data Set the TRQ bit TRQ = 1 TRQ = 0 note1.When a message is received, it will be set to each received packet buffer ID and masking perform receive filtering.
Page 924 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-52. Transition to operating mode OPMODE[2:0]=00H LikeN bus busy [Receive mode only]. OPMODE[2:0]=03H OPMODE[2:0]=00H OPMODE[2:0]=00H CAN bus busy CAN bus busy [In normal OPMODE[2:0]=03H operating mode with [Single-shot mode]. Abbot]. OPMODE[2:0]=04H OPMODE[2:0]=02H OPMODE[2:0]=00H Inter-frame space...
Page 925 BAT32A2x9 user manual | Chapter 22 CAN control 22.9 Message reception 22.9.1 Message reception In all operating modes, the full packet buffer area is analyzed to find the appropriate buffer to store the newly received packets. All message buffers that meet the following criteria are included in the evaluation (RX search process): Packet cache used (The MA0 bit of CnMCONFm is 1).)
Page 926 BAT32A2x9 user manual | Chapter 22 CAN control 22.9.2 Receive data reads To maintain data consistency when Figure 22-74-74 Fig.22-76. During packet reception, the CAN module sets the DN of the CnMCTRLm register twice: at the beginning of storing the data into the packet buffer, and again at the end of this stored procedure. In this stored procedure, the MUC bit of the message buffer CnMCTRLm register is set.
Page 927 BAT32A2x9 user manual | Chapter 22 CAN control 22.9.3 Receive history list function The Receive History List (RHL) function in the Receive History List records the number of receive message buffers that are received and stored for each data frame or remote frame. RHL consists of a storage element equivalent to up to 23 messages, the last packet-in pointer (LIPT) has the corresponding CnLIPT register and the Receive History List Fetch Pointer (RGPT) has the corresponding CnRGPT register.
Page 928 BAT32A2x9 user manual | Chapter 22 CAN control As long as the RHL contains 23 or fewer entries, the order of occurrence is maintained. If more receives occur while the host processor is not reading THEHL, the full receive sequence cannot be resumed. Figure 22-54.
Page 929 BAT32A2x9 user manual | Chapter 22 CAN control 22.9.4 Blocking function For any packet buffer used for reception, you can choose to allocate a quarter of the receive mask (or no mask). By using the masking function, packet ID comparisons can be reduced by masking bits, allowing multiple different IDs to be received into a buffer.
Page 930 BAT32A2x9 user manual | Chapter 22 CAN control 22.9.5 Multi-buffer receive block capability The Multiple Buffer Receive Block (MBRB) feature is used to store data blocks sequentially in two or more packet buffers without CPU interaction by setting the same ID to two or more packet buffers with the same packet buffer type.
Page 931 BAT32A2x9 user manual | Chapter 22 CAN control 22.9.6 Remote frame reception In all operating modes, when a remote frame is received, a packet buffer that can store the remote frame is searched from all packet buffers that meet the following criteria. Used for packet caching (Bit MA0 of the CnMCONFm register is set to 1).
Page 932 BAT32A2x9 user manual | Chapter 22 CAN control 22.10 Message sending 22.10.1 Message sending In all operating modes, if the TRQ bit is set to 1 in the packet buffer that meets the following criteria, the search for the packet buffer to transmit the message begins. It is used for packet caching (MA0 position 1 of the CnMCONFm register).
Page 933 BAT32A2x9 user manual | Chapter 22 CAN control Priority condition description The message frame of the lowest value represented by the first 11 bits of the ID is sent first. If the value of the 11-bit standard ID The value of the first 11 bits of is equal to or less than the first 11 bits of the 29-bit extension ID, 1 (high).
Page 934 BAT32A2x9 user manual | Chapter 22 CAN control 22.10.2 Send history list function The Transmission History List (THL) feature records the number of the packet buffer that sends data or remote frames in the transmission history list. THL contains storage elements equivalent to up to seven messages, the last outgoing message pointer (LOPT) with the corresponding CnLOPT register, and the Transmit History List Fetch Pointer (TGPT) of the CnTGPT register.
Page 935 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-56. Send a list of histories transmit histoical list(THL) transmit histoical list(THL) event: - CPU confirms message message buffer 4 cache 6,9 and 2 Transmit message buffer 3 completion. message buffer 7 message buffer 7 - message 3 and 4 Tx last...
Page 936 BAT32A2x9 user manual | Chapter 22 CAN control 22.10.3 Automatic Block Transfer (ABT). The Automatic Block Transfer (ABT) feature is used to successfully transmit two or more data frames in succession without CPU interaction. The maximum number of transmit packet buffers allocated to the ABT function is 8 (packet buffer numbers 0 to 7).
Page 937 BAT32A2x9 user manual | Chapter 22 CAN control Note Set the ABTCLR bit to 1 and the ABTTRG bit to 0 to resume ABT operation at buffer number 0. If the ABTCLR bit is set to 1 and the ABTTRG bit is set to 1, subsequent operations are not guaranteed.
Page 938 BAT32A2x9 user manual | Chapter 22 CAN control (3) ABT transmissions are aborted in normal operating mode with automatic block transfers To abort the started ABT, clear the ABTTRG bit of the CnGMABT register to 0. In this case, if the ABT message is currently being transmitted and until the transfer is complete (successful or not), the ABTTRG bit will remain at 1 and cleared to 0 immediately after the transfer is complete.
Page 939 BAT32A2x9 user manual | Chapter 22 CAN control 22.11 Power-saving mode 22.11.1 CAN sleep mode CAN sleep mode can be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can enter CAN sleep mode from all operating modes. The release of the CAN sleep mode returns the CAN module to the operating mode before entering CAN sleep mode In CAN sleep mode, the CAN module does not transmit messages even if the transfer request is issued or suspended.
Page 940 BAT32A2x9 user manual | Chapter 22 CAN control The state of the CAN sleep mode The CAN module is in the following state after entering CAN sleep mode The internal operating clock has stopped with minimal power consumption The CAN acceptance pin (CRxD) of the detected falling edge function remains active to wake up the CAN module from the CAN bus.
Page 941 BAT32A2x9 user manual | Chapter 22 CAN control 22.11.2 CAN stop mode THE CAN STOP MODE CAN BE USED TO SET THE CAN CONTROLLER TO STANDBY MODE TO REDUCE POWER CONSUMPTION. The CAN module can only enter CAN stop mode from CAN sleep mode.
Page 942 BAT32A2x9 user manual | Chapter 22 CAN control 22.11.3 Example of power saving mode In some application systems, it may be necessary to put the CPU into power-saving mode to reduce power consumption. By using a power-down mode specific to the CAN module and a CPU-specific power- down mode, the CAN bus can wake up the CPU from the power-down state.
Page 943 BAT32A2x9 user manual | Chapter 22 CAN control 22.12 Interrupt function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in the interrupt status register. Four separate interrupt request signals are generated from six interrupt sources. When generating an interrupt request signal that corresponds to two or more interrupt sources, you can use the interrupt status register to identify the interrupt source.
Page 944 BAT32A2x9 user manual | Chapter 22 CAN control 22.13 Diagnostic functions and special operating modes The CAN module provides receive-only mode, single-shot mode and self-test mode to support the operation of the CAN bus diagnostic function or specific CAN communication methods. 22.13.1 Receive mode only Receive-only mode is used to monitor incoming messages without any interference with the CAN bus...
Page 945 BAT32A2x9 user manual | Chapter 22 CAN control Note: If only two CAN nodes are connected to the CAN bus and one of the nodes is running in receive-only mode, there is no ACK on the CAN bus. Due to the lack of an ACK, the transport node transmits the active error flag and sends the message frame repeatedly.
Page 946 BAT32A2x9 user manual | Chapter 22 CAN control 22.13.3 Self-test mode In self-test mode, packet frame transmission and reception can be tested without connecting the CAN node to the CAN bus without affecting the CAN bus. In self-test mode, the CAN module is completely disconnected from the CAN bus, but the transmission and reception loop internally.
Page 947 BAT32A2x9 user manual | Chapter 22 CAN control 22.13.4 Receive/send operations in operation mode Table 22-21shows a summary of receive/send operations for each mode of operation. Table 22-21. Send/receive profiles in operation mode Send Send Automatic Block Sets the Store data to the Mode of operation data/remote Send a reply...
Page 948 BAT32A2x9 user manual | Chapter 22 CAN control 22.14 Timestamp function CAN is an asynchronous serial protocol. All nodes connected to the CAN bus have local autonomous clocks. Therefore, the clocks of the nodes have no relationship (that is, the clocks are asynchronous and may have different frequencies).
Page 949 BAT32A2x9 user manual | Chapter 22 CAN control Note: The timestamp function using the TSLOCK bit stops switching the TSOUT bit by receiving a data frame in packet buffer 0. Therefore, message buffer 0 must be set to receive packet buffer.
Page 950 BAT32A2x9 user manual | Chapter 22 CAN control 22.15 Baud rate setting 22.15.1 Baud rate setting Make sure to set within the limit value to ensure proper operation of the CAN controller as shown below. (a) 5TQ SPT(sample point) 17TQSPT=TSEG1+1TQ (b) 8TQ DBT (Data Bit Time) 25TQ...
Page 951 BAT32A2x9 user manual | Chapter 22 CAN control Table22-22. Configurable bit rate combination(1/3) Valid bit rate settings CnBTR register setting Sample points value (%) in %) DBT length Synchronize Propagate Phase Phase TSEG1[3:0] TSEG2[2:0] segments segments segment 1 segment 2 1111 68.0 1110...
Page 952 BAT32A2x9 user manual | Chapter 22 CAN control Table22-22. Configurable bit rate combination (2/3) Valid bit rate settings CnBTR register setting Sample points value (%) in %) DBT length Synchro Propaga Phase Phase TSEG1[3:0] TSEG2[2:0] nize segment 1 segment 2 segments segments 1000...
Page 953 BAT32A2x9 user manual | Chapter 22 CAN control Table22-22. Configurable bit rate combination (3/3) CnBTR register Valid bit rate settings setting Sample points value (%) in %) Synchronize Propagate Phase segment 1 Phase segment 2 TSEG1[3:0] TSEG2[2:0] DBT length segments segments 0101 63.6...
Page 954 BAT32A2x9 user manual | Chapter 22 CAN control 22.15.2 A representative example of baud rate settings Table 22-23and Table 22-24show a representative example of the baud rate setting. Table 22-23. Representative example of baud rate setting (f =8MHz) (1/2). CANMOD The CnBTR register Set the The effective bit rate setting (in kbps).
Page 955 BAT32A2x9 user manual | Chapter 22 CAN control Table22-23. Representative example of baud rate setting (f =8MHz) (2/2 CANMOD The CnBTR register Set the The ratio of CnBRP The effective bit rate setting (in kbps setting value baud rate Sample the division Register value in...
Page 956 BAT32A2x9 user manual | Chapter 22 CAN control Table 22-24. Representative example of baud rate setting (f =16MHz) (1/2 CANMOD The CnBTR register Set the The effective bit rate setting (in kbps). The ratio of CnBRP setting value baud rate Sample the division Register...
Page 957 BAT32A2x9 user manual | Chapter 22 CAN control Table 22-24. Representative example of baud rate setting (f =16MHz) (2/2 CANMOD The CnBTR register Set the The effective bit rate setting (in kbps). The ratio of CnBRP Sample setting value baud rate the division Register point...
Page 958 BAT32A2x9 user manual | Chapter 22 CAN control 22.16 The operation of the CAN controller The operating procedures in this chapter are the operational processing procedures for the CAN controller. Please refer to the process of development in this chapter. Note m=0 to 15 Fig.22-61.initialize Begin...
Page 959 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-62.Reinitialize Begin PMODE INITmode Set the CnBRP register, cnBTR register Set the CnIE registers Set the CnMASK register Initialize the message buffer C0ERC and C0INFO Register clearing? Set upCCERC bit Configure C0CTRL register (set OPMODE) Note: After the CAN module is set to initialization mode, do not immediately set it to another operating mode.
Page 960 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-63. Packet cache initialization Begin RDY= 1? Clear RDY bit RDY= 0? Set the C0MCONFm register Set the C0MeDHm register, C0MeDlm register Send message cache? Set the C0MDLCm register Clear the C0MDBm register Set the C0MCTRLm register Set the RDY bit Note: 1.
Page 961 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-64shows the receive packet cache processing (CnMCONFm register MT[2:0] bits = 001B to 101B). Fig.22-64. Packet cache redefinition Begin Clear VALID bit RDY=1? Clear the RDY bit RDY=0? RSTAT=0Or Note1 InALID=1? Note2 Wait for 4 CAN data bits Set up message...
Page 962 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-65shows the processing of the transmit packet buffer during transmission (CnMCONFm register MT [2:0] bits = 000B). Figure 22-65. Packet cache redefinition during sending Begin Send abort processing Clear the RDY bit RDY= 0? Data frames Remote frames...
Page 963 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-66shows the transmit packet cache processing (CnMCONFm register MT [2:0] bit = 000B). Figure 22-66. Packet sending processing Begin TRQ = 0? Clear the RDY bit RDY= 0? Data frames Remote frames Data frame or remote frame? Set the C0MDATAxm register Set the...
Page 964 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-67shows the cache processing of the transmit message (CnMCONFm register MT[2:0] bit = 000B). Fig.22-67. Abbot Packet sending processing Begin OffTTRG =0? Clear the RDY bit RDY= 0? Set the CnMDATAxm register Set the CnMDLCm register Clear the CnMCONFm register RTR bit...
Page 965 BAT32A2x9 user manual | Chapter 22 CAN control Figure22-68. Send through interrupts (using the CnLOPT register). Begin Send completes interrupt processing Read the C0LOPT register Clear the RDY bit RDY= 0? Data frames Remote frames Data frame or remote frame? Set up C0MDATAxmregister Set the C0MDLCm register Set the C0MDLCm register...
Page 966 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-69. Send via interrupt (using the CnTGPT register). Begin Send completes interrupt processing Read the C0TGPT register TOVF=1? Clear TOVF bit Clear the RDY bit RDY=0? Data Remote frames frames Data frame or remote frame? Set up C0MDATAxmregister Set Set up C0MDLCmregister...
Page 967 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-70. Transfer via software polling Begin CINTS0=1? Clear the CINTS0 bits Read the C0TGPT register TOVF=1? Clear the TOVF bit Clear the RDY bit RDY=0? Data Remote Data frame or frames frames remote frame Set upC0MDLCmregister...
Page 968 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-71 Transmission abort processing (except for normal operating mode with ABT). Begin Clear the TRQ bit Wait 11CAN data bits TSTAT=0 Read the C0LOPT register Was the message cache that matches the C0LOPT register aborted? The transfer abort request succeeded...
Page 969 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-72 Transmit abort processing (except for ABT transmissions) (normal operation with ABT). Begin Clear ABTTRG bit OffTTRG =0? Clear TRQ bit Nexcerpt Wait 11CAN data bits TSTAT=0? Read register C0LOPT The aborted packet cache and register C0LOPT match? Successfully sent for suspension...
Page 970 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-73shows that the transmission packet stops when the transmission ABT packet cache is aborted without skipping the recovery process Figure 22-73. ABT transmits abort processing (normal mode of operation with ABT). Begin TSTAT=0? Clear ABTTRG bit...
Page 971 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-74shows that the processing of the sending message stops skipping the recovery when the transmission ABT packet cache is aborted. . Figure 22-74. ABT sends a request to abort processing (normal mode of operation with ABT). Begin Clear the TRQ bit in the packet cache sent...
Page 972 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-75. Receive via interrupt (using register CnLIPT). Begin A receive completion interrupt is generated Read register C0LIPT Clear DN bits Read C0MDATAxm,C0M0DLCm, C0MIDLm,andC0MIDHmregister DN=0 Note MUC=0 Note Use read checks for MUC and DN bits Note: To check the MBON flags at the beginning and end of an interrupt in order to check access to the message buffer and the receive history list register in case of a pending execution of sleep mode.
Page 973 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-76. Receive through interrupts(Use registers CnRGPT) Begin A receive completion interrupt is generated Read register C0RGPT RTheVF= Clear ROVF bit RHPM=1? Clear DN bits Read CnMDATAxm, CnMDLCm, CnMIDLm, CnMIDHm register DN = 0 Note MUC = 0 The received data...
Page 974 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-77. Receive through software polling Begin CINTS1=1? purgeCINTS1位 Read register C0RGPT RVf=1? Clear ROVF bit RHPM=1? Clear DN bit Read C0MDATAx m,C 0MDLCm C0MeDLm,C 0MIDHmregister DN=0 Note MUC=0 Data read Illegal data is read successfully Note Use read checks for MUC and DN bits Note 1 Check the MBON flags for the start and end of polling in order to check access to the message...
Page 975 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-78. Set the CAN sleep/stop mode Start (PSMODE[1:0]= 00B) Set upPSMODE0 bit PSMFROME0= CAN sleep mode Set upPSMODE1 bit PSMFROME1= Apply CAN Sleep Mode Again? CAN stop mode ThePMODE INITmode? Access registers other than the C0CTRL and C0GMCTRL registers Settings -- C0CTRL...
Page 976 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-79. Clear CAN sleep/stop mode Start Can Stop mode clear PSMODE1 bit when CAN clock is activated, when CAN clock disabled, activate release CAN sleep mode CAN Sleep mode activate release CAN sleep mode via CAN Bus via CAN Bus after explicit edge is...
Page 977 BAT32A2x9 user manual | Chapter 22 CAN control Fig.22-80. Bus shutdown resume (Normal mode operation with ABT) Begin BOFF= 1? Note Clears all TRQ bits Set the register CnCTRL (ClearOPMODE Access registers other than CnCTRL and CnGMCTRL Force recovery from bus shutdown? Settings-C0CTRL Set upCCERC bit...
Page 978 BAT32A2x9 user manual | Chapter 22 CAN control Fig 22-81. Bus shutdown resume(Normal mode operation with ABT) Begin BOFF= 1? Clear ABTTRG bits Note Clear all TRQ bits Set the register CnCTRL (ClearOPMODE visit Registers and registers other than CnCTRL cnGMCTRL Force recovery from bus shutdown? Settings-C0CTRL...
Page 979 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-82. Normal Shut down processing Begin INIT mode Clear Gather bits Closed successfully GOM=0,EFSD=0 Figure 22-83. Force shutdown processing Begin SetEFSD bit Must be followed by a write ClearGOM bit GOM=0? Closed successfully GOM=0,EFSD=0 Note: Between setting the EFSD bit and clearing the GOM bit, do not read or write any registers through...
Page 980 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-84. Error handling Begin The error is interrupted CINTS2 =1? Check the CAN module status (read register C0INFO). Clear CINTS2 bit CINTS3 =1? Check the CAN protocol error status (read register C0LEC).
Page 981 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-85. Set CPU standby (from CAN sleep mode). Begin Set the PSMODE0 bit PSMODE0=1? CAN sleep mode MBONbit=0? CINTS5bit=1? Set the CPU standby mode Clear PSMODE0 bits Clear ThereNTS5 bit Note: Before the CPU is set to enter CPU standby mode, check if CAN is in sleep mode. When CAN sleep mode is detected, until the CPU is set to standby mode, CAN sleep mode may be canceled by the wake-up of the CAN bus.
Page 982 BAT32A2x9 user manual | Chapter 22 CAN control Figure 22-86. Set CPU standby (stop mode from CAN). Begin Set the PSMODE0 bit PSMODE0=1? CAN sleep mode Set the PSMODE1 bit PSMODE1=1? Clear PSMODE0 bits CAN stop mode Note Clear ThereNTS5 bit MBONbit=0? Set the CPU standby mode Note In interrupt wake-up...
Page 983 BAT32A2x9 user manual | Chapter 23 LCD bus interface Chapter 23 LCD bus interface The LCD bus interface function is a proprietary function of BAT32A279. The LCD bus interface is used to connect the internal bus system and the external LCD controller/driver. The interface includes an asynchronous 8bit parallel data bus and two control lines.
Page 984 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.2 LCD bus interface configuration The LCD bus interface includes the following configurations: Table 23-1 LCD bus interface configuration project Configuration Data I/O pins 8 pins (DBD7 to DBD0). Control pins DBW R, DBRD (Mode 80(IMD=0)).
Page 985 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.2.1 LCD bus interface data register (LBDATA, LBDATAL). LBDATA is used to store data transmitted through the LCD bus interface and supports both 8-bit and 16-bit read-write. The value of LBDATA after reset is 0000H Figure 23-2 Format of the LCD bus interface data register (LBDATA, LBDATAL Address: 0x40045410 Reset value: 0000HRW LBDATAL...
Page 986 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.2.2 LCD bus interface read data registers (LBDATAR, LBDATARL). LBDATAR is a read-only register. It contains the data that was last read and transmitted through the LCD bus interface. Reading this register does not initiate a new read transfer on the LCD bus interface. This register supports either a 16-bit read operation or an 8-bit read operation.
Page 987 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.3 Control registers for the LCD bus interface The following 10 registers are used to control the LCD bus interface: • LCD Bus Interface Mode Register (LBCTL • LCD bus interface cycle register (LBCYC). •...
Page 988 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.3.2 LCD Bus Interface Mode Register (LBCTL). LBCTL is used to control the operation of the LCD bus interface. Set lbcTL via 8-bit memory operation instructions The reset value is 00H Figure 23-5 Format of the LCD bus interface mode register (LBCTL Address: 0x40047400 Reset value 00H R/W...
Page 989 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.3.3 LCB bus interface periodic control register (LBCYC). LBCYC registers are used to control the cycle time of the LCD bus interface. The cycle time is the duration of one 8-bit data transmission per bus access. LBCYC uses 8-bit memory manipulation instructions for setup. When resetting, the LBCYC register resets to 00H Figure 23-6 LCB bus interface periodic control register (LBCYC Address: 0x40047401...
Page 990 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.3.5 Pin-mode control registers When using the LCD bus interface pins, the control registers for the multiplexed port function (port mode register (PMxx), port register (Pxx), and port mode control register (PMCxx)) must be set. For details, please refer to "2.3.1 Port Mode Register (PMxx)", "2.3.2 Port Register (Pxx)."...
Page 991 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.4 Runtime order This section describes the timing of general operations, and then describes examples of sequential write and read operations. 23.4.1 Timing relationships The following figure shows the general timing when using the 80 pattern. It illustrates the effect of LBCYC and LBWST register settings.
Page 992 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.4.2 LCD bus interface status When the chip pins are configured for use with the LCD data bus interface DB [7:0], the input and output modes of the pins are automatically switched by the LCD module. After the pin is configured as DB[7:0], the pin is in input mode.
Page 993 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.4.3 Write the LCD bus This section describes typical 16-bit and 8-bit write timing for LCD buses. (1). 16-bit write A 16-bit write transfers two 8-bit data to an external LCD controller/driver. Figure 23-9 Write contiguous 16 bits timing (80 mode: LBTCTL.
Page 994 BAT32A2x9 user manual | Chapter 23 LCD bus interface (2). 8-bit write Write 8 bits of data continuously and transfer these 8 bits to an external LCD controller/driver. Figure23-10. 68 mode: LBTCTL. IMD=1) Write consecutive 8bits timings LBWST=5,LBCYC=8,LBCTL. TCIS=0 Description: Timing diagrams are for feature description purposes only and have no association with the actual hardware implementation.
Page 995 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.4.4 Read from the LCD bus Supports reading data in 8-bit or 16-bit format from the LCD bus. The following shows a typical timing of reading 8 bits. (1). 16-bit read The figure below shows a 16 bits read action in 80 mode.
Page 996 BAT32A2x9 user manual | Chapter 23 LCD bus interface (2). 8-bit read The figure below shows the 8 bits read action in 68 mode. Figure 23-12 (68 mode: LBTCTL. IMD=1): Read consecutive 8 bits timing LBWST=4,LBCYC=7,LBCTL. TCIS=0 Description: Timing diagrams are for feature description purposes only and have no association with the actual hardware implementation.
Page 997 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.4.5 Write-read-write timing on the LCD bus shows an example of a write access to the LCD bus followed by a read access and vice versa. In Figure 23-13 80 mode (LBCTL. IMD=0) 8 bits transfer as an example. In 68 mode (LBCTL.
Page 998 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.5 Note for LCD bus interfaces 23.5.1 Write to lbDATA/LBDATAL registers When the LCD data bus is in transit, a write operation to the LBDATAx register may cause a collision of data transfers.
Page 999 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23.6 Example of LCD bus interface transmission 23.6.1 Example of transmission with an external LCD driver Example 1 The BAT32A279 can be used as a master chip to provide a clock for display to the slave chip (LCD driver) via the CLKBUZ0 pin.
Page 1000 BAT32A2x9 user manual | Chapter 23 LCD bus interface 23-22 Connection example 1 LCD driver pins LCD drive function Port name note Used to indicate whether D0 to D7 is data or instructions note Select 1 note Select 2 D0 to D7 8-bit bidirectional data bus DBD0 to DBD7 Mode 80: Read the...

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Cmsemicon BAT32A2 9 Series User Manual

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