Cmsemicon CMS32L051 User Manual

Ultra-low-power 32-bit microcontroller based on the arm cortex-m0+

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CMS32L051 User Manual |Chapter 1 CPU

CMS32L051 User Manual

Ultra-low-power 32-bit microcontroller based on the ARM

Cortex

-M0+

V1.2.2

Please note the following CMS IP policy

*Zhongwei Semiconductor (Shenzhen) Co., Ltd. (hereinafter referred to as the Company) has applied for a patent and enjoys absolute legal

rights and interests. The patent rights related to the Company's MCUs or other products have not been authorized to be licensed, and any

company, organization or individual who infringes the Company's patent rights through improper means will take all possible legal actions to curb

the infringer's improper infringement and recover the losses suffered by the Company as a result of the infringement or the illegal benefits

obtained by the infringer.

＊The name and logo of Zhongwei Semiconductor (Shenzhen) Co., Ltd. are registered trademarks of the Company.

＊The Company reserves the right to further explain the reliability, functionality and design improvements of the products in the data sheet.

However, the Company is not responsible for the use of the Specification Contents. The applications mentioned herein are for illustrative

purposes only and the Company does not warrant and does not represent that these applications can be applied without further modification, nor

does it recommend that its products be used in places that may cause harm to persons due to malfunction or other reasons. The Company's

products are not licensed for lifesaving, life-sustaining devices or systems as critical devices. The Company reserves the right to modify the

product without prior notice, please refer to the official website www.mcu.com.cn for the latest information.

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Summary of Contents for Cmsemicon CMS32L051

Page 1 CMS32L051 User Manual |Chapter 1 CPU CMS32L051 User Manual Ultra-low-power 32-bit microcontroller based on the ARM Cortex -M0+ ® ® V1.2.2 Please note the following CMS IP policy *Zhongwei Semiconductor (Shenzhen) Co., Ltd. (hereinafter referred to as the Company) has applied for a patent and enjoys absolute legal rights and interests.
Page 2: Documentation Instructions
CMS32L051 User Manual |Chapter 1 CPU Documentation Instructions This manual is a technical reference manual for CMS32L051 microcontroller products, and the technical reference manual is an application note on how to use this series of products, including the structure, functional description, and function description of each functional module.
Page 3: Table Of Contents
CMS32L051 User Manual |Chapter 1 CPU Contents Documentation Instructions ...................... 2 Chapter 1 CPU......................14 1.1 Overview ............................. 14 1.2 Cortex-M0+ core features ........................14 1.3 Debugging features ..........................14 1.4 SWD interface pin ..........................16 1.5 ARM reference document ........................17 Chapter 2 Pin Function ....................
Page 4 CMS32L051 User Manual |Chapter 1 CPU 4.3.9 High-speed internal oscillator trim register (HIOTRM) ............... 78 4.3.10 Subsystem clock selection register (SUBCKSEL) ..............79 4.4 System clock oscillation circuit ......................80 4.4.1 X1 oscillation circuit ........................80 4.4.2 XT1 oscillation circuit ........................80 4.4.3...
Page 5 CMS32L051 User Manual |Chapter 1 CPU 5.3.15 Registers for controlling timer input/output pin port functions ..........140 5.4 Basic rules of the universal timer unit ....................141 5.4.1 Basic rules of the multi-channel linkage operation function ............. 141 5.4.2 Basic rules for the 8-bit timer to operate the function (limited to Channel 1 and Channel 3 of Unit 5.5 Operation of the counter ........................
Page 6 CMS32L051 User Manual |Chapter 1 CPU 6.4.3 Example of register setting ....................... 216 6.5 Example of stepper motor control ..................... 217 6.5.1 Example of a hardware connection ..................217 6.5.2 Control method ......................... 218 6.5.3 Example of register setting ....................... 219 Chapter 7 Real-Time Clock ..................
Page 7 CMS32L051 User Manual |Chapter 1 CPU 9.3.1 Clock output select register n (CKSn) ..................253 9.3.2 Registers for controlling the function of the clock output/buzzer output pin port ..... 255 9.4 Operation of clock output/buzzer controller ..................256 9.4.1 Operation of output pin ......................256 9.5 Cautions for clock output/buzzer output control circuitry ..............
Page 8 CMS32L051 User Manual |Chapter 1 CPU Chapter 12 Universal Serial Communication Unit ............295 12.1 Function of universal serial communication unit ................296 12.1.1 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) ......... 296 12.1.2 UART (UART0~UART2) ......................297 12.1.3...
Page 9 CMS32L051 User Manual |Chapter 1 CPU 12.7.2 UART reception ........................422 12.7.3 Calculation of the baud rate ...................... 429 12.7.4 Handling steps when an error occurs during UART (UART0~UART 2) communication ..433 12.8 Operation of LIN communication ...................... 434 12.8.1...
Page 10 CMS32L051 User Manual |Chapter 1 CPU 14.5.3 Designation of transmission direction ..................503 14.5.4 Acknowledge (ACK) ........................504 14.5.5 Stop Conditions......................... 505 14.5.6 Wait ............................506 14.5.7 Release method of wait ......................508 14.5.8 Interrupt request (INTIICAn) generation timing and wait control..........509 14.5.9...
Page 11 CMS32L051 User Manual |Chapter 1 CPU 16.4.3 Repeat pattern .......................... 596 16.4.4 Chain transfer ........................... 599 16.5 Precautions when using DMA ......................601 16.5.1 DMA controls the settings of data and vector tables ..............601 16.5.2 DMA controls the allocation of data areas and DMA vector table areas ........601 16.5.3...
Page 12 CMS32L051 User Manual |Chapter 1 CPU 22.2 Structure of power-on reset circuit ....................645 22.3 Operation of power-on reset circuit ....................645 Chapter 23 Voltage Detection Circuit ................649 23.1 Function of voltage detection circuit ....................649 23.2 Structure of voltage detection circuit ....................650 23.3 Registers for controlling voltage detection circuit ................
Page 13 CMS32L051 User Manual |Chapter 1 CPU 27.3.3 Flash erase control register (FLERMD) ..................697 27.3.4 Flash status register (FLSTS) ....................698 27.3.5 Flash full-chip erase time control register (FLCERCNT) ............698 27.3.6 Flash sector erase time control register (FLSERCNT) ............. 699 27.3.7...
Page 14: Chapter 1 Cpu
CMS32L051 User Manual |Chapter 1 CPU Chapter 1 CPU 1.1 Overview This section briefly introduces the features and debugging features of the ARM Cortex-M0+ core on this product, please refer to the relevant ARM documentation for details. 1.2 Cortex-M0+ core features ⚫...
Page 15 CMS32L051 User Manual |Chapter 1 CPU Debug block diagram of Cortex-M0+ Figure 1-1 MCU debug support Cortex - M0+ debug support Cortex - M0+ System bus core Bus matrix Bridge SWDIO SW - DP AHB - AP SWCLK NVIC DBGMCU Debug AP Note: SWD does not work in deep sleep mode, please debug in active and sleep modes.
Page 16: 1.4 Swd Interface Pin
CMS32L051 User Manual |Chapter 1 CPU 1.4 SWD interface pin The two GPIOs of this product can be used as SWD interface pins, which are present in all packages. Table 1-1 SWD debug port pins SWD port name Debugging capabilities...
Page 17: 1.5 Arm Reference Document
CMS32L051 User Manual |Chapter 1 CPU 1.5 ARM reference document The built-in debugging features in the Cortex®-M0+ kernel is part of the ARM® CoreSight design suite. For related documents, please refer to: Cortex-M0®+ Technical Reference Manual (TRM) ⚫ ARM® debug interface V5 ⚫...
Page 18: Chapter 2 Pin Function
CMS32L051 User Manual |Chapter 2 Pin Function Chapter 2 Pin Function 2.1 Port function Refer to the data sheets for each product family. 2.2 Port multiplexing function Refer to the data sheets for each product family. V1.2.2 www.mcu.com.cn 18 / 703...
Page 19: 2.3 Registers For Controlling Port Functions
CMS32L051 User Manual |Chapter 2 Pin Function 2.3 Registers for controlling port functions The port function is controlled through the following registers. • Port Mode Register (PMxx) • Port Register (Pxx) • Pull-Up Resistor Selection Register (PUxx) • Pull-Down Resistor Selection Register (PDxx) •...
Page 20 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-1 Registers assigned to each product PMxx, Pxx, PSETxx, PCLRxx, PUxx, PDxx, POMxx, PMCxx and their bits (2/2) Bit name port PMxx PSETxx PCLRxx PUxx PDxx POMxx PMCxx Pins Pins Pins Pins...
Page 21: Port Mode Register (Pmxx)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.1 Port mode register (PMxx) When a port is used as a digital channel, this is the register that sets its input/output in bits. After the reset signal is generated, the ports except the P130 port default to the input state. When using a “...
Page 22: Port Register (Pxx)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.2 Port register (Pxx). This is the register that sets the value of the port output latch in bits. Reading this register in input mode gives the pin level, while reading it in output mode gives the value of the port's output latch. After the reset signal is generated, the value of the register becomes “00H”.
Page 23: Port Set Control Register (Psetxx)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.3 Port set control register (PSETxx) This is the register to set the port output latch in bit units. After a reset signal is generated, the value of the register becomes “00H”. Register address = base address + offset address; the base address of the port set control register is 0x40040000, and the offset address is shown in the figure below.
Page 24: Port Clear Control Register (Pclrxx)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.4 Port clear control register (PCLRxx) This is the register to set the port output latch in bit units. After a reset signal is generated, the value of the register becomes “00H”. Register address = base address + offset address; the base address of the port Clearance control register is 0x40040000, and the offset address is shown in the following figure.
Page 25: Pull-Up Resistor Selection Register (Puxx)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.5 Pull-up resistor selection register (PUxx) Selection register for internal pull-up resistors. The internal pull-up resistor can only be used in bits for bits specified by the pull-up resistor select register using the pin using the internal pull-up resistor and the POMmn “0”...
Page 26: Pull-Down Resistor Selection Register (Pdxx)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.6 Pull-down resistor selection register (PDxx) Selection register for internal pull-down resistors. The internal pull-down resistor can only be used in bits for bits specified by the drop-down resistor select register using the pin using the internal pull-down resistor and “0”...
Page 27: Port Output Mode Register (Pomxx)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.7 Port output mode register (POMxx) This is the register that sets the output mode in bits. When communicating serially with external devices with different potentials and simple I2C communication with external devices with different potentials, an N- channel open-drain output mode can be selected for the SDA xx pin.
Page 28: Port Mode Control Register (Pmcxx)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.8 Port mode control register (PMCxx) The PMC register sets the port in bits to be used as a digital input/output or as an analog channel. After the reset signal is generated, P10, P26, P130 are used as digital channels by default (PMC10, PMC26, PMC130 reset value is “0”,), and other ports are used as analog channels by default.
Page 29: Port Output Multiplexing Function Configuration Register (Pxxcfg)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.9 Port output multiplexing function configuration register (PxxCFG) The port output multiplexing configuration register enables the output functions of a subset of peripheral modules to be mapped to any port. Reset value of the port output multiplexing function configuration register is “00H”, in which case the port is the default concurrent function and GPIO function.
Page 30 CMS32L051 User Manual |Chapter 2 Pin Function P130CFG 0x048 P136CFG 0x04e P137CFG 0x04f P140CFG 0x050 P146CFG 0x056 P147CFG 0x057 Figure 2-10 Format of port output multiplexing function configuration register symbol address after reset R/W PxxCFG pxxcfg[3:0] see figure above By configuring the PxxCFG register, it is possible to map 15 concurrent output functions (TO10, TO11, TO12, TO13, SDO00, TxD0, SDO20, TxD2, IrTXD, CLKBUZ0, SCLKO00, SCL00, SCLKO20, SCL20, TxD1) to any port, other than these 15 concurrent outputs can only be mapped to a fixed port.
Page 31 CMS32L051 User Manual |Chapter 2 Pin Function Table2-2 Configuration method for the concurrent output function The feature name Input/output PxxCFP PMCxx PMxx POMxx Remark All analog functions are directed to fixed ports only and are not Analog channel Input/output 4'h0 ×...
Page 32 CMS32L051 User Manual |Chapter 2 Pin Function Configuration Instructions: ➢ When using the port's concurrent output function, the port must be configured in digital mode (PMCxx=0). ➢ When using the port's concurrent output function, the port must be configured in output mode (push- pull or open-drain) (PMxx=0).
Page 33: Port Input Multiplexing Function Configuration Registers
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.10 Port input multiplexing function configuration registers (TI10PCFG, TI11PCFG, TI12PCFG, TI13PCFG, INTP0PCFG, INTP1PCFG , INTP2PCFG, INTP3PCFG, SDI00PCFG, SCLKI00PCFG, SS00PCFG , SDI20PCFG, SCLKI20PCFG, SDAA0PCFG, SCLA0PCFG, RXD1PCFG ) The Port Input Multiplexing Configuration Register enables the mapping of the input functions of peripheral modules to individual ports.
Page 34 CMS32L051 User Manual |Chapter 2 Pin Function The xxPCFG register is used to map redirectable concurrent inputs to any port. Register name Register settings Function 6'h00 Concurrent input does not map to any port 6'h01 Maps to P00 6'h02 Map to P01...
Page 35 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-3 Configuration method of concurrent input function Function name Input/output xxxPCFP[5:0] PMCxx PMxx POMxx Remark All analog functions are directed to fixed ports only Simulation function Input/output × × and are not configurable, Refer to the data sheets...
Page 36 CMS32L051 User Manual |Chapter 2 Pin Function Configuration Instructions: ➢ When using the port's concurrent input function, the port must be configured in digital mode (PMCxx=0). ➢ When using the port's concurrent input function, the port must be configured to input mode (PMxx=1).
Page 37: Spi Port Multiplexing Configuration Register (Spipcfg)
CMS32L051 User Manual |Chapter 2 Pin Function 2.3.11 SPI port multiplexing configuration register (SPIPCFG) The SPI Port multiplexing configuration register (SPIPCFG) enables the SPI communication function to be mapped to three different sets of port combinations. The reset value of the SPI port multiplexing function configuration register is “00H”, and the SPI communication function is not mapped to any port.
Page 38: 2.4 Handling Of Unused Pins
CMS32L051 User Manual |Chapter 2 Pin Function 2.4 Handling of unused pins The treatment of each unused pin is shown in Table 2-5. Table 2-5 Handling of each unused pin Pin name Input/output Recommended connection method when not in use...
Page 39: Register Setting When Using The Multiplexed Function
CMS32L051 User Manual |Chapter 2 Pin Function 2.5 Register setting when using the multiplexed function 2.5.1 Basic idea when using the multiplexed output feature First, for analog pins, the port mode control register (PMCxx) sets whether the pin is used as an analog function or as a digital input/output.
Page 40: Example Of Register Settings Using Port Functions And Multiplexing Functions
CMS32L051 User Manual |Chapter 2 Pin Function 2.5.2 Example of register settings using port functions and multiplexing functions Examples of register settings using the port function and the multiplexing function (48 pin products) are shown in Table Table 2-7to Table 2-17. “×” in the table indicates that the register does not require configuration, and “-”...
Page 41 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-8 Example of register settings when using the P10 to P17 pin functions PxxCFG (Output Features used xxPCFG (Input Multiplexing SPIPCF Multiplexing Configuration remark name Configuration The feature name Input/output Register) Register) input ×...
Page 42 CMS32L051 User Manual |Chapter 2 Pin Function PxxCFG Features used xxPCFG (Input (Output Multiplexing PMCxx PMxx POMxx Multiplexing SPIPCFG remark name Configuration The feature name Input/output Configuration Register) Register) input × × × × × output × P14CFG=4’h0 N-channel ×...
Page 43 CMS32L051 User Manual |Chapter 2 Pin Function 2.3.11 output × × Please refer to P17CFG=4’h0 ≠2’b01 epwmo07 output × 2.5.3 Mappable concurrent Configure Please refer to input × × × × inputs xxPCFG 2.3.9 Mappable concurrent Configure Please refer to ≠2’b01...
Page 44 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-9 Example of register setting when using P20 to P27 pin functions PxxCFG (Output xxPCFG (Input Features used Multiplexing Multiplexing SPIPCF Remark Input/outp name Configuration Configuration The feature name Register) Register) input ×...
Page 45 CMS32L051 User Manual |Chapter 2 Pin Function PxxCFG Features used (Output xxPCFG (Input Multiplexing PMCxx PMxx POMxx Multiplexing SPIPCFG remark Configuration Register) The feature name Input/output Configuration Register) input × × × × × ≠2’b11 output P24CFG=4’h N-channel × ≠2’b11...
Page 46 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-10 Example of register settings when using P30 to P31 pin functions PxxCFG Features used (Output Multiplexin xxPCFG (Input PMCx POMx SPIPCF Multiplexing Configuration remark Input/outp The feature name Configurati Register) Register) input ×...
Page 47 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-11 Example of register setting when using P40 to P41 pin functions PxxCFG Features used (Output PMCx POMx xxPCFG (Input Multiplexing SPIPCF Multiplexing remark Input/outp Configuration Register) The feature name Configuratio n Register) input ×...
Page 48 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-12 Example of register settings when using P50 to P51 pin functions PxxCFG Features used (Output xxPCFG (Input POMx PMCxx Multiplexing Multiplexing SPIPCFG remark The feature name Input/output Configuration Configuration Register) name...
Page 49 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-13 Example of register setting when using P60 to P63 pin functions PxxCFG Features used (Output xxPCFG (Input PMxx POMxx Multiplexing Multiplexing Configuration SPIPCFG remark name The feature name Input/output Configuration Register)
Page 50 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-14 Example of register settings when using the P70 to P75 pin functions PxxCFG Features used (Output PMCx POMx xxPCFG (Input Multiplexing SPIPCF Multiplexing remark Configuration Register) Input/outp The feature name Configuratio...
Page 51 CMS32L051 User Manual |Chapter 2 Pin Function PxxCFG Features used (Output xxPCFG (Input PMxx POMxx Multiplexing Multiplexing Configuration SPIPCFG remark name The feature name Input/output Configuration Register) Register) input × × × × × output × P73CFG=4’h0 N-channel × open-drain ×...
Page 52 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-15 Example of register settings when using P120 to P124 pin functions PxxCFG xxPCFG (Input (Output Multiplexing Features used POMxx Multiplexing SPIPCFG remark Configuration Configuration Register) name Register) Input/out The feature name input ×...
Page 53 CMS32L051 User Manual |Chapter 2 Pin Function open- drain output EXCLKS=0, × × × × × OSCSELS=1 EXCLKS=1, EXCLKS input × × × × × OSCSELS=1 For EXCLKS=0 and Mappable Configure input × × × OSCSELS=0, refer concurrent inputs xxPCFG to 2.3.9...
Page 54 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-16 Example of register settings when using P130, P136, P137 pin functions PxxCFG (Output xxPCFG (Input Features used Multiplexing Multiplexing SPIPC remark name Configuration Configuration The feature name Input/output Register) Register) input ×...
Page 55 CMS32L051 User Manual |Chapter 2 Pin Function Table 2-17 Example of register configuration of using P140, P146, P147 pin function PxxCFG (Output xxPCFG (Input Features used Multiplexing Multiplexing SPIPC remark name Configuration Configuration The feature name Input/output Register) Register) input ×...
Page 56: Epwm Port Configuration Method
CMS32L051 User Manual |Chapter 2 Pin Function 2.5.3 EPWM port configuration method When using the EPWM output control circuit function, the EPWM output pin is fixed and mapped to P10~P17 as follows: The port function Input/output PxxCFP PMCxx PMxx POMxx...
Page 57: Chapter 3 System Structure
CMS32L051 User Manual |Chapter 3 System Structure Chapter 3 System Structure 3.1 Overview This product system consists of the following parts: • 2 AHB bus master: Cortex-M0+ Enhanced DMA • 4 AHB bus slavas: FLASH memory SRAM memory 0 SRAM memory 1...
Page 58: 3.2 System Address Partition
CMS32L051 User Manual |Chapter 3 System Structure 3.2 System address partition Figure 3-2 Schematic diagram of address area partition FFFF_FFFFH reserve E00F_FFFFH Cortex-M0+ specific resource region for peripherals E000_0000H reserve 4005_FFFFH resource region for peripherals 4000_0000H reserve 2000_1FFFH SRAM (Max 8KB)
Page 59 CMS32L051 User Manual |Chapter 3 System Structure Peripheral address assignment Table 3-1 Start addresses of the peripheral's register group Start address Peripheral Remark 0x4000_0000 - 0x4000_4FFF Reserved 0x4000_5000 - 0x4000_5FFF 0x4000_6000 - 0x4000_6FFF Interrupt control 0x4000_7000 - 0x4001_8FFF Reserved 0x4001_9000 - 0x4001_9FFF...
Page 60: Chapter 4 Clock Generation Circuit
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Chapter 4 Clock Generation Circuit The presence or absence of resonator connection pins for master system clock/external clock input pins, resonator connection pins for subsystem clocks/external clock input pins varies depending on the product.
Page 61 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit (3) Low-speed internal oscillator clock (low-speed OCO). Clock oscillation of f =15kHz can be made. You can use the low-speed internal oscillator clock as the system clock. When option byte (000C0H) bit4 (WDTON) or the subsystem clock provides a mode control register (OSMC) of bit4 (WUTMMCK0).
Page 62: 4.2 Structure Of Clock Generation Circuit
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.2 Structure of clock generation circuit The clock generation circuit consists of the following hardware. Table 4-1 Structure of the clock generation circuit item structure Clock operation mode control register (CMC). System clock control registers (CKCs).
Page 63 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-1 Block diagram of clock generation circuit V1.2.2 www.mcu.com.cn 63 / 703...
Page 64 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit remark : X1 clock oscillation frequency : The clock frequency of the high-speed internal oscillator HOCO : The clock frequency of the high-speed internal oscillator : The external master system clock frequency...
Page 65: 4.3 Registers For Controlling Clock Generation Circuit
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3 Registers for controlling clock generation circuit The clock generation circuit is controlled by the following registers. • Clock operation mode control register (CMC) • System clock control registers (CKC) • Clock operation status control register (CSC) •...
Page 66 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-2 Format of clock operating mode control register (CMC Address: 40020400H After reset: 00H Symbol EXCLK OSCSEL EXCLKS Note OSCSELS Note AMPHS1 Note AMPHS0 Note AMPH High speed system clock X1/P121 pins...
Page 67: System Clock Control Register (Ckc)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.2 System clock control register (CKC) This is the register that selects the CPU/peripheral hardware clock and the main system clock. The CKC egister is set via an 8-bit memory operation instruction.
Page 68: Clock Operation Status Control Register (Csc)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.3 Clock operation status control register (CSC) This is a register that controls the operation of the high-speed system clock, the high-speed internal oscillator clock, and the secondary system clock (except for the low-speed internal oscillator clock). Set the CSC register via an 8-bit memory operation instruction.
Page 69: Status Register Of The Oscillation Stabilization Time Counter (Ostc)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.4 Status register of the oscillation stabilization time counter (OSTC) This is the register that indicates the counting status of the oscillation settling time counter of the X1 clock. It is possible to confirm the oscillation settling time of the X1 clock in the following cases.
Page 70 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-5 Format of status register of the oscillation stabilization time counter (OSTC) Address: 40020402H After reset: 00H R Symbol OSTC MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 Oscillation steady-time state...
Page 71: Oscillation Stabilization Time Selection Register (Osts)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.5 Oscillation stabilization time selection register (OSTS) This is the register that selects the oscillation settling time of the X1 clock. If the X1 clock is oscillated, it automatically waits for the time the OSTS register is set after the X1 oscillation circuit runs (MSTOP=0).
Page 72: Peripheral Enable Registers 0, 1 (Per0, Per1)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.6 Peripheral enable registers 0, 1 (PER0, PER1). This is the register that sets the clock that is allowed or disallowed for each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 73 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-7 Format of peripheral enable register 0 (PER0) (2/3) Address: 40020 420H After reset: 00H R/W symbol PER0 IICAEN RTCEN IRDAEN ADCEN SCI1EN SCI0EN TM41EN TM40EN Provides control of the input clock of the serial interface IRDA IRDAEN Stop supplying the input clock.
Page 74 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-7 Format of peripheral enable register 0 (PER0) (3/3) Address: 40020 420H After reset: 00H R/W symbol PER0 IICAEN RTCEN IRDAEN ADCEN SCI1EN SCI0EN TM41EN TM40EN Provides control of the input clock of the general-purpose timer unit 1 TM41EN Stop supplying the input clock.
Page 75 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-8 Format of eripheral enable register 1 (PER1 Address: 4002081AH After reset: 00H R/W symbol PER1 SPIEN DMAEN EPWMEN Provides control of the input clock of the SPI SPIEN Stop supplying the input clock.
Page 76: Subsystem Clock Supply Mode Control Register (Osmc)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.7 Subsystem clock supply mode control register (OSMC) OSMC registers are registers that reduce power consumption by stopping unwanted clock functions. If RTCLPC bit set to “1”, it stops providing clock to peripheral functions other than the real-time clock and 15-bit interval timer in deep sleep mode or sleep mode where the CPU runs on the subsystem clock, thus reducing power consumption.
Page 77: High-Speed Internal Oscillator Frequency Selection Register (Hocodiv)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.8 High-speed internal oscillator frequency selection register (HOCODIV) This is the register that changes the high-speed internal oscillator frequency set by option byte (000C2H). However, the frequency that can be selected varies depending on the value of the FRQSEL 4 and FRQSEL3 bits of the option byte (000C2H).
Page 78: High-Speed Internal Oscillator Trim Register (Hiotrm)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.9 High-speed internal oscillator trim register (HIOTRM) This is a register to correct the accuracy of the high-speed internal oscillator. Self-measurement and accuracy correction of the frequency of the internal oscillator at high speed can be performed using a timer with a high-precision external clock input.
Page 79: Subsystem Clock Selection Register (Subcksel)
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.3.10 Subsystem clock selection register (SUBCKSEL) The SUBCKSEL register is the register that selects the subsystem clock fSUB and the low-speed internal oscillator clock FIL. The SUBCKSEL registers are set via 8-bit memory operation instructions.
Page 80: 4.4 System Clock Oscillation Circuit
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.4 System clock oscillation circuit 4.4.1 X1 oscillation circuit The X1 oscillation circuit is oscillated by a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input, in which case the clock signal must be input to the EXCLK pin.
Page 81 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-14 Example of an external circuit for XT1 oscillation circuit Note When using the X1 oscillation circuit and the XT1 oscillation circuit, in order to avoid the influence of the routing capacitance, etc., the dotted lines in Figure 4-13 and Figure 4-14 must be routed as follows:...
Page 82 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit An example of an incorrect resonator connection is shown in Figure 4-15. Figure 4-15 Example of an incorrect resonator connection (1/2 (a) The routing connecting the circuit is too long (b) the signal lines cross...
Page 83 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-17 Example of an incorrect resonator connection (2/2 (f) Current flows along grounding of oscilation circuit (e) varying high current source close to singal lines (Point A, B, C has difference in electric potential)
Page 84: High-Speed Internal Oscillator
4.4.3 High-speed internal oscillator The CMS32L051 has a built-in high-speed internal oscillator. The frequency can be selected from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz and 2MHz via the option byte (000C2H). The oscillation can be controlled via bit 0 (HIOSTOP) of the Clock Operation Status Control Register (CSC).
Page 85: 4.5 Operation Of Clock Generation Circuit
 CPU/peripheral hardware clock f After the CMS32L051 is released, the CPU starts operating through the output of a high-speed internal oscillator. The operation of the clock generation circuit when the power is turned on is shown in Figure 4-16.
Page 86 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Figure 4-16 Operation of clock generation circuit when the power is turned on at least 10us low limit of working voltage range voltage of power source (V power on reset signal RESETB pin...
Page 87: Clock Control
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.6 Clock control 4.6.1 Example of setting up a high-speed internal oscillator The CPU/peripheral hardware clock (fCLK) must run at the high-speed internal oscillator clock after a reset has been released. The frequency of the high-speed internal oscillator can be selected from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz and 2MHz via 4 bits FRQSEL0 to FRQSEL of the option byte (000C2H).
Page 88 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit [Setting of the Frequency Selection Register (HOCODIV) of the High Speed Internal Oscillator]. Address: 0x40021C20 Symbol HOCODIV2 HOCODIV1 HOCODIV0 HOCODIV Selection of clock frequency for high-speed internal oscillators FRQSEL4=0 FRQSEL4=1 HOCODIV2 HOCODIV1 HOCODIV0...
Page 89: Example Of Setting Up An X1 Oscillation Circuit
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.6.2 Example of setting up an X1 oscillation circuit After the reset is released, the CPU/peripheral hardware clock (f ) must be running at a high-speed internal oscillator clock. Thereafter, if the oscillation clock is changed to X1, the oscillation circuit is set and the oscillation start control is controlled by the oscillation settling time selection register (OSTS), the clock operation mode control register (CMC), and the clock running state control register (CSC).
Page 90: Example Of Setting Up An Xt1 Oscillation Circuit
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.6.3 Example of setting up an XT1 oscillation circuit After the reset is released, the CPU/peripheral hardware clock (f ) must be running at a high-speed internal oscillator clock. Thereafter, if the XT1 oscillation clock is changed, the mode control register (OSMC),...
Page 91: State Transition Graph Of The Cpu Clock
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.6.4 State transition graph of the CPU clock The CPU clock state transfer diagram of this product is shown in Figure 4-17. Figure 4-17 State transfer diagram of the CPU clock Power on...
Page 92 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Examples of CPU clock transfer and SFR register settings are shown in Table 4-3. Table 4-3 Example of CPU transfering and SFR register setting (1/5 (1) After the reset is released (A), the CPU is transferred to the high-speed internal oscillator clock to run (B).
Page 93 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Table 4-3 Example of CPU transfering and SFR register setting (2/5 (4) The CPU shifts from high-speed internal oscillator clock operation (B) to high-speed system clock operation (C). (Order of setting SFR registers...
Page 94 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Table 4-3 Example of CPU transfering and SFR register setting (3/5 (6) The CPU shifts from high-speed system clock operation (C) to high-speed internal oscillator clock operation (B). (Order of setting SFR registers).
Page 95 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Table 4-3 Example of CPU transfering and SFR register setting (4/5 (9) The CPU shifts from subsystem clock operation (D) to high-speed system clock operation (C). (Order of setting SFR registers). The setting flag of the SFR register...
Page 96 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Table 4-3 Example of CPU transfering and SFR register setting (5/5 (11) • The CPU is transferred to deep sleep mode (H) while the high-speed internal oscillator clock is running (B). •...
Page 97: Conditions Before Cpu Clock Transfer And Processing After Transfer
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.6.5 Conditions before CPU clock transfer and processing after transfer The conditions before the CPU clock transfer and the handling after the transfer are as follows. Table4-4 Regarding CPU clock transfer (1/2)
Page 98 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit Table 4-4 Transfers of CPU clocks (2/2) CPU clock Before After Conditions before transfer Post-transfer processing transferring transferring High-speed The high-speed internal oscillator is internal oscillating and the high-speed internal is oscillator...
Page 99: Time Required To Switch Between Cpu Clock And Main System Clock
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.6.6 Time required to switch between CPU clock and main system clock CPU clock switching (master system clock) can be performed by setting bit6 and bit4 (C SS, MCM0) of the system clock control register (CKC).
Page 100: Condition Before The Clock Oscillation Stops
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.6.7 Condition before the clock oscillation stops The register flag settings and conditions before stopping clock oscillation (invalid external clock input) are as follows. Table 4-8 Conditions and flag settings before clock oscillation stops...
Page 101: 4.7 High-Speed Internal Oscillation Correction
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.7 High-speed internal oscillation correction 4.7.1 High-speed internal oscillation self-adjustment function This function measures the frequency of high-speed internal oscillators with the subsystem clock fSUB (32.768KHz) and corrects the frequency accuracy of high-speed internal oscillators fHOCO in real time.
Page 102: Register Description
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.7.2 Register description Table 4-10 is a list of registers used for the high-speed internal oscillation frequency correction function. Table 4-10 Format of high-speed internal vibration frequency correction function registers item structure...
Page 103: Operation Description
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.7.3 Operation description 4.7.3.1 Operation overview The high-speed internal oscillation frequency correction function uses the subsystem clock (fSUB) as a reference to generate a correction period, measure the frequency of high-speed internal oscillation, and correct the frequency accuracy of high-speed internal oscillator in real time.
Page 104 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit （1） Continuous operation mode In continuous operation mode, the high-speed internal oscillator clock frequency correction operation is carried out all the time. The FCMD bit of the HOCOFC register is set to 0, which is a continuous operation mode.
Page 105 CMS32L051 User Manual |Chapter 4 Clock Generation Circuit （2） Interval operation mode In interval operation mode, high-speed internal oscillator clock frequency correction is performed intermittently using timer interrupts, etc. The FCMD bit of the HOCOFC register is set to 1, which is the interval Operation mode.
Page 106: Precautions For Use
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit 4.7.3.2 Operation setup flow The operation start/stop flow when the high-speed internal oscillator clock frequency correction function is used is shown in the following figure. Figure 4-23 Operation mode setting process (example) ＜Continuous action mode＞...
Page 107: Chapter 5 Universal Timer Unit (Timer4)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Chapter 5 Universal Timer Unit (Timer4) This product is equipped with two universal timer units, each containing 4 channels. Note: 1. The label “m” in the following part of this chapter represents the unit number, this product is equipped with two universal timers Timer4, so m=0,1.
Page 108: 5.1 Function Of Universal Timer Unit
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.1 Function of universal timer unit The universal timer unit has the following functions: 5.1.1 Independent channel operation function The independent channel operation function is a function that can use any channel independently regardless of the operation mode of other channels.
Page 109 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) (6) Measurement of the high and low level width of the input signal The high or low width of the input signal is measured by counting on one edge of the input signal at the timer input pin (TImn) and the count value is captured on the other edge.
Page 110: Multi-Channel Linkage Operation Function
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.1.2 Multi-channel linkage operation function The multi-channel linkage operation function is a combination of the master channel (the reference timer for the main control period) and the slave channel (the timer that operates in accordance with the master channel).
Page 111: 8-Bit Timer Operation Function (Limited To Channel 1 And Channel 3 Of Unit 0)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.1.3 8-bit timer operation function (limited to Channel 1 and Channel 3 of Unit 0). The 8-bit timer run function is the ability to use the 16-bit timer channel as two 8-bit timer channels. Only Channel 1 and Channel 3 can be used.
Page 112: 5.2 Structure Of The Universal Timer Unit
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.2 Structure of the universal timer unit The universal timer unit consists of the following hardware. Table 5-1 Structure of the universal timer unit Item Structure counter Timer count register mn (TCRmn).
Page 113 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) The block diagram of the universal timer unit is shown in Figure 5-1. Figure 5-1 Block diagram of universal timer unit 0 Timer clock selection register0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000...
Page 114 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-2 Block diagram of universal timer unit 1 Timer clock selection register0 (TPS1) PRS131 PRS130 PRS121 PRS120 PRS113 PRS112 PRS111 PRS110 PRS103 PRS102 PRS101 PRS100 pre-scaler（f ） peripheral enable register0 TM41EN （PER0）...
Page 115: List Of Universal Timer Unit 0 Registers
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.2.1 List of universal timer unit 0 registers Register base address for unit 0: 0x40041C00 Offset address Register name Bit width Reset value 0x180 TCR00 FFFFH 0x182 TCR01 FFFFH 0x184 TCR02...
Page 116: List Of Universal Timer Unit 1 Registers
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.2.2 List of universal timer unit 1 registers Register base address for unit 1: 0x400420 00 Offset address Register name Bit width Reset value 0x180 TCR10 FFFFH 0x182 TCR11 FFFFH 0x184...
Page 117: Timer Count Register Mn (Tcrmn)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.2.3 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register that counts the clock. Increments or decrements the count in sync with the rising edge of the counting clock.
Page 118: Timer Data Register Mn (Tdrmn)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.2.4 Timer data register mn (TDRmn) This is a 16-bit register that can be used for switching between the capture function and the comparison function. The operating mode is selected by the MDmn3~MDmn0 bits of the timer mode register mn (TMRmn), and the capture function and the comparison function are switched.
Page 119: 5.3 Registers For Controlling General-Purpose Timer Unit
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3 Registers for controlling general-purpose timer unit The registers that control the general-purpose timer unit are as follows: • Peripheral enable register 0 (PER0). • Timer clock selection register m (TPSm).
Page 120: Peripheral Enable Register 0 (Per0)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets the clock to be enabled or disenabled to be supplied to each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 121: Timer Clock Select Register M (Tpsm)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.2 Timer clock select register m (TPSm) TPSm register is a 16-bit register that selects 2 or 4 common operating clocks (CKm0, CKm1, CKm2) available to each channel, CKm3). CKm0 is selected by bits 3 to 0 of the TPSm register, and CKm1 is selected by bits 7 to 4 of the TPSm register.
Page 122 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-7 Format of the timer clock selection register m (TPSm)(1/2) Symbol 15 TPSm Note Selection of the running clock (CKmk) PRSmk3 PRSmk2 PRSmk1 PRSmk0 (k=0, 1) Note that in case of changing the clock selected as f (changing the value of the system clock control register (CKC)), the general-purpose timer unit (TTm=000FH) must be stopped.
Page 123 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-8 Format of the timer clock selection register m (TPSm)(2/2) Symbol TPSm Selection of the running clock PRSm21 PRSm20 Note (CKm2) Selection of the running clock PRSm31 PRSm30 Note (CKm3)
Page 124: Timer Mode Register Mn (Tmrmn)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.3 Timer mode register mn (TMRmn) The TMRmn register is the register for setting the operation mode of channel n. It carries out the selection of the operation clock (f ), the selection of the count clock, the selection of the master/slave,...
Page 125 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-9 Table of timer mode register mns TMRmn) (1/4) Symbol 15 TMRmn (n=2) TERmn Symbol 15 SPLIT TMRmn (n=1, 3) Symbol 15 Note TMRmn (n=0) CKSmn1 CKSmn0 Channel n running clock (f MCK ) selection The timer clock selects the operating clock CKm0 set by register m (TPSm).
Page 126 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-10 Table of timer mode register mns (TMRmn) (2/4) Symbol TMRmn (n=2) TERmn Symbol SPLIT TMRmn (n=1, 3) Symbol Note TMRmn (n=0) (bit11 of TMRmn(n=2)) MASTERmn Choice of independent channel operation / multi-channel linkage operation (slave or master) of...
Page 127 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-11 Table of timer mode register mns (TMRmn) (3/4) Symbol 15 TMRmn (n=2) TERmn Symbol 15 TMRmn SPLIT (n=1, 3) Symbol 15 Note TMRmn (n=0) CISmn1 CISmn0 Valid edge selection for the TImn pin...
Page 128 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-12 Table of timer mode register mns (TMRmn) (4/4) Symbol TMRmn (n=2) TERmn Symbol SPLIT TMRmn (n=1, 3) Symbol Note TMRmn (n=0) The setting of the Corresponding functions The count of TCR...
Page 129: Timer Status Register Mn (Tsrmn)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.4 Timer status register mn (TSRmn) The TSRmn register is a register that represents the overflow status of the channel n counter. The TSRmn register is only valid in capture mode (MDmn3 to MDmn1=010B) and capture & single count mode (MDmn3 to MDmn1=110B).
Page 130: Timer Channel Enable Status Register M (Tem)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.5 Timer channel enable status register m (TEm) TEm registers are registers that represent the enabled or stopped state of each channel timer operation. Each of the TEm registers corresponds to each of the timer channel start register m (TSm) and the timer channel stop register m (TTm).
Page 131: Timer Channel Start Register M (Tsm)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.6 Timer channel start register m (TSm). The TSm register is a trigger register that initializes the timer count register mn (TCRmn) and sets the start of each channel count operation. If each position is “1”, the timer channel allows the corresponding bit of the status register m (TEm) to be set to “1”.
Page 132: Timer Channel Stop Register M (Ttm)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.7 Timer channel stop register m (TTm) The TTm register is the trigger register that sets the count stop for each channel. If each position is “1”, the timer channel allows the corresponding bit of the status register m (TEm) to be cleared “0”.
Page 133: Timer Input-Output Select Register (Tios0)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.8 Timer input-output select register (TIOS0) The TIOS0 register is used to select the input and output of unit 0. Select the timer inputs for Channel 0 and Channel 1 of Unit 0 and the timer output for Channel 2. The TIOS0 register is set via an 8-bit memory operation command.
Page 134: Timer Output Enable Register M (Toem)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.9 Timer output enable register m (TOEm) The TOEm register is a register that sets the enable or disallow timer outputs for each channel. For channel n that enable timer output, the value of the TOmn bit of the timer output register m (TOm) described later cannot be rewritten by software, and the value reflected by the timer output function of the counting operation is from the timer's output pin (TOmn) output.
Page 135: Timer Output Register M (Tom)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.10 Timer output register m (TOm). TOm registers is a buffer register for each channel timer output. The value of this register bit is output from the output pin (TOmn) of each channel timer.
Page 136: Timer Output Level Register M (Tolm)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.11 Timer output level register m (TOLm) The TOLm register is a register that controls the output level of each channel timer. When the timer output (TOEmn=1) is enabled and the multichannel linkage operation function (TOMmn=1) is used, the timing of the set and reset of the timer output signal reflects the inverting setting of each channel n made by this register.
Page 137: Timer Output Mode Register M (Tomm)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.12 Timer output mode register m (TOMm) The TOMm register is a register that controls the output mode of each channel timer. When used as a standalone channel operation function, the corresponding position of the channel used is “0”.
Page 138: Noise Filter Enable Register 1 (Nfen1)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.13 Noise filter enable register 1 (NFEN1) The NFEN1 register sets whether the noise filter is used for the input signal of the timer input pins of each channel of Unit 0. For pins that need to be noise canceled, the corresponding position “1” must be placed for the noise filter to be effective.
Page 139: Noise Filter Enable Register 2 (Nfen2)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.14 Noise filter enable register 2 (NFEN2) The NFEN2 register sets whether the noise filter is used for the input signal of the timer input pins of each channel of Element 1. For pins that need to be noise canceled, the corresponding position “1”...
Page 140: Registers For Controlling Timer Input/Output Pin Port Functions
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.3.15 Registers for controlling timer input/output pin port functions When using a general-purpose timer unit, the input/output pins of timer 0 are multiplexed to a fixed port, and the input/output pins of timer 1 can be arbitrarily configured to ports except RESETB. For details, please refer to “Chapter 2 Pin Functions”.
Page 141: 5.4 Basic Rules Of The Universal Timer Unit
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.4 Basic rules of the universal timer unit 5.4.1 Basic rules of the multi-channel linkage operation function The multi-channel linkage operation function is a combination of the master channel (the reference timer that mainly counts cycles) and the slave channel (the timer that obeys the operation of the master channel), and several rules need to be observed when used.
Page 142 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Example 1 Timer4 Channel Group 1 (multi-channel linked operation function) CK00 Channel 0: Master control Channel 1: Slave Channel Group 2 (multi-channel linked operation function) CK01 Channel 2: Master control Channel group 1 and channel group 2 can Channel 3: Slave be different operation clocks.
Page 143: Basic Rules For The 8-Bit Timer To Operate The Function
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.4.2 Basic rules for the 8-bit timer to operate the function (limited to Channel 1 and Channel 3 of Unit 0). The 8-bit timer operation function is the function of using the channel of the 16-bit timer as the channel of two 8-bit timers.
Page 144: 5.5 Operation Of The Counter
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.5 Operation of the counter 5.5.1 Count clock (f TCLK The Count Clock of the General-Purpose Timer Unit (f ) can select any of the following clocks via TCLK the CCSmn bit of the timer mode register mn (TMRmn).
Page 145 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Selecting the active edge of the TImn pin input signal (CCSmn=1) The Count Clock (fTCLK) is the signal that detects the active edge of the input signal of the TImn pin and synchronizes it with the rising edge of the next fMCK.
Page 146: Start Timing Of Counter
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.5.2 Start timing of counter The timer count register mn (TCRmn) enters the operating enable state by placing the TSmn position bit of the timer channel start register m (TSm). The operation from the counting enabled state to the start of the timer count register mn (TCRmn) is shown in Table 5-5.
Page 147: Operation Of Counter
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.5.3 Operation of counter The following describes the counter operation for each mode. Operation of interval timer mode writing “1” (1) Enter the operating enabled state (TEmn=1) by the TSmn bit. The timer count register mn (TCRmn) holds the initial value until the count clock is generated.
Page 148 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Operation of event counter mode (1) During the operation stop state (TEmn=0), the timer count register mn (TCRmn) maintains the initial value. (2) Enter the operating enabled state (TEmn=1) by writing “1” to the TSmn bit.
Page 149 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Operation of capture mode (interval measurement of input pulses (1) Enter the operating enabled state (TEmn=1) by writing “1” to the TSmn bit. (2) The timer count register mn (TCRmn) maintains the initial value until the count clock is generated.
Page 150 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Operation of single-count mode writing “1” (1) Enter the operating enabled state (TEmn=1) by the TSmn bit. (2) The timer count register mn (TCRmn) holds the initial value until a start trigger signal is generated.
Page 151 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Capture & single count mode operation (measurement of high-level width) the start register m (TSm) is written “1” through the given timer channel to (1) The TSmn bit of enter the operating enable state (TEmn=1).
Page 152: Control Of The Channel Output (Tomn Pin)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.6 Control of the channel output (TOmn pin) 5.6.1 Structure of the TOmn pin output circuit Figure 5-31 Structure of output circuitry Interrupt signal of master TOmn register channel （INTTMmn） interrupt singal of slave...
Page 153: Output Setting Of The Tomn Pin
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.6.2 Output setting of the TOmn pin The steps and state changes from the initial setting of the TOmn output pin to the start of the timer operation are shown below.
Page 154: Cautions For Channel Output Operation
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.6.3 Cautions for channel output operation (1) Change of TOm, TOEm, TOLm, and TOMm register settings during timer operation The operation of the timer (the operation of the timer count register mn (TCRmn) and the timer data register mn (TDRmn)) and the TOmn output circuit are independent of each other.
Page 155 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Start of operation in slave channel output mode (TOMmn=1) (PWM output) In slave channel output mode (TOMmn=1), the effective level depends on the setting of the timer output level register m (TOLmn).
Page 156 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) TOmn pin change regarding slave channel output mode (TOMmn=1) (a) When the setting of the timer output level register m (TOLm) is changed during timer operation If you change the setting of the TOLm register while the timer is running, the setting is valid when the TOmn pin change condition is generated.
Page 157 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-36 Reset/set timing operation status Basic operation timing TCLK INTTMmn master channel internal reset signal TOmn Pin/TOmn swap swap internal reset signal delay 1 clock cycle INTTMmp slave channel internal reset signal...
Page 158: One-Time Operation Of The Tomn Bit
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.6.4 One-time operation of the TOmn bit Like the timer channel start register m (TSm), the timer output register m (TOm) has the set bit (TOmn) for all channels. This allows the TOmn bit of all channels to be operated at once.
Page 159: Timer Interrupt And Tomn Pin Output When Counting Starts
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.6.5 Timer interrupt and TOmn pin output when counting starts In interval timer mode or capture mode, the MDmn0 bit of the timer mode register mn (TMRmn) is the bit that sets whether a timer interrupt is generated at the start of the count.
Page 160: Control Of Timer Input (Timn)
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.7 Control of timer input (TImn) 5.7.1 Structure of TImn pin input circuit The signal from the timer input pin is input to the timer control circuit through the noise filter and edge detection circuitry. For pins that need to be noise removed, the corresponding pin noise filter must be set to active.
Page 161: Noise Filter
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.7.2 Noise filter When the noise filter is invalid, it is only synchronized by the running clock of channel n (f ); When the noise filter is valid, the two clocks are detected to be consistent after synchronization through the operating clock of channel n (f ).
Page 162: Considerations When Manipulating Channel Inputs
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.7.3 Considerations when manipulating channel inputs When set to not use the timer input pin, no operating clock is provided to the noise filter circuit. Therefore, the following wait times are required from the channel operation that is set to use the timer input pin to the channel operation corresponding to the set timer input pin.
Page 163: 5.8 Independent Channel Operation Function Of The Universal Timer Unit
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.8 Independent channel operation function of the universal timer unit 5.8.1 Operates as an interval timer / square wave output Interval timer It can be used as a reference timer to generate INTTMmn (timer interrupt) at regular intervals. The interrupt...
Page 164 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-42 Basic timing example of operation as a spacer timer / square wave output (MDmn0=1) note operational clock Timer count register mn output Tomn Pin (TCRmn) control circuit Timer data register mn...
Page 165 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-44 Example of register setting contents at interval timer/square wave output Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 note MDmn3 MDmn2 MDmn1 TMRmn...
Page 166 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-45 Operation procedure for interval timer/square wave output function Software operation Hardware status The input clock of the timer unit m is in a stopped supply state. (stop providing clock, cannot write registers)
Page 167: Operate As External Event Counter
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.8.2 Operate as external event counter It can be used as an event counter to count the detected valid edges (external events) of the TImn pin input, and if the specified count value is reached, an interrupt is generated. The specified count values can...
Page 168 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-47 Example of register setting content in external event counter mode Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 note MDmn3 MDmn2 MDmn1 TMRmn...
Page 169 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-48 Opeation procedure for external event counter function Software operation Hardware status The input clock of the timer unit m is in a state where supply is stopped. (stop providing clock, cannot write registers)
Page 170: Operates As Frequency Divider
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.8.3 Operates as frequency divider The clock input to the TI00 pin can be divided and used as a divider for the output of the TO00 pin. The divider clock frequency of the TO00 output can be calculated using the following equation: •...
Page 171 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-50 Example of register setting content for operation as a frequency divider Timer mode register 00 (TMR00). CKS001 CKS000 CCS00 STS002 STS001 STS000 CIS001 CIS000 MD000 MD003 MD002 MD001 TMR00...
Page 172 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-51 Opeation procedure for frequency divider function Software operation Hardware state Timer Unit 0 input clock is in stopped state (stop providing clock, not able to write into registers) Timer 4 initial...
Page 173: Operates As Input Pulse Interval Measurement
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.8.4 Operates as input pulse interval measurement Counts can be captured at TImn effective edges and the interval between TImn input pulses can be measured. During the TEmn bit of “1”, the software operation (TSmn=1) can also be set to capture the trigger to capture the count value.
Page 174 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-53 Example of register settings when measuring input pulse intervals Timer mode register mn (TMRmn). Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn operation mode of Channel N...
Page 175 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-54 Operation procedure when entering the pulse interval measurement function software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers)
Page 176: Operation As Input Signal High And Low Level Width Measurement
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.8.5 Operation as input signal high and low level width measurement Notice: When used as a LIN-bus support function, bit1 (ISC1) of the input switch control register (ISC) must be set to “1”, and in the following instructions, RxD0 must be used Instead of TImn.
Page 177 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-55 Example of basic timing for operation as input signal high and low level width measurement TSmn TEmn TImn TCRmn 0000H TDRmn INTTMmn Note 1. m: unit number (m= 0) n: channel number (n=0 ~ 3).
Page 178 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-56 Example of register settings when measuring the high and low level widths of an input signal Timer mode register mn (TMRmn). CKSmn1 Note CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1...
Page 179 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-57 Operation procedure for the input signal high and low level width measurement function software operation hardware state Timer Unit 0 input clock is in stopped state (stop providing clock, not able to write into registers)
Page 180: Operation As Delay Counter
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.8.6 Operation as delay counter The decreasing count can be started by a valid edge detection (external event) at the TImn pin input and the INTTMmn is generated at any set interval (Timer interrupt).
Page 181 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-59 Example of register setting contents for delay counter function Timer mode register mn (TMRmn). CKSmn1 CKSmn0 Note CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn operation mode of Channel N...
Page 182 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-60 Operation procedure for delay counter function software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers) set TM4mEN bit of peripheral enable register 0...
Page 183: 5.9 Multi-Channel Linkage Operation Of The Universal Timer Unit
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.9 Multi-channel linkage operation of the universal timer unit 5.9.1 Operates as single-trigger pulse output function Using 2 channels in pairs, a single-trigger pulse with any delay pulse width can be generated from the input of the TImn pin.
Page 184 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-61 Block diagram of operation as a single-trigger pulse output function master control channel (single counting mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register mn control...
Page 185 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-62 Example of basic timing for operation as a single trigger pulse output function TSmn TEmn TImn master FFFFH control channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp...
Page 186 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-63 Example of register settings for single-trigger pulse output function (master channel) Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn...
Page 187 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-64 Example of register settings (slave channels) for single-trigger pulse output functions Timer mode register mp (TMRmp). Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp0 MDmp3 MDmp2 MDmp1...
Page 188 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-65 Operation procedure for single trigger pulse output function (1/2) software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write...
Page 189 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-66 Operation procedure for single trigger pulse output function (2/2) set TOEmp bit (slave) to '1' (only limit to restart operation). Set TSmn bit)(master control) and TSmp bit(slave) of timer TEmn bit and Temp bit turn into '1' and master channel enter into start channel start register m(TSm) both to '1'.
Page 190: Operates As Pwm Function
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.9.2 Operates as PWM function Using 2 channels in pairs, pulses of any period and duty cycle can be generated. The period and duty cycle of the output pulse can be calculated using the following calculation formula: Pulse Pulse Cycle = {set value of TDRmn (master) +1} ×counting clock period...
Page 191 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-67 Block diagram of operation as a PWM function master control channel (interval Timer mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register mn control interrupt signal...
Page 192 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-68 Example of basic timing for operation as a PWM function TSmn TEmn FFFFH TCRmn 0000H master control channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp slave 0000H channel TDRmp...
Page 193 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-69 Example of register setting contents for PWM function (master channel) Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn Note...
Page 194 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-70 Example of register setting contents for PWM function (slave channel) Timer mode register mp (TMRmp). Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0 TMRmp...
Page 195 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-71 Operation procedure for the PWM function (1/2) Softeware operation Hardware status Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers)
Page 196 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-72 Operation procedure for the PWM function (2/2 set TOEmp bit (slave) to '1' (only limit to restart operation). Set TSmn bit)(master control) and TSmp bit(slave) of timer TEmn bit and TEmp bit both turns into '1'.
Page 197: Operates As Multiplex Pwm Output Function
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) 5.9.3 Operates as multiplex PWM output function This is the ability to perform multiple PWM outputs by extending the PWM functionality and using multiple slave channels for different duty cycles. For example, when 2 slave channels are used in pairs, the period and duty cycle of the output pulse can be calculated using the following formula: Pulse period = { set value of TDRmn (master) +1} ×...
Page 198 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-73 Block diagram of operation as multiple PWM output function (when outputting 2 kinds of PWM) master control channel (interval Timer mode) operational clock Timer count register mn (TCRmn) interrupt...
Page 199 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-74 Block diagram of operation as multiple PWM output function (when outputting 2 kinds of PWM) TSmn TEmn FFFFH TCRmn 0000H master channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp...
Page 200 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Note 1. m: Unit number (m= 0,1) n: master channel number (n=0). p: slave channel number q: slave channel number n ＜ p ＜ q ≤ 3 (p and q are integers greater than n) 2.
Page 201 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-75 Example of register setting contents for multiple PWM output function (master channel) (a) Timer mode register mn (TMRmn). CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1...
Page 202 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-76 Example of register setting contents for multiple PWM output function (slave channel) (when outputting 2 types of PWM) Timer mode registers mp mq (TMRmp, TMRmq). Note CKSmp1 CKSmp0 CCSmp...
Page 203 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-77 Operation procedure for multiple PWM output function (in case of 2 PWM outputs) (1/2) software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers)
Page 204 CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4) Figure 5-78 Operation procedure for multiple PWM output function (in case of 2 PWM outputs) (2/2) (only during restart operation, TOEmp bit and TOEmq bit (slave) will set to '1'). Set TSmn bit(master), TSmp bit and TSmq bit (slave) of timer Start operation channel start register m(TSm) all set to '1' at the same time.
Page 205: Chapter 6 Function Of Epwm Output Control Circuit
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit Chapter 6 Function of EPWM Output Control Circuit Using the PWM output function of Timer, one DC motor or two stepper motors can be controlled. The output can be truncated by truncating the source CMP0 output, the INTP0 input, and the EVENTC event. The software allows you to select from four outputs: Hi-Z output, low output, high output, and anti-truncation output during forced truncation.
Page 206: 6.2 Registers For Controlling Epwm Output Control Circuit
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.2 Registers for controlling EPWM output control circuit The real-time output control circuit is controlled by the following registers. ⚫ Peripheral enable register 0 (PER1 ⚫ EPWM nput source selection register (EPWMSRC ⚫...
Page 207: Peripheral Enable Register 1 (Per1)
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.2.1 Peripheral enable register 1 (PER1). The PER1 register is a register that sets the clock that allows or disables clocking each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 208: Epwm Force Truncated Input Selection Register (Epwmstc)
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit EPWM force truncated input selection register (EPWMSTC) 6.2.4 The EPWMSTC register makes the selection of the input source forced truncation. The EPWMSTC register is set via 8-bit memory operation instructions.
Page 209: Epwm Force Truncated Output Selection Register (Epwmstl)
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit EPWM force truncated output selection register (EPWMSTL 6.2.5 The output state of the EPWMO terminal when the EPWMSTL register is forcibly truncated. The EPWMSTL registers are set via 16-bit memory operation instructions.
Page 210 CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.2.7 Control registers for the port function of the EPWM output pins When using the EPWM output, the control register (Port Mode Register (PMxx, PMCxx)) for the port function multiplexed with the EPWM output pin (EPWMOn pin) must be set. For details, refer to “2.3.1 Port Mode Register (PMxx)”.
Page 211: 6.3 Operation Of Epwm Output Control Circuit
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.3 Operation of EPWM output control circuit 6.3.1 Initial setup The timer waveform selects the TAU output (TO01, TO03) as the source clock through the EPWSRC register. The positive or inverting phase of the timer waveform can be fixed by setting the EPWMCTL register.
Page 212: Normal Operation
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.3.2 Normal operation Depending on the register settings, four output data can be selected, namely forward waveform output, inverted waveform output, low level output, and high-level output. The EPWMCTL registers can be changed at runtime.
Page 213 CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit Figure 6-9 Timing diagram for generation and release of INTP0 truncation (HS_SEL=0, REL_SEL=0) clk_epwm timer_tout3 intp0 Generate forced truncation signal Software release HI-Z EPWMO Note: Short pulses may be generated when switching from “normal operation” to “Hi-Z”, “fixed low” or “fixed high” during forced cutoff caused by the cutoff signal INTP0, or when returning to the forced cutoff state by immediate release.
Page 214: 6.4 Control Example Of Brushless Dc Motor
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.4 Control example of brushless DC motor The following is an example of using the EPWM control function to control a brushless DC motor (hereinafter referred to as a BLDC motor).
Page 215: Control Timing Of Three-Phase Brushless Dc Motors
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.4.2 Control timing of three-phase brushless DC motors Figure 6-11 Control timing of a three-phase brushless DC motor carrier Hall a Hall b Hall c V1.2.2 www.mcu.com.cn 215 / 703...
Page 216: Example Of Register Setting
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.4.3 Example of register setting In this example, the EPWM source selection registers (EPWMSRC) and EPWM control registers (EPWMCTL) are initialised to simultaneously output a waveform of positive rotation from EPWM00 to EPWM05 to the BLDC motor.
Page 217: 6.5 Example Of Stepper Motor Control
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.5 Example of stepper motor control The following is an example of using eight real-time outputs to control two 2-phase stepper motors. 6.5.1 Example of a hardware connection An example of a hardware connection to control two stepper motors is shown in Fig. 6-12.
Page 218: Control Method
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.5.2 Control method The stepper motor is rotated, reversed or stopped in two-phase excitation mode by using eight EPWMOs. Control the rotation speed via Timer's PWM mode. In this example, Timer's CH0 and CH1 are used for the control of stepper motor 1, CH2 and CH3 are used for the control of stepper motor 2.
Page 219: Example Of Register Setting
CMS32L051 User Manual |Chapter 6 Function of EPWM Output Control Circuit 6.5.3 Example of register setting Table 6-5 Example of setting the register that controls the stepper motor State Setting value of EPWMSRC Setting value of EPWMCTL ① 0x00 0x4400 ②...
Page 220: Chapter 7 Real-Time Clock
CMS32L051 User Manual |Chapter 7 Real-Time Clock Chapter 7 Real-Time Clock 7.1 Function of real-time clock The real-time clock has the following functions. • Hold counters for years, months, weeks, days, hours, minutes, and seconds, up to 99 years. • Fixed cycle interrupt function (period: 0.5 seconds, 1 second, 1 minute, 1 hour, day, 1 month).
Page 221 CMS32L051 User Manual |Chapter 7 Real-Time Clock Figure 7-1 Block diagram of real-time clock real time clock control register 1 real time clock control register 0 secondary system provide mode control register (OSMC) alarm week alarm hour alarm minute register...
Page 222: 7.3 Registers For Controlling Real-Time Clock
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3 Registers for controlling real-time clock The real-time clock is controlled by the following registers. • Peripheral enable register 0 (PER0). • Real-time clock selection register (RTCCL). • Real-time clock control register0 (RTCC0).
Page 223: Peripheral Enable Register 0 (Per0)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.1 Peripheral enable register 0 (PER0). The PER0 register is the register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 224: Real-Time Clock Selection Register (Rtccl)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.2 Real-time clock selection register (RTCCL) The real-time clock and the count clock (fRTC) of the 15-bit interval timer can be selected via RTCCL. Figure 7-3 Format of real-time clock selection register (RTCCL)
Page 225: Real-Time Clock Control Register0 (Rtcc0)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.3 Real-time clock control register0 (RTCC0) This is an 8-bit register that sets the start or stop of operation of the real-time clock, control of the RTC1HZ pin, 12/24-hour system, and fixed-cycle interrupt function.
Page 226: Real-Time Clock Control Register1 (Rtcc1)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.4 Real-time clock control register1 (RTCC1) This is the 8-bit register that controls the alarm interrupt function and the counter waits. The RTCC1 register is set via an 8-bit memory operation command. After the reset signal is generated, the value of this register becomes “00H”.
Page 227 CMS32L051 User Manual |Chapter 7 Real-Time Clock Figure 7-5 Format of real-time clock control register 1 (RTCC1) (2/2) RIFG Fixed-period interrupt status flag No fixed-cycle interruptions are generated. A fixed-cycle interruption is generated. This is a status flag that indicates a fixed-cycle interruption. This flag is “1” when a fixed-period interrupt occurs.
Page 228: Clock Error Correction Register (Subcud)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.5 Clock error correction register (SUBCUD) This is a register that can correct clock speed with high accuracy by changing the overflow value (reference value: 7FFFH) from the internal counter (16 bits) to the second count register (SEC).
Page 229: Second Count Register (Sec)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.6 Second count register (SEC) This is an 8-bit register that represents the second count value from 0 to 59 (decimal). Increment counting is performed by overflow of the internal counter (16-bit). At write time, data is first written to the buffer and to the counter after up to 2 FRTC clocks. The decimal 00 to 59 must be set in BCD code.
Page 230: Hour Count Register (Hour)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.8 Hour count register (HOUR). This is an 8-bit register that represents the hour count value in 00 ~ 23 or 01 ~ 12, 21 ~ 32 (decimal). Incremental counting is performed by means of the overflow of the minute counter.
Page 231 CMS32L051 User Manual |Chapter 7 Real-Time Clock The relationship between the config value of the AMPM bit, the value of the hour count register (HOUR), and the time is shown in Table 7-2. Table 7-2 Representation of the time bits...
Page 232: Day Count Register (Day)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.9 Day count register (DAY) This is an 8-bit register that represents the daily count value from 1 to 31 (decimal). The count is incremented by the overflow of the hour counter. The counter performs the following counts.
Page 233: Week Count Register (Week)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.10 Week count Register (WEEK) This is an 8-bit register that represents the day of the week count value from 0 to 6 (decimal). Increment counting synchronized with the day counter. At write time, data is first written to the buffer and to the counter after up to 2 f clocks.
Page 234: Month Count Register (Month)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.11 Month count register (MONTH) This is an 8-bit register that represents the monthly count value from 1 to 12 (decimal). The count is incremented by the overflow of the day counter. At write time, data is first written to the buffer and to the counter after up to 2 fRTC clocks. Overflow of the day count register is ignored during the write operation and set to a write value.
Page 235: Alarm Minute Register (Alarmwm)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.13 Alarm minute register (ALARMWM) This is the register that sets the alarm for minutes. The ALARMWM register is set via an 8-bit memory operation command. After the reset signal is generated, the value of this register becomes “00H”.
Page 236: Alarm Week Register (Alarmww)
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.3.15 Alarm week register (ALARMWW) This is the register that sets the alarm for the week. The ALARMWW register is set via an 8-bit memory operation command. After the reset signal is generated, the value of this register becomes “00H”.
Page 237: Operation Of Real-Time Clock
CMS32L051 User Manual |Chapter 7 Real-Time Clock Operation of real-time clock 7.4.1 Start of real-time clock operation Figure 7-17 Steps to start the operation of the real time clock start configure to provide Note1 RTCEN=1 input clock RTCE=0 configure to stop counting 。...
Page 238: Shifting To Sleep Mode After Starting Operation
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.4.2 Shifting to sleep mode after starting operation To transfer to sleep (including deep sleep) mode immediately after the RTCE set to “1”, one of the following treatments must be performed. However, after the RTCE set to “1” is taken, these processing is not required if you want to move to sleep mode after an INTRTC interrupt occurs.
Page 239: Read And Write To The Real-Time Clock Counter
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.4.3 Read and write to the real-time clock counter Read or write the counter after setting “1” to RWAIT first. Set RWAIT to “0” after completion of reading or writing the counter. Figure 7-19...
Page 240 CMS32L051 User Manual |Chapter 7 Real-Time Clock Figure 7-20 Read operation steps of the real-time clock counter Start configure as SEC~Year counter RWAIT=1 stop operating, enter into read/ write mode of counter. confirm counter wait state RWST=1? 设定SEC Write SEC...
Page 241: Alarm Setting For Real-Time Clock
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.4.4 Alarm setting for real-time clock You must first set the WALE to “0” (the alarm is not working) and then set the alarm time. Figure 7-21 Alarm setting steps Start WALE=0 alarm alignment operation invalid...
Page 242: 1Hz Output Of The Real-Time Clock
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.4.5 1Hz output of the real-time clock Figure 7-22 Steps for setting 1Hz output Start RTCE=0 configure to stop counting 设定SEC Configure Port Pxx=1'b0,PMxx=1'b0 RCLOE1=1 allow RTC1HZ pin output (1Hz). RTCE=1 configure start counting...
Page 243: Example Of Clock Error Correction For A Real-Time Clock
CMS32L051 User Manual |Chapter 7 Real-Time Clock 7.4.6 Example of clock error correction for a real-time clock Clock fast and slow correction can be performed with high accuracy by setting the clock error correction register. An example of the calculation method for correcting values The correction value when correcting the count value of the internal counter (16-bit) can be calculated using the following calculation formula.
Page 244 CMS32L051 User Manual |Chapter 7 Real-Time Clock Correction examples Example of correcting from 32767.4Hz to 32768Hz (32767.4Hz+18.3ppm). [Measurement of oscillation frequency] When the clock error correction register (SUBCUD) is the initial value (“0000H”), the oscillation frequency of each product is measured by outputting a signal of approximately 1Hz from the RTC1HZ pin.
Page 245: Chapter 8 15-Bit Interval Timer
CMS32L051 User Manual |Chapter 8 15-Bit Interval Timer Chapter 8 15-Bit Interval Timer 8.1 Function of 15-bit interval timer Interrupts (INTITs) are generated at any pre-set interval and can be used to wake up from deep sleep mode. 8.2 Structure of 15-bit interval timer The 15-bit interval timer consists of the following hardware.
Page 246: 8.3 Registers For Controlling 15-Bit Interval Timer
CMS32L051 User Manual |Chapter 8 15-Bit Interval Timer 8.3 Registers for controlling 15-bit interval timer The 15-bit interval timer is controlled by the following registers. • Peripheral enable register 0 (PER0). • Real-time clock selection register (RTCCL). • 15-bit interval timer control register (ITMC) 8.3.1...
Page 247: Real-Time Clock Selection Register (Rtccl)
CMS32L051 User Manual |Chapter 8 15-Bit Interval Timer 8.3.2 Real-time clock selection register (RTCCL) The real-time clock and the count clock (f RTC) of the 15-bit interval timer can be selected via RTCCL Figure 8-3 Format of real-rime clock selection register (RTCCL)
Page 248: 15-Bit Interval Timer Control Register (Itmc)
CMS32L051 User Manual |Chapter 8 15-Bit Interval Timer 8.3.3 15-bit interval timer control register (ITMC) This is the register that sets the start and stop of operation of the 15-bit interval timer and the comparison value. The ITMC registers are set via 16-bit memory operation instructions.
Page 249: 8.4 15-Bit Interval Timer Operation
CMS32L051 User Manual |Chapter 8 15-Bit Interval Timer 8.4 15-bit interval timer operation 8.4.1 15-bit interval timer operation timing Runs as a 15-bit interval timer for repeated interrupt requests (INTITs) at intervals set by ITCMP14 RINTE set to “1”, the 15-bit counter starts counting.
Page 250: Start Of Count Operation And Re-Enter To Sleep Mode After Returned From Sleep Mode
CMS32L051 User Manual |Chapter 8 15-Bit Interval Timer 8.4.2 Start of count operation and re-enter to sleep mode after returned from sleep mode After returning from sleep mode, if you want to transfer the RINTE set to “1” and transfer it to sleep mode again, you must confirm that the RENTE bit is reflected after the RINTE set to “1”, or at least pass after the...
Page 251: Chapter 9 Clock Output/Buzzer Output Controller
CMS32L051 User Manual |Chapter 9 Clock output/Buzzer Output Controller Chapter 9 Clock output/Buzzer Output Controller Note: The following sections in this chapter are mainly for 48-pin products. 9.1 Functions of clock output/buzzer output controller The clock output is the function of the output to the clock of the peripheral IC, and the buzzer output is the function of the square wave of the output buzzer frequency.
Page 252 CMS32L051 User Manual |Chapter 9 Clock output/Buzzer Output Controller Figure 9-1 Block diagram of clock output/buzzer output controller Internal Bus clock output selection register 1(CKS1) PCLOE1 CSEL1 CCS12 CCS11 CCS10 pre-scaler MAIN PCLOE1 MAIN MAIN clock/buzzer Pxx/PCLBUZ1 MAIN MAIN control circuit...
Page 253: 9.2 Structure Of Clock Output/Buzzer Output Controller
CMS32L051 User Manual |Chapter 9 Clock output/Buzzer Output Controller 9.2 Structure of clock output/buzzer output controller The clock output/buzzer output controller consist of the following hardware. Table 9-1 Structure of clock output/buzzer output controller Item Structure Clock output select register n (CKSn).
Page 254 CMS32L051 User Manual |Chapter 9 Clock output/Buzzer Output Controller Figure 9-2 Format of clock output selection register n (CKSn) Address: 0x40040FA5 (CKS0), 0x40040FA6 (CKS1) After reset: 00HR/W Symbol PCRead 0 CHerselfLn CCSn2 CCSn1 CCSn0 CKSn CLKBUZn pin output enable/disable specification PCLOEn Disable output (default).
Page 255 CMS32L051 User Manual |Chapter 9 Clock output/Buzzer Output Controller 9.3.2 Registers for controlling the function of the clock output/buzzer output pin port This product can multiplex the clock output/buzzer output function CLKBUZ0 to any port except RESETB, and CLKBUZ1 can be multiplexed to P15. When using the clock output/buzzer output function, the port multiplexing function configuration register (Pxx CFG), port register (Pxx), port mode register (PMxx), and port mode control register (PMCxx) must be set.
Page 256: 9.4 Operation Of Clock Output/Buzzer Controller
CMS32L051 User Manual |Chapter 9 Clock output/Buzzer Output Controller 9.4 Operation of clock output/buzzer controller It can be selected with 1 pin as clock output or buzzer output. The CLKBUZ0 pin outputs the clock/buzzer selected by clock output select register 0 (CKS0).
Page 257: Chapter 10 Watchdog Timer
CMS32L051 User Manual |Chapter 10 Watchdog Timer Chapter 10 Watchdog Timer 10.1 Function of watchdog timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates with a low-speed internal oscillator clock (f A watchdog timer is used to detect a program that is out of control.
Page 258 CMS32L051 User Manual |Chapter 10 Watchdog Timer Figure 10-1 Block diagram of watchdog timer interval time control circuit option bytes (000C0H) interval time (count value overflow time x3/4 WDTINT +1/2fIL) option bytes (000C0H) WDCS2~WDCS0 interval clock overflow signal counter input...
Page 259: Registers For Controlling Watchdog Timer
CMS32L051 User Manual |Chapter 10 Watchdog Timer 10.3 Registers for controlling watchdog timer Control the watchdog timer through the watchdog timer enable register (WDTE). 10.3.1 Watchdog timer enable register (WDTE) By writing “ACH” to the WDTE register, clear the counter for the watchdog timer and restart the count.
Page 260: Lockup Control Register (Lockctl)And Its Protection Register (Prcr)
CMS32L051 User Manual |Chapter 10 Watchdog Timer 10.3.2 LOCKUP control register (LOCKCTL)and its protection register (PRCR) The LOCKCTL register is the configuration register for whether the Cortex-M0+ LockUp feature causes the watchdog timer to run, and the PRCR is its write-protected register.
Page 261: Operation Of The Watchdog Timer
CMS32L051 User Manual |Chapter 10 Watchdog Timer 10.4 Operation of the watchdog timer 10.4.1 Operational control of the watchdog timer When using the watchdog timer, set the following via option bytes (000C0H): • The bit4 (WDTON) of option byte (000C0H) must be set to “1” to enable the watchdog timer's count to run (after the reset is released, the counter starts running) (see Section 1 Chapter 26 Option Byte for details).
Page 262: Watchdog Timer Overflow Time Setting
CMS32L051 User Manual |Chapter 10 Watchdog Timer 10.4.2 Watchdog timer overflow time setting Set the overflow time of the watchdog timer by option bytes (000C0H) bit3~1 (WDCS2~WDCS0). In the event of an overflow, an internal reset signal is generated. If the window opens before the overflow time, the allowed register for the watchdog timer is given (WDTE) writes “ACH”, clears the count and restarts the count.
Page 263: Setting Window Open Period Of Watchdog Timer
CMS32L051 User Manual |Chapter 10 Watchdog Timer 10.4.3 Setting window open period of watchdog timer Set the watchdog timer window open by option bytes (000C0H) bit6 bit5 (WINDOW1, WINDOW0). The window is summarized as follows: If you write “ACH” to the enable register (WDTE) of the watchdog timer while the window is open, the •...
Page 264: Setting Watchdog Timer Interval Interruption
CMS32L051 User Manual |Chapter 10 Watchdog Timer 10.4.4 Setting watchdog timer interval interruption Interval interrupt (INTWDTI) can be generated when 75% +1/2f of the overflow time is reached by setting bit7 (WDTINT) of option byte (000C0H). Table 10-5 Setting of watchdog timer interval interrupt...
Page 265: A/D Converter
CMS32L051 User Manual |Chapter 11 A/D Converter Chapter 11 A/D Converter The number of analog input channels for A/D converters varies by product, and detailed pins refer to the corresponding product data sheet. Number 32-pin 40 pins 44-pin 48 pins...
Page 266 CMS32L051 User Manual |Chapter 11 A/D Converter Figure11-1 Block diagram of A/D converter selector selector digital port control Note: Please refer to 0 for the selection of analog input channel ANIx V1.2.2 www.mcu.com.cn 266 / 703...
Page 267: Control Registers Of A/D Converter
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2 Control registers of A/D converter The registers that control the A/D converter are as follows: Register base address: CSC_BASE=4002_0420H; ADC_BASE=4004_5000H; PORT_BASE=4004_0000H Register name Register description Reset value Register address PER0 Peripheral enable register 0...
Page 268: Peripheral Enable Register 0 (Per0)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets the clock to be enable or disable to be supplied to each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 269: A/D Converter Mode Register 0 (Adm0)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2.2 A/D converter mode register 0 (ADM0) A register for setting the A/D conversion clock, conversion start, or stop. The ADM0 register is set with 8- bit memory operation instructions. After the reset signal is generated, the value of this register becomes “00H”.
Page 270 CMS32L051 User Manual |Chapter 11 A/D Converter Table11-1 Configuration of ADCS and ADCE bits A/D conversion operation ADCS ADCE Transition stop Transition standby Disable settings. Transition run Table11-2 Setting and clearing conditions for ADCS bits A/D conversion mode Set condition...
Page 271 CMS32L051 User Manual |Chapter 11 A/D Converter Figure11-4 Diagram of using various modes of A/D ADCS write ADCS Auto clear to zero while A/D write conversion completes software trigger mode Note1 (ADCS) conversion stops conversion idle conversion ongoing conversion idle...
Page 272 CMS32L051 User Manual |Chapter 11 A/D Converter Table 11-3 A/D conversion time (1/2) (1) No A/D power stabilization wait time (software trigger mode/hardware trigger no wait mode). Note 2 12-bit resolution conversion time A/D converter A/D sampling time Convert mode register 0...
Page 273 CMS32L051 User Manual |Chapter 11 A/D Converter Table11-4 A/D conversion times (2/2) Note 1 (2) There is an A/D power stabilization wait time (hardware triggered wait mode A/D converter A/D sampling time A/D power A/D power supply Convert mode register 0...
Page 274: A/D Converter Mode Register 1 (Adm1)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2.3 A/D converter mode register 1 (ADM1) This is the register that sets the A/D conversion mode. The ADM1 register is set via 8-bit memory operation instructions. After the reset signal is generated, the value of this register becomes “00H”.
Page 275: A/D Converter Mode Register 2 (Adm2)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2.4 A/D converter mode register 2 (ADM2) The ADM2 register is set by 8-bit memory operation instructions. After the reset signal is generated, the value of this register becomes “00H”. Figure11-6 Format of A/D converter mode register 2 (ADM2) (1/3)
Page 276: A/D Converter Trigger Mode Register (Adtrg)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2.5 A/D converter trigger mode register (ADTRG) This is the register that sets the A/D conversion trigger mode and the hardware trigger signal. The AD TRG register is set via an 8-bit memory operation command.
Page 277: Analog Input Channel Specification Register (Ads)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2.6 Analog input channel specification register (ADS) This is the register that specifies the analog voltage input channel to be A/D converted. The ADS registers are set with 8-bit memory operating instructions. After the reset signal is generated, the value of this register becomes “00H”.
Page 278 CMS32L051 User Manual |Chapter 11 A/D Converter ○ Scan mode (ADM1. ADMD=1) Analog input channels ADISS ADS3 ADS2 ADS1 ADS0 Scan 0 Scan 1 Scan 2 Scan 3 ANI0 ANI1 ANI2 ANI3 ANI1 ANI2 ANI3 ANI4 ANI2 ANI3 ANI4 ANI5...
Page 279: 12-Bit A/D Conversion Result Register (Adcr)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2.7 12-bit A/D conversion result register (ADCR) This is a 16-bit register that holds the results of the A/D conversion, and this register is readable only. Whenever the A/D conversion ends, the conversion result notes are loaded from the successive approximation register (SAR).
Page 280: 8-Bit A/D Conversion Result Register (Adcri)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.2.8 8-bit A/D conversion result register (ADCRI) This is an 8-bit register that holds the results of the A/D conversion, holding a high 8-bit note with 12-bit resolution. The ADCRH register is read through an 8-bit memory operation instruction.
Page 281: A/D Converter Sampling Time Extension Control Register (Adsmpwait)
CMS32L051 User Manual |Chapter 11 A/D Converter Figure11-13 Format of Conversion result comparison lower limit setting register (ADLL) Reset value: 00H R/W ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLL0 ADLL Note 1 Only the 12-bit A/D is converted to the high 8-bit and ADUL registers of the result register (ADCR) and the ADLL Registers are compared.
Page 282: Input Voltage And Conversion Results
CMS32L051 User Manual |Chapter 11 A/D Converter 11.3 Input voltage and conversion results The analog input voltage at the analog input pin (ANIx) and the theoretical A/D conversion result (12-bit A/D Conversion Result Register (ADCR)) are related by the following expressions.
Page 283: Operation Mode Of A/D Converter
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4 Operation mode of A/D converter The operation of each mode of the A/D converter is as follows. For the setting steps for each mode, refer “ Setup Flow Diagram of 11.5 A/D Converter“.
Page 284: Software Trigger Mode (Select Mode, Single Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.2 Software trigger mode (select mode, single conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” and enters the A/D transition standby state.
Page 285: Software Trigger Mode (Scan Mode, Continuous Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.3 Software trigger mode (scan mode, continuous conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” and enters the A/D transition standby state.
Page 286: Software Trigger Mode (Scan Mode, Single Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.4 Software trigger mode (scan mode, single conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” and enters the A/D transition standby state.
Page 287: Hardware Triggered No-Wait Mode (Select Mode, Continuous Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.5 Hardware triggered no-wait mode (select mode, continuous conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” and enters the A/D transition standby state.
Page 288: Hardware Trigger No-Wait Mode (Select Mode, Single Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.6 Hardware trigger no-wait mode (select mode, single conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” and enters the A/D transition standby state.
Page 289: Hardware Trigger No-Wait Mode (Scan Mode, Continuous Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.7 Hardware trigger no-wait mode (scan mode, continuous conversion mode ) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” and enters the A/D transition standby state.
Page 290: Hardware Trigger No-Wait Mode (Scan Mode, Single Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.8 Hardware trigger no-wait mode (scan mode, single conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” and enters the A/D transition standby state.
Page 291: Hardware Trigger Wait Mode (Select Mode, Continuous Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.9 Hardware trigger wait mode (select mode, continuous conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” into a hardware-triggered standby state.
Page 292: Hardware Trigger Wait Mode (Select Mode, Single Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.10 Hardware trigger wait mode (select mode, single conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” into a hardware-triggered standby state.
Page 293: Hardware Trigger Wait Mode (Scan Mode, Continuous Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.11 Hardware trigger wait mode (scan mode, continuous conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” into a hardware-triggered standby state.
Page 294: Hardware Trigger Wait Mode (Scan Mode, Single Conversion Mode)
CMS32L051 User Manual |Chapter 11 A/D Converter 11.4.12 Hardware trigger wait mode (scan mode, single conversion mode) (1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is “1” into a hardware-triggered standby state.
Page 295: Chapter 12 Universal Serial Communication Unit
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Chapter 12 Universal Serial Communication Unit Unit 0 of the universal serial communication unit has 4 serial channels and unit 1 has 2 serial channels, each channel can achieve 3-wire serial (SSPI), UART, and simple I C communication function.
Page 296: Function Of Universal Serial Communication Unit
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.1 Function of universal serial communication unit The characteristics of each serial interface supported by this product are as follows. 12.1.1 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Data is transmitted and received synchronously with the serial clock (SCLK) output by the master device.
Page 297: Uart (Uart0~Uart2)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.1.2 UART (UART0~UART2) This is a function that communicates asynchronously through a total of two lines: serial data transmission (TxD) and serial data reception (RxD). Using these two communication lines, data is sent and received asynchronously (using the internal baud rate) with other communicating parties in a data frame (consisting of a start bit, data, parity bit, and stop bit).
Page 298: Simple I 2 C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.1.3 Simple I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) This is a function that synchronizes clock communication with multiple devices through a total of 2 lines of serial clock (SCL) and serial data (SDA). Because this simple I2C is designed for single communication with EEPROM, flash memory, A/D converters, etc., it is only used as a master device.
Page 299: Structure Of Universal Serial Communication Unit
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.2 Structure of universal serial communication unit The universal serial communication unit consists of the following hardware. Table 12-1 Structure of universal serial communication unit Project Structure Note 1 Shift register...
Page 300 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit A block diagram of universal serial communication unit 0 is shown in Figure 12-1. Figure 12-1 Diagram of universal serial communication unit 0 noise filter enable serial output register (SO0) regsiter 0 (NFEN0)
Page 301 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit A block diagram of a universal serial communication unit 1 is shown in Figure 12-2. Figure 12-2 Diagram of universal serial communication unit 1 serial output register 1(SO1) noise filter enable...
Page 302: Shift Register
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.2.1 Shift register This is a 9-bit register that converts parallel and serial to and from each other. Note 1 For UART communication at 9 bits of data length, use 9 bits (bit0 to 8) .
Page 303 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-3 Format of serial data register mn (SDRmn) (mn=00 10, 11) Address: 40041310H (SDR00), 40041312H (SDR01) after reset: 0000HR/W 40041748H(SDR10), 4004174AH(SDR11) 40041211H (in the case of SDR00) 40041310H (in the case of SDR00).
Page 304: Registers For Controlling Universal Serial Communication Unit
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3 Registers for controlling universal serial communication unit The registers that control the universal serial communication unit are as follows: • Peripheral enable register 0 (PER0). • Serial clock selection register m (SPSm).
Page 305: Peripheral Enable Register 0 (Per0)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.1 Peripheral enable register 0 (PER0). The PER0 register is a register that sets the clock to be allowed or disallowed to be supplied to each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 306: Serial Clock Select Register M (Spsm)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that selects two common operating clocks (CKm0, CKm1) available to each channel. CKm1 is selected by bit7~4 of the SPSm register, and by bit3~0 CKm0.
Page 307: Serial Mode Register Mn (Smrmn)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets the channel n operating mode, selects the operating clock (f ), specifies whether the serial clock (f...
Page 308 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-7 Format of serial mode register mn (SMRmn) (2/2) Address: 40041110H(SMR00)~40041116H(SMR03) After reset: 0020HR/W 40041550H(SMR10)~40041552H(SMR11) Symbol 15 SMRmn 0 STS 0 SISm 0 MD Note1 Note1 Note1 Level inversion control of received data for channel n in UART mode SISmn0 Detect the falling edge as the starting bit.
Page 309: Serial Communication Operation Setting Register Mn (Scrmn)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.4 Serial communication operation setting register mn (SCRmn) The SCRmn register is the communication operation setting register for channel n, which sets the data transmit and receive modes, data and clock phases, whether to mask error signals, parity bits, start bits, stop bits, and data length.
Page 310 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-8 Format of serial communication operation setting register mn (SCRmn) (2/2) Address: 40041118H(SCR00)~4004111EH(SCR03) After reset: 0087HR/W 40041558H(SCR10)~4004155AH(SCR13) Symbol 15 SCRmn 0 EOC 0 SLC 1 DlSm Note1 Note2 Setting of parity bits in UART mode...
Page 311: Serial Data Register Mn (Sdrmn)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.5 Serial data register mn (SDRmn). The SDRmn register is the data register (16 bits) that channel n transmits and receives. The bits 8 to 0 (low 9 bits) of SDR00 and SDR01 or bits 7 to 0 (low 8 bits) of SDR02, SDR03, SDR10 and...
Page 312 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit be greater than or equal to “0000001B”. 4. When the operation is stopped (SEmn=0), it is forbidden to override SDRmn [7:0] via 8-bit memory operation instructions (otherwise, SDRmn [15:9] is all cleared “0”).
Page 313: Serial Flag Clear Trigger Register Mn (Sirmn)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.6 Serial flag clear trigger register mn (SIRmn) This is the trigger register used to clear each error flag of channel n. If you set the various (FECTmn, PECTmn, OVCTmn) to “1”, the corresponding bits (FEFmn, PEFmn, OVFmn) clear “0”.
Page 314: Serial Status Register Mn (Ssrmn)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.7 Serial status register mn (SSRmn) The SSRmn register indicates the communication status of channel n and the occurrence of errors. The errors represented are frame errors, parity errors, and overflow errors. The SSRmn register is read via 16-bit memory operation instructions.
Page 315 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-11 Format of serial status register mn (SSRmn) (2/2) Address: 40041100H (SSR00) ~ 40041106H (SSR03) After reset: 0000HR 40041540H(SSR10)~40041542H(SSR11) Symbol 15 SSRmn 0 TSF FEFm Note1 Note1 FEFmn Detection flag for channel n frame errors No errors occurred.
Page 316: Serial Channel Start Register M (Ssm)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that sets the communication/start count enabled for each channel. If you write “1” to you (SSmn), set the corresponding bit (SEmn) of the serial channel enable status register m (SEmn) to “1”...
Page 317: Serial Channel Stop Register M (Stm)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.9 Serial channel stop register m (STm) The STm register is a trigger register that sets the communication/stop count allowed for each channel. If a "1" is written to each bit (STmn), the corresponding bit (SEmn) in the serial channel enable status register m (SEm) is cleared to "0"...
Page 318: Serial Channel Enable Status Register M (Sem)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.10 Serial channel enable status register m (SEm) SEm registers are used to confirm the allowed or stopped status of serial transmits and receivings for each channel. If "1" is written to each of the serial start allow register m (SSm), the corresponding bit is set to "1". If you write "1"...
Page 319: Serial Output Enable Register M(Soem)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.11 Serial output enable register m(SOEm) SOEm register settings allow or stop the output of serial communication for each channel. For channel n that allows serial output, the value of the SOmn bit of the serial output register m (SOm) described later cannot be rewritten by software, and the value reflected by the communication operation is output from the serial data output pin.
Page 320: Serial Output Register M (Som)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.12 Serial output register m (SOm) The SOm register is a buffer register for the serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.
Page 321: Serial Output Level Register M (Solm)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.13 Serial output level register m (SOLm) The SOLm register is a register that sets the inverting of the data output level of each channel. This register can be set only in UART mode. In SSPI mode and Simplified I C mode, the corresponding bit must be set to "0".
Page 322 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit When UART is transmitted, an example of the level inversion of the transmitted data is shown in Figure 12-18. Figure 12-18 Example of level inversion of transmitted data (a)Non-inverting output (SOLmn=0)
Page 323: Input Switching Control Register (Isc)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.14 Input switching control register (ISC) When implementing LIN-bus communication via UART0, the ISC1 and ISC0 bits of the ISC register are used for the coordination of external interrupts and timer array units. If bit0 is set to “1”, the input signal from the serial data input (RxD0) pin is selected as the input for the external interrupt (INTP0) and therefore passes The INTP0 interrupt detects the wake-up signal.
Page 324: Noise Filter Enable Register 0 (Nfen0)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.15 Noise filter enable register 0 (NFEN0) The NFEN0 register sets whether the noise filter is used for the input signal of the serial data input pins of each channel. C communication, the corresponding bit must be “0” to invalidate the For pins used for SSPI or simple I noise filter.
Page 325: Registers Controlling The Function Of The Serial Input/Output Pin Port
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.3.16 Registers controlling the function of the serial input/output pin port When using a general-purpose serial communication unit, the control registers for the multiplexed port function (Port Mode Register (PMxx), Port Multiplexing Function Configuration Register (PxxCFG), Port Output Mode Register (POMxx), and Port Mode Control Register must be set (PMCxx)).
Page 326: Operation Stop Mode
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.4 Operation stop mode Each serial interface of the universal serial communication unit has a stop-and-run mode. Serial communication is not possible in run-stop mode, so power consumption can be reduced. In addition, pins for the serial interface can be used as port functions in run-stop mode.
Page 327: Stopping The Operation By Channels
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.4.2 Stopping the operation by channels Stop-operation by channel is set by each of the following registers. Figure 12-22 Setting of each register when stopping the operation by channels (a) Serial channel stop register m (STm)... This is the register that sets the communication/stop count allowed for each channel.
Page 328: 3-Wire Serial I/O (Sspi00, Sspi01, Sspi10, Sspi11, Sspi20, Sspi21) Communication
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.5 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication This is a clock synchronization communication function implemented by a total of 3 wires of serial clock (SCLK) and serial data (SDI and SDO).
Page 329: Master Transmission
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.5.1 Master transmission Master transmission refers to the operation of this product output transmission clock and sending data to other devices. 3-wire serial SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21 Object Channel 0 of...
Page 330 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Register setting Figure 12-23 3 wire serial I/O(SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register settings when the master is transmitted (a) serial mode register mn (SMRmn) channel n operational clock （f ）...
Page 331 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-24 Initial setup step of the master transmission initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 332 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-25 Master send abort step termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 333 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-26 Restart step of the master transmission restart configuration starts. wait till commuication target (slave (mandatory) slave device ready? device) stops or communication ends via Configure port register and port...
Page 334 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (3) Process flow (single-transmit mode Figure 12-27 Timing diagram of the main transmission (single-pass transmission mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn transmit data1 transmit data2 transmit data3 SDRmn SCLKp pin...
Page 335 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-28 Flow of master transmission (single transmit mode) SSPI communication starts relevant initial configuration, refer to diagram 19~26 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag (via...
Page 336 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (4) Process flow (continuous transmit mode). Figure 12-29 Timing diagram of the master transmission (continuous transmit mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn transmit transmit data2 transmit data3 SDRmn data1...
Page 337 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-30 Flowchart of the master transmission (continuous transmit mode) SSPI communication starts relevant initial configuration, refer to diagram 19~34 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag...
Page 338: Master Reception
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.5.2 Master reception Master reception refers to the operation of this product output transmission clock and receiving data from other devices. 3-wire serial I/O SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21 Channel 0 of...
Page 339 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Register setting Figure 12-31 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register setting content when the master receives (a) serial mode register mn(SMRmn) channel n operational clock （f ）...
Page 340 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-32 Initial setup step of master reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 341 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-34 Restart step of master reception restart configuration starts. wait till commuication target (slave device) stops or communication ends (mandatory) slave device ready? via Configure port register and port mode...
Page 342 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (3) Process flow (single receive mode). Figure 12-35 Timing diagram of the master receive (single receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception2 data reception3 data reception1 SDRmn...
Page 343 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-36 Flowchart of the master receive (single receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19~34 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear...
Page 344 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow (continuous receive mode). Figure 12-37 Timing diagram of the master receive (continuous receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception3 SDRmn data reception2 virtual data virtual data...
Page 345 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-38 Flowchart of the master receive (continuous receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19~34(select buffer empty interrupt) SCI initial configuration For the received data, set the storage area and the...
Page 346: Master Transmission And Reception
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.5.3 Master transmission and reception The transmission and reception of the master refers to the operation of the output transmission clock of this product and the transmission and reception of data with other devices.
Page 347 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-39 3-wire serial I/O(SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register settings when the master transmits and receives (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 348 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-40 Initial setup step of master transmit and receive initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 349 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-42 Restart steps of the master transmit and receive restart configuration starts. wait till commuication target (slave device) (mandatory) slave device ready? stops or communication ends via Configure port register and port mode...
Page 350 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Processing flow (single send and receive mode). Figure 12-43 Timing diagram of the master transmit and receive (single-pass transmit and receive mode) (Type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception1...
Page 351 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-44 Flowchart of the master transmit and receive (single transmit and receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19~42 (select transmission SCI initial configuration completion interrupt)
Page 352 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow (continuous send and receive mode). Figure 12-45 Timing diagram of the main transmit and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception 3...
Page 353 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-46 Flowchart of the master transmit and receive (continuous transmit and receive mode) SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19~42(select buffer empty interrupt) regarding transmit data, configure storage region and...
Page 354: Slave Transmission
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.5.4 Slave transmission Slave transmission refers to the operation of the CMS32L051 microcontroller to send data to other devices in the state of transmitting the clock from the input of other devices. 3-wire serial I/O...
Page 355 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-47 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register settings at the time of slave transmission (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 356 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-48 Initial setup steps for slave sending initial configuration starts release universal serial communication configure PER0 register unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 357 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-50 Restart setup step of slave sending restart configuration starts. wait till commuication target (master device) master device stops or communication ends (mandatory) preparation complete? via Configure port register and port mode...
Page 358 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (3) Process flow (single-send mode Figure 12-51 Timing diagram of slave send (single-send mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 SCLKp pin transmit data1...
Page 359 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-52 Flowchart of slave send (single send mode) SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19~50 (select transmission completion interrupt) regarding transmit data, configure storage region and...
Page 360 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow (continuous send mode) Figure 12-53 Timing diagram of slave transmit (continuous transmit mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1 SCLKp pin...
Page 361 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-54 Flowchart of slave sending (continuous transmission mode). SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19~50 (select buffer empty interrupt) regarding transmit data, configure storage region and data...
Page 362: Slave Receiving
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.5.5 Slave receiving Slave reception refers to the operation of this product to receive data from other devices in the state of transmitting clocks from other devices. 3-wire serial SSPI00 SSPI01...
Page 363 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-55 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register settings at slave receive (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 364 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation steps Figure 12-56 Initial setup step of slave reception initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 365 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-58 Restart setup step of slave reception restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 366 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (3) Processing flow (single-receive mode). Figure 12-59 Timing diagram of slave receive (single-receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception3 SDRmn data reception1 data reception2 Read Read Read...
Page 367 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-60 Flowchart of slave receive (single-receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19-58 SCI initial configuration (select transmission completion interrupt) configure receiving data storage region, clear receiving...
Page 368: Slave Send And Receive
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.5.6 Slave send and receive Slave transmit and receive refers to the operation of the microcontroller and other devices of this product to transmit and receive data in the state of transmitting clocks from other devices.
Page 369 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Register setting Figure 12-61 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Example of register settings when slave transmit and receive (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 370 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-62 Initial setup steps for slave send and receive initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 371 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-63 Stop steps for slave send and receive termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 372 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-64 Restarts setup steps of slave send and receive restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 373 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Processing flow (single send and receive mode) Figure 12-65 Timing diagram of slave transmit and receive (single transmit and receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception1 data reception2...
Page 374 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-66 Flowchart of slave send and receive (single send and receive mode). SSPI communication starts relevant initial configuration, refer to diagram 19-64 SCI initial configuration (select transmission completion interrupt) regarding transmit and receive data, configure storage...
Page 375 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow (continuous send and receive mode). Figure 12-67 Timing diagram of slave transmit and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception 3...
Page 376 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-68 Flowchart of Slave transmit and receive (continuous transmit and receive mode) SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-64(select buffer empty interrupt) regarding transmit data, configure storage region and data count (via...
Page 377: Calculation Of Transmit Clock Frequency
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.5.7 Calculation of transmit clock frequency 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication transmission clock frequency can be calculated using the following calculation equations. (1) Master device (transmit clock frequency) = {the operating clock of the object channel...
Page 378 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Table 12-2 Selection of 3-wire serial I/O running clocks SMRmn Note Runing clock (f SPSm register register =32MHz operation CKSmn 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.63kHz...
Page 379: Procedure For Handling Errors During 3-Wire Serial I/O Communication (Sspi00, Sspi01, Sspi10, Sspi11, Sspi20, Sspi21)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Procedure for handling errors during 3-wire serial I/O communication (SSPI00, 12.5.8 SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) In 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20 SSPI21), the processing steps when an error occurs during communication are shown in Figure 12-69.
Page 380: Operation Of Clock-Synchronous Serial Communication With Slave Selection Input Function
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.6 Operation of clock-synchronous serial communication with slave selection input function Channel 0 of SCI0 is the channel that supports clock-synchronous serial communication with the slave select input function. [Transmit and receive data] •...
Page 381 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit By using the slave select input function, one master device can be connected to multiple slave devices for communication. The master device outputs a slave selection signal to the slave device (1) of the communication object, and each slave device determines whether it is selected as a communication object and controls the output of the SDO pin.
Page 382 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-71 Slave timing diagram of the select input function DAPmn=0 configure transmit data BFFmn TSFmn SSEmn SCLKmn (CKPmn=0) SDImn sample timing sequence SDOmn SSmn During SSmn is high, even on the falling edge of the SCKmn (serial clock), no transmission occurs, and no sampling of received data synchronized with the rising edge is taken.
Page 383: Slave Transmission
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.6.1 Slave transmission Slave transmission refers to the operation of this product to send data to other devices in the state of input transmission clock from other devices. Slave Select Input function...
Page 384 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-72 Example of register settings when slave select input function (SSPI00) slave transmits (1/2) (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n...
Page 385 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-72 Example of register settings when slave select input function (SSPI00) slave transmits (2/2) (f) serial channel start register m (SSm) Only set bit of target channel to 1. (g) input switch control register (ISC) This is controlled by SS00 pin of SSPI00 slave channel (channel 0 of unit 0).
Page 386 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-73 Initial setup steps for slave sending initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 387 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-74 Stop step of slave send termination configuration starts if there are ongoing data transmission, TSFmn = 0？ (selection) then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 388 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-75 Restart setup step of slave sending restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 389 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow (single send mode) Figure 12-76 Timing diagram of slave send (single send mode) (Type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn transmit data1 SDRmn transmit data 2 transmit data 3...
Page 390 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-77 Flowchart of slave send (single send mode). SSPI communication starts relevant intial configure, please refer to diagram 19-79 (select transmission SCI initial configuration completion interrupt) regarding transmit data, configure storage region and data...
Page 391 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow (continuous send mode) Figure 12-78 Timing diagram of slave transmit (continuous transmit mode) (type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1 SCLKp pin...
Page 392 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-79 Flowchart of slave transmission (continuous send mode) SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19-79 (select buffer empty interrupt) regarding transmit data, configure storage region...
Page 393: Slave Receiving
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.6.2 Slave receiving Slave reception refers to the operation of this product to receive data from other devices in the state of transmitting clocks from other devices. Slave Select Input function...
Page 394 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Register setting Figure 12-80 Select Input Function SSPI00) Example of register setting content when slave receive (1/2). (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n...
Page 395 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-81 Select Input Function SSPI00) Example of register settings when slave receive (2/2). (f) serial channel start register m (SSm) Only set bit of target channel to 1. (g) input switch control register (ISC) This is controlled by SS00 pin of SSPI00 slave channel (channel 0 of unit 0).
Page 396 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-82 Initial setup step of slave reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 397 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-84 Restart setup step of slave reception restart configuration starts. wait till commuication target (master device) master device stops or communication ends preparation complete? (mandatory) via Configure port register and port mode...
Page 398 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Processing flow (single receive mode). Figure 12-85 Timing diagram of slave receive (single receive mode) (Type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3 SDRmn transmit data1 transmit data 2...
Page 399 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-86 Flowchart of slave receive (single receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19-58 SCI initial configuration (select transmission completion interrupt) configure receiving data storage region, clear receiving...
Page 400: Slave Transmission And Reception
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.6.3 Slave transmission and reception Slave transmit and receive refers to the operation of this product and other devices for data transmission and reception in the state of transmitting clocks from other devices.
Page 401 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-87 Slave select input function (SSPI00) Example of register setting content when slave send and receive (1/2) (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 402 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-87 Slave select input function (SSPI00) Example of register setting content when slave send and receive (2/2) (f) serial channel start register m (SSm) Only set bit of target channel to 1.
Page 403 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-88 Initial setup steps for slave send and receive initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 404 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-89 Stop steps of slave send and receive termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 405 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-90 Restart setup steps of Slave send and receive restart configuration starts. wait till commuication target (master device) master device preparation (mandatory) stops or communication ends complete? via Configure port register and port mode...
Page 406 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Processing flow (single send and receive mode) Figure 12-91 Timing diagram of slave transmit and receive (single-send and receive mode) (Type 1: DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception1 data reception2...
Page 407 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-92 Flowchart of slave send and receive (single send and receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19-93 SCI initial configuration (select transmission completion interrupt) regarding transmit and receive data, configure storage...
Page 408 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (4) Process flow (continuous send and receive mode) Figure 12-93 Timing diagram of slave transmit and receive (continuous transmit and receive mode) (type 1: DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3...
Page 409 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-94 Flowchart of slave send and receive (continuous send and receive mode) SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-93(select buffer empty interrupt) regarding transmit data, configure storage region and...
Page 410: Calculation Of The Transmit Clock Frequency
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.6.4 Calculation of the transmit clock frequency The transmit clock frequency of the slave select input function (SSPI00) communication can be calculated using the following calculation formula. Slave device Note (transmit clock frequency) = {Serial clock (SCLK) frequency provided by the master device} [Hz].
Page 411: Procedure For Handling Errors During Clock-Synchronous Serial Communication With The Slave Selection Input Function
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.6.5 Procedure for handling errors during clock-synchronous serial communication with the slave selection input function The processing steps when an error occurs during clock-synchronous serial communication that is subordinate to the select input function are shown in Figure 12-95.
Page 412: Operation Of Uart (Uart0~Uart2) Communication
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.7 Operation of UART (UART0~UART2) communication This is a function that communicates asynchronously through a total of two lines: serial data transmission (TxD) and serial data reception (RxD). Using these two communication lines, data that are transmitted and received asynchronously (using internal baud rate) with other communicating parties in data frames (consisting of start bits, data, parity bits, and stop bits) are used to send and receive data.
Page 413: Uart Transmission
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.7.1 UART transmission UART transmission is the operation of the microcontroller of this product to send data asynchronously to other devices. An even number of the 2 channels used by the UART are used for UART sending.
Page 414 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-96 Example of register settings when UART is sent by UART (UART0~UART 2) (1/2) (a) serial mode register mn (SMRmn) channel n operational clock (fMCK) channel n interrupt source...
Page 415 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-96 Example of register settings when UART is sent by UART (UART0~UART 2) (2/2) (e) serial output register m (SOm) Only configure bit of target channel Note Note 0: serial data output value as "0"...
Page 416 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-97 Initial setup steps for UART sending initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 417 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-99 Restart setup steps for UART sending restart configuration starts. wait till commuication target (slave device) stops or (mandatory) Ready to communicate? communication ends The data output of the target channel is disabled by...
Page 418 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow (single-send mode Figure 12-100 UART transmission (single-send mode) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2 transmit data3 shift register mn...
Page 419 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-101 UART transmission (single-send mode) UART communication starts relevant initial configuration, refer to diagram 19-102 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag...
Page 420 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow (continuous send mode) Figure 12 12-102 UART transmission (continuous send mode) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2 transmit data3...
Page 421 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-103 UART transmission (continuous send mode) UART communication starts relevant initial configuration, refer to diagram 19-102 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication...
Page 422: Uart Reception
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.7.2 UART reception UART reception is the operation of other devices of this product's microcontroller to receive data asynchronously. An odd number of the 2 channels used by the UART are used for UART reception. However, the SMR registers for both odd and even channels need to be set.
Page 423 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-104 Example of register settings when UART is received by UART (UART0~UART2) (1/2) (a) serial mode register mn (SMRmn) 0: normal receiving channel n operational clock (fMCK)
Page 424 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-104 Example of register settings when UART is received by UART (UART0~UART 2) (2/2) (e) serial output register m (SOm) Not used in this mode. (f) serial output enable register m (SOEm) Not used in this mode.
Page 425 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-105 Initial setup steps for UART reception initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 426 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-107 Restart setup step for UART reception restart configuration starts. wait till commuication target stops or commuication target (mandatory) communication ends ready？ re-configure when modifing operational clock modify SPSm register...
Page 427 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow Figure 12-108 diagram of UART reception SSmn STmn SEmn transmit data 3 SDRmn transmit data1 transmit data 2 RxDq pin data reception 3 data reception 1 data reception 2...
Page 428 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-109 UART reception UART communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-110 (select transmission completion interrupt) configure reciving data storage region and communication data count (via software, any configured internal RAM storage configure receiving data region, receiving data pointer and communication data count).
Page 429: Calculation Of The Baud Rate
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.7.3 Calculation of the baud rate (1) Formula for calculating the baud rate The baud rate of UART (UART0~UART2) communication can be calculated using the following formula: ) frequency}× (SDRmn[15:9]+ 1) ÷2[bps] (baud rate) = {Clock of the object channel Note The SDRmn [15:9] of the serial data register mn (SDRmn) is disabled from being set to “0000000B”...
Page 430 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Table 12-4 Selection of the UART operating clock SMRmn Note Run clock (f SPSm register register =32MHz operation CKSmn 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.63kHz 7.81kHz...
Page 431 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (2) Baud rate error at the time of sending The baud rate error of UART (UART0~UART2) communication can be calculated using the following calculation formula, and the baud rate of the sender must be set within the Enable range of the receiver's baud rate.
Page 432 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (3) Enable range of the baud rate at reception The baud rate tolerance range of UART (UART0~UART2) communication reception can be calculated using the following calculation formula, and the baud rate of the sender must be set within the acceptor's baud rate tolerance.
Page 433: Handling Steps When An Error Occurs During Uart (Uart0~Uart 2) Communication
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.7.4 Handling steps when an error occurs during UART (UART0~UART 2) communication The handling steps when an error occurs during UART (UART0~UART 2) communication are shown in Figure 12-111and Figure 12-112.
Page 434: Operation Of Lin Communication
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.8 Operation of LIN communication 12.8.1 LIN transmission In UART sending, UART0 supports LIN communication. LIN sends channel using unit 0. UART UART0 UART1 UART2 LIN communication support — — Object channel Channel 0 for SCI0 —...
Page 435 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit LIN is short for Local Interconnect Network and is a low-speed (1 to 20kbps) serial communication protocol to reduce the cost of automotive networks. LIN communication is a single master communication, a master device can connect up to 15 slave devices.
Page 436 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-114 LIN sending hardware operation(reference) LIN transmit start Transmit wakeup signal frame (80H->TxD0) generate wakeup signal frame 8 bit Transmit wakeup TxD0 TSF00=0? Note signal frame transmit data wait for transmit result stop UART0(1->ST00 bit)
Page 437: Lin Reception
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.8.2 LIN reception In UART reception, UART0 supports LIN communication. The LIN receives the channel 1 of the Unit0. UART UART0 UART1 UART2 UART3 LIN communication support — — — Channel 1 of SCI0 Object channel —...
Page 438 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit A summary of the receive operation of LIN is shown in Figure 12-115. Figure 12-115 Receive operation of LIN wake up signal frame interval field sync field identifier data field data field...
Page 439 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-116 LIN reception LIN Bus signal state and hardware operation. LIN communication starts wake up signal frame wait for wake up signal INTTM03 occurs? RxD0 pin NOTE. frame. edge detection...
Page 440 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit The port structure diagram for LIN receive operation is shown in Figure 12-117. The wake-up signal sent by the LIN master is received by the edge detection of the external interrupt (INTP0).
Page 441 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit The peripheral functions used for LIN communication operation are summarized as follows: < Peripheral Features Used > • External Interrupt (INTP0): Detection of wake-up signals Purpose: Detects the edge of the wake-up signal and the start of communication.
Page 442: Simplified I C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21) Communication Operation
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.9 Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication operation This is a function that synchronizes clock communication with multiple devices through a total of 2 lines of serial clock (SCL) and serial data (SDA). Because this simplified I C is designed for single communication with EEPROM, flash memory, A/D converters, etc., it is only used as a master device.
Page 443: Address Segment Transmission
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.9.1 Address segment transmission Address segment sending is the first transmission operation to specifically specify the transmitting object (slave device) that is the first to occur during I C communication. After generating the start condition, the address (7 bits) and the transmission direction (1 bit) are sent as 1 frame.
Page 444 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-118 Example of register setting contents when sending address segments of Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (a) serial mode register mn (SMRmn) Note1 Note1 channel n operational clock （fMCK）...
Page 445 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Operation Steps Figure 12-119 Initial setup step for the address segment transmission initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 446 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (3) Process flow Figure 12-120 Timing diagram of the address segment transmission address field transmit SDLr output bit operation SDAr output Somn bit operation address SDAr input shift operation shift register mn...
Page 447 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-121 Flowchart of the address segment transmission address field transmit Please refer to the previous flow chart of initial configuration initial settings set SOmn bit to '0'. set SOmn bit to '0'.
Page 448: Data Transmission
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.9.2 Data transmission Data transmission is the operation of transmitting data to the transmission object (slave device) after the address segment is transmitted. A stop condition is generated after all data is sent to the object slave and the bus is released.
Page 449 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Register setting Figure12-122 Example of register setting contents for simple I2C data transmission (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 450 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow Figure 12-123 Timing diagram of data transmission transmit data 1 SDLr output SDAr output SDAr input shift register mn shift operation Figure 12-124 Flow chart of data transmission address field transmit completes.
Page 451: Data Reception
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.9.3 Data reception Data reception is the operation of receiving data from a transmitting object (slave device) after sending an address segment. A stop condition is generated after receiving all data from an object slave and the bus is released.
Page 452 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit (1) Register setting Figure 12-125 Example of register setting contents for simple I2C data reception (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 453 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Process flow Figure 12-126 Timing diagram of data reception (a) Start of receiving data virtual data(FFH) receiving data SCLr output SDAr output SDAr input shift register mn shift operation (b) The case in which the last data is received...
Page 454 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Figure 12-127 Flowchart of data reception address field transmit completes. data reception stop operation in order to modify set STmn bit to 1. SCRmn register cofigure channel operation mode to write "0" to TXEmn bit, write "1" to RXEmn bit receiving set SSmn bit to 1.
Page 455: Generation Of Stop Condition
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.9.4 Generation of stop condition After all data is sent and received with the object slave, a stop condition is created and the bus is released. (1) Process flow Figure 12-128 Timing diagram for generating stop condition...
Page 456: Calculation Of The Transfer Rate
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.9.5 Calculation of the transfer rate Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) The transmission rate of communication can be calculated using the following calculation formula. (Transfer Rate) = {Running clock (f MCK ) frequency of the object channel}× (SDRmn[15:9]+ 1) ÷2 Notice Setting SDRmn[15:9] to “0000000B”...
Page 457 CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit Table 12-5 Simplified I C Running Clock Selection SMRmn Note Running clock (f SPSm register register =32MHz operation CKSmn 32MHz 16MHz 8MHz 4MHz 2MHz 1MHz 500kHz 250kHz 125kHz 62.5kHz 31.25kHz 15.63kHz...
Page 458: Processing Steps When An Error Occurs In A Simple I2C (Iic00, Iic01, Iic10, Iic11, Iic20, Iic21)
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit 12.9.6 Processing steps when an error occurs in a simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication process The processing steps when an error occurs during a simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication are shown in Figure 12-130 and Figure 12-131.
Page 459: Chapter 13 Serial Interface Spi
CMS32L051 User Manual |Chapter 13 Serial Interface SPI Chapter 13 Serial Interface SPI 13.1 Serial interface SPI function The serial interface SPI has the following two modes. (1) Operation Stop mode This is a mode used when no serial transfer is taking place, which reduces power consumption.
Page 460: Registers For Controlling Spi
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.3 Registers for controlling SPI is controlled through the following registers The serial interface SPI • Peripheral enable register 0 (PER0). • Serial operating mode register (SPIM). • Serial clock selection register (SPIC).
Page 461: Peripheral Enable Register 0 (Per0)
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.3.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets the clock to be allowed or disallowed to be supplied to each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 462: Spi Operating Mode Register (Spim)
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.3.2 SPI operating mode register (SPIM) SPIM is used to select the operating mode and control the allow or disallow of the operation. SPIM can be set by 8-bit storage operation instructions.
Page 463: Spi Clock Selection Register (Spic)
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.3.3 SPI clock selection register (SPIC) This register specifies the timing of data sending/receiving and sets the serial clock. It can be set by 8-bit storage operation instructions. A reset signal is generated to clear the register to 00H.
Page 464: Transmit Buffer Registers (Sdro)
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.3.4 Transmit buffer registers (SDRO) This register sets the data to be sent. When bits 7 (SPIE) and 6 (TRMD) of the serial operating mode register (SPIM) are set to 1, data is written through SDRO starts sending/receiving.
Page 465: Spi Pin Port Function Control Register
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.3.6 SPI pin port function control register When using SPI, the control registers (port mode registers (PMxx, PMCxx) of the port function that are multiplexed with the SPI input and output pins must be set. For details, please refer to “2.3.1 Port Mode Register (PMxx)”.
Page 466: Operation Of Spi
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.4 Operation of SPI In 3-wire serial I/O mode, data is sent or received in 8- or 16-bit units. The data bit is transmitted or received in synchronously with the serial clock.
Page 467: Master Tramission And Reception
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.4.1 Master tramission and reception If bit 6 (TRMD) of the Serial Operating Mode Register (SPIM) is 1, data can be sent or received. When a value is written to the send buffer register (SDRO), the send/receive begins.
Page 468 CMS32L051 User Manual |Chapter 13 Serial Interface SPI Figure13-7 Stop step of the master transmit/receive Abort the start of the setting i If there is data being SPTF=0? transferred, wait for the transfer to end Put the SPIE position "0"...
Page 469 CMS32L051 User Manual |Chapter 13 Serial Interface SPI (2) Processing process Figure 13-8 Timing diagram of receive timing (single transmit mode) (INTMD=0, DAP=0, CKPmn=0) SPIE 写SDRO Write SDRO transmit data1 发送数据1 transmit data2 发送数据2 SDRO 移位运行移位运行 shift register 移位寄存器...
Page 470: Master Reception
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.4.2 Master reception If Bit 6 (TRMD) of the Serial Operating Mode Register (SPIM) is 0, only data can be received. Receive begins when data is read from the receive buffer register (SDRI).
Page 471 CMS32L051 User Manual |Chapter 13 Serial Interface SPI Figures 13-11 Stop step of master receive Abort the start of the setting i Note 1 The penultimate (n-1) reads out the data Put the SPIE position "0" to Write the SPIM...
Page 472 CMS32L051 User Manual |Chapter 13 Serial Interface SPI (2) Processing process Figure 13-12 Timing diagram of the receiving (DAP=0, CKPmn=0) SPIE 读SDRI Read SDRI Receiving& Receiving& 接收&移位运行接收&移位运行移位寄存器 shift register shift operation shift operation receiving data1 接收数据1 receiving data2 接收数据2...
Page 473: Slave Send And Receive
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.4.3 Slave send and receive If bit CKS2-0 of the serial clock select register (SPIC) selects slave mode and bit 6 (TRMD) of the serial operation mode register (SPIM) is 1, the slave transmit/receive mode is entered. When a value is written to the transmit buffer register (SDRO), wait for the clock of the master device and start transmitting/receiving.
Page 474 CMS32L051 User Manual |Chapter 13 Serial Interface SPI Figure 13-14 Stop step of slave send/receive Abort the start of the setting i If there is data being SPTF=0? transferred, wait for the transfer to end Put the SPIE position "0"...
Page 475 CMS32L051 User Manual |Chapter 13 Serial Interface SPI 2) Processing Figure 13-15 Transmit/receive timing diagram (single transmit mode) (INTMD=0, DAP=0, CKPmn=0). SPIE 发送数据1 发送数据2 transmit data1 transmit data2 SDRO shift register 移位运行 shift operation shift operation 移位运行移位寄存器 receiving data1 接收数据1...
Page 476: Slave Reception
CMS32L051 User Manual |Chapter 13 Serial Interface SPI 13.4.4 Slave reception If bit CKS2-0 of the serial clock select register (SPIC) selects slave mode and bit 6 (TRMD) of the serial operation mode register (SPIM) is 0, the slave receive mode is entered. When data is read from the receive buffer register (SDRI), wait for the clock of the master device and start receiving.
Page 477 CMS32L051 User Manual |Chapter 13 Serial Interface SPI Figure 13-18 Stop step of slave reception Abort the start of the setting i Note 1 The penultimate (n-1) reads out the data Put the SPIE position "0" to stop the SPI from...
Page 478 CMS32L051 User Manual |Chapter 13 Serial Interface SPI (2) Processing Figures 13-19 Timing diagram of the receiving (DAP=0, CKPmn=0). SPIE 读SDRI Read SDRI Receiving& Receiving& 接收&移位运行接收&移位运行 shift register 移位寄存器 shift operation shift operation 接收数据1 接收数据2 receiving data1 receiving data2...
Page 479: Chapter 14 Serial Interface Iica
CMS32L051 User Manual |Chapter 14 Serial interface IICA Chapter 14 Serial interface IICA 14.1 Function of IICA The serial interface IICA has the following three modes. (1) Operation stop mode This is a mode used when no serial transfer is taking place, which reduces power consumption.
Page 480 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-1 Block diagram of the serial interface IICA V1.2.2 www.mcu.com.cn 480 / 703...
Page 481 CMS32L051 User Manual |Chapter 14 Serial interface IICA An example of the structure of a serial bus is shown in Figure 14-2. Figure 14-2 Example of a serial bus structure for a I2C serial data bus master control CPU2 master CPU1...
Page 482: Structure Of The Serial Interface Iica
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.2 Structure of the serial interface IICA The serial interface IICA consists of the following hardware. Table 14-1 Structure of serial Interface IICA Item Structure IICA shift register n (IICAn) Register Slave address register n (SVAn).
Page 483 CMS32L051 User Manual |Chapter 14 Serial interface IICA (2) Slave address register n (SVAn) This is the register that holds the 7-bit local station address {A6, A5, A4, A3, A2, A1, A0} when used as a slave. The SVAn register is set via an 8-bit memory operation command. However, when the STDn bit is “1”...
Page 484 CMS32L051 User Manual |Chapter 14 Serial interface IICA (9) Ack generation circuit, stop condition detection circuit, start condition detection circuit, Ack detection circuit These circuits generate and detect various states. (10) Data hold time correction circuit This circuit generates a data hold time for the serial clock to fall.
Page 485: Registers For Controlling Serial Interface Iica
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.3 Registers for controlling serial interface IICA The serial interface IICA is controlled through the following registers. • Peripheral enable register 0 (PER0). • IICA control register n0 (IICCTLn0). • IICA flag register n (IICFn).
Page 486: Peripheral Enable Register 0 (Per0)
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.3.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets the clock to be allowed or disallowed to be supplied to each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 487 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-6 Format of IICA control register n0 (IICCTLn0) (1/4) Address: 0x40041A30 After reset: 00HR/W symbol IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn IICCTLn0 IICEn C operation enable Note 1 Disable operation. Reset to IICA status register n (IICSn and stop internal operation.
Page 488 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-6 Format of IICA control register n0 (IICCTLn0 2/4) Note1 Enable or disable interrupt requests generated by stop condition detection SPIEn Disable Enable When the WUPn bit of IICA control register n1 (IICCTLn1) is “1”, even if the SPIEn is “1” It also does not produce a stop condition interrupt.
Page 489 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-6 Format of IICA control register n0 (IICCTLn0) (3/4) Note1, 2 STTn The trigger of the start condition Start conditions are not generated. When the bus is released (standby, IICBSYn bit is “0”): If this bit is “1”, a start condition is generated (as the start of the...
Page 490 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-6 Format of IICA control register n0 (IICCTLn0) (4/4) Note The trigger of the stop condition SPTn No stop condition is generated. Generate a stop condition (as the end of the transfer of the master device).
Page 491: Iica Status Register N (Iicsn)
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.3.3 IICA status register n (IICSn) This is the register that represents the I C state. The 8-bit memory operation instruction can read the IICSn register only during the STTn bit being “1” and waiting.
Page 492 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-7 Format of IICA status register n (IICSn 2/3) Receive detection of expansion codes EXCn The extension code was not received. The extension code is received. Clear condition (EXCn=0). Set condition (EXCn=1).
Page 493: Iica Flag Register N (Iicfn)
CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-7 Format of IICA status register n (IICSn) (3/3) Detection of ACK ACKDn No reply detected. An answer is detected. Clear condition (ACKDn=0). Set condition (ACKDn=1). • When a stop condition is detected •...
Page 494 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-8 Format of IICA flag register n(IICFn) Note Address: 0x40041B52 After reset: 00HR/W symbol 5432 IICFn STCFn IICBSYn STCENn IICRSVn STTn clears the flag STCFn Release start conditions. The STTn flag could not be cleared while the start condition could be issued.
Page 495: Iica Control Register N1 (Iicctln1)
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.3.5 IICA control register n1 (IICCTLn1) This is a register used to set the I C operating mode and detect the status of the SCLAn pin and the SDAAn pin. The IICCTLn1 register is set via an 8-bit memory operation command. However, only CLDn bits and DADn bits can be read.
Page 496 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-9 Format of IICA control register n1 (IICCTLn1) (2/2) CLDn Level detection of the SCLAn pin (valid only when the IICEn bit is “1” A low SCLAn pin is detected. A high SCLAn pin is detected.
Page 497: Iica Low Level Width Setting Register N (Iicwln)
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.3.6 IICA low level width setting register n (IICWLn) This register controls the SCLAn pin signal low width (tLOW) and the SDAAn pin signal of the serial interface IICA output. The IICWLn register is set via an 8-bit memory operation command.
Page 498: Registers Controlling The Iica Pin Port Function
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.3.8 Registers controlling the IICA pin port function This product can multiplex IICA pin functions to any port except RESETB. The SCALn pin and the SDAAn pin can be configured to both ports by setting the port multiplexing function configuration registers (SCLA0PCFG and SDAA0PCFG).
Page 499: Function Of I C-Bus Mode
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.4 Function of I C-bus mode 14.4.1 Pin structure The structure of the serial clock pin (SCLAn) and the serial data bus pin (SDAAn) is as follows. (1) SCLAn..input/output pin of the serial clock The outputs of the master and slave devices are N-channel open-drain outputs, and the inputs are Schmitt inputs.
Page 500: Setting The Transmit Clock Via Iicwln Register And Iicwhn Register
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.4.2 Setting the transmit clock via IICWLn register and IICWHn register (1) The setting method of the master controller transmitting the clock T r a n s m i t c l o c k...
Page 501: Definition And Control Method Of I C-Bus
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5 Definition and control method of I C-bus The following describes the serial data communication format and signals used by the I C-bus. Each transmission timing of "start condition", "address", "data" and "stop condition" generated on the serial data bus of the I C bus is shown in the figure below.
Page 502: Start Conditions
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.1 Start conditions When the SCLAn pin is high, a start condition is generated if the SDAAn pin changes from high to low. The start condition for the SCLAn pin and the SDAAn pin is the signal generated when the master device starts serial transmission to the slave.
Page 503: Address
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.2 Address The next 7 bits of data for the start condition are defined as addresses. The address is the 7-bit data output by the master device in order to select a specific slave device from multiple slaves connected to the bus.
Page 504: Acknowledge (Ack)
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.4 Acknowledge (ACK) The serial data status of the sender and receiver can be confirmed by ACK. The receiver returns an answer each time it receives 8 bits of data. Usually, the sender receives a reply after sending 8-bit data. When the receiver returns an answer, it considers that it has received normally and continues processing.
Page 505: Stop Conditions
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.5 Stop Conditions When the SCLAn pin is high, a stop condition is generated if the SDAAn pin changes from low to high. The stop condition is the signal generated when the master device ends the serial transmission to the slave device.
Page 506: Wait
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.6 Wait Wait to notify the other party that the master or slave device is preparing for the send/receive of data (waiting status). By setting the SCLAn pin low, the other party is notified that it is waiting. If both the master and slave wait states are released, the next transfer can begin.
Page 507 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-19 Wait (2/2) The case where both the master and slave devices are waiting for 9 clocks (Master device: send, slave device: receive, ACKEn=1). master device and master slave device all enter...
Page 508: Release Method Of Wait
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.7 Release method of wait In general, I C can release the wait with the following processing. • Write data to IICA shift register n (IICAn). • Set bit5 (WRELn) of IICA control register n0 (IICCTLn0) (wait release).
Page 509: Interrupt Request (Intiican) Generation Timing And Wait Control
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.8 Interrupt request (INTIICAn) generation timing and wait control Control register (IICCTLn0) by setting bit3 (WTIMn) by setting IICA in Table 14-2 The timing shown generates INTIICAn and performs wait control. Table 14-2 Timing and wait control of INTIICAn...
Page 510: Detection Method For Address Matching
CMS32L051 User Manual |Chapter 14 Serial interface IICA (4) Release method of the wait There are 4 ways to undo the waiting: • Write data to IICA shift register n (IICAn). • Set bit5 (WRELn) of IICA control register n0 (IICCTLn0) (unwait).
Page 511: Extension Code
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.11 Extension code (1) When the high 4 bits of the receive address are “0000” or “1111”, as the extension code is received, the extension code receive flag (EXCn) is set to “1”, and in the 8th The falling edge of the clocks generates an interrupt request (INTIICAn).
Page 512: Arbitration
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.12 Arbitration When multiple master devices generate start conditions at the same time (in the case of STTn is “1” before the STDn bit becomes “1”), the communication of the master device is carried out while adjusting the clock until the data is different.
Page 513 CMS32L051 User Manual |Chapter 14 Serial interface IICA Table 14-4 Status of the arbitration and the timing of the interrupt request Status at the time arbitration occurred Timing of the interrupt request The address is sent during the sending process...
Page 514: Wake-Up Function
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.13 Wake-up function This is a subordinate function of I2C, which is the function of generating an interrupt request signal (INTIICAn) when the local station address and extension code are received. The processing efficiency is improved by not generating unwanted INTIICAn signals at different addresses.
Page 515 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-22 Flow when the WUPn bit is set to "0" by address matching (including receiving extension codes) deep sleep mode state INTIICAn=1？ WUPn=0 wait wait for 5 fMCK clock. Read IICSn after confirming serial interface IICA operation status, process accordingly.
Page 516 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-23 Operation as a master device after being released from deep sleep mode by an interrupt other than INTIICAn START SPIEn=1 WUPn=1 wait deep sleep instruction deep sleep mode state release deep sleep mode using other interrupt release deep sleep mode than INTIICAn.
Page 517: Communicate With Reservation
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.14 Communicate with reservation (1) Cases where the communication reservation function is allowed (bit0(IICRSVn) = 0 for IICA flag register n (IICFn)) To perform the next master communication without joining the bus, you can send a start condition when the bus is released by making a communication appointment.
Page 518 CMS32L051 User Manual |Chapter 14 Serial interface IICA The timing of the communication reservation is shown in the following figure. Figure 14-24 Timing of communication reservation program Write STTn=1 IICAn processing. hardware SPDn and communi STDnset INTIICAn cation processing. to '1'...
Page 519 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-26 Steps to communicate an appointment stop interrupt request set STTn flag to '1' STTn=1 (communication preserve) define communication define as in communication preserve state. preservation ( to configure and set user flag of any RAM)
Page 520 CMS32L051 User Manual |Chapter 14 Serial interface IICA When the communication reservation function is disabled (bit0 (IICRSVn) of IICA flag register n (IICFn) = 1) During bus communication, if bit1(STTn) of IICA control register n0 (IICCTLn0) is set to “1” in the state of not participating in this communication, this request is rejected without generating a start condition.
Page 521: Other Cautions
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.15 Other cautions (1) When the STCENn bit is “0” After just allowing I C to run (IICEn=1), it is considered a communication state (IICBSYn=1) independent of the actual bus state. To communicate with the master without detecting a stop condition, it is necessary to create a stop condition and communicate with the master after the bus is released.
Page 522: Communication Operation
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.16 Communication operation The following 3 running steps are represented here by a flowchart. (1) Master operation of a single-master system The flowchart used as a master device in a single master system is shown below.
Page 523 CMS32L051 User Manual |Chapter 14 Serial interface IICA Master operation of a single-master system Figure 14-27 Master operation of a single-master system START release serial interface IICA from reset state, configure PER0 register start providing clock. I2C bus initialization. Note.
Page 524 CMS32L051 User Manual |Chapter 14 Serial interface IICA Master operation of multi-master systems Figure 14-28 Master operation of multi-master systems (1/3) START release serial interface IICA from reset state, configure PER0 register start providing clock. configure pins and multiplexed ports to be used.
Page 525 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-28 Master operation of multi-master systems (2/3) allow communication preservation prepare starting STTn=1 communication. (generate stop condition) ensure wait time via Wait Note. software. MSTSn=0？ does INTIICAn interrupt occur? wait to release bus.
Page 526 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-28 Master operation of multi-master systems (3/3) Start communication. Write IICAn (Specify address and transfer direction) does INTIICAn interrupt wait for detecing occur? acknowledgement MSTSn=1？ ACKDn=1？ TRCn=1？ ACKEn=1 WTIMn=0 WTIMn=1 start...
Page 527 CMS32L051 User Manual |Chapter 14 Serial interface IICA (3) Slave operation The processing steps for the slave operation are as follows. Dependent operations are basically event-driven, so they need to be handled by INTIICAn interrupts (which requires a lot of change processing of the operational state such as stop condition detection in communications).
Page 528 CMS32L051 User Manual |Chapter 14 Serial interface IICA communication mode flag and the readiness flag are used to communicate (because the stop condition and start condition are processed by interrupt, the status is confirmed by the flag here). At the time of sending, the send is repeated until the master device does not return a reply. If the master does not return a reply, communication ends.
Page 529 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-29 Slave operation step (1) START release serial interface IICA from reset state, configure PER0 register start providing clock. configure pins and multiplexed ports to be used. Configure Port First port configured to be input mode and output latch set to 0“...
Page 530 CMS32L051 User Manual |Chapter 14 Serial interface IICA An example of a step for a slave to process via an INTIICAn interrupt is shown below (in this case, it is assumed that no extension code is used). The status is confirmed by INTIICAn interrupt and the following processing is performed.
Page 531: Generation Timing Of I C Interrupt Request (Intiican)
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.5.17 Generation timing of I C interrupt request (INTIICAn) The values of the transmit and receive timing of the data, the generation timing of the INTIICAn interrupt request signal, and the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Page 532 CMS32L051 User Manual |Chapter 14 Serial interface IICA (1) Master operation Start~Address Data~Data~Stop When WTIMn = 0 SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B Note 3:IICSn=1000X000B(set WTIMn bit to 4:IICSn=1000XX00B(set SPTn bit to 1 ) 5:IICSn=00000001B Note: to generate stop condition, must set WTIMn bit to '1' and modify INTIICAn interrupt requet signal generation timing sequenc e.
Page 533 CMS32L051 User Manual |Chapter 14 Serial interface IICA Start~Address~Data~Start~Address~Data~Stop (Restart) When WTIMn = 0 STTn=1 SPTn=1 ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=1000X110B Note1 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000XX00B(set WTIMn bit to Note 2 and set STTn bit to 4:IICSn=1000X110B...
Page 534 CMS32L051 User Manual |Chapter 14 Serial interface IICA ~Dat end extension code) Start~Code Data a~Stop (S When WTIMn = 0 SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1010X110B 2:IICSn=1010X000B Note 3:IICSn=1010X000B(set WTIMn bit to 4:IICSn=1010XX00B(set SPTn bit to 1 ) 5:IICSn=00000001B Note：...
Page 535 CMS32L051 User Manual |Chapter 14 Serial interface IICA Slave operation ( receiving a slave address) When Start~Address~Data~Data~Stop When WTIMn = 0 ST AD6~AD0 D7~D0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X000B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) When WTIMn=1...
Page 536 CMS32L051 User Manual |Chapter 14 Serial interface IICA Start~Address~Data~Start~Address~Data~Stop WTIMn = 0 (SVAn is the same after restart). When ST AD6~AD0 R/W ACK D7~D0 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) When WTIMn = 1 (SVAn is the same after restart).
Page 537 CMS32L051 User Manual |Chapter 14 Serial interface IICA Start~Address~Data~Start~Code~Data~Stop (i) I WTIMn=0 (different addresses after restarting (extension code)). When ST AD6~AD0 R/W ACK D7~D0 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 538 CMS32L051 User Manual |Chapter 14 Serial interface IICA Start~Address~Data~Start~Address~Data~Stop WTIMn=0 different addresses after restart (no When n-extension)). ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=00000110B 4:IICSn=00000001B 备注 must generate only generate while SPIEn bit is '1' (ii) WTIMn=1 (different addresses after restarting (non-extension)).
Page 539 CMS32L051 User Manual |Chapter 14 Serial interface IICA Slave operation (case of receiving extension code). Always participate in communication when receiving extension codes. Start~Code~Data~Data~Stop When WTIMn = 0 ST AD6~AD0 D7~D0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X000B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 540 CMS32L051 User Manual |Chapter 14 Serial interface IICA Start~Code~Data~Start~Address~Data~Stop WTIMn = 0 SVAn is the same after restart). When ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 541 CMS32L051 User Manual |Chapter 14 Serial interface IICA Start~Code~Data~Start~Code~Data~Stop WTIMn=0 (extension code received after res When tarting). ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) When WTIMn=1 (extension code received after res tarting).
Page 542 CMS32L051 User Manual |Chapter 14 Serial interface IICA Start~Code~Data~Start~Address~Data~Stop WTIMn=0 different addresses after restart (non-exten When sion)). ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=00000X10B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) WTIMn=1 (different addresses after restarting (non-extension)).
Page 543 CMS32L051 User Manual |Chapter 14 Serial interface IICA Do not participate in the running of the communication Start~Code~Data~Data~Stop ST AD6~AD0 D7~D0 D7~D0 1:IICSn=00000001B only generate while SPIEn bit is '1' Remark The failed operation of the arbitration (running as a slave after the arbitration failed When used as a master device in a multi-master system, the MSTSn bit must be read each time the INTIICAn interrupt request signal is generated to confirm the arbitration result.
Page 544 CMS32L051 User Manual |Chapter 14 Serial interface IICA When WTIMn=1 (ii) ST AD6~AD0 D7~D0 D7~D0 1:IICSn=0101X110B 2:IICSn=0001X100B 3:IICSn=0001XX00B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' A condition in which arbitration fails during the sending of the extension code...
Page 545 CMS32L051 User Manual |Chapter 14 Serial interface IICA When WTIMn=1 (ii) ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=0110X010B 2:IICSn=0010X110B 3:IICSn=0010X100B 4:IICSn=0010XX00B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' The failed operation of the arbitration (do not participate in the communication after the arbitration...
Page 546 CMS32L051 User Manual |Chapter 14 Serial interface IICA A condition in which arbitration fails during the sending of the extension code ST AD6~AD0 D7~D0 D7~D0 1:IICSn=01000110B set LRELn bit to '1' via software 2:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 547 CMS32L051 User Manual |Chapter 14 Serial interface IICA When WTIMn=1 (ii) ST AD6~AD0 D7~D0 D7~D0 1:IICSn=10001110B 2:IICSn=01000100B 3:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' A situation in which arbitration fails due to restart conditions when transferring data...
Page 548 CMS32L051 User Manual |Chapter 14 Serial interface IICA (ii) Extension code ST AD6~AD0 D7~Dm ST AD6~AD0 D7~D0 1:IICSn=1000X110B 2:IICSn=01000010B set LRELn bit to '1' via software 3:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' m=0~6 A situation in which arbitration fails at the time of transmission due to a stop condition...
Page 549 CMS32L051 User Manual |Chapter 14 Serial interface IICA A condition in which arbitration fails because the data is low when you want to generate a restart condition When WTIMn = 0 STTn=1 ST AD6~AD0 D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to...
Page 550 CMS32L051 User Manual |Chapter 14 Serial interface IICA A situation in which arbitration fails because of a stop condition when you want to generate a restart condition When WTIMn = 0 STTn=1 ST AD6~AD0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to...
Page 551 CMS32L051 User Manual |Chapter 14 Serial interface IICA A condition in which arbitration fails because the data is low when you want to generate a stop condition When WTIMn = 0 SPTn=1 ST AD6~AD0 D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMN bit to 1 )
Page 552: Timing Diagram
CMS32L051 User Manual |Chapter 14 Serial interface IICA 14.6 Timing diagram In I C-bus mode, the master device selects a slave device for a communication object from multiple slave devices by giving the serial bus output address. The master device sends the TRCn bit (bit3 of the IICA status register n (IICSn)) indicating the direction of data transmission after the slave device address serial communication with the slave begins.
Page 553 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-31 Example of a slave device→a master device (Master device: select 9 clocks of waiting, slave device: select 9 clocks of waiting) (1/4) (1) Start condition ~ address ~ data master control...
Page 554 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-31 “(1) start condition ~ address ~ data” (1) ~ (6) descriptions are as follows: (1) If the start condition is triggered by the master (STTn=1), the bus data line (SDAAn) drops, generating a start condition (changing SDAAn from “1”...
Page 555 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-31 Communication example of a master device → slave device (Master device: select 9 clocks of waiting, slave device: select 9 clocks of waiting) (2/4) (2) Address ~ Data ~ Data...
Page 556 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-31 “(2) address ~ data ~ data” (3) ~ (10) of the descriptions are as follows: (3) On the slave, if the receiving address and the local station address (the value of the SVAn) are the same note, the ACK is sent to the master through the hardware.
Page 557 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-31 Communication example of a master device → slave device (Master device: select 9 clocks of waiting, slave device: select 9 clocks of waiting) (3/4) Data~Data~Stop condition master control IICAn note1 ACKDn （ACK...
Page 558 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-31The descriptions of (7) to (15) of "(3) Data - Data - Stop condition" in Figure 14-31are as follows: ⑦ At the end of the data transfer, the ACK is sent to the master controller through the hardware because the ACKEn bit of the slave is “1”.
Page 559 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-31 Communication example of a master device → slave device (Master device: select 9 clocks of waiting, slave device: select 9 clocks of waiting) (4/4) Data~Restart condition~Address master control IICAn <3>...
Page 560 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-31The operation of "(4) Data ~ Restart condition ~ Address" in Figure 14-31 is explained as follows. After executing steps ⑦ and ⑧, execute <1> to <3>, and return to the data sending step in step (3).
Page 561 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-32 Communication example of a slave device→master device (Master device: select 8 clocks of waiting, slave device: select 9 clocks of waiting) (1/3) Start condition ~ address ~ data master control...
Page 562 CMS32L051 User Manual |Chapter 14 Serial interface IICA The descriptions of ① to ⑦ of "(1) Start condition ~ Address ~ Data" in Figure 14-32 are as follows: (1) If the start condition is triggered by the master (STTn=1), the bus data line (SDAAn) drops, generating a start condition (changing SDAAn from “1”...
Page 563 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-32 Communication example of a slave device→master device (Master device: select 8 clocks of waiting, slave device: select 9 clocks of waiting) (2/3). (2) Address ~ Data ~ Data master control...
Page 564 CMS32L051 User Manual |Chapter 14 Serial interface IICA The description of ③ to ⑫ of "(2) Address - Data - Data" in Figure is as follows: (3) On the slave side, if the receiving address and the local station address (the value of SVAn) are the same, the ACK is sent to the master controller through the hardware.
Page 565 CMS32L051 User Manual |Chapter 14 Serial interface IICA Figure 14-32 Communication example of a slave device→master device (Master device: select 8 → 9 clocks waiting, slave device: select 9 clocks waiting) (3/3) (3) Data ~ Data ~ Stop Condition master control...
Page 566 CMS32L051 User Manual |Chapter 14 Serial interface IICA 2. After the release of the stop condition, the time from the SCLAn pin signal to generate the stop condition is at least 4.0us when set to standard mode and at least 0.6us when set to fast mode.
Page 567 CMS32L051 User Manual |Chapter 14 Serial interface IICA The description of ⑧~⑲ of "(3) Data - Data - Stop condition" in Fig. 16-32 is as follows: ⑧. The master enters a waiting state (SCLAn=0) on the falling edge of the 8th clock and generates an interrupt (INTIICAn: End of Transmission Neutral).
Page 568: Chapter 15 Irda
CMS32L051 User Manual |Chapter 15 IrDA Chapter 15 IrDA IrDA enables the transmission and reception of IrDA communication waveforms in accordance with the IrDA (InfraredDataAssociation) 1.0 protocol in cooperation with the Universal Serial Communication Unit (SCI). 15.1 Function of IrDA If the IrDA function is set to active through the IRE bit of the IRCR register, SCI's TxD2 signal and RxD2 signal can encode or decode the waveform that conforms to the IrDA1.0 protocol (IrTxD/IrRxD pins), and then...
Page 569: Registers For Controlling The Irda
CMS32L051 User Manual |Chapter 15 IrDA 15.2 Registers for controlling the IrDA Control the IrDA function through the following registers. • Peripheral enable register 0 (PER0). • IrDA control register (IRCR). 15.2.1 Peripheral enable register 0 (PER0) The PER0 register is a register that sets the clock to be enable or disable to be supplied to each peripheral hardware.
Page 570: Irda Control Register (Ircr)
CMS32L051 User Manual |Chapter 15 IrDA 15.2.2 IrDA control register (IRCR) This is the register that controls the IrDA function. Selects for polarity switching of received and transmitted data, clock selection for IrDA, and switching of serial input/output pin functions (typically serial and IrDA functions).
Page 571: Operation Of Irda
CMS32L051 User Manual |Chapter 15 IrDA 15.3 Operation of IrDA 15.3.1 Operating steps for IrDA communication (1) Initial setup process for IrDA communication Follow the steps below to initialize IrDA. Set the IRDAEN bit of the PER0 register to "1".
Page 572: Transmission
CMS32L051 User Manual |Chapter 15 IrDA 15.3.2 Transmission At the time of transmission, the output signal (UART frame) from the SCI is converted to an IR frame via IrDA (see Figure 15-4). At IRTXINV bit “0” and serial data is “0”, the output bit period (1-bit width period) x 3/16 high level pulse (initial value).
Page 573: High Level Pulse Width Selection
CMS32L051 User Manual |Chapter 15 IrDA 15.3.4 High level pulse width selection If the pulse width at the time of transmission is less than the bit rate x 3/16, the applicable IRCKS2 ~ IRCKS0 bit setting (minimum pulse width) and the high-level pulse width at the time of setting are shown in Table 15-2.
Page 574: Chapter 16 Enhanced Dma
CMS32L051 User Manual |Chapter 16 Enhanced DMA Chapter 16 Enhanced DMA 16.1 The function of DMA DMA is a function that does not use a CPU and transfers data between memories. Initiate DMA for data transfer via peripheral function interrupts. When DMA and CPU access the same unit in FLASH, SRAM0, SRAM1, or peripheral modules at the same time, their bus usage rights are higher than those of the CPU.
Page 575 CMS32L051 User Manual |Chapter 16 Enhanced DMA Table 16-1 DMA specification (2/2) item Specification When transferring the DMACTj register from “1” to “0”, an interrupt from the startup Normal mode source is requested to the CPU and interrupt handling is performed.
Page 576: Structure Of Dma
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.2 Structure of DMA The block diagram of DMA is Figure 16-1 Figure 16-1 Block diagram of DMA peripherial interrupt signal interrupt source/ transmit start data transmission source selection control peripherial interrupt signal...
Page 577: Registers For Controlling Dma
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3 Registers for controlling DMA The registers that control the DMA are shown in Table 16-2. Table 16-2 Registers for controlling DMA Register Name Symbol Peripheral enable register 1 PER1 DMA boot enable register 0...
Page 578: Dma Control Data Areas And Dma Vector Table Areas Allocation
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.1 DMA control data areas and DMA vector table areas allocation The control data allocated to the DMA and the 416-byte region of the vector table are set to the RAM area via the DMABAR register.
Page 579: Control Data Allocation
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.2 Control data allocation Starting from the start address, follow DMACRj, DMBLSj, DMACTj, DMRLDj, DMSARj, DMDARj ( j=0~23) registers are assigned control data sequentially. The start address is set by the DMABAR register, and the lower 10 bits are set separately by the vector table assigned by each startup source.
Page 580 CMS32L051 User Manual |Chapter 16 Enhanced DMA Table 16-4 Starting address of control data address address baseaddr+D0H baseaddr+190H baseaddr+C0H baseaddr+180H baseaddr+B0H baseaddr+170H baseaddr+A0H baseaddr+160H baseaddr+90H baseaddr+150H baseaddr+80H baseaddr+140H baseaddr+70H baseaddr+130H baseaddr+60H baseaddr+120H baseaddr+50H baseaddr+110H baseaddr+40H baseaddr+100H baseaddr+30H baseaddr+F0H baseaddr+20H baseaddr+E0H...
Page 581: Vector Table
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.3 Vector table Once the DMA is started, the control data is determined by reading the data from the vector table allocated by each startup source, and the control data assigned to the DMA control data area is read.
Page 582 CMS32L051 User Manual |Chapter 16 Enhanced DMA Table 16-5 DMA startup source and vector address DMA start source (the source where the interrupt The source The address of the vector Priority number request occurred). The setting address of the DMABAR...
Page 583: Peripheral Enable Register 1 (Per1)
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.4 Peripheral Enable Register 1 (PER1) The PER1 register is a register that sets the clock that enable or disables clocking each peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
Page 584 CMS32L051 User Manual |Chapter 16 Enhanced DMA Figure 16-6 Format of DMA control register j (DMACRj) Address: Refer to “16.3.2 Control data allocation “. A fter reset: Indefinite value Symbol: DMACRj RPTINT CHNE DAMOD SAMOD RPTSEL MODE Selection of transmitted data length...
Page 585: Dma Block Size Register J (Dmblsj) (J=0~23)
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.6 DMA block size register j (DMBLSj) (j=0~23) This register sets the block size of the 1 initiation transfer of data. Figure 16-7of DMA block size register j (DMBLSj Address: Refer to 16.3.2 Control data allocation “.
Page 586: Dma Transmit Count Register J(Dmactj) (J=0~23)
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.7 DMA transmit count register j(DMACTj) (j=0~23) This register sets the number of data transfers to the DMA. Decrements 1 for every DMA transfer started. Figure 16-8 Format of DMA transmit count register J (DMACTj...
Page 587: Dma Transmit Count Reload Register J(Dmrldj) (J=0~23)
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.8 DMA transmit count reload register j(DMRLDj) (j=0~23). This register sets the initial value of the number of transfers register in repeat mode. In repeat mode, because the value of this register is reloaded into the DMACT register, the set value must be the same as the initial value of the DMACT register.
Page 588: Dma Source Address Register J(Dmsarj) (J=0~23)
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.9 DMA source address register j(DMSARj) (j=0~23). This register specifies the source address at which data is transferred. When the SZ bit of the DMACRj register is “01” (16 bits transferred), the lowest bit is ignored and processed as an even address.
Page 589: Dma Boot Enable Register I (Dmaeni) (I=0~2)
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.11 DMA boot enable register i (DMAENi) (i=0~2). This is the 8-bit register that controls the boot of the DMA through each interrupt source. The corresponding connection between the interrupt source and the DMAENi0~DMAENi7 bits is shown in Table 16-6.
Page 590 CMS32L051 User Manual |Chapter 16 Enhanced DMA DMAENi2 DMA boot enable i2 Disable startup. Enable startup. Depending on the condition under which the end-of-transmission interrupt occurs, the DMAENi2 bit “ becomes 0” (disable start). DMAENi1 DMA boot enable i1 Disable startup.
Page 591: Dma Base Address Register (Dmabar)
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.3.12 DMA base address register (DMABAR). This is a 32-bit register that sets the vector address that holds the start address of the DMA control data area and the address of the DMA control data area.
Page 592: Dma Operation
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.4 DMA operation Once the DMA is started, the control data is read from the DMA control data area, the data is transmitted according to this control data, and the control data after the data transmission is written back to the DMA control data area.
Page 593: Normal Mode
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.4.2 Normal mode In the case of 8-bit transmission, the transmission data for 1 start is 1 to 65535 bytes; in the case of 16-bit transmission, the transmission data for 1 start is 2 to 131070 bytes; in the case of 32-bit transmission, the transmission data for 1 start is 4 to 262140 bytes.
Page 594 CMS32L051 User Manual |Chapter 16 Enhanced DMA (1) Example 1 of the use of normal mode: Continuous A/D conversion results DMA is started by an A/D conversion end interrupt, and the value of the A/D conversion result register is transferred to RAM.
Page 595 CMS32L051 User Manual |Chapter 16 Enhanced DMA Example 2 of the use of normal mode: UART0 transmits continuously DMA is started through a blank interrupt from UART0's send buffer, and the value of RAM is transferred to UART0's send buffer.
Page 596: Repeat Pattern
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.4.3 Repeat pattern The transfer data for one initiation is 1 to 65535 bytes. The source or destination is designated as a repeat area, and the number of transfers is 1 to 65535 times. Once the specified number of transfers is complete, initialize the DMACTj(j=0~23) register and the address specified as a repeat, and then repeat the transfer.
Page 597 CMS32L051 User Manual |Chapter 16 Enhanced DMA Figure 16-18 Data transfer in repeat mode DMACTj register ≠1 FFFFFFFFH 1The second boot to be delivered The data block size (N bytes). DMBLSj register = N DMACTj register ≠1 DMSARj register =...
Page 598 CMS32L051 User Manual |Chapter 16 Enhanced DMA Example of the use of repeat mode: Use the stepper motor of the port to control the pulse output The DMA is started using the Channel 0 interval timer function of the Timer40, and the mode of the motor control pulse saved in the code flash memory is transferred to the universal port.
Page 599: Chain Transfer
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.4.4 Chain transfer When the CHNE bit of the DMACRj(j=0~23) register is “1” (allow chain transfer), multiple data can be transferred continuously through one startup source. Once the DMA is started, the control data is selected by reading the data from the corresponding vector address of the startup source, and the control data assigned to the DMA control data area is read.
Page 600 CMS32L051 User Manual |Chapter 16 Enhanced DMA (1) Example of using chain transfer: Continuous A/D conversion result for UART0 transmission DMA is started by interrupting the end of the A/D conversion, and the A/D conversion result is transferred to RAM for UART0 transmission.
Page 601: Precautions When Using Dma
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.5 Precautions when using DMA 16.5.1 DMA controls the settings of data and vector tables • The DMA Base Address Register (DMABAR) must be changed with all DMA boot sources set to a state that disables startup.
Page 602: Number Of Execution Clocks For Dma
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.5.3 Number of execution clocks for DMA The execution and number of clocks required at DMA startup are shown in Table 16-9. Table 16-9 Execution and number of clocks required when DMA is started...
Page 603: Response Time Of Dma
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.5.4 Response time of DMA The DMA response time is shown in Table 16-12. DMA response time refers to the time from the time the DMA boot source is detected to the start of the DMA transfer, excluding the number of execution clocks for the DMA.
Page 604: Operation In Standby Mode
CMS32L051 User Manual |Chapter 16 Enhanced DMA 16.5.6 Operation in standby mode state DMA operation Sleep mode Can be operated (disable operation in low-power RTC mode). Deep sleep mode Can accept the DMA start source and make DMA transfer Note 1...
Page 605: Chapter 17 Linkage Controller (Eventc)
CMS32L051 User Manual |Chapter 17 Linkage Controller (EVENTC) Chapter 17 Linkage Controller (EVENTC) 17.1 Feature of EVENTC EVENTC links the events output by each peripheral function to each other between the peripheral functions. It can be operated directly through the event chain without going through the CPU, and can be operated directly between peripheral functions.
Page 606: Control Registers
CMS32L051 User Manual |Chapter 17 Linkage Controller (EVENTC) 17.3 Control registers The controller registers are shown in Table 17-1. Table 17-1 Control registers of EVENTC Register name Symbol Event output target selects register 00 ELSELR00 Event output target selects register 01...
Page 607: Output Target Selection Register N (Elselrn) (N=00~14)
CMS32L051 User Manual |Chapter 17 Linkage Controller (EVENTC) 17.3.1 Output target selection register n (ELSELRn) (n=00~14) The ELSELRn register links each event signal to the event receiver peripheral function (link target peripheral function) to run when the event accepts the event. You cannot link multiple event inputs to the same event output destination (event acceptor).
Page 608 CMS32L051 User Manual |Chapter 17 Linkage Controller (EVENTC) Table 17-2 ELSELRn registers (n=00~14) and peripheral functions Register Content Event occurrence source (output source for event input n) name ELSELR00 INTP0 External interrupt edge detection 0 External interrupt edge detection1 ELSELR01...
Page 609 CMS32L051 User Manual |Chapter 17 Linkage Controller (EVENTC) Table 17-3 Correspondence between the setting value of ELSELRn register (n=00~14) and the operation when the link target peripheral function accepts the event ELSELRn register Link the target Operation when the event is accepted...
Page 610: Operation Of Eventc
CMS32L051 User Manual |Chapter 17 Linkage Controller (EVENTC) 17.4 Operation of EVENTC The path used by the event signal generated by each peripheral function as an interrupt request for the interrupt control circuit and the path used as an eventc event are independent of each other.
Page 611: Chapter 18 Interrupt Function
CMS32L051 User Manual |Chapter 18 Interrupt Function Chapter 18 Interrupt Function The Cortex-M0+ processor has a built-in Nested Vector Interrupt Controller (NVIC) that supports up to 32 interrupt request (IRQ) inputs, as well as one non-maskable interrupt (NMI) input, and multiple internal exceptions.
Page 612 CMS32L051 User Manual |Chapter 18 Interrupt Function Table 18-1 List of interrupt sources (1/3) The source of the interrupt name trigger interior INTLVI Voltage detection Note 2 Detection of pin input edges exterior INTP0 Detection of pin input edges INTP1...
Page 613 CMS32L051 User Manual |Chapter 18 Interrupt Function Table 18-1 List of interrupt sources (2/3) Source of the interrupt Name Trigger The end of transmission interi INTST1/ sent by UART1 or the end INTSSPI10/ of transmission of buffer null INTIIC10/ interrupt/SSPI10 or the end...
Page 614 CMS32L051 User Manual |Chapter 18 Interrupt Function Table 18-1 List of interrupt sources (3/3) Source of the interrupt Name Trigger Watchdog timer interval interrupt INTWDT interior Note 2 Note 1 The basic composition types (A) to (C) correspond to Figure 18-1 (A)~(C).
Page 615 CMS32L051 User Manual |Chapter 18 Interrupt Function Figure 18-1 Basic structure of the interrupt function (A) Internally maskable interrupts Internal bus CPU. IRQ Standby release signal (B)Externally maskable interrupt (INTPn) Internal bus The outer break edge Allow registers （EGN，EGP) edge CPU.
Page 616: Registers Controlling Interrupt Function
CMS32L051 User Manual |Chapter 18 Interrupt Function 18.3 Registers controlling interrupt function The interrupt function is controlled by the following four registers. • Interrupt request flag register (IF00~IF31). • Interrupt mask flag register (MK00~MK31 • External interrupt rising edge enable register (EGP0).
Page 617: Interrupt Mask Flag Register (Mk00~Mk31)
CMS32L051 User Manual |Chapter 18 Interrupt Function 18.3.2 Interrupt mask flag register (MK00~MK31) The interrupt masking flag setting allows or disables the corresponding maskable interrupt processing. Set the MK00L~MK31L registers via 8-bit memory operation instructions or set MK00~MK31 registers via 32-bit memory operation instructions.
Page 618: Register (Egn0)
CMS32L051 User Manual |Chapter 18 Interrupt Function Table 18-2 Relationship between interrupt sources and flag registers Interrupt Interrupt Number Source of the interrupt request flag mask flag register register IF00. IFL MK00. MKL INTLVI IF01.IFL MK01.MKL INTP0 IF02.IFL MK02.MKL INTP1 IF03.IFL...
Page 619 CMS32L051 User Manual |Chapter 18 Interrupt Function Figure 18-4 Relationship between each flag register and CPU.IRQ V1.2.2 www.mcu.com.cn 619 / 703...
Page 620 CMS32L051 User Manual |Chapter 18 Interrupt Function 18.3.3 External interrupt rising edge enable register (EGP0), External interrupt falling edge enable register (EGN0) These registers set the effective edges of INTP0 to INTP3. Set the EGP0 and EGN0 registers via 8-bit memory operation instructions.
Page 621 CMS32L051 User Manual |Chapter 18 Interrupt Function Table 18-3 Interrupt request signals corresponding to the EGPn and EGNn bits Detect enable bits Interrupt request signal EGP0 EGN0 INTP0 EGP1 EGN1 INTP1 EGP2 EGN2 INTP2 EGP3 EGN3 INTP3 Note If you switch the input port used by the external interrupt function to output mode, a valid edge may be detected and an INTPn interrupt may be generated.
Page 622: Operation Of Interrupt Handling
CMS32L051 User Manual |Chapter 18 Interrupt Function 18.4 Operation of interrupt handling 18.4.1 Acceptance of maskable interrupt requests “1” and the masked (MK) flag for the interrupt request is cleared “0”, it If the interrupt request flag is set to enters a state that accepts maskable interrupt requests and can pass the interrupt request to NVIC.
Page 623: Chapter 19 Key Interrupt Function
CMS32L051 User Manual |Chapter 19 Key Interrupt Function Chapter 19 Key Interrupt Function The number of channels entered by key interrupt varies by product. 19.1 Function of key interrupt A key interrupt (INTKR) can be generated by giving the key interrupt input pin (KR0 to KR5) on the falling edge of the input.
Page 624 CMS32L051 User Manual |Chapter 19 Key Interrupt Function Figure 19-1 Diagram of the key interrupt INTKR KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register V1.2.2 www.mcu.com.cn 624 / 703...
Page 625: Registers For Controlling Key Interrupt
CMS32L051 User Manual |Chapter 19 Key Interrupt Function 19.3 Registers for controlling key interrupt Interrupt function via the following register control keys. • Key return mode register (KRM). • Port mode register (PMx 19.3.1 Key return mode register (KRM) KRM0~KRM5-bit control KR0~KR5 signal.
Page 626: Port Mode Register (Pmx)
CMS32L051 User Manual |Chapter 19 Key Interrupt Function 19.3.2 Port mode register (PMx) When used as a key interrupt input pin (KR0~KR5), the PMCxn bit must be set to “0” and the PMxn bit must be set to “1” respectively. In this case, the output latch of Pxn can be “0” or “1”.
Page 627: Chapter 20 Standby Function
CMS32L051 User Manual |Chapter 20 Standby Function Chapter 20 Standby Function 20.1 Standby function The standby function is a function that further reduces the operating current of the system, and there are two modes. (1) Sleep mode Sleep mode is the mode that stops the CPU from running the clock. Each clock continues to oscillate before setting the sleep mode, such as if the high-speed system clock oscillation circuit, the high-speed internal oscillator, or the subsystem clock oscillation circuit is oscillating.
Page 628: Sleep Mode
CMS32L051 User Manual |Chapter 20 Standby Function 20.2 Sleep mode 20.2.1 Setting of the sleep mode When the SLEEPDEEP bit of the SCR register is 0, the WFI instruction is executed and sleep mode is entered. In sleep mode, the CPU stops operating, but the values of the internal registers are still maintained and peripheral modules remain in the state they were in before they entered sleep mode.
Page 629 CMS32L051 User Manual |Chapter 20 Standby Function area function General CRC When DMA executed in the operation of the RAM , it can be run. RAM parity function It can run when performing DMA. SFR protection function Note Stop running: Automatically stops running when transferred to sleep mode.
Page 630 CMS32L051 User Manual |Chapter 20 Standby Function Table 20-1 Operation status in sleep mode (2/2) Setting of the sleep mode Execution of WFI instructions while the CPU is running at the subsystem clock CPU running at XT1 clock (F CPU running on external subsystem...
Page 631: Release Of Sleep Mode
CMS32L051 User Manual |Chapter 20 Standby Function 20.2.2 Release of sleep mode Sleep mode can be interrupted with any interrupt as well as an external reset terminal, POR reset, low voltage sense reset, RAM parity error reset, WDT reset, and software reset to be released.
Page 632: Deep Sleep Mode
CMS32L051 User Manual |Chapter 20 Standby Function 20.3 Deep sleep mode 20.3.1 The setting for deep sleep mode When the SLEEPDEEP bit of the SCR register is 1, the WFI instruction is executed and deep sleep mode is entered. In this mode, the CPU, most peripheral modules, and the oscillator stop functioning. However, the values of the CPU's internal registers, RAM data, peripheral modules, and I/O status are maintained.
Page 633 CMS32L051 User Manual |Chapter 20 Standby Function RAM parity function SFR protection function Note Stop Running: Automatically stops running when transferred to deep sleep mode. Disable Run: Stop running before moving to deep sleep mode. : High-speed internal oscillator clock...
Page 634: Release Of Deep Sleep Mode
CMS32L051 User Manual |Chapter 20 Standby Function 20.3.2 Release of deep sleep mode Deep sleep mode can be released in the following two ways. Release through an unmasked interrupt request If an unmasked interrupt request occurs, deep sleep mode is released. After the oscillation settling time, the deep sleep mode is released and the CPU begins to process the interrupt service program.
Page 635 CMS32L051 User Manual |Chapter 20 Standby Function Release by generating a reset signal Deep sleep mode is released by generating a reset signal. Then, as with the usual reset, execute the program after transferring to the reset vector address. Figure 20-4...
Page 636: Chapter 21 Reset Function
CMS32L051 User Manual |Chapter 21 Reset Function Chapter 21 Reset Function The following 7 methods generate a reset signal. (1) An external reset is entered via the RESETB pin. (2) An internal reset is generated by a program runaway detection of the watchdog timer.
Page 637 CMS32L051 User Manual |Chapter 21 Reset Function Figure 21-1 Block diagram of reset function internal bus reset control flag register （RESF） SYSRF WDTRF RPERF IAWRF LVIRF reset reset reset reset reset watchdog timer reset signal erase erase erase erase erase...
Page 638 CMS32L051 User Manual |Chapter 21 Reset Function Reset timing When low is input to the RESETB pin, a reset is generated. Then, if RESETB is quoted high, the reset state is released, and execution begins with a high-speed internal oscillator clock after the reset process is complete.
Page 639 CMS32L051 User Manual |Chapter 21 Reset Function For resets generated by voltage sensing of POR circuits and LVD circuits, if the VDD≥ V POR or VDD≥ is satisfied after the reset VLVD is released from the reset state and execution begins with a high- speed internal oscillator clock after the reset process.
Page 640 CMS32L051 User Manual |Chapter 21 Reset Function Table 21-1 Operational status during reset Item During reset System clock Stop supplying clocks to the CPU. The master Stop running. system clock Stops operation (pins X1 and X2 are in input port mode).
Page 641: Register For Confirming The Reset Source
Register for confirming the reset source 21.1.1 Reset control flag register (RESF) The CMS32L051 microcontroller has multiple internal reset sources. The Reset Control Flag Register (RESF) holds the reset source where the reset request occurred. RESF registers can be read via 8-bit memory operation instructions.
Page 642 CMS32L051 User Manual |Chapter 21 Reset Function The status of the RESF registers at the time of the reset request is shown in Table 21-2. Table 21-2 RESF register status when a reset request occurs Reset Reset The reset Access the...
Page 643 CMS32L051 User Manual |Chapter 21 Reset Function Figure 21-5 Confirmation steps for resetting the source after reset accepted read RESF register, save RESF value to any RAM location read RESF register (clear RESF register) SYSRF of RESF register = 1?
Page 644: Chapter 22 Power-On Reset Circuit
Note that when the power-on reset circuit generates an internal reset signal, clear the reset control flag register (RESF) to “00H”. Note 1 The CMS32L051 contains several hardware that generates an internal reset signal. Flags used to indicate the reset source are assigned when an internal reset signal is generated by the access of a watchdog timer (WDT), voltage detection (LVD) circuit, system reset request position bit, RAM parity error, or illegal memory RESF registers;...
Page 645: Structure Of Power-On Reset Circuit
CMS32L051 User Manual |Chapter 22 Power-On Reset Circuit 22.2 Structure of power-on reset circuit A block diagram of the power-on reset circuit is shown in Figure 22-1. Figure 22-1 Block diagram of power-on reset circuit internal reset signal basic voltage source 22.3...
Page 646 CMS32L051 User Manual |Chapter 22 Power-On Reset Circuit Figure 22-2 Timing of internal reset signal generation for power-on reset circuit and voltage detection circuit (1/3) A case of using an external reset input on the RESETB pin power supply voltage(V...
Page 647 CMS32L051 User Manual |Chapter 22 Power-On Reset Circuit Figure 22-2 Timing of internal reset signal generation for power-on reset circuit and voltage detection circuit (2/3) LVD is in interrupt & reset mode (option bytes 000C1H LVIMDS1, LVIMDS0=1, 0). power supply...
Page 648 CMS32L051 User Manual |Chapter 22 Power-On Reset Circuit Figure 22-2 Timing of internal reset signal generation for power-on reset circuit and voltage detection circuit (3/3) (3) LVD reset mode case (option byte 000C1H LVIMDS1, LVIMDS0=1, 1). power supply voltage(V low limit of working voltage range =1.51V(TYP.)
Page 649: Chapter 23 Voltage Detection Circuit
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Chapter 23 Voltage Detection Circuit 23.1 Function of voltage detection circuit The voltage detection circuit sets the operating mode and sense voltage (V ) via option LVDH LVDL bytes (000C1H). Voltage Detection (LVD) circuitry has the following functions.
Page 650: Structure Of Voltage Detection Circuit
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit 23.2 Structure of voltage detection circuit A block diagram of the voltage detection circuit is shown in Figure 23-1. Figure 23-1 Block diagram of voltage detection circuit internal reset N-ch signal voltage...
Page 651: Registers For Controlling Voltage Detection Circuit
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit 23.3 Registers for controlling voltage detection circuit The voltage detection circuit is controlled by the following registers. • Voltage Sense Register (LVIM). • Voltage Sense Level Register (LVIS). 23.3.1 Voltage sense register (LVIM).
Page 652: Voltage Sense Level Register (Lvis)
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit 23.3.2 Voltage sense level register (LVIS) This is the register that sets the voltage sense level. The LVIS registers are set via 8-bit memory operation instructions. After the reset signal is generated, the value of this register becomes “00H/01H/81H”...
Page 653 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Table 23-1 Format of user option bytes (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt & reset mode) Detection Setting value of the option byte...
Page 654 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Table 23-1 Format of user option bytes (000C1H) (2/2) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt mode) Detection Setting value of the option byte voltage Mode setting...
Page 655: Operation Of Voltage Detection Circuit
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit 23.4 Operation of voltage detection circuit 23.4.1 Settings when used in reset mode The operating mode (reset mode (LVIMDS1, LVIMDS0=1, 1)) and the sense voltage (V) are set by option byte 000C1H LVD). If reset mode is set, operation begins in the following initial state.
Page 656 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Figure 23-4 Generation timing of the internal reset signal (LVIMDS1, LVIMDS0=1, 1 for option bytes) power supply voltage(VDD) VLVD low limit of working voltage range VPOR=1.51V(TYP.) VPDR=1.50V(TYP.) Time clear LVIF flag not cleared...
Page 657: Settings When Used In Interrupt Mode
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit 23.4.2 Settings when used in interrupt mode The operating mode (interrupt mode (LVIMDS1, LVIMDS0=0, 1)) and the sense voltage (V) are set by option byte 000C1H LVD). If you set the interrupt mode, it starts operating in the following initial state.
Page 658 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Figure 23-5 Generation timing of interrupt signals (option bytes LVIMDS1, LVIMDS0=0, 1) Note2 power supply Note2 voltage(V low limit of working voltage range =1.51V(TYP.) =1.50V(TYP.) Time LVIMK logo Note1 (mask interrupt) (set by software)
Page 659: Settings For Interrupt & Reset Mode
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit 23.4.3 Settings for interrupt & reset mode The operating mode (interrupt & reset mode (LVIMDS1, LVIMDS0=1, 0)) and the sense voltage (V LVDH VLVDL) are set by option byte 000C1H). If the interrupt & reset mode is set, it starts operating in the following initialization state.
Page 660 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Figure 23-6 Generation timing of reset & interrupt signal (LVIMDS1 for option bytes, LVIMDS0=1, 0) (1/2) if after release mask no reset is generated, then it can be tell that VDD has recovered to value VLVDH.
Page 661 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Note 1. After the reset signal is generated, the LVIMK flag changes to “1”. 2. When using the interrupt & reset mode, it must be set after the interrupt occurs in accordance with the “Confirmation Figure 23-7 Setup steps for confirmation/reset of the operating voltage“.
Page 662 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Figure 23-6 Generation timing of interrupt & reset signal (LVIMDS1 for option bytes LVIMDS0=1, 0) (2/2) after release mask while VDD＜VLVDH, due to LVIMD=1(reset mode), the reset will be generated. power supply...
Page 663 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit Note 1. After the reset signal is generated, the LVIMK flag changes to “1”. 2. When using the interrupt & reset mode, it must be set after the interrupt occurs in accordance with the “Confirmation Figure 23-7...
Page 664 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit If the interrupt & reset mode is set (LVIMDS1, LVIMDS0=1, 0), it is required after the LVD reset (LVIRF=1) is released. Voltage detection settling wait time of 400us or 5 f-IL clocks. The LVIMD bit clear “0”...
Page 665: Considerations For Voltage Detection Circuits
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit 23.5 Considerations for voltage detection circuits Regarding voltage fluctuations when the power is turned on For systems where the supply voltage (V DD ) fluctuates for a certain amount of time near the LVD sense voltage, it is possible to repeatedly enter the reset state and the reset release state.
Page 666 CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit (2) The delay from the generation of the LVD reset source to the generation or release of the LVD reset From meeting the supply voltage (V DD )＜LVDDetection voltage (V LVD ) to generate LVDA delay occurs until the reset.
Page 667: Chapter 24 Security Features
Security Features 24.1 Overview In response to IEC60730 and EC61508 safety standards, the CMS32L051 has the following built-in safety features. The purpose of this safety function is to safely stop working when a fault is detected through self- diagnosis of the microcontroller.
Page 668: Registers Used By Security Functions
CMS32L051 User Manual |Chapter 24 Security Features 24.2 Registers used by security functions Each function of the safety function uses the following registers. Register name Functions of the security function • Flash CRC Control Register (CRC0CTL). Flash CRC operation function •...
Page 669 CMS32L051 User Manual |Chapter 24 Security Features Flash CRC control register (CRC0CTL) This is a register that sets the operating control and operation range of a high-speed CRC operator. The CRC0CTL register is set via an 8-bit memory operation command. After the reset signal is generated, the value of this register becomes “00H”.
Page 670 CMS32L051 User Manual |Chapter 24 Security Features 24.3.1.1 Flash CRC result register (PGCRCL). This is the register that holds the results of high-speed CRC operations. The PGCRCL register is set via a 16-bit memory operation command. After the reset signal is generated, the value of this register changes to “0000H”.
Page 671 CMS32L051 User Manual |Chapter 24 Security Features < Operation Flow > Figure 24-3 Flow chart of flash CRC operation function (high-speed CRC) Start save expected value of CRC calculation result to last 4 bytes ahead of time configure CRC calculation range...
Page 672: Crc Operation Function (General Crc)
CMS32L051 User Manual |Chapter 24 Security Features 24.3.2 CRC operation function (general CRC) In order to ensure safety during operation, the IEC61508 standard requires that the data need to be confirmed even in CPU operation. This generic CRC can be used as a peripheral function for CRC operations in CPU operation. Generic CRC is not limited to code flash areas but can be used for multi-purpose inspections.
Page 673 CMS32L051 User Manual |Chapter 24 Security Features 24.3.2.1 CRC input registers (CRCINs) This is the 8-bit register that sets the CRC calculation data for the general-purpose CRC. The range that can be set is “00H~FFH”. The CRCIN registers are set via 8-bit memory operation instructions. After the reset signal is generated, the value of this register becomes “00H”.
Page 674 CMS32L051 User Manual |Chapter 24 Security Features 24.3.2.2 CRC data register (CRCD) This is the register that holds the results of a general-purpose CRC operation. The range that can be set is “0000H~FFFFH”. After writing the CRCIN register, a CPU/peripheral hardware clock (f C LK) is passed to save the CRC operation results to the CRCD Register.
Page 675: Ram Parity Error Detection Function
CMS32L051 User Manual |Chapter 24 Security Features 24.3.3 RAM parity error detection function The IEC60730 standard requires confirmation of RAM data. Therefore, the CMS32L051's RAM appends 1-bit parity bit every 8 bits. The RAM parity error detection function appends parity bits when writing data, checks parity bits when reading data, and can produce a reset when parity errors occur.
Page 676 CMS32L051 User Manual |Chapter 24 Security Features Figure 24-8 Flow of RAM parity check parity check start Note PRERF=1 disable reset due to parity check error RAM parity check RAM parity check Read RAM parity check error occurs confirm parity check...
Page 677: Sfr Protection Function
CMS32L051 User Manual |Chapter 24 Security Features 24.3.4 SFR protection function In order to ensure safety during operation, the IEC61508 standard requires that even if the CPU is out of control, important SFRs need to be protected from overriding the SFR protection function for the protection of port functions, interrupt functions, clock control functions, voltage detection circuitry and RAM The parity error detection function controls the data of the register.
Page 678: Frequency Detection Function
CMS32L051 User Manual |Chapter 24 Security Features 24.3.5 Frequency detection function The IEC60730 standard requires confirmation of whether the oscillation frequency is normal. The frequency detection function uses the clock frequency (f ) of the CPU/peripheral hardware and can determine whether the ratio relationship between the two clocks is correct by measuring the Timer40 channel 1 input pulse.
Page 679: A/D Test Function
CMS32L051 User Manual |Chapter 24 Security Features 24.3.6 A/D test function The IEC60730 standard requires testing of A/D converters. This A/D test function is performed with a positive (+) reference voltage for the A/D converter, a negative (–) reference, an analog input channel (ANI), an output voltage for a temperature sensor, and an internal reference A/D conversion to confirm that the A/D converter is operating properly.
Page 680 CMS32L051 User Manual |Chapter 24 Security Features 24.3.6.1 A/D test registers (ADTES). This register selects the A/D converter's positive (+) reference, negative (–) reference, analog input channel (ANIxx), temperature sensor output voltage, and internal reference voltage (1.45V). as an A/D conversion object.
Page 681: Digital Output Signal Level Detection Function For Input/Output Pin
CMS32L051 User Manual |Chapter 24 Security Features 24.3.7 Digital output signal level detection function for input/output pin The IEC60730 standard requires confirmation of proper I/O functionality. The digital output signal level detection function of the input/output pin reads the digital output level of the pin when the pin is in output mode.
Page 682: Product Unique Identification Register
CMS32L051 User Manual |Chapter 24 Security Features 24.3.8 Product unique identification register A product's unique identification is ideal for: • Used as a serial number (e.g. USB character serial number or other terminal application). • Used as a password, this unique identifier is used in conjunction with a software encryption and decryption algorithm when writing flash memory to improve the security of the code in flash memory.
Page 683: Chapter 25 Temperature Sensor
CMS32L051 User Manual |Chapter 25 Temperature Sensor Chapter 25 Temperature Sensor 25.1 Function of temperature sensor The on-chip temperature sensor measures and monitors the core temperature of the product, thus ensuring the reliable operation of the product. The voltage output by the temperature sensor is proportional to the core temperature, and there is a linear relationship between voltage and temperature.
Page 684: Instructions For Use With The Temperature Sensor
CMS32L051 User Manual |Chapter 25 Temperature Sensor 25.3 Instructions for use with the temperature sensor 25.3.1 How the temperature sensor is used The temperature (T) is proportional to the sensor voltage output (Vs), so the temperature is calculated as follows: T = (Vs - V1) / slope + T1 T: Measured temperature (°...
Page 685: How To Use The Temperature Sensor
CMS32L051 User Manual |Chapter 25 Temperature Sensor 25.3.2 How to use the temperature sensor Method 1: In this product, the TSN25 register stores the voltage conversion value (CAL25) of the temperature sensor measured under the conditions of Ta=Tj=25° C and AVCC0=3.0v. The TSN85 register stores the voltage conversion values of the temperature sensor measured at Ta=Tj=125°...
Page 686: Chapter 26 Option Byte
26.1 Function of option byte CMS32L051's flash memory 000C0H~000C3H, 500004H is the option byte area. Option bytes consist of user option bytes (000C0H~000C2H) and flash data protection option bytes (000C3H, 500004H). When the power is turned on or reset starts, the specified function is automatically set by referring to the option byte.
Page 687: Flash Data Protection Option Bytes (000C3H, 500004H)
CMS32L051 User Manual |Chapter 26 Option Byte 26.1.2 Flash data protection option bytes (000C3H, 500004H). ⚫ Control of flash data protection during on-chip debugging Level0: Allows read/write/erase operations on flash data via debugger Level1: Allows hip full erase of flash data via debugger, not allowed to read or write operations.
Page 688: Format Of User Option Byte
CMS32L051 User Manual |Chapter 26 Option Byte 26.2 Format of user option byte Figure 26-1 Format of user option bytes (000C0H) Address: 000C0H Symbol WDTINT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYO Interval interruption of watchdog timer use/non-use WDTINT Interval interrupts are not used.
Page 689 CMS32L051 User Manual |Chapter 26 Option Byte Figure 26-2 Format of user option bytes (000C1H) (1/4) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt & reset mode) Detection voltage Setting value of the option byte...
Page 690 CMS32L051 User Manual |Chapter 26 Option Byte Figure 26-2 Format of User Option Bytes (000C1H) (2/4) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (reset mode) Detection voltage Setting value of the option byte Mode setting...
Page 691 CMS32L051 User Manual |Chapter 26 Option Byte Figure 26-2 Format of User Option Bytes (000C1H) (3/4) Note Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt mode). Detection voltage Setting value of the option byte Mode setting...
Page 692 CMS32L051 User Manual |Chapter 26 Option Byte Figure 26-2 Format of user option bytes (000C1H) (4/4) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD is OFF (Use RESETB External reset input for the pin) Detection The setting value of the option byte...
Page 693 CMS32L051 User Manual |Chapter 26 Option Byte Figure 26-3 Format of User Option Bytes (000C2H) Address: 000C2H FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 The clock frequency of the high- FRQSEL4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 speed internal oscillator HOCO 64MHz 64MHz 48MHz...
Page 694: Format Of Flash Data Protection Option Bytes
CMS32L051 User Manual |Chapter 26 Option Byte 26.3 Format of flash data protection option bytes The format of the Flash Data Protection Options byte is as follows. Figure 26-4 Format of flash data protection option bytes (000C3H) Address: 000C3H Symbol...
Page 695: Chapter 27 Flash Control
CMS32L051 User Manual |Chapter 27 FLASH Control Chapter 27 FLASH Control 27.1 Description of FLASH control This product contains a 64KByte capacity FLASH memory, divided into 128 sectors, each with capacity of 512-byte. It can be used as program memory, data memory. This module supports erasing, programming, and reading of this memory.
Page 696: Registers For Controlling Flash
CMS32L051 User Manual | FLASH Control 27.3 Registers for controlling FLASH The registers that control FLASH are as follows: Flash write protection register (FLPROT). ⚫ Flash operation control register (FLOPMD1, FLOPMD2). ⚫ Flash erase mode control register (FLERMD) ⚫ ⚫...
Page 697: Flash Operation Control Registers (Flopmd1, Flopmd2)
CMS32L051 User Manual | FLASH Control 27.3.2 FLASH operation control registers (FLOPMD1, FLOPMD2) Flash operation control registers for setting the erase and write operations of FLASH. Address: 0x40020004 After reset: 000000000H R/W symbol FLOPMD1 FLOPMD1[7:0] Address: 0x40020008 after reset: 00HR/W...
Page 698: Flash Status Register (Flsts)
CMS32L051 User Manual | FLASH Control 27.3.4 Flash status register (FLSTS) The status register allows you to query the status of the FLASH controller. Address: 0x40020000 after reset: 00HR/W Symbol FLSTS Note note The FLASH erasing operation is finished with the flag...
Page 699: Flash Sector Erase Time Control Register (Flsercnt)
CMS32L051 User Manual | FLASH Control 27.3.6 Flash sector erase time control register (FLSERCNT) the time of The FLSERCNT register allows the FLASH full film erase to be set. Address: 0x40020014 After reset: Indefinite symbol load FLSERCNT[9:0] FLSERCNT Erase the selection of the time setting Note...
Page 700: Flash Write Time Control Register (Flprocnt)
CMS32L051 User Manual | FLASH Control 27.3.7 Flash write time control register (FLPROCNT). The FLPROCNT register allows you to set the FLASH WORD write time. Address: 0x4002001C After reset: Indefinite symbol Load1 FLPGSCNT[8:0] Load0 FLPROCNT[8:0] FLPROCNT Write time (Tprog) setting Note...
Page 701: Flash Operation Method
CMS32L051 User Manual | FLASH Control 27.4 FLASH operation method 27.4.1 Sector erase Sector erase, and the erase time are implemented by hardware or can be configured by FLSERCNT. The operation flow is as follows: 1) Set FLERMD. ERMD0 is 1'b0,...
Page 702: Chip Erase
CMS32L051 User Manual | FLASH Control 27.4.2 Chip erase Chip erase, and the erase time are implemented by hardware and can also be configured via FLCERCNT. The operation process is as follows: 1) Set FLERMD. ERMD0 is 1'b 1, select chip erase mode;...
Page 703: Appendix Revision History
CMS32L051 User Manual | Appendix Revision History Appendix Revision History Version Date Revised content V1.0 2021/8/2 Initial version V1.1 2021/12/20 24.3.8: Modified the unique product identification address 20.4.2: Modified deep sleep mode release conditions and added V1.2 2022/05/19 some notes V1.2.1...

Cmsemicon CMS32L051 User Manual

Chapter 1 CPU

Chapter 2 Pin Function

Chapter 3 System Structure

Chapter 4 Clock Generation Circuit

Chapter 5 Universal Timer Unit (Timer4)

Chapter 6 Function of EPWM Output Control Circuit

Chapter 7 Real-Time Clock

Chapter 8 15-Bit Interval Timer

Chapter 9 Clock Output/Buzzer Output Controller

Chapter 10 Watchdog Timer

Chapter 12 Universal Serial Communication Unit

Chapter 13 Serial Interface SPI

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