Cmsemicon BAT32G137 User Manual

Ultra-low power 32-bit microcontroller based on arm cortex-m0+

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BAT32G137 User's Guide |Documentation Usage Instructions

BAT32G137 User Manual

Ultra-

power

-bit microcontroller based on ARM® Cortex®-M0+

low

Rev.2.1.1

Please be reminded about following CMS's policies on intellectual property

＊Cmsemicron Limited(denoted as 'our company' for later use) has already applied for relative patents and entitled legal rights. Any patents

related to CMS's MCU or other producrts is not authorized to use. Any individual, organization or company which infringes s our company's

interlectual property rights will be forbidden and stopped by our company through any legal actions, and our company will claim the lost and

required for compensation of any damage to the company.

＊ The name of Cmsemicron Limited and logo are both trademarks of our company.

＊Our company preserve the rights to further elaborate on the improvements about products' function, reliability and design in this manual.

However, our company is not responsible for any usage about this munal. The applications and their purposes in this manual are just for

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Page 1 BAT32G137 User's Guide |Documentation Usage Instructions BAT32G137 User Manual Ultra- power -bit microcontroller based on ARM® Cortex®-M0+ Rev.2.1.1 Please be reminded about following CMS’s policies on intellectual property ＊Cmsemicron Limited(denoted as ‘our company’ for later use) has already applied for relative patents and entitled legal rights. Any patents related to CMS’s MCU or other producrts is not authorized to use.
Page 2: Documentation Instructions
BAT32G137 User's Guide |Documentation Usage Instructions Documentation Instructions This manual is the technical reference manual for the BAT32G137 microcontroller product. The technical reference manual is the application instruction material on how to use this series of products, including the structure, function description, working mode and register configuration of each functional module.
Page 3: Table Of Contents
BAT32G137 User's Guide |Documentation Usage Instructions Index Documentation Instructions ................... 2 Chapter 1 CPU ........................20 verview................................... 20 Cortex-M0+ core features ............................20 Debug features ..............................20 SWD interface pin ..............................22 ARM reference document ............................23 Chapter 2 Pin function ......................24 port function ................................
Page 4 BAT32G137 User's Guide |Documentation Usage Instructions 4.3.9 High speed internal oscillator fine-tuned register (HIOTRM) ................73 System clock oscillating circuit ..........................74 4.4.1 X1 oscillating circuit ............................. 74 4.4.2 XT1 oscillating circuit ............................74 4.4.3 high speed internal oscillator ..........................78 4.4.4...
Page 5 BAT32G137 User's Guide |Documentation Usage Instructions 6.3.9 timer output allow register m (TOEm) ........................ 126 6.3.10 Timer output register m (TOm) .......................... 127 6.3.11 Timer output level register m (TOLm) ........................ 128 6.3.12 Timer output mode register m (TOMm) ......................129 6.3.13 Input switch control register (ISC) ........................
Page 6 BAT32G137 User's Guide |Documentation Usage Instructions 7.3.3 timer A count register 0 (TA0)..........................202 7.3.4 timer A control register 0 (TACR0)........................203 7.3.5 Timer AI/O control register 0 (TAIOC0) ......................204 7.3.6 timer A control register 0 (TAMR0)........................206 7.3.7...
Page 7 BAT32G137 User's Guide |Documentation Usage Instructions 8.4.1 Common Issues Concerning Multiple Models and Functions ................236 8.4.2 timer mode (input capture function) ........................241 8.4.3 timer mode (output comparison function) ......................244 8.4.4 PWM mode ................................ 248 8.4.5 phase counting mode ............................252 timer B interrupt ..............................
Page 8 BAT32G137 User's Guide |Documentation Usage Instructions 10.3 Register for controlling timer M ..........................278 10.3.1 Peripheral Enable Register 1 (PER1) ........................ 279 10.3.2 timer M EVENTC register (TMELC) ........................280 10.3.3 Timer M Start Register (TMSTR) ........................281 10.3.4 timer M mode register (TMMR) .......................... 282 10.3.5 Timer M PWM Function Selection Register (TMPMR) ..................
Page 9 BAT32G137 User's Guide |Documentation Usage Instructions 10.8 PWMOP ................................370 10.8.1 Features of PWMOP ............................371 10.8.2 Register for PWMOP ............................371 10.8.3 Running of PWMOP ............................377 10.8.3.1 output forced cut-off ............................377 10.8.3.2 Hardware Undoing (HS_SEL=0) ........................377 10.8.3.3 Software Undoing (HS_SEL=1) ........................
Page 10 BAT32G137 User's Guide |Documentation Usage Instructions 12.3.1 Peripheral Enable Register 0 (PER0)........................ 424 12.3.2 Real-time clock selection register (RTCCL) ....................... 425 12.3.3 Control register for 15-bit interval timer (ITMC) ....................426 12.4 Operation of a 15-bit interval timer ........................427 12.4.1 Run-time sequence of 15-bit interval timer ......................
Page 11 BAT32G137 User's Guide |Documentation Usage Instructions 15.2.12 A/D Sample Time Extension Register (ADSMPWAIT) ..................460 15.2.13 A/D test register (ADTES) ..........................461 15.2.14 A/D status register (ADFLG) ..........................462 15.2.15 A/D charge/discharge control register (ADNDIS) ....................463 15.2.16 Register for controlling analog input pin port function ..................464 15.3...
Page 12 BAT32G137 User's Guide |Documentation Usage Instructions 17.3.1 Peripheral Enable Register 1 (PER1) ........................ 496 17.3.2 Comparator mode set-up register (COMPMDR) ....................497 17.3.3 Comparator filter control register (COMPFIR) ....................498 17.3.4 Comparator output control register (COMPOCR) ....................500 17.3.5 Comparator built-in reference voltage control register (CVRCTL) ..............502 17.3.6 Comparator built-in reference voltage selection register (CiRVM) ..............
Page 13 BAT32G137 User's Guide |Documentation Usage Instructions 19.3.10 Serial channel allows state register m (SEm)....................542 19.3.11 Serial output allows register m (SOEm) ......................543 19.3.12 Serial output register m (SOm).......................... 544 19.3.13 Serial output level register m (SOLm) ........................ 545 19.3.14 Input switch control register (ISC) ........................
Page 14 BAT32G137 User's Guide |Documentation Usage Instructions 20.1 The Function of Serial Interface IICA ........................682 20.2 Structure of Serial Interface IICA ......................... 685 20.3 Register for controlling serial interface IICA ......................688 20.3.1 Peripheral Enable Register 0 (PER0)........................ 689 20.3.2 IICA control register n0 (IICCTLn0) ........................
Page 15 BAT32G137 User's Guide |Documentation Usage Instructions 21.2.5 overload frame ..............................781 21.3 Features................................782 21.3.1 bus priority setting ............................. 782 21.3.2 bit filling ................................782 21.3.3 multi-master ............................... 782 21.3.4 multicast ................................782 21.3.5 CAN Sleep Mode/CAN Stop Mode Features ..................... 782 21.3.6 error control function ............................
Page 16 BAT32G137 User's Guide |Documentation Usage Instructions 21.13.4 Receive/Send Operation in Operation Mode ..................... 874 21.14 timestamp function ............................... 875 21.14.1 timestamp function ............................875 21.15 Baud rate setting ..............................877 21.15.1 Baud rate setting ............................... 877 21.15.2 Representative example of baud rate setting ....................881 21.16...
Page 17 BAT32G137 User's Guide |Documentation Usage Instructions 23.5.4 Response time for DMA ............................ 946 23.5.5 Start Source for DMA ............................946 23.5.6 Operation in standby mode ..........................947 Chapter 24 Coordination Controller(EVENTC) ..............948 24.1 Features of EVENTC ............................948 24.2 Structure of EVENTC ............................
Page 18 BAT32G137 User's Guide |Documentation Usage Instructions Chapter 30 voltage detection circuit .................. 995 30.1 Function of Voltage Detection Circuit ........................995 30.2 Structure of voltage detection circuit ........................996 30.3 Register for controlling voltage detection circuit ....................997 30.1.1 Voltage detection register (LVIM) ........................997 30.3.1 Voltage detection level register (LVIS) ......................
Page 19 BAT32G137 User's Guide |Documentation Usage Instructions 33.1 Feature of option bytes ............................1032 33.1.1 User Option Bytes (000C0H~000C2H/010C0H~010C2H) ................1032 33.1.2 Flash Data Protection Option Bytes (000C3H/010C3H,50004H~500005H) ............ 1034 33.2 Format of user option bytes ..........................1035 33.3 Format of Flash Data Protection Option bytes ....................1041 Chapter 34 FLASH control ....................
Page 20: Chapter 1 Cpu
BAT32G137 user manual | Chapter 1 CPU Chapter 1 CPU 1.1 verview This Chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+ kernel on which this product is built. Please refer to the ARM documentation for details.
Page 21 BAT32G137 user manual | Chapter 1 CPU Debug Block Diagram for Cortex-M0+ Figure 1-1 MCU debug support Cortex - M0+ debug support Cortex - M0+ system bus core bus matrix Bridge SWDIO SW - DP AHB - AP SWCLK NVIC DBGMCU Note: SWD does not work in Deep Sleep mode, please debug in active and sleep mode.
Page 22: Swd Interface Pin
BAT32G137 user manual | Chapter 1 CPU 1.4 SWD interface pin 2 GPIO of the product can be used as SWD interface pins that are present in all packages. Table 1-1 SWD Debug Port Pin SWD port name Debug Function...
Page 23: Arm Reference Document
BAT32G137 user manual | Chapter 1 CPU 1.5 ARM reference document The built-in debugging features in the Cortex®-M0+ kernel are part of the ARM® CoreSight design suite. For documentation, refer to: Cortex®-M0+ Technical Reference Manual (TRM) ⚫ ARM® Debug Interface V5 ⚫...
Page 24: Chapter 2 Pin Function
BAT32G137 user manual | Chapter 2 Pin function Chapter 2 Pin function 2.1 port function Refer to datasheet for each product family. 2.2 port multiplex Refer to datasheet for each product family. www.mcu.com.cn 24 / 1052 V2.1.1...
Page 25: Register For Controlling Port Function
BAT32G137 user manual | Chapter 2 Pin function 2.3 Register for controlling port function Control the port through the following registers. • Port Mode Registers (PMxx) • Port Registers (Pxx) • Pull-up resistor selection registers (PUxx) • Port Input Mode Registers (PIMx) •...
Page 26 BAT32G137 user manual | Chapter 2 Pin function Table 2-2: PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and bits (2/2) bit name Port PMxx PUxx PIMxx POMxx PMCxx register register register register register register — — ○ ○ ○ ○...
Page 27: Port Mode Register (Pmxx)
BAT32G137 user manual | Chapter 2 Pin function 2.3.1 Port Mode Register (PMxx) This is a register that sets the port input/output in bits. After the reset signal is generated, the values of these registers become "FFH". When using a port pin as a pin for a multiplexing function, it must be configured according to reference to "2.5 Register settings when using multiplexing function”.
Page 28: Port Register (Pxx)
BAT32G137 user manual | Chapter 2 Pin function 2.3.2 Port Register (Pxx) This is a register that sets the value of the port output latch in bits. The pin level is read in the input mode and the output latch value of the port is read in the output mode. After the reset signal is generated, the values of these registers change to '00H'.
Page 29: Pull-Up Resistance Selection Register (Puxx)
BAT32G137 user manual | Chapter 2 Pin function 2.3.3 Pull-up resistance selection register (PUxx) Selection register for internal pull-up resistance. Internal pull-up resistors can only be used in bit units if the POMmn bit is '0' and set to the input mode (PMmn=1). For the bit set to the output mode, the internal pull-up resistor is not connected regardless of the setting of the pull-up resistor selection register.
Page 30: Port Input Mode Register (Pimxx)
BAT32G137 user manual | Chapter 2 Pin function 2.3.4 Port input mode register (PIMxx) This is a register that sets the input buffer in bits. The TTL input buffer can be selected in serial communication with external devices of different potentials. After the reset signal is generated, the values of these registers change to '00H'.
Page 31: Port Output Mode Register (Pomxx)
BAT32G137 user manual | Chapter 2 Pin function 2.3.5 Port output mode register (POMxx) This is a register that sets the output mode in bits. When serial communication is performed with external devices of different potentials and simple I2C communication is performed with external devices of same potential, N channel drain open output mode is selected for SDAxx pin.
Page 32: Port Mode Control Register (Pmcxx)
BAT32G137 user manual | Chapter 2 Pin function 2.3.6 Port mode control register (PMCxx) A digital input/output or analog input that is set in bits by the PMC register. After the reset signal is generated, the values of these registers become "FFH".
Page 33: Peripheral I/O Redirection Register 0 (Pior0)
BAT32G137 user manual | Chapter 2 Pin function 2.3.7 Peripheral I/O Redirection Register 0 (PIOR0) This is register 0 that sets the ability to allow or prohibit peripheral I/O redirection. The peripheral I/O redirection function switches ports to which multiplexing is assigned.
Page 34 BAT32G137 user manual | Chapter 2 Pin function INTP3 INTP4 INTP8 INTP9 www.mcu.com.cn 34 / 1052 V2.1.1...
Page 35: Peripheral I/O Redirection Register 1 (Pior1)
BAT32G137 user manual | Chapter 2 Pin function 2.3.8 Peripheral I/O Redirection Register 1 (PIOR1) This is setting to allow or disable peripheral I/O redirection feature register 1. The peripheral I/O redirection function switches ports to which multiplexing is assigned.
Page 36: Peripheral I/O Redirection Register 2 (Pior2)
BAT32G137 user manual | Chapter 2 Pin function 2.3.9 Peripheral I/O Redirection Register 2 (PIOR2) This is setting to enable or disable peripheral I/O redirection feature register 2. The peripheral I/O redirection function switches ports to which multiplexing is assigned. After the reset signal is generated, the value of this register changes to "00H".
Page 37: Peripheral I/O Redirection Register 3 (Pior3)
BAT32G137 user manual | Chapter 2 Pin function 2.3.10 Peripheral I/O Redirection Register 3 (PIOR3) This is setting to enable or disable peripheral I/O redirection feature register 3. The peripheral I/O redirection function switches ports to which multiplexing is assigned. After the reset signal is generated, the value of this register changes to "00H".
Page 38 BAT32G137 user manual | Chapter 2 Pin function PIOR37 PIOR36 TMIA0 TMIOB0 TMIOC0 TMIOD0 TMIA1 TMIOB1 TMIOC1 TMIOD1 P1 0 P1 3 P1 1 P1 1 P1 0 P1 3 P1 3 P1 1 P1 0 Disable setting Note: x indicates that the bit must be set to the initial value of 0.
Page 39: Handling Of Unused Pins
BAT32G137 user manual | Chapter 2 Pin function 2.4 Handling of unused pins The handling of each unused pin is as following Table2-3. Table2-3 Handling of each unused pin name of Input/Output Recommended connection method when not in use the pin P00~P06 Input : The EVDD or EVSS are connected by resistance alone .
Page 40: Register Settings When Using Multiplexing
BAT32G137 user manual | Chapter 2 Pin function 2.5 Register Settings When Using Multiplexing 2.5.1 The Basic principal of Using Multiplexing Function First, you must set the pins that can be multiplexed with the analog function to either been used as the analog function or as the digital input/output through port mode control register (PMCxx).
Page 41: Examples Of Register Settings For Port And Multiplexing Functions Used
BAT32G137 user manual | Chapter 2 Pin function 2.5.2 Examples of Register Settings for Port and Multiplexing Functions Used Examples of register settings (64 pin products) using port functions and multiplexing functions are shown in Tables 2-5 through 2-10. Table 2-5: Example of Register Setting When Using the P00~P06 Pin Function...
Page 42 BAT32G137 user manual | Chapter 2 Pin function — — — SCL10 output — — — — — Input × — — — — — output — — — — Input × (INTP10) PIOR01=1 — — — — — Input ×...
Page 43 BAT32G137 user manual | Chapter 2 Pin function — — × — — Input TMIOB0 PIOR37=0, PIOR36=1 — — — output SDO11=1 — — × — — Input TMIOB1 PIOR37=1, PIOR36=0 — — — output SDO11=1 — — × —...
Page 44 BAT32G137 user manual | Chapter 2 Pin function Table 2-6: Example of Register Setting When Using the P10~P17 Pin Function (3/3) Functions Used Output of multiplexing functions name of PIORx POMxx PMCxx PMxx Feature SCI's the feet Input/Output Outside SCI...
Page 45 BAT32G137 user manual | Chapter 2 Pin function Table 2-7: Example of Register Setting When Using the P20~P27 Pin Function Functions Used name of the PIORx PMCxx PMxx feet Feature Name Input/Output — × Input — output — × ANI0...
Page 46 BAT32G137 user manual | Chapter 2 Pin function Table 2-8: Example of Register Setting When Using the P30~P43 Pin Function Functions Used Output of multiplexing functions name of PIORx POMxx PMCxx PMxx Feature SCI's the feet Input/Output Outside SCI Name output function —...
Page 47 BAT32G137 user manual | Chapter 2 Pin function Table 2-9: Example of Register Setting When Using the P50~P55 Pin Function Functions Used Output of multiplexing functions name of PIORx POMxx PMCxx PMxx Feature Output Function of the feet Input/Output Beyond SCI/CAN...
Page 48 BAT32G137 user manual | Chapter 2 Pin function Table 2-10: Example of Register Setting When Using the P60~P63 Pin Function Functions Used Output of multiplexing functions name of PIORx POMxx PMCxx PMxx Feature SCI's the feet Input/Output Outside SCI Name output function —...
Page 49 BAT32G137 user manual | Chapter 2 Pin function Table 2-11: Example of Register Setting When Using the P70~P77 Pin Function Functions Used Output of multiplexing functions name of PIORx POMxx PMCxx PMxx Feature SCI's the feet Input/Output Outside SCI Name output function —...
Page 50 BAT32G137 user manual | Chapter 2 Pin function — — — — — × Input — — — — × INTP11 Input PIOR01=0, PIOR07=0 — — — — (TxD2) output PIOR01=1 Figure 2-12: Example of Register Setting When Using the P120 Pin Feature...
Page 51: Chapter 3 System Structure
BAT32G137 user manual | Chapter 3 system structure Chapter 3 system structure 3.1 Overview This product system consists of the following components: 2 AHB buses Master: ⚫ - Cortex-M0+ - Enhanced DMA 4 AHB buses Slaves: ⚫ - FLASH Storage...
Page 52: System Address Partitioning
BAT32G137 user manual | Chapter 3 system structure 3.2 system address partitioning Figure3-2 Map of Address Area FFFF_FFFFH reserve E00F_FFFFH Cortex-M0+ specific resource region for peripherals E000_0000H reserve 4005_FFFFH resource region for peripherals 4000_0000H reserve 2000_2FFFH SRAM （max 12KB） 2000_0000H...
Page 53 BAT32G137 user manual | Chapter 3 system structure peripheral address assignment Table3-1 Register group start address for peripheral Start Address peripheral Remark 0x4000_000 - 0x4000_4FFF Reserve 0x4000_5000 - 0x4000_5FFF 0x4000_6000 - 0x4000_6FFF interrupt control 0x4000_7000 - 0x4001_8FFF Reserve 0x4001_9000 - 0x4001_9FFF...
Page 54: Chapter 4 Clock Generator
BAT32G137 user manual | Chapter 4 clock generator Chapter 4 clock generator The presence of resonator connection pin/external clock input pin for the main system clock and the resonator connection pin/external clock input pin for the secondary system clock are different among products.
Page 55 BAT32G137 user manual | Chapter 4 clock generator sub-system clock · XT1 oscillating circuit The XT1 pin and XT2 pin a 32.768kHz resonator to oscillate the clock with are connected to fXT=32.768kHz and to stop the oscillation by setting a XTSTOP bit (bit6 of the clock operation status control register (CSC)).
Page 56: Structure Of Clock Generating Circuit
BAT32G137 user manual | Chapter 4 clock generator 4.2 Structure of clock generating circuit The clock generating circuit is composed of the following hardware. Table4-1 Structure of clock generating circuit Project structure Clock Run Mode Control Register (CMC) System Clock Control Register (CKC)
Page 57 BAT32G137 user manual | Chapter 4 clock generator Figure4-1 Block diagram of clock generating circuit www.mcu.com.cn 57 / 1052 V2.1.1...
Page 58: Register For Controlling Clock Generation Circuit
BAT32G137 user manual | Chapter 4 clock generator Remark : X1 clock oscillation frequency : Clock frequency of high speed internal oscillator (maximum 64MHz) fHOCO oscillator : Clock frequency (maximum 48 MHz) of high-speed internal : External master clock frequency...
Page 59: Clock Run Mode Control Register (Cmc)
BAT32G137 user manual | Chapter 4 clock generator 4.3.1 Clock Run Mode Control Register (CMC) This is a register that sets the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, XT2/EXCLKS/P124 pin and selects the gain of the oscillating circuit. The CMC register can only be written 1 time by the 8-bit memory operation instruction after reset. The register can be read by an 8-bit memory operation instruction.
Page 60: System Clock Control Register (Ckc)
BAT32G137 user manual | Chapter 4 clock generator 5. The stability time of fXT must be counted by software. 6. The upper limit of the system clock is 48MHz, but the upper limit of the X1 oscillator circuit is 20MHz.
Page 61: Clock Operational Status Control Register (Csc)
BAT32G137 user manual | Chapter 4 clock generator Note: 1. bit0~3 must be set to 0. 2. Provides CSS bit setting clocks for the CPU and peripheral hardware. If you change the CPU clock, change the peripheral hardware clock at the same time (except for real-time clocks, 15-bit interval timers, clock output/buzzer output, and watchdog timer).
Page 62 BAT32G137 user manual | Chapter 4 clock generator confirmed by OSTC. When you want to start XT1 oscillation by setting the XSTOP bit, you must wait for the oscillation stabilization time required by the secondary system clock through software. The clock selected as the CPU/peripheral hardware clock ( ) cannot be stopped the CSC register.
Page 63: State Register Of The Oscillation Stabilization Time Counter (Ostc)
BAT32G137 user manual | Chapter 4 clock generator 4.3.4 State register of the oscillation stabilization time counter (OSTC). This is a register that represents the count state of the oscillating steady-time counter of the X1 clock. The oscillation stability time of the X1 clock can be confirmed under the following circumstances:...
Page 64 BAT32G137 user manual | Chapter 4 clock generator Figure4-5 The Format of State Register (OSTC) for Oscillatory Stable Time Counters Address: 40020402H After reset: 00H symbol OSTC MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 oscillatory steady-time state MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18...
Page 65: Oscillating Stable Time Select Register (Osts)
BAT32G137 user manual | Chapter 4 clock generator 4.3.5 Oscillating Stable Time Select Register (OSTS) This is a register that selects the oscillation steady time of the X1 clock. If the X1 clock is oscillated, the time set by the OSTS register is automatically waited after the X1 oscillation circuit (MSTOP=0).
Page 66: Peripheral Enable Registers 0, 1 (Per0, Per1)
BAT32G137 user manual | Chapter 4 clock generator 4.3.6 Peripheral Enable Registers 0, 1 (PER0, PER1) This is a register that sets a clock that is enabled or disabled for each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 67 BAT32G137 user manual | Chapter 4 clock generator Figure4-7 Format of Peripheral Enable Register 0 (PER0) (2/3) Location: 40020420H After reset: 00H symbol PER0 ICAHN RTCEN IRDEN ADCEN SCI1EN SCI0EN CAN0 TM40E Provides control of input clock for serial interface IICA1 IRDEN Stop provide an input clock.
Page 68 BAT32G137 user manual | Chapter 4 clock generator Figure4-7 Format of Peripheral Enable Register 0 (PER0) (3/3) Location: 40020420H After reset: 00H symbol PER0 ICAHN RTCEN IRDEN ADCEN SCI1EN SCI0EN CAN0 TM40EN Control of input clock of CAN module CAN0 Stop provide an input clock.
Page 69 BAT32G137 user manual | Chapter 4 clock generator TMMEN Note Control of an input clock of a timer M is provided Stop provide an input clock. · SFR used by timer M cannot be written. · The timer M is in a reset state.
Page 70 BAT32G137 user manual | Chapter 4 clock generator Control of an input clock of timer A is provided TMAEN Stop provide an input clock. · SFR used by timer A cannot be written. · Timer A is in a reset state.
Page 71: Secondary System Clock Provides Mode Control Register (Osmc)
BAT32G137 user manual | Chapter 4 clock generator 4.3.7 Secondary system clock provides mode control register (OSMC) The OSMC register is a register that reduces power consumption by stopping an unwanted clock function. If that RTCLPC position" 1", the clock is stop supplied to peripheral functions other than the real-time clock and the 15-bit interval timer in deep sleep mode or sleep mode of the CPU running with a secondary system clock.
Page 72: Frequency Selection Register (Hocodiv) For High Speed Internal Oscillator
BAT32G137 user manual | Chapter 4 clock generator 4.3.8 Frequency selection register (HOCODIV) for high speed internal oscillator. This is a register that changes the high-speed internal oscillator frequency set by the option byte (000C2H). However, the frequency that can be selected varies depending on the values of the FRQSEL4 bit and FRQSEL3 bit of the option byte (000C2H).
Page 73 BAT32G137 user manual | Chapter 4 clock generator 4.3.9 High speed internal oscillator fine-tuned register (HIOTRM) This is a register that corrects the accuracy of the high speed internal oscillator. Self-measurement of the frequency of the high speed internal oscillator and accuracy correction can be performed using a timer or the like with a high precision external clock input.
Page 74 BAT32G137 user manual | Chapter 4 clock generator 4.4 System clock oscillating circuit 4.4.1 X1 oscillating circuit The X1 oscillation circuit oscillates by a crystal resonator or a ceramic resonator (1 to 20MHz) connecting the X1 pin. An external clock can also be input, at which time a clock signal must be input to the EXCLK pin.
Page 75 BAT32G137 user manual | Chapter 4 clock generator Figure4-13 Example of External Circuit of XT1 Oscillation Circuit Note: To avoid the effect of wiring capacitance or the like when using the X1 oscillator circuit and the XT1 oscillator circuitFigure4-12andFigure4-13The dotted section in routes: ·...
Page 76 BAT32G137 user manual | Chapter 4 clock generator incorrect resonator connection examples such asFigure4-14in the Figure4-14 Examples of incorrect resonator connections (1/2) (a) The wiring of the connection circuit is too long (b) Signal line crossing PORT (c) Cross-wiring of signal lines for X1 and X2...
Page 77 BAT32G137 user manual | Chapter 4 clock generator Figure4-14 Examples of incorrect resonator connections (2/2) (f) Current flows along grounding of oscilation circuit (e) varying high current source close to singal lines (Point A, B, C has difference in electric potential)
Page 78 BAT32G137 user manual | Chapter 4 clock generator 4.4.3 high speed internal oscillator The BAT32G137 has a built-in high speed internal oscillator. Frequency can be selected from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, 2MHz, 1MHz and via option bytes (000C2H). The CPU clock is 2-division clock when 64MHz is selected.
Page 79 CPU/peripheral hardware clock fCLK The CPU starts to run through the output of the high speed internal oscillator after the BAT32G137 is reset-free. The operation of the clock generating circuit when the power is turned on is as shown in Figure4- www.mcu.com.cn...
Page 80 BAT32G137 user manual | Chapter 4 clock generator Figure4-15 Operation of clock generating circuit when power is turned on at least 10us low limit of working voltage range voltage of power source (V power on reset signal RESETB pin switching via...
Page 81 BAT32G137 user manual | Chapter 4 clock generator 4.6 clock control 4.6.1 Example of high speed internal oscillator set-up The CPU/peripheral hardware clock ( ) must run at high internal oscillator clock. High speed internal oscillator fCLK frequencies can be selected from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, 2MHz and 1MHz by FRQSEL0~FRQSEL4 bits of option bytes (000C2H).
Page 82 BAT32G137 user manual | Chapter 4 clock generator [Setting of HOCODIV for high speed internal oscillator] Address: 0x40021C20 symbol HOCODIV HOCODIV2 HOCODIV1 HOCODIV0 Selection of Clock Frequency of High Speed Internal Oscillator FRQSEL4=0 FRQSEL4=1 HOCODIV2 HOCODIV1 HOCODIV0 FRQSEL3=0 FRQSEL3=1 FRQSEL3=0...
Page 83 BAT32G137 user manual | Chapter 4 clock generator 4.6.2 An example of X1 oscillation circuit The CPU/peripheral hardware clock ( ) must run at high internal oscillator clock. Thereafter, if the X1 fCLK oscillating clock is changed, setting of the oscillating circuit and controlling the oscillation start are performed...
Page 84 BAT32G137 user manual | Chapter 4 clock generator 4.6.3 Setting example of XT1 oscillation circuit The CPU/peripheral hardware clock ( ) must run at high internal oscillator clock. After that, the setting fCLK of the oscillation circuit and the control of the oscillation start are performed by the sub-system clock supply...
Page 85 BAT32G137 user manual | Chapter 4 clock generator 4.6.4 CPU Clock State Transition Diagram The CPU clock state transition diagram of this product is as shown in Figure4-16. Figure4-16 CPU Clock State Transition Diagram Power on X1 oscilation / EXCLK input: stop (input port mode)
Page 86 BAT32G137 user manual | Chapter 4 clock generator Examples of CPU clock transfer and SFR register setting are in theTable4-3 Table4-3 Examples of CPU clock transfer and SFR register set-up (1/5) (1). After the reset (A) is released, the CPU is transferred to the high speed internal oscillator clock operation (B).
Page 87 BAT32G137 user manual | Chapter 4 clock generator Remarks: 1.×: Ignore 2. Table 4-3 (A)-I corresponding to (A)-(I) FIG. Table4-3 Examples of CPU clock transfer and SFR register set-up (2/5) (4). The CPU is transferred from a high speed internal oscillator clock operation (B) to a high speed system clock operation (C).
Page 88 BAT32G137 user manual | Chapter 4 clock generator Remarks: 1.×: Ignore 2. Table 4-3 (A)-I corresponding to (A)-(I) FIG. Table4-3 Examples of CPU clock transfer and SFR register set-up (3/5) (6). The CPU is transferred from a high-speed system clock operation (C) to a high speed internal oscillator clock operation (B).
Page 89 BAT32G137 user manual | Chapter 4 clock generator (Order in which SFR registers are set) Settings flag for SFR register CSC register CKC register OSTS state transition OSTC register register MSTOP (D) → (C) Confirmation Note ≤10MHz) (X1 clock: 1MHz≤...
Page 90 BAT32G137 user manual | Chapter 4 clock generator Table 4-3 Examples of CPU clock transfer and SFR register set-up (5/5) (11)· The CPU is transferred to a deep sleep mode (H) in high speed internal oscillator clock operation. · The CPU is transferred to a deep sleep mode (I) in a high speed system clock operation.
Page 91 BAT32G137 user manual | Chapter 4 clock generator 4.6.5 Conditions before CPU clock transfer and post-transfer processing The conditions before and after the CPU clock transfer are as follows. Table4-4 Transfer of CPU clock (1/3) CPU Clock Before After Conditions before transfer...
Page 92 BAT32G137 user manual | Chapter 4 clock generator Table4-4 Transfer of CPU clock (2/2) CPU Clock Before After Conditions before transfer Post-transfer processing Transfer Transfer high speed A high speed internal oscillator is oscillating internal and a high speed internal is selected...
Page 93 BAT32G137 user manual | Chapter 4 clock generator 4.6.6 Time required to switch CPU clock and main system clock It can switch CPU clock (main system clock↔sub system clock) and main system clock (high speed internal oscillator clock↔high speed system clock) by setting bit6 and bit4 (CSS, MCM0) of system clock control register.
Page 94 BAT32G137 user manual | Chapter 4 clock generator 4.6.7 Conditions before clock oscillation stops The register flag settings for stopping clock oscillations (invalid external clock input) and the conditions before stopping are as follows. Table4-8 Condition and flag setting before clock oscillation stops...
Page 95 BAT32G137 user manual | Chapter 5 hardware divider Chapter 5 hardware divider The hardware divider is dedicated hardware that supports high-performance computing. The hardware divider is a 32-bit signed integer divider that outputs a 32-bit signed quotient and remainder result.
Page 96 BAT32G137 user manual | Chapter 5 hardware divider 5.3.1 division register (DIVIDEND) The divisor register is a register that holds the divisor and its value participates in the division operation as a 32-bit signed integer. DIVIDEN [31:24] DIVIDEN [23:16] DIVIDEN [15:8] DIVIDEN [7:0] 5.3.2 Divisor register (DIVISOR)
Page 97 BAT32G137 user manual | Chapter 5 hardware divider 5.3.5 status register (STATUS) The status of the hardware divider can be queried through the status register, including the zero-division flag and the BUSY flag. Reserve Reserve Reserve DIVBYZE BUSY Reserve DIVBYZERO Used to indicate the case of a division, updated each time the division register is written.
Page 98 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Chapter 6 Universal Timer Unit Timer4 The product is carried with a universal timer unit and contains four channels. The number of channels of the universal timer unit varies depending on the product. See table below:...
Page 99 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 The universal timer unit has four 16-bit timers. Each 16-bit timer is called a "channel" and can be used as a separate timer or a combination of multiple channels for advanced timer functions.
Page 100 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.1 Function of universal timer unit The universal timer unit has the following functions: 6.1.1 Stand-alone channel operation Independent channel operation function is independent of the other channel operation mode to use any channel function.
Page 101 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Measurement of High and Low Level Width of Input Signal The input signal of the TImn is counted at one edge of the input pin at the timer and the count value is captured at the other edge, thereby measuring the high and low level width of the input signal.
Page 102 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.1.2 multi-channel coordinated operation function The multi-channel coordinated operation function is a function which combines the main control channel (the reference timer of the main control period) and the subordinate channel (the timer which follows the main control channel).
Page 103 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Note: For details on the Multi-Channel Coordinated Operation Functional Rules, refer to "6.4.1 Basic Rules for Multi- Channel Coordinated Operation Functions. m: Cell number (m=0,1)n: Channel number (n=0~3)p,q: Slave channel number (n<p<q≤ 3) Note: 6.1.3 8-bit timer operation function (only for channel 1 and channel 3 of unit 0).
Page 104 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.2 Structure of universal timer unit The universal timer unit consists of the following hardware. Table 6-1 Structure of universal timer unit Project structure counter timer count register mn (TCRmn).
Page 105 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Whether the timer input/output pins of each channel of the universal timer unit are different depends on the product. Table 6-2 The products have timer input/output pins. Whether the Input/Output Pins of Each Product Have...
Page 106 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 The block diagram of the universal timer unit is shown in Figure 6-1. Figure6-1 Overall block diagram of universal timer unit 0 Timer clock selection register0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000...
Page 107 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.2.1 Universal timer unit register list Register Base Address: 0x40041C00 Read and Write offset address register name bit width Reset Value Properties 0x180 TCR00 FFFFFH 0x182 TCR01 FFFFFH 0x184 TCR02...
Page 108 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.2.2 Timer count register mn (TCRmn). The TCRmn register is a 16-bit read-only register that counts the count clock. Count is increased or decreased in synchronization with the rising edge of the count clock.
Page 109 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 As shown below, the read value of the TCRmn register varies depending on the mode and state of operation. Table 6-3: Read value of timer count register mn (TCRmn) in each running mode...
Page 110 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.2.3 timer data register mn (TDRmn) This is a 16-bit register that can be used for switching between capture and comparison functions. The operation mode is selected by the MDmn3~MDmn0 bit of the timer mode register mn(TMRmn) to switch the capture function and comparison function.
Page 111 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3 Register for controlling universal timer unit The registers that control the universal timer units are as follows: · Peripheral Enable Register 0 (PER0). · Timer clock selection register m (TPSm) ·...
Page 112 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.1 Peripheral Enable Register 0 (PER0) The PER0 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 113 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.2 Timer Clock Select Register m (TPSm). The TPSm register is a 16-bit register that selects two or four common runtime clocks (CKm0, CKm1, CKm2, CKm3). CKm0 is selected by bit3~0 of the TPSm register and CKm1 is selected by bit7~4 of the TPSm register. In addition, only channel 1 and channel 3 can select CKm2 and CKm3, select CKm2 by bit9~8 of TPSm register, and select CKm3 by bit13 and bit12 of TPSm register.
Page 114 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-6 Table (1/2) of timer clock selection register m (TPSm) symbol TPSm CKmk) Selection note for runtime clock ( (k=0,1) =2MHz =4MHz =8MHz =20MHz =32MHz fCLK fCLK fCLK fCLK...
Page 115 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-7 Table (2/2) of timer clock selection register m (TPSm) symbol TPSm CKm2) Selection Note for Runtime Clock ( PRSm21 PRSm20 =2MHz =4MHz =8MHz =20MHz =32MHz fCLK fCLK fCLK...
Page 116 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.3 timer mode register mn (TMRmn) The TMRmn register is a register for setting channel n running mode, selecting fMCK, counting clock, controlling/dependent,16bit/8 bit timer (only for channel 1 and channel 3), triggering and capturing, selecting the effective edge of timer input and running mode (interval, capture, event counter, single count, capture &...
Page 117 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Note: 1. bit11 is a read-only bit, fixed to "0", ignoring write operations. Note: 1. bit13, 5, 4 must be set to 0. 2. To change the clock selected as fCLK (change the value of the System Clock Control Register (CKC), the timer array...
Page 118 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Note: 1. bit11 is a read-only bit, fixed to "0", ignoring write operations. Note: m: Cell number (m=0)n: Channel Number (n=0~3) Figure 6-10 Table (3/4) of timer mode register mn (TMRmn)
Page 119 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-11 Table (4/4) of timer mode register mn (TMRmn) symbol TMRmn CKSmn CKSmn MASTER STSm STSm STSm CISm CISm CCSmn (n=2) symbol TMRmn CKSmn CKSmn STSm STSm STSm CISm...
Page 120 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.4 timer status register mn (TSRmn) The TSRmn register is a register that represents the overflow status of the channel n counter. The TSRmn register is valid only in capture mode (MDmn3~MDmn1=010B) and capture & single count mode (MDmn3~MDmn1=110B.
Page 121 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.5 Timer channel allows state register m (TEm) to be The TEm register is a register that represents the permitted or stopped state of operation of each channel timer. Each of the TEm registers corresponds to the bits of the timer channel start register m (TSm) and the timer channel stop register m (TTm).
Page 122 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.6 Timer channel start register m (TSm). The TSm register initializes the timer count register mn (TCRmn) and sets the trigger register when each channel count operation starts. If each position is "1", the counter bit of the timer channel allows state register m (TEm) to be "1. Because TSmn bits, TSHm1 bits, and TSHm3 bits are trigger bits, clear TSmn bits, TSHm1 bits, and TSHm3 bits immediately if it becomes run-enabled (TEmn, TEHm1, TEHm3=1).
Page 123 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.7 Timer channel stop register m (TTm). The TTm register is a trigger register that sets that count stop for each channel. If each position is" 1", the counter bits of the timer channel allow state register m (TEm) are cleared. Because the TTmn bit, TTHm1 bit, and TTHm3 bit are trigger bits, the TTmn bit, TTHm1 bit, and TTHm3 bit are cleared immediately if the idle state (TEmn, TEHm1, TEHm3=0) occurs.
Page 124 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.8 Timer Input-Output Selection Register (TIOS0, TIOS1) A channel 0 and a timer input of the channel 1 of the TIOS0 register selection unit 0 and a timer output of the channel 2.
Page 125 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 A timer input of a channel 2 of the TIOS1 register selection unit 0. The TIOS1 register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of the TIOS1 register changes to "00H".
Page 126 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.9 timer output allow register m (TOEm) The TOEm register is a register that sets the output of each channel timer to be allowed or disabled. For the channel n, the value of the TOmn bit of the timer output register m (TOm) cannot be rewritten by software.
Page 127 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.10 Timer output register m (TOm) The TOm register is a buffer register output by each channel timer. The value of each bit of this register is outputted from the output pin (TOmn) of each channel timer.
Page 128 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.11 Timer output level register m (TOLm) The TOLm register is a register that controls the output level of each channel timer. When a timer output (TOEmn=1) is allowed and a multi-channel coordinated operation function (TOMmn=1) is used, the setting and reset timing of the output signal of the timer reflect the reversed setting of each channel n by this register.
Page 129 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.12 Timer output mode register m (TOMm) The TOMm register is a register that controls the output mode of each channel timer. When used as a stand- alone channel operation function, the corresponding position of the used channel is "0".
Page 130 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.13 Input switch control register (ISC) The ISC1 bit and ISC0 bit of the ISC register are used for the coordination of channel 3 and universal serial communication unit to realize LIN bus communication. If the ISC1 position" 1", the input signal of the serial data input pin (RxD0) is selected as the input of the timer.
Page 131 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.14 Noise Filter Admission Register (NFEN1) The NFEN1 register sets whether the noise filter is used for the input signal of the input pin of each channel timer. For pins that need to be eliminated from noise, the corresponding position "1" must be taken to make the noise filter effective.
Page 132 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.3.15 Register for controlling timer input/output pin port function When using a universal timer unit, you must set the port-functional control registers (PMxx, Pxx, and PMCxx). Refer to "2.3.1 Port Mode Register (PMxx), "2.3.2 Port Register (Pxx)" and "2.3.6 Port Mode Control Register (PMCxx) "...
Page 133 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.4 Basic rules for universal timer units 6.4.1 Basic Prinicpal of Multi-channel Coordinated Operation Function The function of multi-channel coordinated operation is a function which combines the main control channel (the reference timer which mainly counts the period) and the slave channel (the timer which follows the main control channel operation), and it needs to abide by several rules.
Page 134 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Example 1 Timer4 Channel Group 1 (multi-channel linked operation function) CK00 Channel 0: Master control Channel 1: Slave Channel Group 2 (multi-channel linked operation function) CK01 Channel 2: Master control...
Page 135 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.4.2 Basic Principal of the 8-bit timer operation function (only for channel 1 and channel 3). The 8-bit timer run function is the function of using the channel of the 16-bit timer as the channel of two 8-bit timers.
Page 136 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.5 Operation of counters 6.5.1 Count Clock ( fTCLK The counting clock ( ) of universal timer unit can select any one of the following clock by the fTCLK CCSmn bit of the timer mode register mn (TMRmn): •...
Page 137 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 The case of selecting a valid edge of the TImn pin input signal (CCSmn=1) The count clock (fTCLK) is a signal that detects an effective edge of the TImn pin input signal and is synchronized with the next fMCK rising edge.
Page 138 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.5.2 Starting sequence of Counter The timer count register mn(TCRmn) enters the enable operation state by setting TSmn position bit of the timer channel start register m (TSm). Execution from counting enable state up to the start of count register mn (TCRmn) is shown in Table 6-6.
Page 139 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.5.3 Operation of counters The following describes the counter operation for each mode. Operation of interval timer mode (1) Enter the running permission state (TEmn=1) by writing "1" to TSmn bits. The timer count register mn (TCRmn) maintains an initial value until a count clock is generated.
Page 140 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Run of event counter mode (1) The timer count register mn (TCRmn) maintains the initial value during the operation of the stop state (TEmn=0). (2) Enter the running permission state (TEmn=1) by writing "1" to TSmn bits.
Page 141 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Operation of capture mode (interval measurement of input pulses) (1) Enter the running permission state (TEmn=1) by writing "1" to the TSmn bit. (2) The timer count register mn(TCRmn) keeps the initial value until the count clock is generated.
Page 142 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Note: This is the timing when no noise filter is used. If a noise filter is used, edge detection delays an additional 2 fMCK cycles (3-4 cycles total) from the TImn input time. The error of 1 cycle is due to the TImn input being out of sync with the count clock fMCK).
Page 143 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Capture & Single Count Mode Operation (Voltage High Level Width Measurement) (1) Enter the running allowed state (TEmn=1) by writing "1" with the TSmn bit of the timer channel start register m.
Page 144 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.6 Control of channel output (TOmn pin) 6.6.1 Structure of TOmn pin output circuit Figure 6-31 Structure of output circuit TOmn register Interrupt signal of master channel （INTTMmn） interrupt singal of slave...
Page 145 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.6.2 Output settings for TOmn pins The steps and status changes from the initial setting of the TOmn output pin to the start of the timer run are shown below.
Page 146 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.6.3 Precaution for Channel Output Operation Change of setting values for TOm, TOEm, TOLm, TOMm registers in timer operation The operation of the timer (timer count register mn (TCRmn) and timer data register mn (TDRmn)) and the TOmn output circuit are independent.
Page 147 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 The case (PWM output) of starting operation in the slave channel output mode (TOMmn=1) In a slave channel output mode (TOMmn=1), the effective level depends on the setting of the timer output level register m (TOLmn).
Page 148 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 TOmn pin changes for dependent channel output mode (TOMmn=1) The case of changing the setting of the timer output level register m (TOLm) in the timer operation If you change the setting of the TOLm register during the timer run, the setting is valid when the TOmn pin change condition occurs.
Page 149 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-36 Set/Reset Timing Operation State basic operation sequence TCLK INTTMmn master control channel internal reset signal Tomn Pin/TOmn swap swap internal reset signal delay 1 clock cycle INTTMmp slave channel...
Page 150 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Note 1. Internal reset signal: TOmn pin reset/alternate signal Internal Placement Signal: Placement Signal for TOmn Pins 2.m: Cell Number (m=0) n: Channel Number n=0~3 (Master Channel: n=0,2) p: Dependent Channel Number...
Page 151 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.6.4 One-time operation of TOmn bits The timer output register m (TOm) has all channel setting bits (TOmn), so it can operate all channel TOmn bits. Figure 6-37Example of one-time operation of TO0 n bits...
Page 152 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.6.5 About timer interrupts and TOmn pin output at start of counting In interval timer mode or capture mode, the MDmn0 bit of timer mode register mn (TMRmn) is set as the bit that generates timer interrupt when counting starts.
Page 153 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.7 Control of timer input (TImn) 6.7.1 Structure of TImn pin input circuit The signal of the timer input pin is input to the timer control circuit through the noise filter and the edge detection circuit.
Page 154 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.7.3 Precautions When Operating Channel Inputs The noise filter circuit is not provided with a run-time clock when the timing input pin is not used. Therefore, the channel operation from the setting to use the timer input pin to the setting to input the timer corresponding to the pin allows triggering, requires the following waiting time.
Page 155 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.8 Independent channel operation function of universal timer unit 6.8.1 Operation as Interval Timer/Square wave Output interval timer Can be used as a reference timer to generate INTTMmn (timer interrupt) at fixed intervals. Interrupt...
Page 156 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-41 Basic Timing Example as Interval Timer/Square Wave Output Operation (MDmn0=1) note operational clock Timer count register mn output Tomn Pin (TCRmn) control circuit Timer data register mn interrupt...
Page 157 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-43 Example of Register Setting Content at Interval Timer/Square Wave Output timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 note MDmn3 MDmn2 MDmn1...
Page 158 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-44 Operation Steps of Interval Timer/Square Wave Output Function software operation Hardware Status The input clock of the timer unit m is in a stopped supply state. (stop providing clock, cannot write registers)
Page 159 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.8.2 Run as External Event Counter Can be used as an event counter to count the valid edges (external events) of detected TImn pin inputs, and interrupt occurs if a specified count value is reached. The specified counter value can be calculated using the...
Page 160 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-46 Example of register setting content in external event counter mode timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 note...
Page 161 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-47 Action Steps for External Event Counter Functionality software operation Hardware Status The input clock of the timer unit m is in a state where supply is stopped. (stop providing clock, cannot write registers) Place the TM4 mEN location "1"...
Page 162 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.8.3 Operation as a frequency divider (only for channel 0 of cell 0) A frequency divider capable of dividing the clock input by the TI00 pin and used as the output of the TO00 pin.
Page 163 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 TE00 : Timer channel allows bit 0 of status register 0 (TE0) TI00 :TI00 pin input signal TCR00: Timer count register 00 (TCR00). TDR.00: timer data register 00 (TDR00). TO00 : TO00 pin output signal...
Page 164 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-50 Operating steps when frequency divider functions software operation hardware state Timer Unit 0 input clock is in stopped state (stop providing clock, not able to write into registers)
Page 165 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.8.4 Operation as an input pulse interval measurement It is possible to capture count value at that effective edge of TImn and measure the interval of the TImn input pulse. During the TEmn bit "1", the software operation (TSmn=1) can also be set to capture the trigger to capture count values.
Page 166 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 TImn :TImn Pin Input Signal TCRmn : timer count register mn (TCRmn) TDRmn : timer data register mn (TDRmn) OVF : bit 0 of timer state register mn (TSRmn). Figure 6-52...
Page 167 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-53 Operating steps when inputting pulse interval measurement functions software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers)
Page 168 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.8.5 Operation as voltage high and low level width measurement of input signal Note: When used as LIN-bus support, the bit1 (ISC1) of the input switch control register (ISC) must be set to "1", and use RxD0 instead of TImn.
Page 169 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-54 Example of a running base time sequence for a high and low level width measurement of an input signal TSmn TEmn TImn TCRmn TDRmn 0000H INTTMmn Remarks: 1.m: Cell number (m=0)n: Channel Number (n=0~3) 2.
Page 170 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-55 Example of register setting content when measuring high and low level width of input signal timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn 注 STSmn2 STSmn1 STSmn0 CISmn1...
Page 171 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-56 Operation step for measuring width of high and low level of input signal software operation hardware state Timer Unit 0 input clock is in stopped state (stop providing...
Page 172 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.8.6 Operation as delay counter Can start decrement counts with valid edge detection (external events) entered through the TImn pin, and generate INTTMmn at arbitrary set-up intervals (Timer interrupt). During the TEmn bit of '1', the TSmn position of '1' can be counted down by software and INTTMmn (timer interrupt) can be generated.
Page 173 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-58 Example of register setting content when delaying counter function (a) timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn 注 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2 MDmn1...
Page 174 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-59 Procedure when delaying counter function software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers) set TM4mEN bit of peripheral enable register 0...
Page 175 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.9 Multi-channel coordinated operation function of universal timer unit 6.9.1 Operation as single trigger pulse output function The two channels are used in pairs, and the single trigger pulse with arbitrary delay pulse width can be generated through the input of the TImn pin.
Page 176 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-60 Block diagram for operating as single trigger pulse output function master control channel (single counting mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register mn...
Page 177 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-61 A Basic Timing Example of Single Trigger Pulse Output Function TSmn TEmn TImn master FFFFH control channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp slave 0000H...
Page 178 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-62 Example of Register Setting Content for Single Trigger Pulse Output Function (Master Channel) (a) Timer mode register mn (TMRmn).. CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3...
Page 179 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-63 Example of Register Setting Content for Single Trigger Pulse Output Function (Slave Channel) (a) timer mode register mp (TMRmp) CKSmp1 注 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0...
Page 180 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-64 Operating step (1/2) for a single trigger pulse output function software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write...
Page 181 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-65 Operating step (2/2) for a single trigger pulse output function set TOEmp bit (slave) to '1' (only limit to restart operation). Set TSmn bit)(master control) and TSmp bit(slave) of timer TEmn bit and Temp bit turn into '1' and master channel enter into start channel start register m(TSm) both to '1'.
Page 182 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.9.2 Operation as PWM Function The two channels are used in pairs, and the pulse with arbitrary period and duty cycle can be generated. The period and duty cycle of the output pulse can be calculated by the following formula: Pulse Period = {TDRmn (Master) Set Value +1×Count Clock Period...
Page 183 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-66 Block diagram for operation as PWM function master control channel (interval Timer mode) operational clock Timer count register mn (TCRmn) interrupt Timer data register mn control interrupt signal...
Page 184 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-67 As an example of the basic timing of the operation of the PWM function TSmn TEmn FFFFH TCRmn 0000H master control channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH...
Page 185 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-68 Example of Register Setting Content for PWM Function (Master Channel) (a) timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2 MDmn1 TMRmn TERmn注...
Page 186 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-69 Example of Register Setting Content for PWM Function (Slave Channel) (a) timer mode register mp (TMRmp) CKSmp1 注 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp0 MDmp3 MDmp2...
Page 187 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-70 Operating steps for PWM functions (1/2) Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers) Timer 4 initial set TM4mEN bit of peripheral enable register 0 (PER0) to '1'...
Page 188 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-71 Operating steps for PWM functions (2/2) set TOEmp bit (slave) to '1' (only limit to restart operation). Set TSmn bit)(master control) and TSmp bit(slave) of timer TEmn bit and TEmp bit both turns into '1'.
Page 189 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.9.3 Operation as Multiple PWM Output Function This is a function of performing multiple PWM outputs with different duty cycles by extending the PWM function and using multiple slave channels.
Page 190 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-72 Block diagram for operating the multiple PWM output function (output of 2 PWM cases) master control channel (interval Timer mode) operational clock Timer count register mn (TCRmn) interrupt...
Page 191 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-73 As an example of the running basic timing of the multiple PWM output function (output of two PWM cases) TSmn TEmn FFFFH TCRmn 0000H master control channel TDRmn...
Page 192 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Remarks: 1, m: Cell number (m=0)n: Master channel number (n=0) p: Slave channel number q: Dependent Channel Number n<p<q≤3 (p and q are integers greater than n) 2. TSmn, TSmp, TSmq: bitn, p,q of timer channel start register m (TSm) TEmn, TEmp, TEmq: Timer channel allows bitn, p, q of state register m (TEm).
Page 193 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-74 Example of Register Setting Content for Multiple PWM Output Functions (Master Channel) (a) timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2...
Page 194 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-75 Example of register setting content for multiple PWM output functions (slave channel) (output of 2 PWM cases) (a) timer mode registers mp, mq (TMRmp, TMRmq) CKSmp1 注 CKSmp0...
Page 195 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-76 Operation steps for multiple PWM output functions (output of 2 PWM cases) (1/2) software operation hardware state Timer Unit m input clock is in stopped state (stop providing clock, not able to write into registers)
Page 196 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 Figure 6-77 Operation steps for multiple PWM output functions (output of 2 PWM cases) (2/2) (only during restart operation, TOEmp bit and TOEmq bit (slave) will set to '1'). Set TSmn bit(master), TSmp bit and TSmq bit (slave) of timer Start operation channel start register m(TSm) all set to '1' at the same time.
Page 197 BAT32G137 user manual | Chapter 6 Universal Timer Unit Timer4 6.10 Precautions when using a universal timer unit 6.10.1 Precautions When Using Timer Output According to the product, the pins to which the timer output function is assigned may also be assigned the output of other multiplexing functions.
Page 198 BAT32G137 user manual | Chapter 7 Timer A Chapter 7 Timer A 7.1 Function of timer A The timer A is a 16-bit timer capable of measuring the pulse output, the pulse width and period of the external input, and counting the external events.
Page 199 BAT32G137 user manual | Chapter 7 Timer A 7.2 Structure of timer A The block diagram and the pin structure of the timer A are shown in Figure 7-1 and Table 7-2 respectively. Figure 7-1 Block diagram of timer A...
Page 200 BAT32G137 user manual | Chapter 7 Timer A 7.3 Register for control timer A The register for controlling timer A is shown in Table 7-3. Table 7-3 Register for control timer A register name symbol Peripheral I/O Redirection Register 1...
Page 201 BAT32G137 user manual | Chapter 7 Timer A 7.3.2 Secondary system clock provides mode control register (OSMC) The runtime clock of timer A can be selected by WUTMMCK0 bits. RTCLPC bits are bits that reduce power consumption by stopping unwanted clock functionality. For RTCLPC bit settings, refer to "Chapter 4 Clock Generation Circuits."...
Page 202 BAT32G137 user manual | Chapter 7 Timer A 7.3.3 timer A count register 0 (TA0) This is a 16-bit register. If this register is written, data is written to the reload register. If you read this register, read the count value. The status of the reload registers and counters varies due to the value of the TSTART bit of the TACR0 register.
Page 203 BAT32G137 user manual | Chapter 7 Timer A 7.3.4 timer A control register 0 (TACR0). The TACR0 register is a register that controls the count and stop of register A and indicates the status of timer The TACR0 register is set by an 8-bit memory operation instruction.
Page 204 BAT32G137 user manual | Chapter 7 Timer A 7.3.5 Timer AI/O control register 0 (TAIOC0) The TAIOC0 register is a register that sets the input/output of the timer A. The TAIOC0 register is set by an 8- bit memory operation instruction.
Page 205 BAT32G137 user manual | Chapter 7 Timer A Table 7-4 Edge and Polarity Switching of TAIO Input/Output operation mode Features timer mode Not used (input/output ports). 0: Output from "H" level (initial level: "H") pulse output mode 1: Output from "L" level (initial level: "L")
Page 206 BAT32G137 user manual | Chapter 7 Timer A 7.3.6 timer A control register 0 (TAMR0). The TAMR0 register is a register that sets the run mode of register A. The TAMR0 register is set by an 8-bit memory operation instruction.
Page 207 BAT32G137 user manual | Chapter 7 Timer A 7.3.7 Timer A Event Pin Selection Register 0 (TAISR0). The TAISR0 register is a register that selects a timer that controls the period of the event count in the event counter mode and sets the polarity. The TAISR0 register is set by an 8-bit memory operation instruction.
Page 208 BAT32G137 user manual | Chapter 7 Timer A 7.3.8 Port Mode Register x (PMx) This is a register that sets the port input/output. When the multiplexed ports (TAIO, TAO, etc.) of the timer output pin are used as the output of the timer, the corresponding bits of the port mode register (PMxx) and port register (Pxx) must "0".
Page 209 BAT32G137 user manual | Chapter 7 Timer A 7.4 Operation of timer A 7.4.1 Reload register and counter override Regardless of the run mode, the rewriting timing of the reload register and counter varies with the value of the TSTART bit of the TACR0 register. When the TSTART bit is "0" (stop counting), the direct write reload register and counter;...
Page 210 BAT32G137 user manual | Chapter 7 Timer A 7.4.2 timer mode This is the mode of decreasing count by the TCK0~TCK2 bit selection of the TAMR0 register. In timer mode, count value is reduced by 1 whenever a count source is entered, and underflow occurs and an interrupt request is generated.
Page 211 BAT32G137 user manual | Chapter 7 Timer A 7.4.3 pulse output mode In this mode, the output level of the TAIO pin and the TAO pin is inverted every time the underflow occurs by the counting source selected by the TAMR0 register TCK0~TCK2 bit.
Page 212 BAT32G137 user manual | Chapter 7 Timer A 7.4.4 Event Counter Mode This is the pattern of decreasing counts by the external event signal (count source) entered through the TAIO pin. Various settings during event counting can be performed through the TIOGT0~TIOGT1 bit and TAISR0 register of TAIOC0 register, and filter function of TAIO input can be specified through TIPF0~TIPF1 bit of TAIOC0 register.
Page 213 BAT32G137 user manual | Chapter 7 Timer A Figure 7-13 Running example of event counter mode example of timing sequence to configure operational mode to following scenario. TAMR0 register: TMOD2, 1, 0=010B (Event counter mode) TAIOC0 register: TIOGT1,0=01B(event count during external interrupt pin defined period)
Page 214 BAT32G137 user manual | Chapter 7 Timer A 7.4.5 pulse width measurement mode This is the mode in which the external signal pulse width of the TAIO pin input is measured. In pulse width measurement mode, if a level specified by the TEDGSEL bit of the TAIOC0 register is input to the TAIO pin, counting is started by the selected count source.
Page 215 BAT32G137 user manual | Chapter 7 Timer A 7.4.6 pulse period measurement mode This is the mode in which the pulse period of the external signal of the TAIO pin input is measured. The counter performs decrement counting by the counter source selected by the TCK0~TCK2 bit of the TAMR0 register.
Page 216 BAT32G137 user manual | Chapter 7 Timer A 7.4.7 Collaboration with EVENTC The ability to set events entered by EVENTC as count sources by working with EVENTC. The TCK0~TCK2 bits of the TAMR0 register are counted at the rising edge of the ELC input. However, EVENTC input does not work in event counter mode.
Page 217 BAT32G137 user manual | Chapter 7 Timer A 7.5 Precautions when using timer A 7.5.1 Start and stop control of count · Event Count Mode or Setting Count Source to Non-EVENTC If the TACR0 register's TSTART bit is written "1" during count stop, the TACR0 register's TCSTF bit is "0" during 3 counts.
Page 218 BAT32G137 user manual | Chapter 7 Timer A 7.5.4 Changes in Patterns The Run Mode Correlation register (TAIOC0, TAMR0, TAISR0) for timer A can only be changed when the TACR0 register has TSTART and TCSTF. When changing the run mode dependent register of timer A, the values of the TEDGF bit and the TUNDF bit are indefinite.
Page 219 BAT32G137 user manual | Chapter 7 Timer A 7.5.8 Configuration steps for deep sleep mode (event counter mode) To make the event counter mode run in deep sleep mode, you must follow the steps below to transfer to deep sleep mode after providing the clock of timer A.
Page 220 BAT32G137 user manual | Chapter 8 Timer B Chapter 8 Timer B 8.1 Function of timer B Timer B has the following three modes: ⚫ Timer mode: Input capture: Counts are made along the rising edge, the falling edge, or the double edges of the rising edge/falling edge.
Page 221 BAT32G137 user manual | Chapter 8 Timer B 8.2 Structure of timer B The block diagram and the pin structure of the timer B are shown in Figure 8-1 and Table 8-1 respectively. Figure 8-1: Block diagram of timer B fCLK、fCLK/2、fCLK/4、fCLK/8、...
Page 222 BAT32G137 user manual | Chapter 8 Timer B 8.3 Register for control timer B The register for controlling timer B is shown in Table 8-2. Table 8-2 Register for control timer B register name symbol Peripheral Enable Register 1 PER1 timer B mode register TBMR.
Page 223 BAT32G137 user manual | Chapter 8 Timer B 8.3.1 Peripheral Enable Register 1 (PER1) The PER1 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 224 BAT32G137 user manual | Chapter 8 Timer B 8.3.2 timer B mode register (TBMR) Figure 8-3 Format of timer B mode register (TBMR) Address: 40042650H After reset: 00H symbol TBMR. TBDFB TBDFA TBMDF TBPWM TBSTART Start of TB Count The count is stopped and the PWM output signal (TBIO0 pin) is initialized (PWM mode).
Page 225 BAT32G137 user manual | Chapter 8 Timer B 8.3.3 Timer B count control register (TBCNTC) A TBCNTC register is used in the phase count mode to set the count condition of the phase count mode. Figure 8-4 Format of timer B count control register (TBCNTC) Location: 40042651H.
Page 226 BAT32G137 user manual | Chapter 8 Timer B 8.3.4 Timer B Control Register (TBCR) The TBMR register must be written with the TBSTART bit of the TBCR register in the state of '0'. Figure 8-5 Timer B Control Register (TBCR) Format...
Page 227 BAT32G137 user manual | Chapter 8 Timer B 8.3.5 Timer B interrupt enable register (TBIER) Figure 8-6 Timer B interrupts the format of the allow register (TBIER) Location: 400426 53H. After reset: 00H symbol TBIER TBUDIE TBIMIEB TBIMIEA Permission for overflow interrupts TBOVIE Interrupts due to TBOVF bits are prohibited.
Page 228 BAT32G137 user manual | Chapter 8 Timer B 8.3.6 Timer B Status Register (TBSR) Figure 8-7 Format of timer B status register (TBSR) Address: 40042654H After reset: 00H symbol TBSR TBDIRF TBOVF TBUDF TBIMFB TBIMFA Count Direction Flag TBDIRF The TB register performs decrement counting.
Page 229 BAT32G137 user manual | Chapter 8 Timer B The object status flag must be written "0" after setting timer B interrupt permit register (TBIER) to "00H". When timer B interrupt enable register (TBIER) has bit of ' 1 ' and interrupt source status flag of '0 ' allowed by this bit.
Page 230 BAT32G137 user manual | Chapter 8 Timer B 8.3.7 Timer BI/O control register (TBIOR) Figure 8-8 The format of the timer BI/O control register (TBIOR) Address: 00H R/W after 40042655H reset After reset: 00H R TBIOR TBBUFB TBIOB2 TBIOB1 TBIOB0...
Page 231 BAT32G137 user manual | Chapter 8 Timer B TBGRA control TBIOA1 TBIOA0 Prevents comparing matching pin outputs. Output "L" level. Output "H" level. Alternate output. The output comparison function is used to compare the output of the TB register and the TBGRA register.
Page 232 BAT32G137 user manual | Chapter 8 Timer B 8.3.8 Timer B Counter (TB) The TB register is connected to the CPU by a 16-bit internal bus, so it must be accessed in 16-bit units. The TB register may be capable of incremental count, free run, periodic count, or external event count. The TB register can be cleared "0000H"...
Page 233 BAT32G137 user manual | Chapter 8 Timer B 8.3.9 timer b general register a, b, c, d (TBGRA, TBGRB, TBGRC, TBGRD) The TBGRA register and the TBGRB register are 16-bit readable and writable registers, which have the functions of output comparison register and input capture register. Function conversion is performed through the TBIOR register.
Page 234 BAT32G137 user manual | Chapter 8 Timer B Table 8-4 TBGRA, TBGRB, TBGRC, TBGRD register features Patterns and register Settings Features Features TBIOR (TBIOA2=1) TBGRA Enter a capture register (holds the value of the TB register) TBMR. (TBPWM=0) input capture...
Page 235 BAT32G137 user manual | Chapter 8 Timer B 8.3.10 port register and port mode register When using the multiplexed port of the timer output pin as the output of the timer, the bit of the port mode register (PMxx) and the location of the port register (Pxx) must (Example) When P50/TBIO0 is used as the timer output, the PM50 position of port mode register 5 is "0".
Page 236 BAT32G137 user manual | Chapter 8 Timer B Operation of timer B 8.4.1 Common Issues Concerning Multiple Models and Functions (1) count source The selection of the count source and the block diagram are shown in Tables 8-5 and Figures 8-12, respectively.
Page 237 BAT32G137 user manual | Chapter 8 Timer B (2) buffer operation The TBGRC register and the TBGRD register can be set as the buffer register of the TBGRA register and the TBGRB register respectively through the TBBUFA bit and the TBBUFB bit of the TBIOR register.
Page 238 BAT32G137 user manual | Chapter 8 Timer B Figure 8-14 Buffer operation for output comparison function compare matching signal TBGRC TBGRA comparator register register register TB register TBGRA register transmit TBGRC register (buffer) TBIO0 output above diagram condition as following: ・TBBUFA bit of TBIOR register is 1 (TBGRC register is the buffer register of TBGRA)
Page 239 BAT32G137 user manual | Chapter 8 Timer B (3) digital filter The TBIOj input (j=0, 1) is sampled and if that signal is the same 3 times, the level is determined. The function of the digital filter and the sampling clock must be selected through the TBMR register.
Page 240 BAT32G137 user manual | Chapter 8 Timer B (4) Events entered from EVENTC The event entered through the EVENTC, timer B makes the input capture run B. At this point, the TBIMFB bit of the TBSR register is "1". To use this feature, you must select the input capture function for timer mode/phase count mode and position "1"...
Page 241 BAT32G137 user manual | Chapter 8 Timer B 8.4.2 timer mode (input capture function) The TB register value can be transferred to the TBGRA register and the TBGRB register after the input edge of the input capture/output comparison pin (TBIO0, TBIO1) is detected. Detection edges can be selected from the rising, falling, and double edges.
Page 242 BAT32G137 user manual | Chapter 8 Timer B Enter an example of set-up steps for a capture run Enter an example of the set-up steps for the capture run as shown in Figure 8-16. Figure 8-16 Enter an example of set-up steps for a capture run...
Page 243 BAT32G137 user manual | Chapter 8 Timer B (3) running example The input capture is shown in Figure 8-18. In this example, the rising/falling edge is selected as the input edge of the TBIO0 pin, the falling edge is selected as the input edge.
Page 244 BAT32G137 user manual | Chapter 8 Timer B 8.4.3 timer mode (output comparison function) This is the mode of detecting whether the contents of the TB register and the contents of the TBGRA register or the TBGRB register are the same (comparison match). If the contents are the same, output any level from the TBIO0 pin or from the TBIO1 pin.
Page 245 BAT32G137 user manual | Chapter 8 Timer B (1) Examples of set-up steps for comparing matched waveform outputs The set-up steps for comparing the matched waveform outputs are shown in Figure 8-19. Figure 8-19 Set-up steps for comparing matched waveform outputs...
Page 246 BAT32G137 user manual | Chapter 8 Timer B (3) running example Examples of the operation of the 'L' level output and the 'H' level output are shown in FIG. 8-21. In this example, that TB register is set to run freely and output an 'L' level when compare match A and an 'H' level.
Page 247 BAT32G137 user manual | Chapter 8 Timer B Figure 8-22 Running Example of Alternate Output Value of TB register clear counter while TBGRB register compare matching TBGRB register TBGRA register 0000H Time TBIO1 output switching output TBIO0 output switching output www.mcu.com.cn...
Page 248 BAT32G137 user manual | Chapter 8 Timer B 8.4.4 PWM mode The PWM mode pairing uses the TBGRA register and the TBGRB register to output the PWM waveform from the TBIO0 output pin. The output setting of the TBIOR register is not valid for output pins set to PWM mode. The "H"...
Page 249 BAT32G137 user manual | Chapter 8 Timer B (1) Example of set-up steps for PWM mode Examples of the set-up steps of the PWM mode are shown in Figure 8-23. Figure 8-23 Example of set-up steps for PWM mode (1) must select counting source via TBTCK0~TBTCK2 bit of TBCR register.
Page 250 BAT32G137 user manual | Chapter 8 Timer B Figure 8-24 Running example of PWM mode (1) Value of TB register clear counter while compare matching A. TBGRA register TBGRB register 0000H Time TBIO0 output (a) clear counter while TBGRA register compare matching Value of TB register clear counter while compare matching B.
Page 251 BAT32G137 user manual | Chapter 8 Timer B Figure 8-25 Operating example of PWM mode (2) Value of TRG register clear counter while compare matching B. TBGRB register TBGRA register 0000H Time TBIO0 output write configuration value write configuration value...
Page 252 BAT32G137 user manual | Chapter 8 Timer B 8.4.5 phase counting mode The phase count mode detects phase differences of the external input signals of the 2 TBCLK0 pins and the TBCLK1 pins and the TB register performs decrement. When the PMxx bit of the PM register is "1", the TBCLK0 pin and the TBCLK1 pin are automatically used as the external clock input pin, and the TB register counts according to the CNTEN0CNTEN7 bit setting of the TBCNTC register.
Page 253 BAT32G137 user manual | Chapter 8 Timer B (1) Example of set-up steps for phase count mode An example of the set-up step of the phase count mode is shown in Fig. 8-26. Figure 8-26 Example of set-up steps for phase count mode...
Page 254 BAT32G137 user manual | Chapter 8 Timer B Figure 8-28 Running example of phase count mode 2 ・whlie TBCNTC register value as "24H" TBCLK1 input TBCLK0 input Value of TB register increment decrement Time Figure 8-29 Running example of phase count mode 3 ・while TBCNTC register value as "28H"...
Page 255 BAT32G137 user manual | Chapter 8 Timer B 8.5 timer B interrupt Timer b generate a timer b interrupt request from four interrupt sources. The relevant registers for timer B interrupts are shown in Table 8-16, and the block diagram for timer B interrupts is shown in Figure 8-31.
Page 256 BAT32G137 user manual | Chapter 8 Timer B • Status of timer B status register (TBSR) Bit to clear request — — — TBOVF TBIMFB TBIMFA TBDIRF TBUDF TBSR The status flag corresponding to the bit that allowed the interrupt (TBOVF, TBIMFA) is "0", so you must write "0"...
Page 257 BAT32G137 user manual | Chapter 8 Timer B 8.6 Precautions when using timer B 8.6.1 Phase difference, overlap and pulse width in phase counting mode The phase difference and overlap of the external input signals of the TBCLK0 pin and the TBCLK1 pin must be at least 1.5 fCLK and at least 2.5 fCLK.
Page 258 BAT32G137 user manual | Chapter 8 Timer B 8.6.4 Set-up steps for TBIO0 and TBIO1 pins After reset, the TBIO0 pin and the TBIO1 pin's multiplexing I/O port are used as input ports. • When you want to export from the TBIO0 and TBIO1 pins, you must follow the steps below.
Page 259 BAT32G137 user manual | Chapter 8 Timer B function in PWM mode or timer mode (TBPWM=1, TBIOB2=0). 2) TB register · The write operation of the TBMR register preferentially resets the count generated by the running condition of timer B.
Page 260 BAT32G137 user manual | Chapter 9 timer C Chapter 9 timer C 9.1 Function of timer C Timer C is a timer that triggers an input capture function through software, comparator 1, and timer M. The actions are as follows:...
Page 261 BAT32G137 user manual | Chapter 9 timer C 9.2 Structure of timer C The block diagram of timer C is shown in Figure 9-1. Figure 9-1 Block diagram of timer C Timer C counter source selection Timer control Trigger event from Timer M Trigger event from Comparator 1 www.mcu.com.cn...
Page 262 BAT32G137 user manual | Chapter 9 timer C 9.3 Register for controlling timer C The register for controlling timer C is shown in Table 9-1. Table 9-1 Register for controlling timer C register name symbol Peripheral Enable Register 1 PER1...
Page 263 BAT32G137 user manual | Chapter 9 timer C 9.3.2 timer C count register (TC) This is a 16-bit register. If this register is written, data is written to the reload register. If you read this register, read the count value.
Page 264 BAT32G137 user manual | Chapter 9 timer C 9.3.4 timer C control register 1 (TCCR1) Figure 9-5: Timer C controls the format of register 1 (TCCR1) Address: 0x40042C54 After reset: 00H symbol TCCR1 TCK2 TCK1 TCK0 START_MD TRIG_MD_SW TRIG_MD_HW TM_TRIG OVIE...
Page 265 BAT32G137 user manual | Chapter 9 timer C 9.3.5 timer C control register 1 (TCCR2) Figure 9-6: Timer C controls the format of register 1 (TCCR2) Address: 0x40042C55 After reset: 00H symbol TCCR2 CMP_TCR1 CMP_TCR0 TSAT Action selection when triggering Timer C by output from...
Page 266 BAT32G137 user manual | Chapter 9 timer C 9.3.6 timer C status register (TCSR) Figure 9-7: Timer C controls the format of register 1 (TCSR) Address: 0x40042C56 After reset: 00H symbol TCSR TCSB TCOVF Timer C Counter Status Flag Note 1...
Page 267 BAT32G137 user manual | Chapter 9 timer C 9.4 Operation of timer C The timer C may be started by a signal trigger count of the timer M and stopped by a signal trigger count of the comparator 1. 9.4.1 count source The action clock of the timer C is determined by the option byte and the frequency division setting of the timer C.
Page 268 BAT32G137 user manual | Chapter 9 timer C 9.4.2.1 Select the Timer M signal as the setting and action for the trigger Reset and start set steps for the Timer C count when TRIG_MD_HW=0: Select the Timer M output signal as the trigger source for the count start: TCCR1.START_MD=1 Select the trigger for Timer C: TCCR1.TRIG_MD_HW=0...
Page 269 BAT32G137 user manual | Chapter 9 timer C 9.4.2.2 Select the settings and actions when the software fires 1. Count Start Source Selection Software Trigger: TCCR1.START_MD=0 2. Timer C count start: TCCR2.TSTART=1 Figure 9-10 Example of Software Trigger Timer C Count Start TC counting source TCCR1.START_MD...
Page 270 BAT32G137 user manual | Chapter 9 timer C 9.4.3 Timer C counts stop actions While counting, timer c may stop the count action by the trigger of comparator 1 or by software setting. 9.4.3.1 Select Comparator 1 as Trigger Settings and Actions 1.
Page 271 BAT32G137 user manual | Chapter 9 timer C 9.4.4 Input capture action If an interrupt is generate by that comparator 1 during the Timer C action, the action of the Timer C may change. Case 1: A count value of TCCR2.CMP1_TCR =01,TimerC is transferred to the count buffer.
Page 272 BAT32G137 user manual | Chapter 9 timer C 9.4.5 timer C count reset action When the Timer C action is started, the output signal of Timer M and the output signal of comparator 1 can reset the counter of Timer C.
Page 273 BAT32G137 user manual | Chapter 9 timer C The output signal of CMP1 resets the count value at TCCR2.CMP1_TCR=10. 1) Count value reset, count action continues: TCCR2.CMP1_TCR=10 (input capture is not allowed) 2) Timer C Count Start: TCCR2.TSTART=1 Figure 9-16 Example of CMP1 triggering a Timer C count reset TC counting source TCCR2.CMP1_TCR...
Page 274 BAT32G137 user manual | Chapter 9 timer C 9.4.6 Interruption of timer C When the counter of timer C overflows, if TCCR1.OVIE=1 is set, the overflowing interrupt signal will be generated. Figure 9-17 Example of interrupt generation when Timer C overflows...
Page 275 BAT32G137 user manual | Chapter 9 timer C 9.5 Precautions for Using Timer C 9.5.1 Read/write of register To set timer C, you must first set the TMCEN location "1" for PER1. When the TMCEN bit is '0', the write operation of the control register of timer C is ignored, and the read values are all initial values.
Page 276 BAT32G137 user manual | Chapter 10 Timer M Chapter 10 Timer M 10.1 Function of timer M Timer M has the following four modes: • timer mode Enter capture: The count value is taken to the register, triggered by an external signal.
Page 277 BAT32G137 user manual | Chapter 10 Timer M 10.2 Structure of timer M The block diagram and the pin structure of the timer M are shown in Figure 10-1 and Table 10-1 respectively. Figure 10-1 Block diagram of timer M...
Page 278 BAT32G137 user manual | Chapter 10 Timer M 10.3 Register for controlling timer M The register for controlling the timer M is shown in Table 10-2. Table 10-2 Register for controlling timer M register name symbol Peripheral Enable Register 1...
Page 279 BAT32G137 user manual | Chapter 10 Timer M 10.3.1 Peripheral Enable Register 1 (PER1) The PER1 register is a register that is set to allow or prohibit providing clocks to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 280 BAT32G137 user manual | Chapter 10 Timer M 10.3.2 timer M EVENTC register (TMELC) Figure 10-3 Format of the timer MEVENTC register (TMELC) Note Address: 0x40042A60 After Reset: 00H symbol TMELC ELCOBE1 ELCICE1 ELCOBE0 ELCICE0 Permission for EVENTC event input 1 (for forcing the cutoff of the pulse output...
Page 281 BAT32G137 user manual | Chapter 10 Timer M 10.3.3 Timer M Start Register (TMSTR) The TMSTR register can be set by an 8-bit memory operation instruction. Refer to the "10.7.1(1)TMSTR register" note when using timer M. Figure 10-4 The format of the timer M start register (TMSTR)
Page 282 BAT32G137 user manual | Chapter 10 Timer M 10.3.4 timer M mode register (TMMR) Figure 10-5 The format of the timer M mode register (TMMR) note 1 Address: 0x40042A64 After reset: 00H symbol TMMR. TMBFD1 TMBFC1 TMBFD0 TMBFC0 TMSYNC of TMGRD1 Register Functions Note 2...
Page 283 BAT32G137 user manual | Chapter 10 Timer M 10.3.5 Timer M PWM Function Selection Register (TMPMR) Figure 10-6 Timer M PWM Function Selection Register (TMPMR) Format [Timer Mode] Note Address: 0x40042A65 After Reset: 00H symbol TMPMR. TMPWMD1 TMPWMC1 TMPWMB1 TMPWMD0...
Page 284 BAT32G137 user manual | Chapter 10 Timer M 10.3.6 Timer M Functional Control Register (TMFCR) Figure 10-7 Format of timer M function control register (TMFCR) H note 1 Address: 0x40042A66 After reset: 80 symbol TMFCR PWM3 STCLK OLS1 OLS0 CMD1...
Page 285 BAT32G137 user manual | Chapter 10 Timer M 10.3.7 Timer M outputs master permissive register 1 (TMOER1) Figure 10-8 Timer M outputs the format of the master permissive register 1 (TMOER1) [Output comparison function, PWM function, reset synchronous PWM mode, complementary PWM mode and...
Page 286 BAT32G137 user manual | Chapter 10 Timer M 10.3.8 Timer M outputs Master Permissive Register 2 (TMOER2). Figure 10-9 Timer M outputs the format of master permissive register 2 (TMOER2) [PWM Function, Reset Synchronous PWM Mode, Complementary PWM Mode, and PWM3 Mode]...
Page 287 BAT32G137 user manual | Chapter 10 Timer M 10.3.9 Timer M Output Control Register (TMOCR) The TMOCR register must be written when both the TSTART0 bit and the TSTART1 bit of the TMSTR register are '0'. Figure 10-10 Timer M Output Control Register (TMOCR) Format [Output Comparison Function]...
Page 288 BAT32G137 user manual | Chapter 10 Timer M 2. When the TMOCR register is set in the case that the pin function of the TMOCR register is waveform output, the initial output level is output. Figure 10-11 Timer M Output Control Register (TMOCR) Format [PWM Function]...
Page 289 BAT32G137 user manual | Chapter 10 Timer M Figure 10-12 Timer M Output Control Register (TMOCR) Format [PWM3 Mode] H note 1 Address: 0x40042A69 After reset: 00 symbol TMOCR TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 TOD1 Selection of initial output level of TMIOD1 Invalid in PWM3 mode.
Page 290 BAT32G137 user manual | Chapter 10 Timer M 10.3.10 timer m digital filter function selection register i (TMDFi) (i=0,1) Figure 10-13 Timer M Digital Filter Function Selection Register i (TMDFi) (i=0,1) Format [Input capture] H note 1 Addresses: 0x40042A6A (TMDF0), 0x40042A6B (TMDF1)
Page 291 BAT32G137 user manual | Chapter 10 Timer M Figure 10-14 Timer M Digital Filter Function Select the format of register i(TMDFi) (i=0,1)[PWM function, reset synchronous PWM mode, complementary PWM mode and PWM3 mode] H note 1 Addresses: 0x40042A6A (TMDF0), 0x40042A6B (TMDF1)
Page 292 BAT32G137 user manual | Chapter 10 Timer M 10.3.11 Timer M control register i (TMCRi) (i=0,1) The TMCR1 register is not used in the reset synchronization PWM mode and the PWM3 mode. Figure 10-15 Timer M Control Register i (TMCRi) (i=0,1) [Input capture and output comparison]...
Page 293 BAT32G137 user manual | Chapter 10 Timer M Figure 10-16 Timer M Control Register i (TMCRi) (i=0,1) Format [PWM] H note 1 Addresses: 0x40042A70 (TMCR0), 0x40042A80 (TMCR1) After reset: 00 symbol TMCRi CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0...
Page 294 BAT32G137 user manual | Chapter 10 Timer M Figure 10-17 Timer M Control Register 0 (TMCR0) Format [Reset Synchronous PWM Mode] H note1 Address: 0x40042A70 After reset: 00 symbol TMCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1...
Page 295 BAT32G137 user manual | Chapter 10 Timer M Figure 10-18 Timer M Control Register 0 (TMCR0) Format [Complementary PWM Mode] H note 1 Address: 0x40042A70 After reset: 00 symbol TMCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1...
Page 296 BAT32G137 user manual | Chapter 10 Timer M Figure 10-19 Timer M Control Register 0 (TMCR0) Format [PWM3 Mode] H note 1 Address: 0x40042A70 After reset: 00 symbol TMCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 CCLR2 CCLR1 CCLR0 Clear Selection of TM0 Counter Must be '001B ' (clear TM0 register when matching with TMGRA0 register).
Page 297 BAT32G137 user manual | Chapter 10 Timer M 10.3.12 Timer MI/O control register Ai(TMIORAi) (i=0,1) Figure 10-20 Timer MI/O Control Register Ai (TMIORAi) (i=0,1) Format [input capture] H note 1 Addresses: 0x40042A71 (TMIORA0), 0x40042A81H (TMIORA1) After reset: 00 symbol TMIORAi...
Page 298 BAT32G137 user manual | Chapter 10 Timer M Figure 10-21 Timer MI/O Control Register Ai (TMIORAi) (i=0,1) Format [output comparison] H note 1 Addresses: 0x40042A71 (TMIORA0), 0x40042A81H (TMIORA1) After reset: 00 symbol TMIORAi IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 Note 2...
Page 299 BAT32G137 user manual | Chapter 10 Timer M 10.3.13 Timer MI/O control register Ci(TMIORCi) (i=0,1) Figure 10-22 Timer MI/O Control Register Ci(TMIORCi) (i=0,1) Format [input capture] H note 1 Addresses: 0x40042A72 (TMIORC0), 0x40042A82 (TMIORC1) After reset: 88 symbol TMIORCi IOD3...
Page 300 BAT32G137 user manual | Chapter 10 Timer M Figure 10-23 Timer M I/O Control Register Ci (TMIORCi) (i=0,1) [output comparison function] H note 1 Addresses: 0x40042A72 (TMIORC0), 0x40042A82 (TMIORC1) After reset: 88 symbol TMIORCi IOD3 IOD2 IOD1 IOD0 IOC3 IOC2...
Page 301 BAT32G137 user manual | Chapter 10 Timer M 10.3.14 Timer M Status Register 0 (TMSR0) Figure 10-24 Timer M Status Register 0 (TMSR0) Format [Input Capture Function] H note 1 Address: 0x40042A73 After reset: 00 symbol TMSR0 IMFD IMFC IMFB...
Page 302 BAT32G137 user manual | Chapter 10 Timer M Note: 3. The results are as follows: • When writing "1," this bit does not change. • In the case of reading "0", even writing "0" remains unchanged (even writing "0" remains).
Page 303 BAT32G137 user manual | Chapter 10 Timer M • Status of timer M status register i (TMSRi) must cclear request bit — — IMFD IMFC IMFB IMFA TMSRi must write 0 to IMFB since the corresponding status flag (OVF, IMFA) of enabled interrupt are "0".
Page 304 BAT32G137 user manual | Chapter 10 Timer M Figure 10-25 Timer M Status Register 0 (TMSR0) Format [Features Other Than Input Capture] H note 1 Address: 0x40042A73 After reset: 00 symbol TMSR0 IMFD IMFC IMFB IMFA Note 3 Overflow Flag...
Page 305 BAT32G137 user manual | Chapter 10 Timer M • Timer M interrupts the state of the allow register i (TMIERi) interrupt enable — — — OVIE IMIED IMIEC IMIEB IMIEA TMIERi interrupt disable • Status of timer M status register i (TMSRi) must cclear request —...
Page 306 BAT32G137 user manual | Chapter 10 Timer M 10.3.15 Timer M Status Register 1 (TMSR1) Figure 10-26 Timer M Status Register 1 (TMSR1) Format [Input Capture Function] note 1 Address: 0x40042A83 After reset: 00H symbol TMSR1 IMFD IMFC IMFB IMFA overflow mark Invalid when using input capture feature.
Page 307 BAT32G137 user manual | Chapter 10 Timer M Note: 3. The results are as follows: • When writing "1," this bit does not change. • In the case of reading "0", even writing "0" remains unchanged (even writing "0" remains).
Page 308 BAT32G137 user manual | Chapter 10 Timer M • Status of timer M status register i (TMSRi) must cclear request — — IMFD IMFC IMFB IMFA TMSRi Because the status flag (IMFA) corresponding to the interrupt enable bit is "1", it is necessary to write "0" to IMFA and IMFB at the same time.
Page 309 BAT32G137 user manual | Chapter 10 Timer M Figure 10-27 Timer M Status Register 1 (TMSR1) Format [Input capture] H note 1 Address: 0x40042A83 After reset: 00 symbol TMSR1 IMFD IMFC IMFB IMFA overflow mark The case of complementary PWM mode...
Page 310 BAT32G137 user manual | Chapter 10 Timer M Note:2. The results are as follows: • When writing "1," this bit does not change. • In the case of reading "0", even writing "0" remains unchanged (even writing "0" remains). •...
Page 311 BAT32G137 user manual | Chapter 10 Timer M • Status of timer M status register i (TMSRi) must cclear request — — IMFD IMFC IMFB IMFA TMSRi Because the status flag (IMFA) corresponding to the interrupt enable bit is "1", it is necessary to write "0" to IMFA and IMFB at the same time.
Page 312 BAT32G137 user manual | Chapter 10 Timer M 10.3.16 timer m interrupt enable register i (TMIERi) (i=0,1) Figure 10-28 Timer M interrupts the format of register i(TMIERi) (i=0,1) H Note Addresses: 0x40042A74 (TMIER0), 0x40042A84 (TMIER1) After Reset: 00 symbol TMIRi...
Page 313 BAT32G137 user manual | Chapter 10 Timer M 10.3.17 timer MPWM function output level control register i (TMPOCRi) (i=0,1) The TMPOCRi register settings are valid only when using the PWM function, otherwise the TMPOCRi register settings are not valid. Figure 10-29 Timer MPWM Function Output Level Control Register i (TMPOCRi) (i=0,1) Format [PWM]...
Page 314 BAT32G137 user manual | Chapter 10 Timer M 10.3.18 timer M counter i (TMi) (i=0,1) [Timer Mode] The TMi register must be accessed in 16 bits and not in 8 bits. [Reset synchronous PWM mode and PWM3 mode] The TM0 register must be accessed in 16 bits and not in 8 bits. The TM1 register is not used in reset synchronization PWM mode and PWM3 mode.
Page 315 BAT32G137 user manual | Chapter 10 Timer M Figure 10-32 Timer M Counter i(TMi) (i=0,1) Format [Complementary PWM mode (TM0)] Note Address: 0x40042A76(TM0), 0x40042A86(TM1) After Reset: 0000H symbol — Features Set Scope You must set the time of the dead zone.
Page 316 BAT32G137 user manual | Chapter 10 Timer M 10.3.19 timer m general register ai, bi, ci, di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) [Enter capture feature] The TMGRAi~TMGRDi register must be accessed in 16 bits and not in 8 bits. The following registers are...
Page 317 BAT32G137 user manual | Chapter 10 Timer M [PWM3 Mode] The TMGRAi~TMGRDi register must be accessed in 16 bits and not in 8 bits. In PWM3 mode, the following registers are invalid: TMPMR, TMDF0, TMDF1, TMIORA0, TMIORC0, TMPOCR0, TMIORA1, TMIORC1, TMPOCR1In PWM3 mode, TMGRC0, TMGRC1, TMGRD0, TMGRD1 registers are not used.
Page 318 BAT32G137 user manual | Chapter 10 Timer M Figure 10-35 timer m general register ai, bi, ci, di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) format [output comparison function] FFFFH Note Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), After reset: 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0), 0x40042A88 (TMGRA1), 0x40042A8A (TMGRB1),...
Page 319 BAT32G137 user manual | Chapter 10 Timer M Figure 10-36 timer m general register ai, bi, ci, di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) format [PWM] note Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), reset:FFFFH 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0), 0x40042A88 (TMGRA1), 0x40042A8A (TMGRB1),...
Page 320 BAT32G137 user manual | Chapter 10 Timer M Figure 10-37 timer m general register ai, bi, ci, di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) format [reset synchronous PWM mode] note Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), reset:FFFFH 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0), 0x40042A88 (TMGRA1), 0x40042A8A (TMGRB1),...
Page 321 BAT32G137 user manual | Chapter 10 Timer M Figure 10-38 timer m general register ai, bi, ci, di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) format [complementary PWM mode] note Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), reset:FFFFH 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0), 0x40042A88 (TMGRA1), 0x40042A8A (TMGRB1),...
Page 322 BAT32G137 user manual | Chapter 10 Timer M Table 10-7 TMGRji register function in complementary PWM mode register Settings register function PWM output pin Generic register, PWM period must be set at the initial setting. Setting Range: Setting Value (Initial Count) for TM0 Register ≤...
Page 323 BAT32G137 user manual | Chapter 10 Timer M Figure 10-39 timer m general register ai, bi, ci, di (TMGRAi, TMGRBi, TMGRCi, TMGRDi) (i=0,1) format [PWM3 mode] note Address: 0x40042A78 (TMGRA0), 0x40042A7A (TMGRB0), reset:FFFFH 0x40042B58 (TMGRC0), 0x40042B5A (TMGRD0), 0x40042A88 (TMGRA1), 0x40042A8A (TMGRB1),...
Page 324 BAT32G137 user manual | Chapter 10 Timer M Table 10-8 TMGRji register function in PWM3 mode register Settings register function PWM output pin Universal register, PWM cycle must be set. Setting Range: Setting Value for the TMGRA1 Register ≤ Setting...
Page 325 BAT32G137 user manual | Chapter 10 Timer M 10.3.20 Port Mode Register (PMxx, PMCxx) This is a register that sets the input/output of the port or the analog input. When the multiplexed ports (Pxx/TMIOD1, Pxx/TMIOC1, etc.) of the timer output pin are used as the output of...
Page 326 BAT32G137 user manual | Chapter 10 Timer M 10.4 Common Issues on Multiple Models 10.4.1 count source The counting source selection method is the same for all modes. However, in PWM3 mode, you cannot select an external clock. Table 10-9...
Page 327 BAT32G137 user manual | Chapter 10 Timer M 10.4.2 buffer operation The TMGRCi register and the TMGRDi register can be set as the buffer register of the TMGRAi register and the TMGRBi register through the TMBFCi (i=0, 1) and TMBFDi bits of the TMMR register.
Page 328 BAT32G137 user manual | Chapter 10 Timer M Figure 10-42 Buffer Operation for Input Capture TMIOAi input (Enter Capture Signal) Number TMGRAi TMGRCi register (buffer) register TMIOAi input TMi register transfe TMGRAi register transfe TMGRCi register (buffer) Notes: i=0,1 The conditions in the above diagram are as follows: The TMBFCi bit of the TMMR register is "1"...
Page 329 BAT32G137 user manual | Chapter 10 Timer M In timer mode (input capture function and output comparison function), the following settings must be made. Use TMGRCi (i=0,1) registers as buffer registers for TMGRAi registers: • The IOC3 location of the TMIORCi register must be "1" (universal or buffer register).
Page 330 BAT32G137 user manual | Chapter 10 Timer M 10.4.3 synchronous operation Synchronize the TM0 register with the TM1 register. • synchronization preset If the TMi register is written when the TMSYNC bit of the TMMR register is "1", the data is written to both the TM0 register.
Page 331 BAT32G137 user manual | Chapter 10 Timer M 10.4.4 Forced Cutoff of Pulse Output When the PWM function is used, or in reset synchronous PWM mode, complementary PWM mode and PWM3 mode, the TMIOji output pin (i=0,1, B,D) can be cut off.
Page 332 BAT32G137 user manual | Chapter 10 Timer M Figure 10-45 Forced Cutoff of Pulse Output ELCOBE0 DFCK1，DFCK0 EVENTC event input 0 TMSHUTS bit TIMER M output data INTP0 input TMIOA0 multiplex I/O TMPTO port output data HI-Z selection signal ELCOBE1...
Page 333 BAT32G137 user manual | Chapter 10 Timer M 10.4.5 Events entered from the Event Coordination Controller(EVENTC) The timer M runs two types of events entered through the EVENTC. Input capture for TMIOD0/TMIOD1 The timer M captures the input of the TMIOD0/TMIOD1 by the events input by EVENTC. At this point, the IMFD bit of the TMSRi register is "1".
Page 334 BAT32G137 user manual | Chapter 10 Timer M 10.4.6 Events output to the event Coordination Controller(EVENTC)/data transfer controller (DMA) The mode of the timer M and the events output to the EVENTC/DMA are shown in Table 10-11. Table 10-11. Mode of timer M and event output to ELC/DMA...
Page 335 BAT32G137 user manual | Chapter 10 Timer M 10.5 Operation of timer M 10.5.1 Input capture function This is a function of measuring the width and period of an external signal. The TMi register (counter) is transferred to the TMGRji register (input capture) by using the external signal of the TMIOji pin (i=0,1, j=A,B,C,D) as the trigger.
Page 336 BAT32G137 user manual | Chapter 10 Timer M Figure 10-46 Block Diagram of Input Capture Function www.mcu.com.cn 336 / 1052 V2.1.1...
Page 337 BAT32G137 user manual | Chapter 10 Timer M Table 10-12 Enter the specifications for the capture function Project Specifications note fHOCO , fCLK, fCLK/2, fCLK/4, fCLK/8,fCLK/32 count source External input signal for the TMCLK pin (program selection of effective edges)
Page 338 BAT32G137 user manual | Chapter 10 Timer M running example The counter value of the timer Mi is reset when input capture or comparison match occurs by setting CCLR0~CCLR2 bits of the TMCRi register (i=0,1). FIGS. 10-47 is an example of operation when the position CCLR2~CCLR0 is "001B".
Page 339 BAT32G137 user manual | Chapter 10 Timer M digital filter The TMIOji input (i=0, 1,j=A,B,C,D) is sampled and if that signal is identical 3 times, the level is determined. The function of the digital filter and the sampling clock must be selected through the TMDFi register.
Page 340 BAT32G137 user manual | Chapter 10 Timer M 10.5.2 output comparison function This is a mode to detect whether the contents of TMi registers (counters) (i=0,1) and TMGRji registers (j=A,D) are identical (compare matching). If the contents are the same, output any level from the TMIOji pin. Because the TMIOji pin and the TMGRji register are used in combination, the pin can be selected as the output comparison function, or other modes and functions.
Page 341 BAT32G137 user manual | Chapter 10 Timer M Table 10-13. Output Comparison Feature Specifications Project Specifications note fHOCO , fCLK, fCLK/2, fCLK/4, fCLK/8,fCLK/32 count source External input signal for the TMCLK pin (program selection of effective edges) Count incremental count ·...
Page 342 BAT32G137 user manual | Chapter 10 Timer M running example The counter value of the timer Mi is reset when input capture or comparison match occurs by setting CCLR0~CCLR2 bits of the TMCRi register (i=0,1). If that expect value is" FFFFH", it will change from" FFFFH" to"...
Page 343 BAT32G137 user manual | Chapter 10 Timer M Changes to the output pin of the TMGRCi register and the TMGRDi register (i=0,1) The TMGRCi register and the TMGRDi register can be used for the output control of the TMIOAi pin and the TMIOBi pin, respectively.
Page 344 BAT32G137 user manual | Chapter 10 Timer M Examples of the operation of using TMGRCi and TMGRDi for output control of the TMIOAi and TMIOBi pins, respectively, are shown in Figure 10-52. Figure 10-52 Example of running TMGRCi and TMGRDi for output control of TMIOAi and TMIOBi...
Page 345 BAT32G137 user manual | Chapter 10 Timer M 10.5.3 PWM function This is the function of the output PWM waveform. At most 3 PWM waveforms can be output through the timer Mi (i=0,1). By synchronizing the timer M0 with the timer M1, up to 6 PWM waveforms can be output in the same cycle.
Page 346 BAT32G137 user manual | Chapter 10 Timer M Figure 10-53 Block diagram of PWM function Table 10-14. Specifications of PWM Functions Specifications Project fHOCO note, , fCLK/4, fCLK, fCLK/2 fCLK fCLK count source External input signal for the TMCLK pin (allows program...
Page 347 BAT32G137 user manual | Chapter 10 Timer M (m-n) Invalid Level Width: 1/fk (n+1) fk: Frequency of the count source m:Setting value for TMGRAi register n:Setting value for the TMGRji register (If the active level is "L") Write "1" to the TSTARTi bit of the TMSTR register.
Page 348 BAT32G137 user manual | Chapter 10 Timer M running example Figure 10-54 Running example of PWM function counting source value in Tmi register Time "L" voltage invalid TMIOBi output "H" voltage valid initial output "L" voltage level before compare matching TMIOCi output "H"...
Page 349 BAT32G137 user manual | Chapter 10 Timer M Figure 10-55 Example of PWM function running (duty cycles of 0% and 100%) value in TMi register TMi寄存器的值 Time TSTRATi bit of TMIOBi will not output "L" voltage level since TMSTR register 因为不发生TMGRBi寄存器的比较匹配，...
Page 350 BAT32G137 user manual | Chapter 10 Timer M 10.5.4 Reset synchronous PWM mode Output 3 positive and 3 inverse (total 6) PWM waveforms (three-phase, sawtooth modulation, dead time). The block diagram and the running example of the reset synchronous PWM mode are shown in Figure 10-56 and Figure 10-57 respectively, and the specification of the reset synchronous PWM mode is shown in Table 10-15.
Page 351 BAT32G137 user manual | Chapter 10 Timer M Table 10-15. Specifications for Reset Synchronous PWM Mode Specifications Project Note fHOCO , fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32TMCLK pin external input signal (can be programmed to select count source effective edges) TM0 is an incremental count (TM1 is not used).
Page 352 BAT32G137 user manual | Chapter 10 Timer M running example Figure 10-57 Operating example of reset synchronous PWM mode counting source TMi寄存器的值 value in TMi register Time TSTRATi bit of TMSTR register TMIOB0 output TMIOD0 output TMIOA1 output TMIOC1 output...
Page 353 BAT32G137 user manual | Chapter 10 Timer M 10.5.5 complementary PWM mode Output 3 positive and 3 inverse (total 6) PWM waveforms (three-phase, triangular modulation, dead time). The complementary PWM mode specification is shown in Table 10-16, and the output model and operation example are shown in Figure 10-60.
Page 354 BAT32G137 user manual | Chapter 10 Timer M Table 10-16 Specifications for Complementary PWM Modes Project Specifications Note 1 fHOCO , fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/32 External input signal for the TMCLK pin (allows program count source selection of effective edges) The TMCR0 register's TCK0~TCK2 bit and the TMCR1 register's TCK0~TCK2 bit must be set to the same value (same count source).
Page 355 BAT32G137 user manual | Chapter 10 Timer M read timer If you read the TMi register, you can read the count value. write timer Can write TMi register. · The input of the pulse output compulsory cutoff signal (reference to "10.4.4 compulsory cutoff of pulse output")
Page 356 BAT32G137 user manual | Chapter 10 Timer M running example Figure 10-59 Output Model of Complementary PWM Mode Value of the TMi register Value ᆘᄬ for the TM0 register ⱘ The value of the TMGRA0 register The value of the TM1...
Page 357 BAT32G137 user manual | Chapter 10 Timer M Figure 10-60 Running example of complementary PWM mode counting source value in TMi register value in TM0 register value in TM1 register Time change to "FFFFH" TSTRATi bit of TMSTR register TMIOB0 output...
Page 358 BAT32G137 user manual | Chapter 10 Timer M 10.5.6 PWM3 mode Output 2 PWM waveforms with same period. The block diagram and running examples of PWM3 mode are shown in Figure 10-61 and Figure 10-62, respectively, and the specification of PWM3 mode is shown in Table 10-17.
Page 359 BAT32G137 user manual | Chapter 10 Timer M Table 10-17. Specifications for PWM3 Mode Project Specifications fHOCO note, , fCLK/4, count source fCLK, fCLK/2 fCLK fCLK Count TM0 is an incremental count (TM1 is not used). PWM Cycle: 1/fk (m+1)
Page 360 BAT32G137 user manual | Chapter 10 Timer M to change fCLK to a clock other than fIH, you must change it after clearing the bit4 (TMMEN) of peripheral enable register 1 (PER1). Note: i=0,1,j=A,B,C,D running example Figure 10-62 Running example of PWM3 mode...
Page 361 BAT32G137 user manual | Chapter 10 Timer M and timer M1. The relevant registers for timer M interrupts are shown in Table 10-18, and the block diagram for timer M interrupts is shown in Figure 10-63. Table 10-18. Correlation register interrupted by timer M...
Page 362 BAT32G137 user manual | Chapter 10 Timer M ⚫ Timer M interrupts the state of the allow register i(TMIERi) interrupt enable — — — OVIE IMIED IMIEC IMIEB IMIEA TMIERi interrupt disable · Status of timer M status register i (TMSRi)
Page 363 BAT32G137 user manual | Chapter 10 Timer M 10.7 Precautions when using timer M 10.7.1 Read and write access to SFR To set timer M, the TMMEN location of the PER1 register must be "1" first. When the TMMEN bit is '0', the write operation of the control register of timer M is ignored and the read values are initial (except for port registers and port mode registers).
Page 364 BAT32G137 user manual | Chapter 10 Timer M 10.7.3 count source • To switch the count source, you must switch after stopping the count. [Change Steps] Set the TSTARTi bit (i=0,1) of the TMSTR register to "0". Change the TCK0~TCK2 bit of the TMCRi register.
Page 365 BAT32G137 user manual | Chapter 10 Timer M 10.7.6 external clock TMCLK The external clock input by the TMCLK pin must have a pulse width of at least 3 operating clock cycles of timer Reset synchronous PWM mode • When this mode is used for motor control, it must be used under OLS0=OLS1 conditions.
Page 366 BAT32G137 user manual | Chapter 10 Timer M Figure 10-64 Running example of TM0 and TMGRA0 register matching in complementary PWM mode TM0 register counting value configure value m of TMGRA0 register Time set to 0 via program remain unchanged...
Page 367 BAT32G137 user manual | Chapter 10 Timer M • The data transfer timing of the buffer register to the general register must be selected through the CMD0 and CMD1 bits of the TMFCR register. However, in the case of 0% duty cycle and 100% duty cycle, the values of the CMD0 bits are independent of the following transmission sequence.
Page 368 BAT32G137 user manual | Chapter 10 Timer M To unset the output level, the buffer register must be set a value (TM0 register value≤set value≤ (TMGRA0 value -TM0 register value). After writing the buffer, regardless of the setting of CMD0 bits, the buffer register value is transferred to the general register and the PWM waveform is output when the TM1 counter underflows.
Page 369 BAT32G137 user manual | Chapter 10 Timer M To unset the output level, the buffer register must be set a value (TM0 register value≤set value≤ (TMGRA0 value -TM0 register value). After writing the buffer, regardless of the setting of CMD0 bits, the buffer register value is transferred to the general register and the PWM waveform is output when the TM1 counter underflows.
Page 370 BAT32G137 user manual | Chapter 10 Timer M 10.8 PWMOP The PWMOP unit can implement the output mandatory cut-off function of TimerM. Cutoff sources can be selected from CMP0, INTP0, and EVENT. This is different from the TimerM's own impulse-Forced cutoff.
Page 371 BAT32G137 user manual | Chapter 10 Timer M 10.8.1 Features of PWMOP PWMOP enables the following: You can select the output of comparator 0, the INTP0 input, and the event input of EVENTC as the source of the output Forced cutoff.
Page 372 BAT32G137 user manual | Chapter 10 Timer M PWMOP control register 0 (OPCTL0) Figure 10-69 Format of PWMOP control register 0 Address: 0x40043C58 After reset: 00H symbol HAZARD_S IN_EG IN_SEL1 IN_SEL0 HZ_REL HS_SEL OPCTL0 Output Force Cutoff hazard Control HAZARD_SET...
Page 373 BAT32G137 user manual | Chapter 10 Timer M HS_REL Output Forced Cutoff Mode Selection Hardware removal: When the hardware is used to release the forced cut-off of the output, the timing is different according to the different operation modes of the timer M.
Page 374 BAT32G137 user manual | Chapter 10 Timer M (1) PWMOP Enforce Cutoff Control Register 0 (OPDF0) Figure 10-70 PWMOP Format of Forced Cutoff Control Register 0 Address: 0x40043C59 After reset: 00H symbol PDF0 DFD01 DFD00 DFC01 DFC00 DFB01 DFB00 DFA01...
Page 375 BAT32G137 user manual | Chapter 10 Timer M PWMOP Force Cutoff Control Register 1 (OPDF1) Figure 10-71 PWMOP Format of Forced Cutoff Control Register 1 Address: 0x40043C5A After reset: 00H symbol PDF1 DFD11 DFD10 DFC11 DFC10 DFB11 DFB10 DFA11 DFA10...
Page 376 BAT32G137 user manual | Chapter 10 Timer M PWMOP along selection register (OPEDGE) When the timer M is in complementary PWM mode and the output is forced off by hardware release, the release time point can be set by OPEDGE register.
Page 377 BAT32G137 user manual | Chapter 10 Timer M 10.8.3 Running of PWMOP You can select the output of comparator 0, the INTP0 input, and the event input of EVENTC as the source of the output Forced cutoff. When you select the output of comparator 0 and the INTP0 input as the source, you can choose to follow the checkout.
Page 378 BAT32G137 user manual | Chapter 10 Timer M Figure 10 74 Example of Output Forced Cutoff / Hardware Undoing Output Forced Cutoff , example of TMIOD0 pin being forced off (TMIOB0, TMIOC0 PWMOP operational clock valid timing signal when TM0 counter at 0000H.
Page 379 BAT32G137 user manual | Chapter 10 Timer M Figure 10 75 Detailed Time Series for Forced Cutoff PWMOP operational clock TIMER M counter0 comparator0 output HZIF0 TMIOB0 output Note 1 from PWMOP. TMIOB0 output Note 2 from Timer M. TMIOC0 output Note 1 from PWMOP.
Page 380 BAT32G137 user manual | Chapter 10 Timer M Figure 10 Detailed Time Series of Forced Cutoff Release (counter source for timer M=Fclk) PWMOP operational clock TIMER M counter0 valid timing signal when TM0 counter at 0000H. comparator0 output HZIF0 TMIOB0 output Note 1 from PWMOP.
Page 381 BAT32G137 user manual | Chapter 10 Timer M Figure 10 77 Detailed Time Series of Forced Cutoff Release (counter source for timer M=Fclk/2) PWMOP operational clock TIMER M counter0 valid timing signal when TM0 counter at 0000H. comparator0 output HZIF0...
Page 382 BAT32G137 user manual | Chapter 10 Timer M The Situation of Complementary PWM Function Output Upon detection of the release source, the edge of the TMIOC0 selected according to the OPEDGE is forced off. Figure 10-78 Example of Hardware Unforced Cutoff (Using TMIOB0,TMIOD0 as an example)
Page 383 BAT32G137 user manual | Chapter 10 Timer M FIG. 10-79 Detailed timing diagram of forced cutoff release (counter source for timer M = Fclk, decremental count) PWMOP operational clock TIMER M counter 1 TMIOC0 output from Timer M comparator0 output...
Page 384 BAT32G137 user manual | Chapter 10 Timer M Figure 10-80 Detailed time series of forced cutoff release (counter source=Fclk, counter=TMGRA0) PWMOP operational clock TIMER M counter0 TMIOC0 output from Timer M Comparator 0 output HZIF0 TMIOB0 output Note 1 from PWMOP.
Page 385 BAT32G137 user manual | Chapter 10 Timer M FIG. 10-81 Detailed timing diagram of forced cutoff release (counter source of timer M = Fclk/2, decremental count) PWMOP operational clock TIMER M counter 1 TMIOC0 output from Timer M Comparator 0 output...
Page 386 BAT32G137 user manual | Chapter 10 Timer M Figure 10-82 Detailed Time Series for Forced Cutoff Release (counter source=Fclk/2 for timer M, counter=TMGRA0) PWMOP operational clock TIMER M counter0 TMIOC0 output from Timer M Comparator 0 output HZIF0 TMIOB0 output Note 1 from PWMOP.
Page 387 BAT32G137 user manual | Chapter 10 Timer M 10.8.3.3 Software Undoing (HS_SEL=1) The force cutoff release timing is different when the ACT settings of OPCTL0 are different. Use software to immediately undock (ACT=0) If ACT=0 is set, once the HZ_REL bit of the OPCTL0 register is set to 1, the force cutoff is immediately lifted.
Page 388 BAT32G137 user manual | Chapter 10 Timer M Figure 10-84 Detailed Time Series for Forced Cutoff Release PWMOP operational clock TIMER M counter0 forced cut-off release control HZ_REL TMIOB0 output Note 1 from PWMOP. TMIOB0 output Note 2 from Timer M.
Page 389 BAT32G137 user manual | Chapter 10 Timer M Figure 10-85 Example of Software Unforced Cutoff (Timer M, 2 Channel Count) PWMOP operational clock TMSTR.TSTART0 TMSTR.TSTART1 valid signal when count of TM0 is 0000H. valid signal when count of TM1 is 0000H.
Page 390 BAT32G137 user manual | Chapter 10 Timer M Figure 10-86 Example of Software Unforced Cutoff (Timer M, 1 Channel Count) PWMOP operational clock TMSTR.TSTART0 TMSTR.TSTART1 valid signal when count of TM0 is 0000H. valid signal when count of TM1 is 0000H.
Page 391 BAT32G137 user manual | Chapter 10 Timer M The timer M works in the case of resetting the synchronous PWM mode Set HZ_REL to 1, and at 0,000H for TM0 count, all TMIO pins are forced off. Figure 10-87 Examples of Software Unforced Cutoff...
Page 392 BAT32G137 user manual | Chapter 10 Timer M The timer works in complementary PWM mode When HZ_REL is set to 1, the edge of the TMIOC0 selected according to the OPEDGE is unforced. Figure 10-88 Examples of Software De-Forced Cutoff (TMIOB0, TMIOD0)
Page 393 BAT32G137 user manual | Chapter 10 Timer M 10.8.3.4 Hazard countermeasure If in that act of force cut-off state/force cut-off release state/timer M, the TMIO pin is at risk of mis-acting while switching between the multiplexing function and the PORT function. You can set HAZAD_SET to 1 to allow hazard countermeasures to avoid this risk.
Page 394 BAT32G137 user manual | Chapter 10 Timer M 10.8.3.5 Output Force Cutoff of Source Checked Out and Unchecked Out The output force cutoff source checks out the level of the selected signal (INTP0, CMP0) by the cutoff source selection bit (OPCTL0.IN_SEL1, OPCTL0.IN_SEL0).
Page 395 BAT32G137 user manual | Chapter 10 Timer M Consistent with the value of TMGRA0, the count value becomes 0000H and the force cutoff state is ⚫ lifted 5) The timer M reaches a count value of 0000H, and the timer M stops working If the timer M stops working while the count value reaches 0,000 H, the forced cut-off cannot be removed.
Page 396 BAT32G137 user manual | Chapter 10 Timer M 10.8.3.7 Configuration Steps The PWMOP may be associate with that timer M, and the setting of the PWMOP may be appended to the setting of the timer M. The steps are as follows:...
Page 397 BAT32G137 user manual | Chapter 10 Timer M 10.8.4 Precautions When the output of the timer M and the output of the PWMOP are working simultaneously, the priority is as follows: Table 10-22 Prioritization at Forced Cutoff Pin status when PWMOP forces a cutoff...
Page 398 BAT32G137 user manual | Chapter 11 real-time clock Chapter 11 real-time clock 11.1 The Function of Real-time Clock The real-time clock has the following functions. • Holds counters for years, months, weeks, days, hours, minutes, and seconds up to a maximum of 99 years.
Page 399 BAT32G137 user manual | Chapter 11 real-time clock Figure 11-1 Block diagram of real-time clock real time clock control register 1 real time clock control register 0 secondary system provide mode control register (OSMC) alarm week alarm hour alarm minute...
Page 400 BAT32G137 user manual | Chapter 11 real-time clock 11.3 Register for controlling real-time clock The real-time clock is controlled through the following registers. · Peripheral Enable Register 0 (PER0). · Real-time clock selection register (RTCCL) · Real-time clock control register 0 (RTCC0) ·...
Page 401 BAT32G137 user manual | Chapter 11 real-time clock 11.3.1 Peripheral Enable Register 0 (PER0). The PER0 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 402 BAT32G137 user manual | Chapter 11 real-time clock 11.3.2 Real-time clock selection register (RTCCL) A real-time clock and a count clock of a 15-bit interval timer ( ) can be selected RTCCL. fRTC through Figure 11-3 Format of Real-Time Clock Selection Register (RTCCL)
Page 403 BAT32G137 user manual | Chapter 11 real-time clock 11.3.3 Real-time clock control register 0 (RTCC0) This is an 8-bit register that sets the start or stop of real-time clock operation, the control of RTC1HZ pins, the 12/24-hour system and fixed cycle interrupts.
Page 404 BAT32G137 user manual | Chapter 11 real-time clock 11.3.4 Real-time clock control register 1 (RTCC1) This is an 8-bit register that controls the alarm clock interrupt function and the counter wait. The RTCC1 register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 405 BAT32G137 user manual | Chapter 11 real-time clock Figure 11-5 Format of real-time clock control register 1 (RTCC1) (2/2) Fixed Cycle Interrupt Status Flag RIFG No fixed cycle interrupt was generated. Interrupt of a fixed cycle is generate. This is a status flag indicating that a fixed cycle interrupt is generated. This flag is "1"...
Page 406 BAT32G137 user manual | Chapter 11 real-time clock 11.3.5 Clock error correction register (SUBCUD) This is a register capable of correcting clock speed with high accuracy by changing the overflow value from the internal counter (16 bits) to the second counter (SEC) (reference value: 7FFFH).
Page 407 BAT32G137 user manual | Chapter 11 real-time clock 11.3.6 Second Count Register (SEC) This is an 8-bit register that represents the value of the second meter in 0-59 decimal. An incremental count is performed by overflowing an internal counter (16 bits).
Page 408 BAT32G137 user manual | Chapter 11 real-time clock 11.3.8 Hour count register (HOUR) This is an 8bit register that represents hourly values with 00-23 or 01-12, 21-32 decimal values. Incrementally count by overflowing the minutes counter. At write time, the data is first written to the buffer and then to the counter after passing up to 2 fRTC clocks. The overflow of the minute count register is ignored during a write operation and set to a write value.
Page 409 BAT32G137 user manual | Chapter 11 real-time clock The setting value of the AMPM bit, the value of the HOUR, and the time are as followsTable11-2in the Table11-2 Representation of Time Frame 24-hour representation (AMPM=1) 12-hour representation (AMPM=0) Time HOUR register...
Page 410 BAT32G137 user manual | Chapter 11 real-time clock 11.3.9 Day count register (DAY) This is an 8-bit register that represents the daily count value in 1-31 decimal. An incremental count is performed by overflowing the hour counter. The counter counts as follows.
Page 411 BAT32G137 user manual | Chapter 11 real-time clock 11.3.10 Week count register (WEEK) This is an 8-bit register that represents the day of the week value in 0-6 decimal. Increment counts in synchronization with the daily counter. At write time, the data is first written to the buffer and then to the counter after passing up to 2 fRTC clocks.
Page 412 BAT32G137 user manual | Chapter 11 real-time clock 11.3.11 Month count register (MONTH) This is an 8-bit register that represents the monthly count value in 1-12 decimal. The incremental count is performed by overflowing the daily counter. At write time, the data is first written to the buffer and then to the counter after passing up to 2 fRTC clocks.
Page 413 BAT32G137 user manual | Chapter 11 real-time clock 11.3.13 Alarm clock minute register (ALARMWM) This is a register that sets alarm minutes. The ALARMWM register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 414 BAT32G137 user manual | Chapter 11 real-time clock An example of setting an alarm clock time is shown below. week 12-hour note Twenty-four hours Sunda Mond Tuesd Wedn Thurs Saturd Friday esday Alarm clock set time 10:00 10:00 hour points...
Page 415 BAT32G137 user manual | Chapter 11 real-time clock 11.4 Operation of real-time clock 11.4.1 Real Time clock Operation start Figure 11-17 Real-time clock start step start configure to provide Note1 RTCEN=1 input clock RTCE=0 configure to stop counting 。 configure RTCCL...
Page 416 BAT32G137 user manual | Chapter 11 real-time clock 11.4.2 Transition to sleep mode after start of operation One of the following processes must be performed to transfer RTCE position "1" to sleep, including deep sleep. However, these proces are not required if you want to move to sleep mode after a INTRTC interrupt occurs, after that RTCE position"...
Page 417 BAT32G137 user manual | Chapter 11 real-time clock 11.4.3 Real-time clock counter reading and writing The RWAIT location "1" must be read and written first. The RWAIT position "0" must be read and written to counters. Figure 11-19 Read operation steps of real-time clock counter...
Page 418 BAT32G137 user manual | Chapter 11 real-time clock Figure 11-20 Read operation steps of real-time clock counter Start configure as SEC~Year counter RWAIT=1 stop operating, enter into read/ write mode of counter. confirm counter wait state RWST=1? 设定SEC Write SEC...
Page 419 BAT32G137 user manual | Chapter 11 real-time clock 11.4.4 Alarm setting for real-time clock The WALE location "0" must be set before the alarm clock is not running properly. Figure 11-21 Alarm Clock Set-up Steps Start WALE=0 alarm alignment operation invalid...
Page 420 BAT32G137 user manual | Chapter 11 real-time clock 11.4.5 1 Hz output of real-time clock Figure 11-22 Set-up steps for 1Hz output Note: 1. The RTCEN position "1" be first set in a state where the count clock (fSUB) is oscillatingly stable.
Page 421 BAT32G137 user manual | Chapter 11 real-time clock 11.4.6 Example of clock deviation calibration for a real-time clock A clock speed correction can be performed with high accuracy by setting a value to a clock error correction register. Example of calculation method of correction value The correction value for correcting the count value of the internal counter (16 bits) can be calculated using the following formula.
Page 422 BAT32G137 user manual | Chapter 11 real-time clock correction example Examples from 32767.4 Hz to 32768Hz (32767.4Hz+18.3ppm) [Measurement of oscillation frequency] The oscillating frequencies of the products are measured by outputting a signal of about 1Hz from the RTC1HZ Note pin when the clock error correction register (SUBCUD) is an initial value Note: Refer to the "1 Hz output of the 10.4.5 real-time clock"...
Page 423 BAT32G137 user manual | Chapter 12 15-bit interval timer Chapter 12 15-bit interval timer 12.1 The function of a 15-bit interval timer An interrupt (INTIT) is generated at any time interval set in advance, which can be used for arousal from deep sleep mode.
Page 424 BAT32G137 user manual | Chapter 12 15-bit interval timer 12.3 Register for controlling 15-bit interval timer The 15-bit interval timer is controlled by the following registers. • Peripheral Enable Register 0 (PER0). • Real-time clock selection register (RTCCL) • 15-bit interval timer control register (ITMC) 12.3.1...
Page 425 BAT32G137 user manual | Chapter 12 15-bit interval timer 12.3.2 Real-time clock selection register (RTCCL) A real-time clock and a counter clock ( ) of a 15-bit interval timer can be selected RTCCL. fRTC through Figure 12-3 Format of Real-Time Clock Selection Register (RTCCL)
Page 426 BAT32G137 user manual | Chapter 12 15-bit interval timer 12.3.3 Control register for 15-bit interval timer (ITMC) This is a register that sets the start and stop of the 15-bit interval timer and compares the values. The ITMC register is set by the 16-bit memory operation instruction.
Page 427 BAT32G137 user manual | Chapter 12 15-bit interval timer 12.4 Operation of a 15-bit interval timer 12.4.1 Run-time sequence of 15-bit interval timer A 15-bit interval timer for repeated generation of interrupt requests (INTIT) is operated at intervals of ITCMP14~ITCMP0 bits. If the RINTE position is "1," the 15-bit counter starts counting.
Page 428 BAT32G137 user manual | Chapter 12 15-bit interval timer 12.4.2 The operation of the counter is started after returning from the sleep mode and the transfer to the sleep mode is repeated After returning from sleep mode, if RINTE position '1' is to be transferred to sleep mode again after at least 1 count clock.
Page 429 BAT32G137 user manual | Chapter 13 Clock output/buzzer output control circuit Chapter 13 Clock output/buzzer output control circuit 13.1 The Function of Clock Output/Buzzer Output Control Circuit The output of the clock is the function of output to the peripheral IC clock, and the output of the buzzer is the function of output the frequency square wave of the buzzer.
Page 430 BAT32G137 user manual | Chapter 13 Clock output/buzzer output control circuit 13.2 Structure of clock output/buzzer output control circuit The clock output/buzzer output control circuit is composed of the following hardware. Table13-1 Register for clock output/buzzer output control circuit Project...
Page 431 BAT32G137 user manual | Chapter 13 Clock output/buzzer output control circuit Note: The output clock must be switched after it is set to disable output (PCLOEn=0). When selecting the main system clock (CSELn=0), if you want to transfer to deep sleep mode, you must set the PCLOEn to "0"...
Page 432 BAT32G137 user manual | Chapter 13 Clock output/buzzer output control circuit 13.3.2 Register for controlling clock output/buzzer output pin port function When used as a clock output/buzzer output function, you must set the control registers (port mode registers (PMxx) and port registers (Pxx)) for the port function multiplexing with the object channel. Refer to "2.3.1 Port Mode Register (PMxx)"...
Page 433 BAT32G137 user manual | Chapter 13 Clock output/buzzer output control circuit 13.4 Operation of clock output/buzzer output control circuit It can be use as clock output or buzzer output with 1 pin selection. The CLKBUZ0 pin outputs a clock/buzzer selected by the clock output selection register 0 (CKS0).
Page 434 BAT32G137 user manual | Chapter 14 watchdog timer Chapter 14 watchdog timer 14.1 Function of watchdog timer The watchdog timer runs with the option byte (000C0H) setting count. The watchdog timer operates at a low speed internal oscillator clock ( ).
Page 435 BAT32G137 user manual | Chapter 14 watchdog timer Figure 14-1 Watchdog timer block diagram interval time control circuit option bytes (000C0H) interval time (count value overflow time x3/4 WDTINT +1/2fIL) option bytes (000C0H) WDCS2~WDCS0 interval clock overflow signal counter input...
Page 436 BAT32G137 user manual | Chapter 14 watchdog timer 14.3 Register for controlling watchdog timer The watchdog timer is controlled by an allowable register (WDTE) of the watchdog timer. 14.3.1 Watchdog timer enable register (WDTE) By writing "ACH" to the WDTE register, the watchdog timer's counter is cleared and counting restarts. The WDTE register is set by an 8-bit memory operation instruction.
Page 437 BAT32G137 user manual | Chapter 14 watchdog timer 14.3.2 WDTCFG configuration register (WDTCFG0/1/2/3) The WDTCFG configuration register is the register that determines whether to force the watchdog timer to run. WDTCFG register is set by 8-bit memory operation instruction. After the reset signal is generated, the value of WDTCFG register becomes "00H".
Page 438 BAT32G137 user manual | Chapter 14 watchdog timer 14.4 Operation of watchdog timer 14.4.1 Operation control of watchdog timer When you use the watchdog timer, set the following by 000C0H: • The bit4 (WDTON) of option bytes (000C0H) must be set to "1" to allow the watchdog timer to count (after reset, the counter starts) (see Chapter 33 option bytes for details).
Page 439 BAT32G137 user manual | Chapter 14 watchdog timer watchdog will occur within the oscillation stable time and reset. Therefore, after releasing the deep sleep mode through interval interruption, the watchdog timer is to be operated and cleared with the X1 oscillating clock.
Page 440 BAT32G137 user manual | Chapter 14 watchdog timer 14.4.3 Watchdog timer window settings during opening Set the window opening period of the watchdog timer by bit6 and bit5 (WINDOW1, WINDOW0) of option bytes (000C0H). The window summary is as follows: •...
Page 441 BAT32G137 user manual | Chapter 14 watchdog timer 14.4.4 Setting of watchdog timer interval interrupt Interval interrupts (INTWDTI) can be generated when 75%+1/2fIL is reached by setting bit7 (WDTINT) of option bytes (000C0H). Table14-5 Setting of watchdog timer interval interrupt...
Page 442 BAT32G137 user manual | Chapter 15 A/D converter Chapter 15 A/D converter The number of analog input channels of the A/D converter varies depending on the product. Pin Number 32 pin 48 pins 64 pins 10ch 15ch 16ch analog transmission...
Page 443 BAT32G137 user manual | Chapter 15 A/D converter Figure 15-1 A/D Converter Block Diagram www.mcu.com.cn 443 / 1052 V2.1.1...
Page 444 BAT32G137 user manual | Chapter 15 A/D converter 15.2 Register for controlling A/D converter The registers that control the A/D converter are as follows: Register Base Address: CSC_BASE=4002_0420H; ADC_BASE=4004_5000H; PORT_BASE=4004_000H Reset Register Name Register Description Register Address Value PER0 Peripheral Enable Register 0...
Page 445 BAT32G137 user manual | Chapter 15 A/D converter 15.2.1 Peripheral Enable Register 0 (PER0). The PER0 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 446 BAT32G137 user manual | Chapter 15 A/D converter 15.2.2 Mode register 0 (ADM0) for A/D converter Register used to set the A/D conversion clock, start of conversion, or stop. The ADM0 register is set by an 8-bit memory operation instruction.
Page 447 BAT32G137 user manual | Chapter 15 A/D converter Table 15-2 Placement and Purge Conditions for ADCS Bits placement A/D conversion mode Clear Condition condition continuous When writing "0" to ADCS bit conversion mode selection mode · When writing "0" to ADCS bits Single Conversion ·...
Page 448 BAT32G137 user manual | Chapter 15 A/D converter Figure 15-4 Action State Diagram with A/D Modes ADCS write ADCS Auto clear to zero while A/D write conversion completes software trigger mode Note1 (ADCS) conversion stops conversion idle conversion ongoing conversion idle...
Page 449 BAT32G137 user manual | Chapter 15 A/D converter Table 15-3 A/D Conversion Time Selection (1/2) (1) No A/D power steady wait time (Software Trigger Mode/Hardware Trigger No Wait Mode) Mode of A/D Converter Mode of A/D Converter Frequency of 12-bit resolution conversion time...
Page 450 BAT32G137 user manual | Chapter 15 A/D converter Table 15-3 A/D Conversion Time Selection (2/2). note 1 (2) Has A/D power steady wait time (hardware triggered wait mode Mode of A/D Mode of A/D Converter A/D power Frequency Converter Register 1 (ADM1)
Page 451 BAT32G137 user manual | Chapter 15 A/D converter 15.2.3 Mode register 1 for A/D converter (ADM1) This is a register that sets the A/D conversion mode. The ADM1 register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 452 BAT32G137 user manual | Chapter 15 A/D converter 15.2.4 Mode register 2 for A/D converter (ADM2) The ADM2 register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 453 BAT32G137 user manual | Chapter 15 A/D converter 15.2.5 A/D converter trigger mode register (ADTRG) This is a register that sets the A/D conversion trigger mode and hardware trigger signal. The ADTRG register is set by an 8-bit memory operation instruction.
Page 454 BAT32G137 user manual | Chapter 15 A/D converter 15.2.6 Analog input channel assignment register (ADS) This is a register that specifies the analog voltage input channel to be A/D converted. The ADS register is set by an 8-bit memory operation instruction.
Page 455 BAT32G137 user manual | Chapter 15 A/D converter ◆ Scan mode (ADM1.ADMD=1) analog input channel ADISS ADS3 ADS2 ADS1 ADS0 Scan 0 Scan 1 Scan 2 Scan 3 ANI0 ANI1 ANI2 ANI3 ANI1 ANI2 ANI3 ANI4 ANI2 ANI3 ANI4 ANI5...
Page 456 BAT32G137 user manual | Chapter 15 A/D converter 15.2.7 12-bit A/D conversion result register (ADCR) This is a 16-bit register that holds the A/D conversion result, which is readable only. Each time the A/D Note conversion ends, the Translation Result Note is loaded from the Successive Approximation Register (SAR) The high 4-bit readout value of the register is fixed to '0' when selecting mode, and the channel number of this conversion result can be configured by ADM2.CHRDE=1.
Page 457 BAT32G137 user manual | Chapter 15 A/D converter 15.2.8 8-bit A/D conversion result register (ADCRH) This is an 8-bit register that holds the A/D conversion result, holding a Note high 8-bit note with 12-bit resolution The ADCRH register is read by an 8-bit memory operation instruction.
Page 458 BAT32G137 user manual | Chapter 15 A/D converter 15.2.9 Conversion Result Compare Upper Value Setting Register (ADUL) This is the setting register for checking the upper limit value of the A/D conversion result. The A/D conversion result is compared with the value of the ADUL register, and the ADRCK in the mode...
Page 459 BAT32G137 user manual | Chapter 15 A/D converter 15.2.11 A/D Sample Time Control Register (ADNSMP) This register controls the A/D sampling time. The ADNSMP register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to '0dH'.
Page 460 BAT32G137 user manual | Chapter 15 A/D converter 15.2.12 A/D Sample Time Extension Register (ADSMPWAIT) This register is used to extend the A/D sampling time. The ADSMPWAIT register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 461 BAT32G137 user manual | Chapter 15 A/D converter 15.2.13 A/D test register (ADTES) This register is used to set the test mode of the A/D converter. The ADTES register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 462 BAT32G137 user manual | Chapter 15 A/D converter 15.2.14 A/D status register (ADFLG) This register represents the state of the A/D converter. The ADFLG register is read by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 463 BAT32G137 user manual | Chapter 15 A/D converter 15.2.15 A/D charge/discharge control register (ADNDIS) The register is used to control the charging and discharging operation and time of the A/D converter. The ADNDIS register is read and written by an 8-bit memory operation instruction.
Page 464 BAT32G137 user manual | Chapter 15 A/D converter 15.2.16 Register for controlling analog input pin port function You must set up a control register (port mode control register (PMCxx)) for the port function that is multiplexed with the analog input of the A/D converter. Refer to the "2.3.6 port mode control register (PMCxx)".
Page 465 BAT32G137 user manual | Chapter 15 A/D converter 15.3 Input voltage and conversion results The analog input voltage of the analog input pin (ANI0~ANI15) and the theoretical A/D conversion result register (ADCR) are related. ×4096+0.5) or (ADCR-0.5)× ≤V <(ADCR+0.5)× ADCR=INT(...
Page 466 BAT32G137 user manual | Chapter 15 A/D converter 15.4 Operation mode of the A/D Converter The modes of the A/D converter are operated as follows. Refer to the "Set-up Flowchart for 15.5A/D Converter" for set-up procedures. 15.4.1 Software trigger mode (select mode, continuous conversion mode) ①...
Page 467 BAT32G137 user manual | Chapter 15 A/D converter 15.4.2 Software Trigger Mode (Select Mode, Single Conversion Mode) ① In the stopped state, the ADCE position "1" of mode register 0 (ADM0) of the A/D converter is switched into standby. ②...
Page 468 BAT32G137 user manual | Chapter 15 A/D converter 15.4.3 Software Trigger Mode (Scan Mode, Continuous Conversion Mode) ① In the stopped state, the ADCE position "1" of mode register 0 (ADM0) of the A/D converter is switched into standby. After the stable waiting time (1μs) is counted by software, the ADCS position of the ADM0 register is 1 ②...
Page 469 BAT32G137 user manual | Chapter 15 A/D converter 15.4.4 Software Trigger Mode (Scan Mode, Single Conversion Mode) ① In the stopped state, the ADCE position "1" of mode register 0 (ADM0) of the A/D converter is switched into standby. ②...
Page 470 BAT32G137 user manual | Chapter 15 A/D converter 15.4.5 Hardware triggers no-wait mode (select mode, continuous conversion mode) ① In the stopped state, the ADCE position "1" of mode register 0 (ADM0) of the A/D converter is switched into standby.
Page 471 BAT32G137 user manual | Chapter 15 A/D converter 15.4.6 Hardware triggers no-wait mode (select mode, Single Conversion Mode) ① In the stopped state, the ADCE position "1" of mode register 0 (ADM0) of the A/D converter is switched into standby.
Page 472 BAT32G137 user manual | Chapter 15 A/D converter 15.4.7 Hardware triggered no-wait mode (scan mode, continuous conversion mode) ① In the stopped state, the ADCE position "1" of mode register 0 (ADM0) of the A/D converter is switched into standby.
Page 473 BAT32G137 user manual | Chapter 15 A/D converter 15.4.8 Hardware triggered no-wait mode (scan mode, Single Conversion Mode) ① In the stopped state, the ADCE position "1" of mode register 0 (ADM0) of the A/D converter is switched into standby.
Page 474 BAT32G137 user manual | Chapter 15 A/D converter 15.4.9 Hardware triggered wait mode (select mode, continuous conversion mode) ① In the stop state, the ADCE position of mode register 0 (ADM0) of the A/D converter enters the hardware triggered standby state.
Page 475 BAT32G137 user manual | Chapter 15 A/D converter 15.4.10 Hardware triggered wait mode (select mode, Single Conversion Mode) ① In the stop state, the ADCE position of mode register 0 (ADM0) of the A/D converter enters the hardware triggered standby state.
Page 476 BAT32G137 user manual | Chapter 15 A/D converter 15.4.11 Hardware triggered wait mode (scan mode, continuous conversion mode) ① In the stop state, the ADCE position of mode register 0 (ADM0) of the A/D converter enters the hardware triggered standby state.
Page 477 BAT32G137 user manual | Chapter 15 A/D converter 15.4.12 Hardware triggered wait mode (scan mode, Single Conversion Mode) ① In the stop state, the ADCE position of mode register 0 (ADM0) of the A/D converter enters the hardware triggered standby state.
Page 478 BAT32G137 user manual | Chapter 15 A/D converter 15.5 Converter Set-up Flowchart The set-up flowchart of the A/D converters for each mode of operation is shown below. 15.5.1 Settings for software trigger mode Figure 15-30 Settings for software trigger mode...
Page 479 BAT32G137 user manual | Chapter 15 A/D converter 15.5.2 Hardware Trigger No Wait Mode Settings Figure 15-31 Hardware Trigger No Wait Mode Settings configuration starts configure PER0 register set ADCEN bit of PER0 register to 1, start provide clock configure PMC register...
Page 480 BAT32G137 user manual | Chapter 15 A/D converter 15.5.3 Settings for Hardware Trigger Wait Mode Figure 15-32 Settings for Hardware Trigger Wait Mode configuration starts configuration PER0 set ADCEN bit of PER0 register to 1, start provide clock register configuration PMC register...
Page 481 BAT32G137 user manual | Chapter 15 A/D converter 15.5.4 Settings when selecting the output voltage/internal reference voltage of the temperature sensor (Take software trigger mode, single conversion mode for example) Figure 15-33 Settings when selecting the output voltage/internal reference voltage of...
Page 482 BAT32G137 user manual | Chapter 15 A/D converter 15.5.5 Settings for test mode Figure 15-34 Settings for the test mode (VSS/half_VDD/VDD as the translation object) configuration starts configure PER0 register set ADCEN bit of PER0 register to 1, start provide clock ADM0 register FR2~FR0 bit: configure A/D conversion time.
Page 483 BAT32G137 user manual | Chapter 16 D/A Converter Chapter 16 D/A Converter The channels of the D/A converter vary depending on the product. Table 1 6-1 Output pin of D/A converter D/A output pin 64PIN 52 PIN 48PIN 40 PIN...
Page 484 BAT32G137 user manual | Chapter 16 D/A Converter 16.2 Structure of D/A converter The D/A converter box is shown in Figure 16-1. Figure 16-1 Block Diagram for D/A Converter internal bus D/A conversion value configuration register0 write DACS0 (DACS0) register...
Page 485 BAT32G137 user manual | Chapter 16 D/A Converter 16.3 Register for controlling D/A converter The D/A converter is controlled through the following registers. · Peripheral Enable Register 1 (PER1) · Mode register (DAM) for D/A converter. · D/A conversion value setting registers 0,1 (DACS0,DACS1) ·...
Page 486 BAT32G137 user manual | Chapter 16 D/A Converter 16.3.2 Mode register (DAM) for D/A converter. This is the register that controls the D/A converter to run. The DAM register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 487 BAT32G137 user manual | Chapter 16 D/A Converter 16.3.4 event output target selection register n(ELSELRn), n=00~21 When the real-time output mode of the D/A converter is used, the event signal of the event link controller is used as the start trigger for D/A conversion. Refer to " 24.3.1 Event Output Target Selection Register n (ELSELRn) (n=00~21)".
Page 488 BAT32G137 user manual | Chapter 16 D/A Converter 16.4 Operation of D/A Converter 16.4.1 Normal mode operation The DACSi register is used as the start trigger to perform D/A conversion. It is set as follows: ① Start supplying the D/A converter with the DACEN position "1" of the PER1 register (Peripheral Enable Register 1).
Page 489 BAT32G137 user manual | Chapter 16 D/A Converter 16.4.2 Operation of Real-time Output Mode Each channel of the D/A converter uses the event signal of EVENTC as the start trigger to perform the D/A conversion. It is set as follows: ①...
Page 490 BAT32G137 user manual | Chapter 16 D/A Converter 16.4.3 Output Timing of D/A Conversion Values The output timing of the D/A conversion values is shown in Figure 16-5. general mode real time output mode (DACEi=1) real time output mode (DACEi=0)
Page 491 BAT32G137 user manual | Chapter 16 D/A Converter 16.5 Precautions of using the D/A converter The following precautions shall be taken taken when using the D/A converter. When the port is set as an analog pin through a PMC register (port mode control register), the input/output function of the digital port multiplexed with ANO0 pin does not work.
Page 492 BAT32G137 user manual | Chapter 17 comparator Chapter 17 comparator This product has a comparator with 2 channels built in. 17.1 Function of comparator The comparator has the following functions: · The input pin of the CMP1 can select an external port, internal reference voltage, and internal DAC reference voltage.
Page 493 BAT32G137 user manual | Chapter 17 comparator 17.2 Structure of comparator 17-1in the The box diagram of the comparator is as followsFigure Figure 17-1 Block diagram for comparator 0 CMP0SEL C0ENB C0FCK C0EPO C0EDG C0IE PGA0 A/D convertor VCIN0 CMP0...
Page 494 BAT32G137 user manual | Chapter 17 comparator Figure 17-2 Block diagram for comparator 1 CMP1SEL C1MON C1ENB C1FCK C1EPO C1EDG C1IE VCIN10 Edge CMP1 选 detection interrupt VCIN11 择 circuit 器 VCIN12 CMP1 EVENTC event VCIN13 noise removal / Digital filter output 选...
Page 495 BAT32G137 user manual | Chapter 17 comparator 17.3 Register for control comparator The registers controlling the comparator are as followsTable17-2in the Table17-2 Register for control comparator register name symbol Peripheral Enable Register 1 PER1 comparator mode setting register COMPMDR. comparator filter control register...
Page 496 BAT32G137 user manual | Chapter 17 comparator 17.3.1 Peripheral Enable Register 1 (PER1) The PER1 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 497 BAT32G137 user manual | Chapter 17 comparator 17.3.2 Comparator mode set-up register (COMPMDR) The COMPMDR register is a register that sets the comparator action permission/prohibition and detects the comparator output. The CiENB bit is not set to '0' when the comparator output license (CiOE position '1' of the COMPOCR register).
Page 498 BAT32G137 user manual | Chapter 17 comparator 17.3.3 Comparator filter control register (COMPFIR) The COMPFIR register is a control register for the digital filter. The COMPFIR register is set by an 8-bit memory operation instruction. After the reset signal is generated, the value of this register changes to "00H".
Page 499 BAT32G137 user manual | Chapter 17 comparator If you change the C0FCK1~C0FCK0 bits, C0EPO bits, and C0EDG bits, you may generate a interrupt request for comparator 0 and event signals output to EVENTC. These bits must be changed after setting the EVENTC ELSELR20 register (output of unlinked comparator 0) to "0".
Page 500 BAT32G137 user manual | Chapter 17 comparator 17.3.4 Comparator output control register (COMPOCR) The COMPOCR register is a control register that sets the polarity of the comparator output, the permission/prohibition of the output, and the permission/prohibition of the interrupt output.
Page 501 BAT32G137 user manual | Chapter 17 comparator Note1. When comparator 1 uses the TIMER WINDOW mode, the bit7 (C1EDG) of register COMPFIR must be set to "1". C1OE and C1OTWMD bits cannot be set at the same time. Set the C1OTWMD bit before setting the C1OE position.
Page 502 BAT32G137 user manual | Chapter 17 comparator 17.3.5 Comparator built-in reference voltage control register (CVRCTL) The CVRCTL register is a register that sets the built-in reference voltage permit/stop action of the comparator. The CVRCTL register is set by an 8-bit memory operation instruction.
Page 503 BAT32G137 user manual | Chapter 17 comparator 17.3.6 Comparator built-in reference voltage selection register (CiRVM) The CiRVM register is a register that sets the built-in reference voltage of the comparator. When the built-in reference voltage stops (CVREi=0), rewrite the CiRVM register The CVRCTL register is set by an 8-bit memory operation instruction.
Page 504 BAT32G137 user manual | Chapter 17 comparator 17.3.7 Comparator 0 input signal selection control register (CMPSEL0) The CMPSEL0 register is a selection register for the input signal of the positive end and the negative end of the comparator 0. When comparator 0 stops (C0ENB=0), override the CMPSEL0 register.
Page 505 BAT32G137 user manual | Chapter 17 comparator 17.3.8 Comparator 1 input signal selection control register (CMPSEL1) The CMPSEL1 register is a selection register for the input signal of the positive end and the negative end of the comparator 1. When comparator 1 stops (C1ENB=0), rewrite the CMPSEL1 register.
Page 506 BAT32G137 user manual | Chapter 17 comparator 17.3.9 Register for controlling analog input pin port function When using the VCIN0 pin, VCIN10-VCIN1 3 pin and VREF0 pin as analog inputs to the comparator, the bits of port mode register (PMxx) and PMCxx.
Page 507 BAT32G137 user manual | Chapter 17 comparator 17.4 Operation Instructions Comparator 0 and Comparator 1 can be run independently. The set-up method is the same as the run. The CMP0 and PGA0 can be combined together. The set-up steps for the comparator's independent operation and interactivity are as followsTable17-3in the...
Page 508 BAT32G137 user manual | Chapter 17 comparator An example of operation of the comparator i (i=0,1) is as followsFigure 17-11in the In the basic mode, when the analog input voltage is higher than the reference input voltage, the CiMON bit of the COMPMDR register is "1";...
Page 509 BAT32G137 user manual | Chapter 17 comparator 17.4.1 Digital filter for comparator i (i=0,1) The comparator i has a built-in digital filter, which can select the sampling clock through the CiFCK1~CiFCK0 bit of the COMPFIR register. The output signal of comparator i is sampled according to each sampling clock, and the digital filter outputs the sampling value.
Page 510 BAT32G137 user manual | Chapter 17 comparator 17.4.3 Event signal output to the Coordination Controller(EVENTC) An event signal output to the COMPFIR is generated by detecting the output edge of the digital filter set by the EVENTC register. However, unlike an interrupt request, the event signal is always output to the EVENTC regardless of the CiIE bit of the COMPOCR register.
Page 511 BAT32G137 user manual | Chapter 17 comparator 17.4.4 Output of comparator i (i=0,1) The comparison result of the comparator can be output to external pin, and output polarity can be set through CiOP bit and CiOE bit of COMPOCR register. Refer to " for register settings and comparator output.17.3.4 Comparator output control register (COMPOCR)".
Page 512 BAT32G137 user manual | Chapter 18 programmable gain amplifier (PGA) Chapter 18 programmable gain amplifier (PGA) 18.1 Function of Programmable Gain Amplifier This product has two programmable gain amplifiers (PGA0 and PGA1) built in. ⚫ Each PGA has 7 choices for amplification: 4x, 8x, 10x, 12x, 14x, 16x, 32x ⚫...
Page 513 BAT32G137 user manual | Chapter 18 programmable gain amplifier (PGA) 18.2 Structure of programmable gain amplifier Figure 18-1: Block diagram of programmable gain amplifier www.mcu.com.cn 513 / 1052 V2.1.1...
Page 514 BAT32G137 user manual | Chapter 18 programmable gain amplifier (PGA) 18.3 Register of programmable gain amplifier Table18-1 Register for controlling programmable gain amplifier Peripheral Admission Register 1 PER1 programmable gain amplifier control register PGACTL Port Mode Control Register 2 PMC2 Port Mode Register 2 18.3.1...
Page 515 BAT32G137 user manual | Chapter 18 programmable gain amplifier (PGA) 18.3.2 programmable gain amplifier control register (PGAnCTL) The PGA0CTL and the PGA1CTL register are used to control the programmable gain amplifier to start working, stop working, and amplify. The PGA0CTL and PGA1CTL registers can be set by 1-bit or 8-bit memory instructions. After the reset signal is generated, the reset value of this register is 00H.
Page 516 BAT32G137 user manual | Chapter 18 programmable gain amplifier (PGA) 18.4 Operation of programmable gain amplifier The analog voltage input by the PGAIN pin is amplified, and the amplification gain has seven choices: 4 times, 8 times, 10 times, 12 times, 14 times, 16 times and 32 times.
Page 517 BAT32G137 user manual | Chapter 18 programmable gain amplifier (PGA) 18.4.2 Stopping operation step of programmable gain amplifier Take PGA0 as an example, set up as follows: Note 1. When restarting PGA and A/D conversion or amplifier, 10us PGA stabilization time is required after setting the PGAEN bit to 1.
Page 518 Unit 0 has 4 serial channels and unit 1 has 2 serial channels, each channel can realize 3-line SSPI, simple I2 UART and The functionality of each channel supported by BAT32G137 is distributed as follows: ○32 pin products unit channel...
Page 519 BAT32G137 user manual | Chapter 19 universal serial communication unit ○64 pin products unit channel Use as SSPI Use as UART Used as Simple I SSPI00 IIC00 (Slave selectionInput UART0 (LIN-bus support) Supported) SSPI01 IIC01 SSPI10 IIC10 UART1 SSPI11 IIC11...
Page 520 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.1 Functions of Universal Serial Communication Unit The features of each serial interface supported by BAT32G137 are shown below. 19.1.1 3-wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Data is transmitted and received synchronously with a serial clock (SCLK) output from the master control device.
Page 521 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.1.2 UART (UART0~UART2) This is the ability to communicate asynchronously over a total of two lines, Serial Data Send (TxD) and Serial Data Receive (RxD). The two communication lines are used to transmit and receive data asynchronously (using internal baud rate) with other communication parties in data frames (consisting of start bit, data, parity bit and stop bit).
Page 522 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.1.3 Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) This is the capability of clock synchronization with multiple devices through two lines of serial clock (SCL) and serial data (SDA). Since this simple I2C is designed for single communication with EEPROM, flash memory, A/D converter, etc., it is only used as master device.
Page 523 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.2 Structure of universal serial communication unit The universal serial communication unit consists of the following hardware. Table 1 9-1 Structure of universal serial communication unit Project structure note 1...
Page 524 BAT32G137 user manual | Chapter 19 universal serial communication unit The block diagram of the universal serial communication unit 0 is shown in Figure 19-1. Figure 19-1 Block diagram of the universal serial communication unit 0 noise filter enable serial output register (SO0)
Page 525 BAT32G137 user manual | Chapter 19 universal serial communication unit The block diagram of the universal serial communication unit 1 is shown in Figure 19-2. Figure 19-2 Block diagram of universal serial communication unit 1 serial output register 1(SO1) noise filter enable...
Page 526 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.2.1 shift register This is a 9-bit register that performs parallel and serial interconversion. note 1 When UART communication is performed with a 9-bit data length, a 9-bit (bit0~8) . when receiving the value to be data, the input data of the serial input pin is converted into parallel data;...
Page 527 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-3 Format of serial data register mn(SDRmn) (mn=00,01,10,11) Address: 40041310H (SDR00), 40041312H (SDR01) Reset:0000H 40041748H (SDR.10), 4004174AH(SDR.11) 40041211H (SDR00 case) 40041310H (SDR00 case) 13 12 SDRmn shift register Remark Refer to "19.3 Register to Control Universal Serial Communication Units"...
Page 528 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3 Register for controlling universal serial communication unit The registers that control the universal serial communication unit are as follows: · Peripheral Enable Register 0 (PER0). · Serial clock selection register m (SPSm) ·...
Page 529 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.1 Peripheral Enable Register 0 (PER0). The PER0 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 530 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.2 Serial clock selection register m (SPSm) The SPSm register is a 16-bit register that selects two common run-time clocks (CKm0, CKm1). CKm1 is selected by bit7~4 of the SPSm register, and CKm0 is selected by bit3~0.
Page 531 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register for setting the channel n operation mode, selecting the fMCK, specifying fSCLK whether the serial clock can be used for input.
Page 532 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-7 Format of serial mode register mn (SMRmn) (2/2) Address: 40041110H(SMR00)~40041116H(SMR03) Reset:0020H 40041550H (SMR.10)~40041552H (SMR.11) symbol 15 SMRmn SISm Note 1 Note 1 gane Note 1 Level inversion control of channel n receiving data in UART mode...
Page 533 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.4 Serial Communication Run Set-up Register mn (SCRmn) The SCRmn register is a communication operation setting register of channel n, setting data sending and receiving mode, data and clock phase, whether shielding error signal, parity check bit, start bit, stop bit and data length.
Page 534 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-8 Serial Communication Run Set-up Register mn (SCRmn) Format (2/2) Address: 40041118H(SCR00)~4004111EH(SCR03) Reset:0087H 40041558H (SCR10)~4004155AH (SCR13) symbol 15 SCRmn SLCm DLSm Note Note gane Settings for parity bits in UART mode...
Page 535 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.5 Serial data register mn (SDRmn) The SDRmn register is a data register (16-bit) sent and received by the channel n. bit8~0 (Low 9 bits) for SDR00, SDR01 or bit7~0 (Low 8 bits) for SDR02, SDR03, SDR10, SDR11 serve as transmit and receive buffer registers, and bit15~9 (High 7 bits) serve as a fractional setting register for runtime clock (fMCK).
Page 536 BAT32G137 user manual | Chapter 19 universal serial communication unit Note 1. The bit8 of the SDR02, SDR03, SDR10, SDR11 register must be set to "0". 2. When using UART, Disable from setting SDRmn[15:9] to "0000000B" and "0000001B". When Simple I using 2C, Disable from setting SDRmn[15:9] to "0000000B", setting value for SDRmn[15:9] must be...
Page 537 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.6 Serial flag clear trigger register mn (SIRmn) This is the trigger register used to clear the error flags of channel n. If the positions (FECTmn, PECTmn, OVCTmn) are set to "1", the corresponding positions (FEFmn, PEFmn, OVFmn) of the serial state register mn (SSRmn) are cleared to "0".
Page 538 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.7 Serial state register mn (SSRmn) The SSRmn register indicates the communication state of the channel n and the occurrence of an error. The errors represented are frame errors, parity errors, and overflow errors. The SSRmn register is read by a 16-bit memory operation instruction.
Page 539 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-11 Format of serial status register mn (SSRmn) (2/2) Address: 40041100H(SSR00)~40041106H(SSR03) After reset: 0000H 40041540H (SSR10)~40041542H (SSR11) symbol 15 SSRmn note 1 FEFmn Note 1 Detection flag for channel n frame errors No error occurred.
Page 540 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.8 Serial channel start register m (SSm). The SSm register is a trigger register that sets a communication/start count for each channel. If you write "1" to each (SSmn), set "1" to the corresponding bit (SEmn) of the serial channel allowed register m (SEm).
Page 541 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.9 Serial channel stop register m (STm). The STm register is a trigger register that sets a communication/stop count that allows each channel. If you write "1" to each (STmn), clear "0" (SEmn) of the Serial Channel Allowed Status Register m (SEm).
Page 542 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.10 Serial channel allows state register m (SEm). The SEm register is used to confirm the allowed or stopped states of serial transmission and reception of each channel. If the bits of register m (SSm) are given permission to start a serial, their corresponding position 1. If the bits of the serial channel stop register m (STm) are written "1", their corresponding bits are "0".
Page 543 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.11 Serial output allows register m (SOEm) The SOEm register setting allows or stops the output of serial communication for each channel. For channel n that allows serial output, the value of the SOmn bit of the serial output register m (SOm) cannot be overridden by software.
Page 544 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.12 Serial output register m (SOm). The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n.
Page 545 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.13 Serial output level register m (SOLm) The SOLm register is a register that sets the reverse phase of the data output level of each channel. This register can only be set in UART mode. In SSPI mode and simple I C mode, the corresponding position must be '0'.
Page 546 BAT32G137 user manual | Chapter 19 universal serial communication unit When UART transmission is performed, a level inversion example of the transmitted data is shown in FIG. 19-18. Figure 19-18 Example of Level Inversion for Transmitting Data (a)positive phase output (SOLmn=0)
Page 547 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.14 Input switch control register (ISC) When LIN-bus communication is implemented by UART0, the ISC1 bit and ISC0 bit of the ISC register are used for external interrupts and coordination of timer array units. If bit0 is set to '1', the input signal of the serial data input (RxD0) pin is selected as the input of the external interrupt (INTP0), thereby detecting the wake-up signal by INTP0 interrupt.
Page 548 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.15 Noise filter allows register 0 (NFEN0). The NFEN0 register sets whether the noise filter is used for the input signal of the serial data input pin of each channel.
Page 549 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.3.16 Register for controlling serial input/output pin port function When using a universal serial communication unit, you must set a port function control register (PMxx), Pxx, PIMxx, POMxx, and PMCxx).
Page 550 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.4 Idle Mode Each serial interface of the universal serial communication unit has a running stop mode. Serial communication is not possible in the operational stop mode, so power consumption can be reduced. In addition, pin used for serial interface can be used as port function in idle mode.
Page 551 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.4.2 Stop by Channel Stop operation by channel via each of the following register settings. Figure 19-24 The settings for each register when stopping operation by channel (a) Serial channel stop register m (STm)..This is a register that sets the communication/stop count for each channel.
Page 552 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5 Operation of Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Communication with 3 Lines This is clock synchronization communication through three lines of SCLK and SDO (SDI and SDO).
Page 553 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5.1 master transmission Master Send is the operation in which BAT32G137 outputs a transfer clock and sends data to other devices. 3-Wire Serial SSPI00 SSPI01 SSPI10 SSPI11 SSPI20 SSPI21 Channel 0 for...
Page 554 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-25 3-wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Example of register setting content when master sending (a) serial mode register mn (SMRmn) channel n operational clock （f ）...
Page 555 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-26 Initial set-up steps sent by master initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 556 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-28 Restart set-up steps for master send restart configuration starts. wait till commuication target (slave (mandatory) slave device ready? device) stops or communication ends via Configure port register and port...
Page 557 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single send mode) Figure 19-29 Timing diagram for master send (single send mode) (Type 1:DAPmn=0, CKPmn=0) SSmn STmn SEmn transmit data1 transmit data2 transmit data3 SDRmn SCLKp pin...
Page 558 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-30 Flowchart for Master Send (single send mode) SSPI communication starts relevant initial configuration, refer to diagram 19~26 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag (via...
Page 559 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (continuous send mode) Figure 19-31 Timing diagram for master send (continuous send mode) (Type 1:DAPmn=0, CKPmn=0) SSmn STmn SEmn transmit transmit data2 transmit data3 SDRmn data1 SCLKp pin...
Page 560 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-32 Flow chart for master send (continuous send mode) SSPI communication starts relevant initial configuration, refer to diagram 19~34 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag...
Page 561 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5.2 master receive Master reception refers to the operation of the BAT32G137 outputting a transmit clock and receiving data from other devices. 3-Wire Serial I/O SSPI00 SSPI01 SSPI10 SSPI11 SSPI20...
Page 562 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-33 3-wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Example of Register Setting Content at Master Reception (a) serial mode register mn(SMRmn) channel n operational clock （f ）...
Page 563 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-34 Initial set-up steps for master reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 564 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-36 Restart set-up steps for master receipt restart configuration starts. wait till commuication target (slave device) stops or communication ends (mandatory) slave device ready? via Configure port register and port mode...
Page 565 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single receive mode) Figure 19-37 Timing diagram of the master receive (single receive mode) (Type 1:DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception2 data reception3 data reception1 SDRmn virtual data used for receiving...
Page 566 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-38 Flowchart for Master Receive (Single Receive Mode) SSPI communication starts relevant initial configuration, refer to diagram 19~34 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear...
Page 567 BAT32G137 user manual | Chapter 19 universal serial communication unit Process Flow (Continuous Receive Mode) Figure 19-39 Timing diagram of the master receive (Continuous Receive Mode) (Type 1:DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception3 SDRmn data reception2 virtual data virtual data...
Page 568 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-40 Flowchart for Master Receive (Continuous Receive Mode) SSPI communication starts relevant initial configuration, refer to diagram 19~34(select buffer empty interrupt) SCI initial configuration For the received data, set the storage area and the...
Page 569 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5.3 Master send and receive The main control of sending and receiving refers to the BAT32G137 output transmission clock and other devices to send and receive data running. 3-Wire Serial...
Page 570 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-41 3-wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Example of register setting content when master sends and receives (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 571 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-42 Initial set-up steps for master send and receive initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 572 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-44 Restart set-up steps for master send and receive restart configuration starts. wait till commuication target (slave device) (mandatory) slave device ready? stops or communication ends via Configure port register and port mode...
Page 573 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single send and receive mode) Figure 19-45 Timing diagram for master send and receive (single send and receive mode) (Type 1:DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception2 data reception3...
Page 574 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-46 Flow chart for master send and receive (single send and receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19~42 (select transmission SCI initial configuration completion interrupt)
Page 575 BAT32G137 user manual | Chapter 19 universal serial communication unit Processing Flow (Continuous Send and Receive Mode) Figure 19-47 Timing diagram for master send and receive (continuous send and receive mode) (Type 1:DAPmn=0, CKPmn=0). SSmn STmn SEmn data reception 3...
Page 576 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-48 Flow chart for master send and receive (sequential send and receive mode) SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19~42(select buffer empty interrupt)
Page 577 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5.4 Slave send Slave sending is the operation of the microcontroller of this product transmitting data to other devices while inputting a transmission clock from other devices. 3-Wire Serial I/O...
Page 578 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-49 3-wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Examples of register setting contents at slave transmission (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 579 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-50 Initial set-up steps for slave transmission initial configuration starts release universal serial communication configure PER0 register unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 580 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-52 Restart the set-up steps for dependent delivery restart configuration starts. wait till commuication target (master device) master device stops or communication ends (mandatory) preparation complete? via Configure port register and port mode...
Page 581 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single send mode) Figure 19-53 Time Series for Slave send (single send mode) (Type 1:DAPmn=0, CKPmn=0) Type 1 SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3...
Page 582 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-54 Flowchart for Slave send (Single Send Mode) SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19~50 (select transmission completion interrupt) regarding transmit data, configure storage region and...
Page 583 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (continuous send mode) Figure 19-55 Time Series for Slave send (Continuous Send Mode) (Type 1:DAPmn=0, CKPmn=0). SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1 SCLKp pin...
Page 584 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-56 Flowchart for Slave send (Continuous Send Mode) SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19~50 (select buffer empty interrupt) regarding transmit data, configure storage region and data...
Page 585 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5.5 slave receive A slave receive is a run in which BAT32G137 receives data from other devices in a state in which a transfer clock is input from other devices. 3-Wire Serial I/O...
Page 586 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-57 3-wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Example of register setting content at slave receive (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 587 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-58 Initial set-up steps for dependent receipts initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 588 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-60 Restart set-up steps for dependent receipts restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 589 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single receive mode) Figure 19-61 Time Series of dependent receipts (single receive mode) (Type 1:DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception3 SDRmn data reception1 data reception2 Read Read...
Page 590 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-62 Flow chart for dependent receipts (single receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19-58 SCI initial configuration (select transmission completion interrupt) configure receiving data storage region, clear receiving...
Page 591 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5.6 Slave send and receive Slave sending and receiving refers to the operation of BAT32G137 microcontroller and other devices to send and receive data in the state of input transfer clock. 3-Wire Serial...
Page 592 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-63 3-wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21) Example of Register Setting Content at Slave transmission and Reception (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 593 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-64 Initial set-up steps for slave transmission and reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 594 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-65 Interrupt steps for slave transmission and reception termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 595 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-66 Restart the set-up steps for slave transmission and reception restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 596 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single send and receive mode) Figure 19-67 Time Series for Slave send and receive (Single Send and Receive Mode) (Type 1: DAPmn=0, CKPmn=0) Figure. SSmn STmn SEmn data reception1...
Page 597 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-68 Flowchart for slave send and receive (single send and receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19-64 SCI initial configuration (select transmission completion interrupt)
Page 598 BAT32G137 user manual | Chapter 19 universal serial communication unit Processing Flow (Continuous Send and Receive Mode) Figure 19-69 Time Series for Slave send and receive (Continuous Send and Receive Mode) (Type 1: DAPmn=0, CKPmn=0) Figure. SSmn STmn SEmn data reception 3...
Page 599 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-70 Flowchart for Slave send and receive (Continuous Send and Receive Mode) SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-64(select buffer empty interrupt) regarding transmit data, configure storage region and data count (via...
Page 600 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5.7 Calculation of transmission clock frequency The transfer clock frequency for 3-line serial I/O (SSPI00, SSPI01, SSPI10, SSPI20,SSPI21) communication can be calculated using the following formula. master device (Transfer Clock Frequency)={Runtime Clock ( }(SDRmn[15:9]+1)2[Hz]...
Page 601 BAT32G137 user manual | Chapter 19 universal serial communication unit Table 19-2 The Choice of 3-line Serial I/O Operating Clock SMRmn Note Runtime Clock ( SPSm register fMCK register =32 MHz Runtime CKSmn fCLK 32MHz fCLK 16MHz fCLK 8MHz fCLK...
Page 602 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.5.8 Processing steps for errors occurring during 3-wire serial I/O (SSPI00, SSPI01, communication SSPI10, SSPI11, SSPI20, SSPI21) The steps for handling errors occurring during 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) communication are shown in Figure 19-75.
Page 603 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.6 Clock synchronization serial communication operation of slave selectioninput function Channel 0 of the SCI0 is a channel for clock synchronous serial communication that supports the dependent select input function.
Page 604 BAT32G137 user manual | Chapter 19 universal serial communication unit The invention can enable 1 main control device to connect a plurality of slave devices to communicate by using the slave selection input function. The master control device outputs a slave selection signal to the slave devices of the communication object, and each slave determines whether it is selected.
Page 605 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-77 Time Series of Slave selectionInput Function DAPmn=0 configure transmit data BFFmn TSFmn SSEmn SCLKmn (CKPmn=0) SDImn sample timing sequence SDOmn SSmn During the period when SSmn is high, no transmission is performed even at the descending edge of SCKmn (serial clock) and no sampling of received data synchronized with the ascending edge is performed.
Page 606 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.6.1 Slave send Slave sending is a run in which BAT32G137 sends data to other devices in a state where a transfer clock is entered from another device. slave selectioninput...
Page 607 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-78 Slave selectionInput Function (SSPI00) Example of register setting content upon slave transmission (1/2) (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n...
Page 608 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-78 Slave selectionInput Function (SSPI00) Example of register setting content upon slave transmission (2/2) (f) serial channel start register m (SSm) Only set bit of target channel to 1.
Page 609 BAT32G137 user manual | Chapter 19 universal serial communication unit Operation Procedure Figure 19-79 Initial set-up steps for slave transmission initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 610 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-80 Abort Step for Slave transmission termination configuration starts if there are ongoing data transmission, TSFmn = 0？ (selection) then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 611 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-81 Set-up Steps for Resuming Slave Transmission restart configuration starts. wait till commuication target (master device) master device (mandatory) stops or communication ends preparation complete? via Configure port register and port mode...
Page 612 BAT32G137 user manual | Chapter 19 universal serial communication unit (3) Process flow (single send mode) Figure 19-82 Time Series for Slave send (single send mode) (Type 1:DAPmn=0, CKPmn=0) Type 1 SSmn STmn SEmn transmit data1 SDRmn transmit data 2...
Page 613 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-83 Flowchart for Slave send (Single Send Mode) SSPI communication starts relevant intial configure, please refer to diagram 19-79 (select transmission SCI initial configuration completion interrupt) regarding transmit data, configure storage region and data...
Page 614 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (continuous send mode) Figure 19-84 Time Series for Slave send (Continuous Send Mode) (Type 1:DAPmn=0, CKPmn=0). SSmn STmn SEmn SDRmn transmit data2 transmit data3 transmit data1 SCLKp pin...
Page 615 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-85 Flowchart for Slave send (Continuous Send Mode) SSPI communication starts relevant intial configure, please refer to SCI initial configuration diagram 19-79 (select buffer empty interrupt) regarding transmit data, configure storage region...
Page 616 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.6.2 slave receive A slave receive is a run in which BAT32G137 receives data from other devices in a state in which a transfer clock is input from other devices. slave selectioninput...
Page 617 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-86 Example of register setting contents (1/2) when a slave selectioninput function (SSPI00) is dependent (a) serial mode register mn (SMRmn) channel n operational clock （fMCK） interrupt source of channel n...
Page 618 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-86 Example of register setting contents (2/2) when a slave selectioninput function (SSPI00) is dependent (f) serial channel start register m (SSm) Only set bit of target channel to 1.
Page 619 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-87 Initial set-up steps for dependent receipts initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 620 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-89 Restart set-up steps for dependent receipts restart configuration starts. wait till commuication target (master device) master device stops or communication ends preparation complete? (mandatory) via Configure port register and port mode...
Page 621 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single receive mode) Figure 19-90 Time Series of dependent receipts (single receive mode) (Type 1:DAPmn=0, CKPmn=0) SSmn STmn SEmn data reception 3 SDRmn transmit data1 transmit data 2...
Page 622 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-91 Flow chart for dependent receipts (single receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19-58 SCI initial configuration (select transmission completion interrupt) configure receiving data storage region, clear receiving...
Page 623 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.6.3 Slave send and Receive Slave sending and receiving refers to the operation of sending and receiving data from BAT32G137 and other devices in the state of input transfer clocks from other devices. slave selectioninput function...
Page 624 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-92 Slave selectionInput Function (SSPI00) Example of Register Setting Content at Slave transmission and Reception (1/2) (a) serial mode register mn (SMRmn) channel n operational clock （fMCK）...
Page 625 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-92 A slave selectioninput function (SSPI00) An example of register setting content upon slave transmission and reception (2/2) (f) serial channel start register m (SSm) Only set bit of target channel to 1.
Page 626 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-93 Initial set-up steps for slave transmission and reception initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 627 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-94 Interrupt steps for slave transmission and reception termination configuration starts if there are ongoing data transmission, (selection) TSFmn = 0？ then wait till transmission completed. (if need urgent stop, then no need to wait).
Page 628 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-95 Restart the set-up steps for slave transmission and reception restart configuration starts. wait till commuication target (master device) master device preparation (mandatory) stops or communication ends complete? via Configure port register and port mode...
Page 629 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single send and receive mode) Figure 19-96 Time Series for Slave send and Receive (Single Send and Receive Mode) (Type 1: DAPmn=0, CKPmn=0) Figure. SSmn STmn SEmn data reception1...
Page 630 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-97 Flowchart for slave send and receive (single send and receive mode) SSPI communication starts relevant initial configuration, refer to diagram 19-93 SCI initial configuration (select transmission completion interrupt)
Page 631 BAT32G137 user manual | Chapter 19 universal serial communication unit Processing Flow (Continuous Send and Receive Mode) Figure 19-98 Time Series for Slave send and Receive (Continuous Send and Receive Mode) (Type 1: DAPmn=0, CKPmn=0) Figure. SSmn STmn SEmn data reception 3...
Page 632 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-99 Flowchart for Slave send and Receive (Continuous Send and Receive Mode) SSPI communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-93(select buffer empty interrupt) regarding transmit data, configure storage region and...
Page 633 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.6.4 Calculation of transmission clock frequency The transfer clock frequency of the SSPI00 communication can be calculated using the following formula. slave (Transfer Clock Frequency)={Serial Clock (SCLK) Frequency provided by the master device} Note Note The maximum allowable transfer clock frequency is fMCK/6.
Page 634 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.6.5 Processing steps when an error occurs during clock synchronization serial communication of a slave selection input function The processing steps when an error occurs during clock synchronization serial communication of a slave selection input function are shown in Figure 19-100.
Page 635 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.7 Operation of UART(UART0~UART2) Communication This is the ability to communicate asynchronously over a total of two lines, Serial Data Send (TxD) and Serial Data Receive (RxD). The two communication lines are used to transmit and receive data asynchronously (using internal baud rate) with other communication parties in data frames (consisting of start bit, data, parity bit and stop bit).
Page 636 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.7.1 UART Send UART Send is an operation where the BAT32G137 microcontroller asynchronously sends data to other devices. The even of the 2 channels used by UART are for UART transmission.
Page 637 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-101 Example of register setting content (1/2) when UART of UART (UART0~UART2) is sent (a) serial mode register mn (SMRmn) channel n operational clock (fMCK) channel n interrupt source...
Page 638 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-101 Example of register setting content (2/2) when UART of UART (UART0~UART2) is sent (e) serial output register m (SOm) Only configure bit of target channel Note Note 0: serial data output value as "0"...
Page 639 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-102 Initial set-up steps sent by UART initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 640 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-104 Restart set-up steps sent by UART restart configuration starts. wait till commuication target (slave device) stops or (mandatory) Ready to communicate? communication ends The data output of the target channel is disabled by...
Page 641 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (single send mode) Figure 19-105 Time Series for UART Send (single send mode) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2...
Page 642 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-106 Flowchart for UART Send (single send mode) UART communication starts relevant initial configuration, refer to diagram 19-102 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication completion flag...
Page 643 BAT32G137 user manual | Chapter 19 universal serial communication unit Process flow (continuous send mode) Figure 19-107 Time Series for UART Send (Continuous Send Mode) SSmn STmn SEmn SDRmn transmit data1 transmit data2 transmit data3 TxDq pin transmit data1 transmit data2...
Page 644 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-108 Flowchart for UART Send (Continuous Send Mode) UART communication starts relevant initial configuration, refer to diagram 19-102 SCI initial configuration (select transmission completion interrupt) configure transmission data and data count, clear communication...
Page 645 19.7.2 UART Receive UART Receive is an operation in which other devices of the BAT32G137 microcontroller receive data asynchronously. The odd number of the 2 channels used by UART is used for UART receiving. However, you need to set up SMR.
Page 646 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-109 Example of register setting content (1/2) for UART reception of UART (UART0~UART2) (a) serial mode register mn (SMRmn) 0: normal receiving channel n operational clock (fMCK)
Page 647 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-109 Example of register setting content (2/2) for UART reception of UART (UART0~UART2) (e) serial output register m (SOm) Not used in this mode. (f) serial output enable register m (SOEm) Not used in this mode.
Page 648 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 1 Initial Set-up Steps for 9-110 UART Reception initial configuration starts release universal serial configure PER0 register communication unit from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 649 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-112 To Restart the Set-up Steps for UART Receipts restart configuration starts. wait till commuication target stops or commuication target (mandatory) communication ends ready？ re-configure when modifing operational clock...
Page 650 BAT32G137 user manual | Chapter 19 universal serial communication unit process flow Figure 19-113 Time Series Received by UART SSmn STmn SEmn transmit data 3 SDRmn transmit data1 transmit data 2 RxDq pin data reception 3 data reception 1 data reception 2...
Page 651 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-114 Flowchart for UART Receipt UART communication starts relevant initial configuration, refer to diagram SCI initial configuration 19-110 (select transmission completion interrupt) configure reciving data storage region and communication data...
Page 652 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.7.3 Calculation of Baud Rate Formula for Baud Rate The baud rate of UART(UART0~UART2) communication can be calculated by the following formula: (baud rate)={Runtime clock ( ) frequency} (SDRmn [15:9]+1)
Page 653 BAT32G137 user manual | Chapter 19 universal serial communication unit Table 19-5. The Choice of UART Running Clock SMRmn Note SPSm register Runtime Clock ( fMCK register CKSmn =32 MHz Runtime fCLK fCLK 32MHz 16MHz fCLK 8MHz fCLK 4MHz fCLK...
Page 654 BAT32G137 user manual | Chapter 19 universal serial communication unit Baud Rate Error at Send The baud rate error of UART (UART0~UART2) communication transmission can be calculated by the following formula, the baud rate of the sender must be set within the acceptable range of the baud rate of the receiver.
Page 655 BAT32G137 user manual | Chapter 19 universal serial communication unit Acceptable range of baud rate at reception The baud tolerance of UART (UART0~UART2) communication when receiving can be calculated by the following formula, the baud rate of the sender must be set within the baud tolerance of the receiver.
Page 656 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.7.4 Processing steps when an error occurs during UART (UART0~UART2) communication The processing steps when an error occurs during UART (UART0~UART2) communication are shown in Figure 19-121 and Figure 19-122.
Page 657 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.8 Operation of LIN Communication 19.8.1 LIN Send UART0 supports LIN communication in UART delivery. LIN sends channel 0 of usage unit 0. UART UART0 UART1 UART2 LIN Communication Support —...
Page 658 BAT32G137 user manual | Chapter 19 universal serial communication unit LIN is the abbreviation of Local Interconnect Network, which is a low-speed (1~20kbps) serial communication protocol to reduce automobile network cost. LIN communications are single-master communications, with up to 15 slave devices connected to a single master device.
Page 659 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-124 Flowchart sent by LIN hardware operation(reference) LIN transmit start Transmit wakeup signal frame (80H->TxD0) generate wakeup signal frame 8 bit Transmit wakeup TxD0 TSF00=0? Note signal frame transmit data wait for transmit result stop UART0(1->ST00 bit)
Page 660 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.8.2 LIN receiving In UART receiving, UART0 supports LIN communication. The LIN receives the channel 1 of the UU. UART UART0 UART1 UART2 UART3 LIN Communication Support Channel 1 for —...
Page 661 BAT32G137 user manual | Chapter 19 universal serial communication unit A summary of the receive operations for the LIN is shown in Figure 19-125. Figure 19-125 Receive operation for LIN wake up signal frame interval field sync field identifier data field...
Page 662 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-126 Flowchart for LIN Receipt LIN Bus signal state and hardware operation. LIN communication starts wake up signal frame wait for wake up signal INTTM03 occurs? NOTE. RxD0 pin frame.
Page 663 BAT32G137 user manual | Chapter 19 universal serial communication unit The port structure diagram for LIN receive operations is shown in Figure 19-127. The wake-up signal sent by the LIN master is received through edge detection of the INTP0. The invention can measure the length of the synchronization segment sent by the LIN master and calculate the baud rate error through external event capture operation.
Page 664 BAT32G137 user manual | Chapter 19 universal serial communication unit Peripheral features for LIN communication operations are summarized as follows: <Peripheral Features Used> · External interrupt (INTP0): Detection of wake-up signal Purposes of use: Detects edges of wake- up signals and the start of communication.
Page 665 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.9 Operation of Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) Communication This is the capability of clock synchronization with multiple devices through two lines of serial clock (SCL) and serial data (SDA). Since this simple 2C is designed for single communication with EEPROM, flash memory, A/D converter, etc., it is only used as master device.
Page 666 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.9.1 address segment sending Address segment sending is a send run that is first performed when I2 communication, specifically specifying a transfer object (slave). After the start condition is generated, the address (7 bits) and the transmission direction (1 bits) are transmitted as 1 frames.
Page 667 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-128 Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) address segments sent Examples of register setting content for (a) serial mode register mn (SMRmn) Note1 Note1 channel n operational clock （fMCK）...
Page 668 BAT32G137 user manual | Chapter 19 universal serial communication unit Procedure Figure 19-129 Initial set-up steps for address segment transmission initial configuration starts release universal serial communication unit configure PER0 register from reset state, start providing clock. configure operational clock configure SPSm register configure operational mode..etc.
Page 669 BAT32G137 user manual | Chapter 19 universal serial communication unit process flow Figure 19-130 Time Sequence Diagram for Address Segment Transmission address field transmit SDLr output bit operation SDAr output Somn bit operation address SDAr input shift operation shift register mn...
Page 670 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-131 Flowchart for address segment delivery address field transmit relevant initial configuration, refer to initial configuration diagram 19-129 set SOmn bit to '0'. set SOmn bit to '0'. generate start condition...
Page 671 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.9.2 data transmission Data transmission is the operation of transmitting data to the transmission object (slave device) after the address segment is transmitted. A stop condition is generated after all data is sent to the object slave and the bus is released.
Page 672 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-132 Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) when sending data Examples of register setting content for (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 673 BAT32G137 user manual | Chapter 19 universal serial communication unit process flow Figure 19-133 Time Series of Data Transmission transmit data 1 SDLr output SDAr output SDAr input shift register mn shift operation Figure 19-134 Flow chart for data delivery address field transmit completes.
Page 674 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.9.3 data receiving Data reception is a run that receives data from a transfer object (slave) after sending an address segment. A stop condition is generated and the bus is released after receiving all the data from the object slave.
Page 675 BAT32G137 user manual | Chapter 19 universal serial communication unit Register settings Figure 19-135 Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) when receiving data Examples of register setting content for (a) serial mode register mn (SMRmn) do not operate this register wihle data is transmitting or receiving.
Page 676 BAT32G137 user manual | Chapter 19 universal serial communication unit process flow Figure 19-136 Time Series for Data Reception (a) Start of receiving data virtual data(FFH) receiving data SCLr output SDAr output SDAr input shift register mn shift operation (b) Status of receipt of final data...
Page 677 BAT32G137 user manual | Chapter 19 universal serial communication unit Figure 19-137 Flow chart for data reception address field transmit completes. data reception stop operation in order to modify set STmn bit to 1. SCRmn register cofigure channel operation mode to write "0"...
Page 678 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.9.4 Generation of Stop Condition After sending and receiving all the data with the object slave, a stop condition is generated and the bus is released. process flow Figure 19-138...
Page 679 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.9.5 Calculation of transfer rate The transfer rate for simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) communication can be calculated using the following formula. (Transfer Rate)={Runtime Clock ( ) Frequency} (SDRmn[15:9]+1)2...
Page 680 BAT32G137 user manual | Chapter 19 universal serial communication unit Table 19-6. Simple I2C Operating Clock Selection SMRmn Note Runtime Clock ( SPSm register fMCK register =32 MHz Runtime CKSmn fCLK 32MHz fCLK 16MHz fCLK 8MHz fCLK 4MHz fCLK 2MHz...
Page 681 BAT32G137 user manual | Chapter 19 universal serial communication unit 19.9.6 Processing steps when an error occurs in a simple I2C (IIC00, IIC01, IIC10, IIC11, communication process IIC20, IIC21) The processing steps when an error occurs during a simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication are shown in Figures 19-140 and 19-141.
Page 682 BAT32G137 user manual | Chapter 20 serial interface IICA Chapter 20 serial interface IICA 20.1 The Function of Serial Interface IICA The serial interface IICA has the following 3 modes. IDLE Mode This is a mode for non-serial transfer, which reduces power consumption.
Page 683 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-1 Block diagram of serial interface IICA www.mcu.com.cn 683 / 1052 V2.1.1...
Page 684 BAT32G137 user manual | Chapter 20 serial interface IICA Examples of serial bus structures are shown in Figure 20-2. Example Figure 20-2 of Serial Bus Structure for I2C Bus serial data bus master control CPU2 master control CPU1 SDAAn SDAAn...
Page 685 BAT32G137 user manual | Chapter 20 serial interface IICA 20.2 Structure of Serial Interface IICA The serial interface IICA consists of the following hardware. Table 20-1 Structure of Serial Interface IICA Project structure IICA shift register n (IICAn) register slave address register n (SVAn).
Page 686 BAT32G137 user manual | Chapter 20 serial interface IICA slave address register n (SVAn) This is a register that holds the 7-bit local station address {A6, A5, A4, A3, A2, A1, A0} when used as a slave. The SVAn register is set by an 8-bit memory operation instruction. However, this register is not allowed to be overwritten when the STDn bit is "1".
Page 687 BAT32G137 user manual | Chapter 20 serial interface IICA response generate circuit, stop condition detection circuit, start condition detection circuit, response detection circuit These circuits generate and detect various states. data hold time correction circuit (10) This circuit generates a data hold time for the serial clock drop.
Page 688 BAT32G137 user manual | Chapter 20 serial interface IICA 20.3 Register for controlling serial interface IICA The serial interface, IICA, is controlled through the following 8 registers. • Peripheral Enable Register 0 (PER0). • IICA control register n0 (IICCTLn0) •...
Page 689 BAT32G137 user manual | Chapter 20 serial interface IICA 20.3.1 Peripheral Enable Register 0 (PER0). The PER0 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 690 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (1/4) Address: 0x40041A30 After reset: 00H symbol ICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn IICCTLn0 ICEn C Run Allowed note 1 Stop running.
Page 691 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (2/4) Note 1 SPIEn Interrupt request generated by allow or disabling stop condition detection prohibition Allow The IICA control register n1(IICCTLn1) does not generate a stop condition interrupt even if the SPIEn position '1' is set.
Page 692 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (3/4) Notes 1, 2 STTn Trigger of Start Condition Do not generate a start condition. When the bus is released (standby, IICBSYn bit is "0"): If this position is "1", a start condition is generated (as the start of...
Page 693 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-6 Format of IICA control register n0 (IICCTLn0) (4/4) Note SPTn Trigger of stop condition No stop condition is generated. Generate a stop condition (end of transfer as master device).
Page 694 BAT32G137 user manual | Chapter 20 serial interface IICA 20.3.3 IICA status register n (IICSn) This is a register that represents the I2C status. The 8-bit memory operation instruction can read the IICSn register only if the STTn bit is "1" and the wait period.
Page 695 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-7 Format of IICA state register n(IICSn) (2/3) Receiving Detection of Spreading Codes EXCn The extension code was not received. An extension code was received. Purge Criteria (EXCn=0) Placement Criteria (EXCn=1) ·...
Page 696 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-7 Format of IICA state register n(IICSn) (3/3) Detection of Acknowledgements (ACKs) ACKDn No replies detected. An acknowledgement was detected. Purge Criteria (ACKDn=0) Placement Criteria (ACKDn=1) · When a stop condition is detected ·...
Page 697 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-8 Format of IICA flag register n(IICFn) W Notes Address: 0x40041B52 After reset: 00H symbol IICFn STCFn ICBSYn STCENn IICRSVn STTn clear flag STCFn Release Start Condition. The STTn flag cannot be cleared by issuing a start condition.
Page 698 BAT32G137 user manual | Chapter 20 serial interface IICA 20.3.5 IICA control register n1 (IICCTLn1) This is a register used to set the I2C run mode and detect the status of the SCLAn and SDAAn pins. The IICCTLn1 register is set by an 8-bit memory operation instruction. However, only CLDn and DADn bits can be read.
Page 699 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-9 Format of IICA control register n1 (IICCTLn1) (2/2) SCLAn pin level detection (only valid if IICEn bit is "1") CLDn The SCLAn pin is detected as low. High SCLAn pin level detected.
Page 700 BAT32G137 user manual | Chapter 20 serial interface IICA 20.3.6 IICA Low level width setting register n (IICWLn) This register controls the SCLAn pin signal low level width (tLOW) and the SDAAn pin signal output by the serial interface IICA.
Page 701 BAT32G137 user manual | Chapter 20 serial interface IICA 20.3.8 Port mode register x (PMx) This register sets the input/output of the port. Port mode register PMx and port output latch Px must be set to '0' when the Pxx/SCLA0 pin is used as clock input/output and Pxx/SDAA0 pin.
Page 702 BAT32G137 user manual | Chapter 20 serial interface IICA 20.4 Functions of I2C bus mode 20.4.1 pin structure The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are structured as follows. (1) SCLAn..Input/output pin for serial clock The output of the master device and the slave device are N-channel drain open circuit output, and the input is Schmidt input.
Page 703 BAT32G137 user manual | Chapter 20 serial interface IICA 20.4.2 Method for setting transmission clock through IICWLn register and IICWHn register Setting method for main control party transmitting clock fMCK Transfer Clock CK tR tF At this point, the best values for the IICWLn register and the IICWHn register are as follows: (Decimal portion of all set values rounded) ·...
Page 704 BAT32G137 user manual | Chapter 20 serial interface IICA 2.IICWLn :IICA low level width set-up register n ICWHn :IICA high level width set-up register n Down time of SDAAn and SCLAn signals rise time of SDAAn and SCLAn signals : IICA Run Clock Frequency fMCK 3.n=0...
Page 705 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.2 Address Subsequent 7-bit data for the start condition is defined as an address. The address is 7 bits of data output by the master control device for selecting a specific slave device from among a plurality of slave devices connected to the bus.
Page 706 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.4 Acknowledge (ACK) The serial data status of the sender and receiver can be confirmed by an acknowledgement (ACK). The receiver returns a reply each time it receives 8 bits of data.
Page 707 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.5 stop condition When the SCLAn pin is a high level, a stop condition is generated if the SDAAn pin changes from a low level to a high level. The stop condition is a signal generated when the master device finishes serial transfer to the slave device.
Page 708 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.6 waiting Notify the other master or slave to prepare the sending/receiving of data by waiting (waiting state). Notify the other party that it is waiting by placing the SCLAn pin at a low level. If both the master device and the slave device wait states are released, the next transfer can begin.
Page 709 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-20 Waiting (2/2) When the master and slave are waiting for 9 clocks (Main control equipment: Send, slave: Receive, ACKEn=1) master device and master slave device all enter device into wait state after output 9th clock.
Page 710 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.7 Waitinging Release Method In general, that I C can relieve the wait by the following treatment. • Write data to IICA shift register n(IICAn). • Set the bit5(WRELn) of the IICA control register n0(IICCTLn0) to Release Waiting.
Page 711 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.8 Generation Timing and Waiting Control of Interrupt Request (INTIICAn) By setting a bit3 (WTIMn) of the IICA control register n0 (IICCTLn0), INTIICAn is generated in the timing shown in Table 20-2 and is subjected to wait control.
Page 712 BAT32G137 user manual | Chapter 20 serial interface IICA (4) Method of rescission of waiting There are four methods for the release of the waiting: · Write data to IICA shift register n(IICAn). · Set the bit5(WRELn) of the IICA control register n0(IICCTLn0) to Release Waiting.
Page 713 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.11 extension code (1) When the 4th bit of the receiving address is '0000' or '1111', the expansion code receiving flag (EXCn) is set '1' and an interrupt request (INTIICAn) is generated at the descending edge of the eighth clock.
Page 714 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.12 arbitration When a plurality of master devices generate start conditions at the same time (STTn position "1" before the STDn bit changes to "1"). This run is called arbitration. When arbitration failure occurs, the master control device sets ALDn of IICA state register n(IICSn) to "1", and sets SCLAn and SDAAn lines to high impedance state, releasing the bus.
Page 715 BAT32G137 user manual | Chapter 20 serial interface IICA Table 20-4 The status at the time of arbitration and the sequence in which the interrupt request is generated Status when arbitration occurs Generation sequence of interrupt requests address sending process...
Page 716 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.13 wake-up function This is a dependent function of I2C, which is the function of generating an interrupt request signal (INTIICAn) upon receipt of the local station address and expansion code. In the case of different addresses, the unnecessary INTIICAn signal is not generated, thereby improving the processing efficiency.
Page 717 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-23 The process of "0" WUPn by address matching, including receiving an extension code deep sleep mode state INTIICAn=1？ WUPn=0 wait wait for 5 fMCK clock. Read IICSn after confirming serial interface IICA operation status, process accordingly.
Page 718 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-24 Operating as a master device after deep sleep mode is removed by an interrupt other than INTIICAn START SPIEn=1 WUPn=1 wait deep sleep instruction deep sleep mode state release deep sleep mode using other interrupt release deep sleep mode than INTIICAn.
Page 719 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.14 communication reservation The case where the communication reservation function is allowed (IICA flag register n(IICFn) bit0(IICRSVn)=0) When the next master control communication is performed in the state of not joining the bus, a start condition can be sent when the bus is released by a communication reservation.
Page 720 BAT32G137 user manual | Chapter 20 serial interface IICA The timing of the communication reservation is shown in Figure 20-25. Figure 20-25 Timing of communication appointments program 写IICAn STTn=1 processing. hardware SPDn and communi STDnset INTIICAn cation processing. to '1'...
Page 721 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-27 Steps for communication reservation stop interrupt request set STTn flag to '1' STTn=1 (communication preserve) define communication define as in communication preserve state. preservation ( to configure and set user flag of any RAM)
Page 722 BAT32G137 user manual | Chapter 20 serial interface IICA Case where communication reservation is disabled (IICA flag register n(IICFn) bit0(IICRSVn)=1) During bus communication, if the bit1(STTn) of IICA control register n0(IICCTLn0) is set to "1" without taking part in this communication, this request is rejected and no start condition is generated. The non-join bus at this time includes the following two states: ·...
Page 723 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.15 Other Precautions (1) Cases with STCENn bit "0" Immediately after I C is allowed to run (IICEn=1), the actual bus state is considered as the communication state (IICBSYn=1). In order to perform the master control communication in a state where no stop condition is detected, the stop condition must be generated, and the master control communication is performed after the bus is released.
Page 724 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.16 communication operation The following 3 run steps are shown through the flowchart. Main Control Operation of Single Master Control System The flow chart used as the master device in a single master system is shown below.
Page 725 BAT32G137 user manual | Chapter 20 serial interface IICA Main Control Operation of Single Master Control System Figure 20-28 Main Control Operation of Single Master Control System START release serial interface IICA from reset state, configure PER0 register start providing clock.
Page 726 BAT32G137 user manual | Chapter 20 serial interface IICA Master Control Operation of Multi-Master Control System Figure 20-29 Main control operation of multi-master control system (1/3) START release serial interface IICA from reset state, configure PER0 register start providing clock.
Page 727 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-29 Main control operation of multi-master control system (2/3) allow communication preservation prepare starting STTn=1 communication. (generate stop condition) ensure wait time via Wait Note. software. MSTSn=0？ does INTIICAn interrupt...
Page 728 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-29 Main control operation of multi-master control system (3/3) Start communication. Write IICAn (Specify address and transfer direction) does INTIICAn interrupt wait for detecing occur? acknowledgement MSTSn=1？ ACKDn=1？ TRCn=1？ ACKEn=1...
Page 729 BAT32G137 user manual | Chapter 20 serial interface IICA slave operation The processing steps for a Slave Run are as follows. Dependent runs are essentially event driven and therefore require processing through INTIICAn interrupts (requiring significant change processing of operational states such as stop condition detection in communications).
Page 730 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-30 Slave Run Step (1) START release serial interface IICA from reset state, configure PER0 register start providing clock. configure pins and multiplexed ports to be used. Configure Port First port configured to be input mode and output latch set to "0“...
Page 731 BAT32G137 user manual | Chapter 20 serial interface IICA An example of the steps for a slave device to process through INTIICAn interrupts is shown below (assuming no processing with an expander in this scenario). The status is interrupted by INTIICAn and the following processing is performed.
Page 732 BAT32G137 user manual | Chapter 20 serial interface IICA 20.5.17 I2C Generation Sequence of Interrupt Requests (INTIICAn) The values for the sending and receiving sequence of the data, the generation sequence of the INTIICAn interrupt request signal, and the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below.
Page 733 BAT32G137 user manual | Chapter 20 serial interface IICA master run Start~Address~Data~Data~Stop (send and receive) WTIMn=0's situation SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B Note 3:IICSn=1000X000B(set WTIMn bit to 4:IICSn=1000XX00B(set SPTn bit to 1 ) 5:IICSn=00000001B Note: to generate stop condition, must set WTIMn bit to '1' and modify INTIICAn interrupt requet signal generation timing sequenc e.
Page 734 BAT32G137 user manual | Chapter 20 serial interface IICA Start~Address~Data~Start~Address~Data~Stop (Start Over) WTIMn=0's situation STTn=1 SPTn=1 ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=1000X110B Note1 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000XX00B(set WTIMn bit to Note 2 and set STTn bit to 4:IICSn=1000X110B...
Page 735 BAT32G137 user manual | Chapter 20 serial interface IICA Start~Code~Data~Data~Stop (send extension code) WTIMn=0's situation SPTn=1 ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=1010X110B 2:IICSn=1010X000B Note 3:IICSn=1010X000B(set WTIMn bit to 4:IICSn=1010XX00B(set SPTn bit to 1 ) 5:IICSn=00000001B Note： to generate stop condition, must set WITIMn bit to '1' and modify INTIICAn interrupt request signal generation timing sequence.
Page 736 BAT32G137 user manual | Chapter 20 serial interface IICA Slave Run (When You Receive a Slave Address) Start~Address~Data~Data~Stop WTIMn=0's situation ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X000B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) WTIMn=1's situation...
Page 737 BAT32G137 user manual | Chapter 20 serial interface IICA Start~Address~Data~Start~Address~Data~Stop The case of WTIMn=0 (SVAn is the same after the restart) ST AD6~AD0 R/W ACK D7~D0 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 738 BAT32G137 user manual | Chapter 20 serial interface IICA Start~Address~Data~Start~Code~Data~Stop The case of WTIMn=0 (different address after restart (extension code)) ST AD6~AD0 R/W ACK D7~D0 ST AD6~AD0 R/W ACK D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 739 BAT32G137 user manual | Chapter 20 serial interface IICA Start~Address~Data~Start~Address~Data~Stop The case of WTIMn=0 (addresses differ after restart (non-expander)) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0001X110B 2:IICSn=0001X000B 3:IICSn=00000110B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) the case of WTIMn=1, with a different address (non-expander) after the restart...
Page 740 BAT32G137 user manual | Chapter 20 serial interface IICA Slave Run (Case of Receiving Extension Code) Always participate in communication when you receive an expansion code. Start~Code~Data~Data~Stop WTIMn=0's situation ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X000B 4:IICSn=00000001B Remark must generate...
Page 741 BAT32G137 user manual | Chapter 20 serial interface IICA Start~Code~Data~Start~Address~Data~Stop The case of WTIMn=0 (SVAn is the same after the restart) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0001X110B 4:IICSn=0001X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 742 BAT32G137 user manual | Chapter 20 serial interface IICA Start~Code~Data~Start~Code~Data~Stop The case of WTIMn=0 (receive an extension after restart) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=0010X010B 4:IICSn=0010X000B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 743 BAT32G137 user manual | Chapter 20 serial interface IICA Start~Code~Data~Start~Address~Data~Stop The case of WTIMn=0 (addresses differ after restart (non-expander)) ST AD6~AD0 D7~D0 ST AD6~AD0 D7~D0 1:IICSn=0010X010B 2:IICSn=0010X000B 3:IICSn=00000X10B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' (ii) the case of WTIMn=1, with a different address (non-expander) after the restart...
Page 744 BAT32G137 user manual | Chapter 20 serial interface IICA Not participating in the operation of the communication Start~Code~Data~Data~Stop Remark The run of the arbitration failure (run as a slave after the arbitration failure) When used as a master device in a multi-master system, the MSTSn bit must be read each time a INTIICAn interrupt request signal is generated to confirm arbitration.
Page 745 BAT32G137 user manual | Chapter 20 serial interface IICA WTIMn=1's situation (ii) ST AD6~AD0 R/W D7~D0 D7~D0 1:IICSn=0101X110B 2:IICSn=0001X100B 3:IICSn=0001XX00B 4:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' Arbitration failure during the sending of an extension code...
Page 746 BAT32G137 user manual | Chapter 20 serial interface IICA WTIMn=1's situation (ii) ST AD6~AD0 R/W ACK D7~D0 D7~D0 1:IICSn=0110X010B 2:IICSn=0010X110B 3:IICSn=0010X100B 4:IICSn=0010XX00B 5:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' Run of arbitration failure (do not participate in communication after arbitration failure) When used as a master device in a multi-master system, the MSTSn bit must be read each time a INTIICAn interrupt request signal is generated to confirm arbitration.
Page 747 BAT32G137 user manual | Chapter 20 serial interface IICA Arbitration failure during the sending of an extension code ST AD6~AD0 D7~D0 D7~D0 1:IICSn=01000110B set LRELn bit to '1' via software 2:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1'...
Page 748 BAT32G137 user manual | Chapter 20 serial interface IICA (ii) WTIMn=1's situation ST AD6~AD0 D7~D0 D7~D0 1:IICSn=10001110B 2:IICSn=01000100B 3:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' A situation where arbitration fails due to restart conditions when data is transmitted Non-expander (e.g., SVAn is different)
Page 749 BAT32G137 user manual | Chapter 20 serial interface IICA (ii) Expander ST AD6~AD0 R/W D7~Dm ST AD6~AD0 D7~D0 1:IICSn=1000X110B 2:IICSn=01000010B set LRELn bit to '1' via software 3:IICSn=00000001B Remark must generate only generate while SPIEn bit is '1' m=0~6 A situation in which arbitration fails due to a stop condition when transferring data...
Page 750 BAT32G137 user manual | Chapter 20 serial interface IICA A case where arbitration fails because the data is low when a restart condition is to be generated WTIMn=0's situation STTn=1 ST AD6~AD0 D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to...
Page 751 BAT32G137 user manual | Chapter 20 serial interface IICA A situation where arbitration fails due to a stop condition when a restart condition is to be generated WTIMn=0's situation STTn=1 ST AD6~AD0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to 3:IICSn=1000XX00B(set STTn bit to 1 )
Page 752 BAT32G137 user manual | Chapter 20 serial interface IICA A case where arbitration fails because the data is low when a stop condition is to be generated WTIMn=0's situation SPTn=1 ST AD6~AD0 D7~D0 D7~D0 D7~D0 1:IICSn=1000X110B 2:IICSn=1000X000B(set WTIMn bit to...
Page 753 BAT32G137 user manual | Chapter 20 serial interface IICA 20.6 Timing diagram In I2C bus mode, a master device selects a slave device as the communication object among a number of slave devices by outputting an address to a serial bus. The master device sends a TRCn bit (bit3 of the IICA status register n (IICSn) representing the data transmission direction after the slave device address and starts serial communication with the slave device.
Page 754 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-32 Communication example of master device slave (Main control equipment: Select 9 clock wait, slave: Select 9 clock wait) (1/4) Start Condition ~ Address ~ Data master control Note IICAn ACKDn （ACK...
Page 755 BAT32G137 user manual | Chapter 20 serial interface IICA Note 1. To unblock the wait during a master send, you must write data to IICAn instead of placing the WRELn location bit. 2. The time to decrease the SDAAn pin signal to the SCLAn pin signal is at least 4.0us when set to standard mode and at least 0.6us when set to fast mode.
Page 756 BAT32G137 user manual | Chapter 20 serial interface IICA FIG. 20-32 Descriptions of (1) to (6) of (1) starting condition ~ address ~ data are as follows: ①If the master triggers the setting (STTn=1), the bus data line (SDAAn) drops and generates a start condition (SDAAn changes from 1 to 0).
Page 757 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-32 Communication example of master device slave (Main control equipment: Select 9 clock wait, slave: Select 9 clock wait) (2/4) Address~Data~Data master control note note 1 IICAn ACKDn （ACK detection ）...
Page 758 BAT32G137 user manual | Chapter 20 serial interface IICA FIG. 20-32 Descriptions of (3) to (10) for (2) Address ~ Data ~ Data: ) are (3) In the secondary party, if the receiving address and the local station address (value of SVAn the same note, the ACK is sent to the master via hardware.
Page 759 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-32 Communication example of master device slave (Main control equipment: Select 9 clock wait, slave: Select 9 clock wait) (3/4) (14) Data~Data~Stop Condition master control IICAn note1 ACKDn （ACK detection ）...
Page 760 BAT32G137 user manual | Chapter 20 serial interface IICA Note 1. To unblock the wait during a master send, you must write data to IICAn instead of placing the WRELn location bit. 2. The time from the SCLAn pin signal to generating the stop condition after issuing the stop condition is at least 4.0us when set to standard mode and at least 0.6us when set to fast mode.
Page 761 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-32 Communication example of master device slave (Main control equipment: Select 9 clock wait, slave: Select 9 clock wait) (4/4) Data ~ Restart Condition ~ Address master control IICAn <3>...
Page 762 BAT32G137 user manual | Chapter 20 serial interface IICA Note 1. The time from the SCLAn pin signal to the generation start condition after the release restart condition is at least 4.7us in standard mode and at least 0.6us in fast mode.
Page 763 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-33 Example of communication for a slave master device (Main control equipment: Select 8-clock wait, slave: Select 9 clock wait) (1/3) Start Condition ~ Address ~ Data master control IICAn ACKDn （ACKdetection）...
Page 764 BAT32G137 user manual | Chapter 20 serial interface IICA FIG. 20-33 Descriptions of (1) to (7) of "1th Condition ~ Address ~ Data" are as follows: (1) If the master triggers the setting (STTn=1), SDAAn descends to generate the starting condition (SCLAn=1 changes SDAAn from "1").
Page 765 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-33 Example of communication for a slave master device (Main control equipment: Select 8-clock wait, slave: Select 9 clock wait) (2/3) Address~Data~Data master control IICAn ACKDn （ACKdetection） WTIMn （8 or 9 clock cycles waiting）...
Page 766 BAT32G137 user manual | Chapter 20 serial interface IICA FIG. 20-33 (3)- (12) of "2) Address-Data" are described as follows: ) are (3) In the secondary party, if the receiving address and the local station address (value of SVAn the same note, the ACK is sent to the master via hardware.
Page 767 BAT32G137 user manual | Chapter 20 serial interface IICA Figure 20-33 Example of communication for a slave master device (Main control equipment: Select 8 9 clock waits, slave: Select 9 clock waits) (3/3) Data~Data~Stop Condition master control IICAn ACKDn （ACKdetection）...
Page 768 BAT32G137 user manual | Chapter 20 serial interface IICA Note 1. To unwait, you must either place the IICAn in "FFH" or place the WRELn position. 2. The time from the SCLAn pin signal to generating the stop condition after issuing the stop condition is at least 4.0us when set to standard mode and at least 0.6us when set to fast mode.
Page 769 BAT32G137 user manual | Chapter 21 CAN Controller Chapter 21 CAN Controller 21.1 Summary Description The chip has on-chip CAN controller (controller LAN) functionality and complies with the standard CAN protocol of ISO 11898. 21.1.1 feature ISO 11898 compliant and tested against ISO/DIS 16845 (CAN compliance) Standard and extended frames for receiving and transmitting Up to 1 Mbps.
Page 770 BAT32G137 user manual | Chapter 21 CAN Controller 21.1.2 Functional Overview Table 21-1 lists the functions of the CAN controller. Table 21-1. Functional Overview Features Details agreement ISO 11898 CAN Protocol (standard and extended frame send/receive) Max: 1 Mbps (CAN input...
Page 771 BAT32G137 user manual | Chapter 21 CAN Controller 21.1.3 configuration The CAN controller consists of the following four modules interaction This module provides an internal interactive bus to send and receive signals between the CAN module and the host. Memory Control Module (MCM) This block controls access to the CAN RAM in the CAN protocol layer and the CAN module.
Page 772 BAT32G137 user manual | Chapter 21 CAN Controller 21.2 CAN protocol CAN (Controller Area Network) is a high speed multi-channel communication protocol for real-time communication in automotive applications. CAN is specified by ISO 11898. For more information, see the ISO 11898 specification.
Page 773 BAT32G137 user manual | Chapter 21 CAN Controller 21.2.2 Frame Type The four frame types in the following table are used in the CAN protocol. Table 21-2. Frame Types Frame Type Description data frame Frames for transmitting data remote frame...
Page 774 BAT32G137 user manual | Chapter 21 CAN Controller (5) remote frame The remote frame is composed of 6 bit fields. Figure 21-4. Remote frames remote frame Interframe Space End Frame (EOF) Acknowledgement Field CRC field control field arbitration field start frame (SOF) Note 1.
Page 775 BAT32G137 user manual | Chapter 21 CAN Controller <2> Arbitration Court Arbitrations are used to set priority, data/remote and frame formats Figure 21-6. The Arbitral Tribunal (in Standard Format) arbitration fields control fields identifier identifier (11 bit) (1 bit) (1bit)
Page 776 BAT32G137 user manual | Chapter 21 CAN Controller <3> control field The control field sets 'DLC' as the number of bytes of data in the data field (DLC=0 to 8). Figure 21-8. Control field (arbitration fields) control fields (Data fields)
Page 777 BAT32G137 user manual | Chapter 21 CAN Controller <4> Data Field The data field contains the amount of data (in bytes) that controls the field settings. Up to 8 data units can be set. Figure 21-9. Data fields Note D: Explicit=0 R: Implicit=1 <5>...
Page 778 BAT32G137 user manual | Chapter 21 CAN Controller <6> acknowledgement field The response field is mainly to respond to normal reception Figure 21-11. Response field Note D: Explicit=0 R: Implicit=1 - If no CRC error is detect, that receive node sets the response to an dominant bit - The sending node outputs two hidden bits <7>...
Page 779 BAT32G137 user manual | Chapter 21 CAN Controller <8> interframe space Interframe space is used to insert between data frames, remote frames, error frames, or overloaded frames to distinguish between two frames. - Different bus states Different error-based states ) Error Activity Node The inter-frame space contains a 3-bit gap field and a bus idle field.
Page 780 BAT32G137 user manual | Chapter 21 CAN Controller 21.2.4 error frame If an error is detected, error frames are sent at the next node. Figure 21-15. Error Frame Note D: Explicit=0 R: Stealth=1 Table 21-7. Definition of Error Frames First Name...
Page 781 BAT32G137 user manual | Chapter 21 CAN Controller 21.2.5 overload frame Overload frames are issued in the following cases. - When the receiving node does not complete the receiving operation - During a gap, if the first two bits are detected...
Page 782 BAT32G137 user manual | Chapter 21 CAN Controller 21.3 Features 21.3.1 bus priority setting (1) When a node starts transmitting: - When the bus is idle, the node output data starts (2) When more than one node starts transmission: - The node continuously outputs the longest dominant bit from the first bit of the arbitration field to capture the priority of the bus (the dominant bit is the bus value if both the dominant bit and the invisible bit transmit simultaneously).
Page 783 BAT32G137 user manual | Chapter 21 CAN Controller 21.3.6 error control function (4) Error Type Table 21-11. Error Types Error Description Detect Status Type detection Send/Receive detection method Field/Frame condition bits of data between the start Comparing output level and...
Page 784 BAT32G137 user manual | Chapter 21 CAN Controller (7) Error Status (a) Type of error status The next three error states are defined by the CAN specification - error initiative - error passive - bus shutdown The error type is determined by the CAN error count register (C0ERC) TEC0 to TEC7 and REC0 to REC6 values, shown in Table 21-13.
Page 785 BAT32G137 user manual | Chapter 21 CAN Controller (b) error counter When the error occurs, the error counter counts upward; When successful acceptance and sending, the error counter counts down. When an error is detected, the value of the error counter is updated immediately.
Page 786 BAT32G137 user manual | Chapter 21 CAN Controller (8) bus shutdown recovery When the CAN module is in the bus closed state, the CAN module permanently sets its output signal (CTxD) as the hidden bit. The CAN module recovers from the bus shutdown state in the following bus shutdown recovery sequence.
Page 787 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-17. Recovery operation from bus-off state by normal recovery sequence TEC>FFH »passive error« »bus turns off « »bus recovery sequence« »actively (generated) error« BOFFbit of C0INFO C0CTRL 中OPMODE[2:0] （user write） C0CTRL 中OPMODE[2:0] （user read）...
Page 788 BAT32G137 user manual | Chapter 21 CAN Controller 21.3.7 baud rate control (10) pre-scaling The CAN controller has a pre-scaling for dividing a clock (fCAN) provided to the CAN. This pre-scaling generates a CAN protocol layer basic clock (fTQ) derived from the CAN module system clock (fCANMOD), divided between 1 and 256 (see 21.6 (12) CAN bit rate pre-scaler register (C0BRP)
Page 789 BAT32G137 user manual | Chapter 21 CAN Controller Reference: The CAN standard, ISO 11898, define that segment that make up the data bit time as shown in Figure 21-19. Figure 21-19. Reference: Data bit time configuration defined by the CAN specification...
Page 790 BAT32G137 user manual | Chapter 21 CAN Controller (12) synchronization data bit - The receiving node establishes synchronization by level changes on the bus because it has no asynchronous signal. - The transmission node transmits data synchronously at the bit time of the transmission node...
Page 791 BAT32G137 user manual | Chapter 21 CAN Controller (b) resynchronization If a level change is detect on that bus during reception, a synchronization is established again (only if the covert level has previously been sampled). - The phase error of the edge is given by the relative position of the detected edge and the synchronization segment.
Page 792 BAT32G137 user manual | Chapter 21 CAN Controller 21.4 Connection to target system The CAN-integrated microcontroller must use an external transceiver to connect to the CAN bus. Figure 21-22. Connecting to the CAN Bus CAN_L CAN_H www.mcu.com.cn 792 / 1052...
Page 793 BAT32G137 user manual | Chapter 21 CAN Controller 21.5 Internal register for CAN controller 21.5.1 CAN controller configuration Table 21-15. List of CAN Controller Registers (1/2) Items register name Peripheral Enable Register 0 (PER0) Serial Communication Pin Selection Register (PIOR3)
Page 794 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-15. List of CAN Controller Registers (2/2) Items register name message cache register CAN message data byte 01 register m (C0MDB01m) CAN message data byte 0 register m (C0MDB0m) CAN message data byte 1 register m (C0MDB1m)
Page 795 BAT32G137 user manual | Chapter 21 CAN Controller 21.5.2 register access type The peripheral I/O registers of the CAN controller are located in the range of 0x40045400 to 0x400455FF. Table 21-16. Register Access Types (1/9) Address register name Symbol read/writ...
Page 796 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-16. Register Access Types (2/9) Address register name Symbol read/ bit operation unit Default write 0x40045500H CAN0 message data byte 01 register 00 C0MDB0100 read/ No definition write 0x40045500H CAN0 message data byte 0 register 00...
Page 797 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-16. Register Access Types (3/9) Address register name Symbol read/ bit operation unit Default write 0x40045520H CAN0 message data byte 01 register 02 C0MDB0102 read/ No definition write 0x40045520H CAN0 message data byte 0 register 02...
Page 798 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-16. Register Access Types (4/9) Address register name Symbol read/ bit operation unit Default write 0x40045540H CAN0 message data byte 01 register 04 C0MDB0104 read/ No definition write 0x40045540H CAN0 message data byte 0 register 04...
Page 799 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-16. Register Access Types (5/9) Address register name Symbol read/ bit operation unit Default write 0x40045560H CAN0 message data byte 01 register 06 C0MDB0106 read/ No definition write 0x40045560H CAN0 message data byte 0 register 06...
Page 800 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-16. Register Access Types (6/9) Address register name Symbol read/ bit operation unit Default write 0x40045580H CAN0 message data byte 01 register 08 C0MDB0108 read/ No definition write 0x40045580H CAN0 message data byte 0 register 08...
Page 801 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-16. Register Access Types (7/9) Address register name Symbol read/ bit operation unit Default write 0x400455A0H CAN0 message data byte 01 register 10 C0MDB0110 read/ No definition write 0x400455A0 CAN0 message data byte 0 register 10...
Page 802 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-16. Register Access Types (8/9) Address register name Symbol read/ bit operation unit Default write 0x400455C0H CAN0 message data byte 01 register 12 C0MDB0112 read/ No definition write 0x400455C0H CAN0 message data byte 0 register 12...
Page 803 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-16. Register Access Types (9/9) Address register name Symbol read/ bit operation unit Default write 0x400455E0H CAN0 message data byte 01 register 14 C0MDB0114 read/ No definition write 0x400455E0H CAN0 message data byte 0 register 14...
Page 804 BAT32G137 user manual | Chapter 21 CAN Controller 21.5.3 register bit configuration Table 21-17. CAN Global Register Bit Configuration Address Symbol Bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 0x40045400H C0GMCTRL(W) ClearGOM...
Page 805 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-18. Bit configuration of CAN module register (1/2) Address Symbol Bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 0x40045440H C0MASK1L CM1ID[7:0] 0x40045441H CM1ID [15:8]...
Page 806 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-18. Bit configuration of CAN module register (2/2) Address Symbol Bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 0x40045458H C0INS CINTS5 CINTS4 CINTS3...
Page 807 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-19. Bit configuration for message buffer registers Address Symbol Bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 0x400455x0H Message Data (Byte0) C0MDB01m 0x400455x1H...
Page 808 BAT32G137 user manual | Chapter 21 CAN Controller 21.6 Bit Settings/Clean-up The CAN control register includes a register whose bit can be set or cleared through a CPU and a CAN interface. If written directly to the following register, an operation error occurs. Do not write any values directly through bit operations, read/modify/write, or direct write to the target value.
Page 809 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-24. 16-bit data in a write operation Set7 Set6 Set5 Set4 Set3 Set2 Set1 Set0 Clear7 Clear6 Clear5 Clear4 Clear3 Clear2 Clear1 Clear0 Seton Clearn Set/Cleared n Status No change No change Note n = 0 to 7 www.mcu.com.cn...
Page 810 BAT32G137 user manual | Chapter 21 CAN Controller 21.7 control register Note m = 0 to 15 Peripheral clock selection register (PER0) PER0 is used to enable or disable each peripheral hardware macro. The PER0 can be set with 8-bit memory manipulation instructions.
Page 811 BAT32G137 user manual | Chapter 21 CAN Controller CAN Global Module Control Register (C0GMCTRL) The C0GMCTRL register is used to control the operation of the CAN module. Figure 21-26. CAN Global Module Control Register Format (C0GMCTRL) (1/2) (a) read (a) write...
Page 812 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-26. CAN Global Module Control Register Format (C0GMCTRL) (2/2) EFSD bit-enabled forcible shutdown Disable Shutdown by Writing GOM=0 Enable to close by writing GOM=0. Note To request a forced shutdown, you must clear the GOM bit of 0 in subsequent operations and write immediately after the EFSD bit is set to 1.
Page 813 BAT32G137 user manual | Chapter 21 CAN Controller CAN Global Module Clock Select Register (C0GMCS) The system clock used by C0GMCS and C1GMCS to select the CAN module. Figure 21-27. CAN Global Module Clock Select Register Format (C0GMCS) C0GMCS CCP3...
Page 814 BAT32G137 user manual | Chapter 21 CAN Controller CAN Global Automatic Block Transfer Control Register (C0GMBT) C0GMABT registers are used to control automatic block transfer (ABT) operations Figure 21-28. Format of CAN Global Automatic Block Transfer Control Register (C0GMBT) (1/2)
Page 815 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-28. Format of CAN Global Automatic Block Transfer Control Register (C0GMBT) (2/2) ATTRG Automatic Block Transmit Status Bit Automatic block transfer stopped Automatic block transfer in progress Note Do not set the ABTTRG bit (ABTTRG =1) in initialization mode. If the ABTTRG bit is set in the initialization mode, the operation cannot be guaranteed after the CAN module enters the normal operation mode using ABT.
Page 816 BAT32G137 user manual | Chapter 21 CAN Controller CAN Global Automatic Block Transfer Delay Set-up Register (C0GMABTD) The C0GMABTD register is used to set the time interval for the transmission of message buffer data allocated to the ABT in normal operation mode of the ABT.
Page 817 BAT32G137 user manual | Chapter 21 CAN Controller CAN module mask register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) The C0MASKaL and C0MASKaH registers extend the number of entries into the same packet cache by comparing the masked portion with the packet ID and invalidating the ID of the masked portion.
Page 818 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-30. Format of the CAN module mask register (C0MASKaL, C0MASKaH) (a = 1, 2, 3, or 4) (2/2) CAN Module Masking 3 register (C0MASK3L, C0MASK3H) CAN Module Masking 4 register (C0MASK4L, C0MASK4H)
Page 819 BAT32G137 user manual | Chapter 21 CAN Controller CAN Module Control Register (C0CTRL) The C0CTRL register is used to control the operation mode of the CAN module. Figure 21-31. Format of CAN Module Control Register (C0CTRL) (1/4) (a) read (b) write...
Page 820 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-31. Format of CAN Module Control Register (C0CTRL) (2/4) TSTAT Transmit Status Bit Transmission stopped Transmission in progress Note - The RSTAT bit is set to 1 under the following conditions...
Page 821 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-31. Format of CAN Module Control Register (C0CTRL) (3/4) PSMODE1 PSMODE0 power saving mode No power saving mode is selected CAN sleep mode Set Off CAN Stop Mode Note 1. Transition to or wake from the CAN stop mode through the CAN sleep mode.
Page 822 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-31. Format of CAN Module Control Register (C0CTRL) (4/4) ClearVALID Set VALID bit VALID hold VALID cleared 0. SetPS ClearP Set PSMODE0 bit MODE0 SMODE0 PSMODE0 cleared 0. PSMODE0 is set to 1.
Page 823 BAT32G137 user manual | Chapter 21 CAN Controller CAN module last error code register (C0LEC) The C0LEC register provides error information for the CAN protocol. Figure 21-32. Format of the CAN module last error code register (C0LEC) Note 1. The contents of the C0 LEC register are not cleared when the CAN switches from the operation mode to the initialization mode.
Page 824 BAT32G137 user manual | Chapter 21 CAN Controller CAN Module Information Register (C0INFO) The C0INFO register indicates the state of the CAN module Figure 21-33. Format of the CAN Module Information Register (C0INFO) BOFF bus off status bit Non-bus off state (transmission error counter less than 255) (transmission counter value less than...
Page 825 BAT32G137 user manual | Chapter 21 CAN Controller (10) CAN Module Error Counter Register (C0ERC) The C0 ERC register records the count value of the transmit/receive error counter. Figure 21-34. CAN Module Error Counter Register Format (C0ERC) REPS Receive error passive status bit Receive error counter is not error passive (<128)
Page 826 BAT32G137 user manual | Chapter 21 CAN Controller (11) CAN Module Interrupt Enable Register (C0IE) The C0 IE register is used to enable or disable interruption of the CAN module. Figure 21-35. CAN Module Interrupt Enable Register Format (C0IE) (1/2)
Page 827 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-35. CAN Module Interrupt Enable Register Format (C0IE) (2/2) SetCIE3 ClearCIE3 Set CIE3 bit CIE3 clear 0. CIE3 Set 1. Other Values CIE3 is unchanged. SetCIE2 ClearCIE2 Set CIE2 bit CIE2 clear 0.
Page 828 BAT32G137 user manual | Chapter 21 CAN Controller (12) CAN Module Interrupt State Register (C0INS) C0INTS register indicates CAN module interrupt state Figure 21-36. CAN Module Interrupt State Register Format (C0INS) (a) read (b) write (a) read UNITS5-UNITS0 CAN interrupt status bit No related interrupt source events are pending.
Page 829 BAT32G137 user manual | Chapter 21 CAN Controller (13) CAN Module Bit Rate Scaling Register (C0BRP) The C0BRP register is used to select the CAN protocol layer basic clock (fTQ). baud rate set to C0BTR register Figure 21-37. CAN Module Bit Rate Scaling Register Format (C0BRP)
Page 830 BAT32G137 user manual | Chapter 21 CAN Controller (14) CAN Module Bit Rate Register (C0BTR) The C0BTR register controls the bit time of the baud rate. Figure 21-39. CAN Module Bit Rate Register Format (C0BTR) (1/2) SJW1 SJW0 Length of the synchronization jump...
Page 831 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-39. CAN Module Bit Rate Register Format (C0BTR) (2/2) TSEG13 TSEG12 TSEG11 TSEG10 Length of time period 1 Disable from setting 10TQ 11TQ 12TQ 13TQ 14TQ 15TQ 16TQ (default) 1 These settings must be performed when the C0 BRP register is 00 H...
Page 832 BAT32G137 user manual | Chapter 21 CAN Controller (15) CAN module last input pointer register (C0LIPT) The C0LIPT register indicates the number of message buffers at which the data frame or remote frame was last stored. Figure 21-41. CAN Module Last Input Pointer Register Format (C0LIPT)
Page 833 BAT32G137 user manual | Chapter 21 CAN Controller (16) CAN module receive history list register (C0RGPT) The C0RGPT register is used to read the received history list. Figure 21-42. CAN Module Receive History List Register Format (C0RGPT) (1/2) (a) read...
Page 834 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-42. CAN module receiving history list register format (C0RGPT) (2/2) (b) write ClearROVF Set ROVF bit ROVF doesn't change. ROVF clear 0. www.mcu.com.cn 834 / 1052 V2.1.1...
Page 835 BAT32G137 user manual | Chapter 21 CAN Controller (17) CAN module last output pointer register (C0LOPT) The C0LOPT register indicates the number of message buffers that were last transferred to a data frame or remote frame. Figure 21-43. CAN Module Last Output Pointer Register Format (C0LOPT)
Page 836 BAT32G137 user manual | Chapter 21 CAN Controller (18) CAN Module Send History List Register (C0TGPT) The C0TGPT register is used to read the list of transmission history. Figure 21-44. CAN Module Send History List Register Format (C0TGPT) (1/2) (a) read...
Page 837 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-44. CAN Module Send History List Register Format (C0TGPT) (2/2) (b) write ClearTOVF Set TOVF bit TOVF hasn't changed TOVF clear 0. (19) CAN Module Timestamp Register (C0TS) C0 TS register for controlling timestamp function Figure 21-45.
Page 838 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-45. CAN Module Timestamp Register Format (C0TS) (2/2) TSSEL Timestamp capture event selection bit Timestamp capture event in SOF. Timestamp capture event last bit in EOF TSEN TSOUT signal operation setting bit TSOUT signal rollover operation is disabled.
Page 839 BAT32G137 user manual | Chapter 21 CAN Controller (20) CAN Message Data Byte Register (C0MDBxm) (x = 0 to 7), (C0MDBzm) (z = 01, 23, 45, 67) The C0MDBxm, C0MDBzm registers are used to store the data of the sending/receiving message. The C0MDBxm register can be accessed in 8-bit units.
Page 840 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-46. CAN message data byte register format (C0MDBxm) (x = 0 to 7), (C0MDBzm) (z = 01, 23, 45, 67) (2/2) MDBzm register - C0 Note m = 0 to 15 www.mcu.com.cn...
Page 841 BAT32G137 user manual | Chapter 21 CAN Controller (21) CAN message data length register m (C0MDLCm) The C0MDLCm register is used to set the number of bytes of the data segment of the message buffer. Figure 21-47. AN Message Data Length Register m Format (C0MDLCm)
Page 842 BAT32G137 user manual | Chapter 21 CAN Controller (22) CAN Message Configuration Register (C0MCONFm) The C0MCONFm register specifies the type of message buffer and sets the mask. Figure 21-48. CAN Message Configuration Register Format (C0MCONFm) (1/2) Address: Reference Table 21-16...
Page 843 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-48. CAN Message Configuration Register Format (C0MCONFm) (2/2) message cache allocation bit Message cache not used Using message caching Note: Make sure you write 0 for bits 1 and 2. Note m = 0 to 15...
Page 844 BAT32G137 user manual | Chapter 21 CAN Controller (24) CAN message control register m (C0MCTRLm) The C0MCTRLm register is used to control the operation of the message buffer. Figure 21-50. CAN Message Control Register m format (C0MCTRLm) (1/3) Address: Reference table 21-16.
Page 845 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-50. CAN Message Control Register m format (C0MCTRLm) (2/3) message cache data update bit Data or remote frames are not stored in the message buffer. Data frames or remote frames are stored in the message buffer.
Page 846 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-50. CAN Message Control Register m format (C0MCTRLm) (3/3) SetTRQ ClearTRQ TRQ set bit TRQ clear 0. TRQ Set 1. Other Values No change in TRQ Note: When a message is received from another node or a transmission cancelation message, the transmission may not start immediately even if the TRQ bit is set to 1.
Page 847 BAT32G137 user manual | Chapter 21 CAN Controller (26) Port Mode Registers 0, 5 (PM0, PM5) The PM0 and PM5 registers are used to set ports 0 and 5 as input or output. When using the P02/CTxD0 or P51/CTxD0 pin for serial data output, clear the PM02 or PM51 bit "0" and set the P02 or P51 output latch to "1".
Page 848 BAT32G137 user manual | Chapter 21 CAN Controller 21.8 CAN controller initialization 21.8.1 CAN module initialization Before enabling the CAN module for operation, the system clock of the CAN module needs to be determined by setting the CCP[3:0] bit of the C0GMCS register by software. Do not change the setting of the CAN module system clock after the CAN module is working.
Page 849 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-53. Setting Send Request (TRQ) to Send Message Cache after Redefinition Waiting for 1-bit CAN data Set TRQ bit TRQ = 1 TRQ = 0 Note 1. When receiving a message, receive filtering is performed according to the ID and mask set as the buffer for each received message.
Page 850 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-54. Transition to Operation mode The transition from the initialization mode to the operation mode is controlled by the bit string OPMODE[2:0] in the C0CTRL register. Changing from one operation mode to another requires a transition from both to the initialization mode. Do not directly change one mode of operation to another mode of operation, otherwise there is no guarantee of operation.
Page 851 BAT32G137 user manual | Chapter 21 CAN Controller 21.9 message receiving 21.9.1 message receiving Under all operation modes, complete message buffer areas are analyzed to find the appropriate buffer to store the newly received messages. All message buffers that meet the following criteria are included in...
Page 852 BAT32G137 user manual | Chapter 21 CAN Controller 21.9.2 read received data To maintain data consistency when reading the CAN message buffer, perform data reading from FIGS. 21- 76 to 21-78. During message reception, the CAN module sets the DN of the C0MCTRLm register twice: At the beginning of storing data into the message buffer, again at the end of this stored procedure.
Page 853 BAT32G137 user manual | Chapter 21 CAN Controller 21.9.3 Receive history list feature The Receive History List (RHL) function in the Receive History List records the number of receive message buffers that receive and store each data frame or remote frame. The RHL is consist of storage elements corresponding to at most 23 messages, that last message entry point (LIPT) has a corresponding C0LIPT register and the receive history list acquisition point (RGPT) has a corresponding C0RGPT register.
Page 854 BAT32G137 user manual | Chapter 21 CAN Controller The order of occurrence is maintained as long as the RHL contains 23 or fewer entries. If more receive occurs when that host processor doe not read the RHL, the complete receive sequence cannot be recovered.
Page 855 BAT32G137 user manual | Chapter 21 CAN Controller 21.9.4 mask function For any message buffer used for receiving, you can select the receive mask (or no mask) assigned to the quarter. By masking, message ID comparisons can be reduced by masking bits, allowing multiple different IDs to be received in a buffer.
Page 856 BAT32G137 user manual | Chapter 21 CAN Controller <3> CAN Module 1 Mask Settings (mask1) (example) (Use the CAN0 module mask 1 registers L and H (C0MASK1L and C0MASK1H)) CMID28 CMID27 CMID26 CMID25 CMID24 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18...
Page 857 BAT32G137 user manual | Chapter 21 CAN Controller 21.9.5 multi-buffer receive block function The multiple buffer receive block (MBRB) function is used to store data blocks sequentially in two or more message buffers without CPU interaction by setting the same ID to two or more message buffers having the same message buffer type.
Page 858 BAT32G137 user manual | Chapter 21 CAN Controller 21.9.6 remote frame receiving In all operation modes, when a remote frame is received, a message buffer that can store the remote frame is searched from all message buffers that meet the following conditions.
Page 859 BAT32G137 user manual | Chapter 21 CAN Controller 21.10 message sending 21.10.1 message sending In all operation modes, if the TRQ bit is set to 1 in the message buffer that satisfies the following conditions, the message buffer for the message to be transmitted is searched.
Page 860 BAT32G137 user manual | Chapter 21 CAN Controller priority Condition Description First send the message frame of the lowest value indicated by the first 11 bits of ID. If the value of the 11-bit standard ID is Value of the first 11 bits...
Page 861 BAT32G137 user manual | Chapter 21 CAN Controller 21.10.2 Send History List Feature The Transmission History List (THL) feature records the number of the message buffer in the Transmission History List where the data or remote frame is sent. The THL contains storage elements corresponding to up to seven messages, a last outgoing message pointer (LOPT) with corresponding C0LOPT registers, and a transmit history list acquisition pointer (TGPT) of the C0TGPT register.
Page 862 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-58. Sending a history list transmit histoical list(THL) transmit histoical list(THL) event: - CPU confirms message message buffer 4 cache 6,9 and 2 Transmit message buffer 3 completion. message buffer 7...
Page 863 BAT32G137 user manual | Chapter 21 CAN Controller 21.10.3 Automatic Block Transfer (ABT) The Automatic Block Transfer (ABT) feature is used to successfully continuously transfer two or more data frames without CPU interaction. The maximum number of transmitted message buffers allocated to the ABT function is 8 (message buffer numbers 0 to 7).
Page 864 BAT32G137 user manual | Chapter 21 CAN Controller Note 1. Set the ABTCLR bit to 1 and clear the ABTTRG bit to 0 to resume ABT operations at 0 buffer count. If the ABTCLR bit is set to 1 and the ABTTRG bit is set to 1, subsequent actions are not guaranteed. .
Page 865 BAT32G137 user manual | Chapter 21 CAN Controller (3) ABT Transmission Abort Handling in Normal Mode with Automatic Block Transmission To abort a started ABT, clear the C0GMABT register with a ABTTRG bit of 0. In this case, if the ABT message is currently being transmitted and the transmission is complete (successful or not), the ABTTRG bit remains 1 and is cleared to 0 immediately after the transmission is complete.
Page 866 BAT32G137 user manual | Chapter 21 CAN Controller 21.11 power saving mode 21.11.1 CAN sleep mode The CAN sleep mode may be use to set that CAN controller to standby mode to reduce power consumption. The CAN module may enter CAN sleep mode from all operation modes. The release of the CAN sleep mode returns the CAN module to an operation mode before entering the CAN sleep mode.
Page 867 BAT32G137 user manual | Chapter 21 CAN Controller Status of CAN sleep mode The CAN module is in the following state after entering the CAN sleep mode. - The internal operating clock has been stopped and power consumption is minimal.
Page 868 BAT32G137 user manual | Chapter 21 CAN Controller 21.11.2 CAN Stop Mode The CAN stop mode may be used to set the CAN controller to standby mode to reduce power consumption. The CAN module can only enter CAN stop mode from CAN sleep mode. Release of CAN stop mode requires CAN module to be in CAN sleep mode.
Page 869 BAT32G137 user manual | Chapter 21 CAN Controller 21.11.3 Power-saving mode In some application systems, it may be necessary to put the CPU in power-saving mode to reduce power consumption. The CAN bus can wake the CPU from the power saving state by using the power saving mode specific to the CAN module and the power saving mode specific to the CPU.
Page 870 BAT32G137 user manual | Chapter 21 CAN Controller 21.12 interrupt function The CAN module provides six different interrupt sources. The occurrence of these interrupt sources is stored in an interrupt state register. Four separate interrupt request signals are generated from six interrupt sources. When generating an interrupt request signal corresponding to two or more interrupt sources, the interrupt state register may be used to identify the interrupt source.
Page 871 BAT32G137 user manual | Chapter 21 CAN Controller 21.13 Diagnostic features and special operation modes The CAN module provides only receive mode, single-shot mode and self-test mode to support operation of CAN bus diagnostic function or specific CAN communication method. .
Page 872 BAT32G137 user manual | Chapter 21 CAN Controller Note: If only two CAN nodes are connected to the CAN bus and one of the nodes is running in receive-only mode, there is no ACK on the CAN bus. Due to the lack of ACKs, the transmission node will transmit the active error flag and repeat the message frames.
Page 873 BAT32G137 user manual | Chapter 21 CAN Controller 21.13.3 self-test mode In the self-test mode, the message frame transmission and reception can be tested without connecting the CAN node to the CAN bus without affecting the CAN bus. . In the self-test mode, the CAN module is completely disconnected from the CAN bus, but the transmission and reception are internally circulated.
Page 874 BAT32G137 user manual | Chapter 21 CAN Controller 21.13.4 Receive/Send Operation in Operation Mode Table 21-21 shows a summary of receive/send operations in each mode of operation. Table 21-21. Summary of Send/Receive in Operational Mode Send Send Transmission Automatic Block...
Page 875 BAT32G137 user manual | Chapter 21 CAN Controller 21.14 timestamp function CAN is an asynchronous serial protocol. All nodes connected to the CAN bus have local autonomous clocks. Therefore, the clock of the node is irrelevant (that is, the clock is asynchronous and may have different frequencies).
Page 876 BAT32G137 user manual | Chapter 21 CAN Controller Note: The timestamp function using TSLOCK bits stops switching TSOUT bits by receiving the data frames in the message buffer 0. Therefore, message buffer 0 must be set as the receive message buffer. Because the receive message buffer cannot receive remote frames, it is not possible to stop the TSOUT bit switching by receiving remote frames.
Page 877 BAT32G137 user manual | Chapter 21 CAN Controller 21.15 Baud rate setting 21.15.1 Baud rate setting Make sure that the settings are within the limits to ensure proper operation of the CAN controller, as shown below. . (a) 5TQ SPT (sampleing points)
Page 878 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-22. Bit rate combinations may be set (1/3) Valid bit rate settings C0BTR register setting Sampling value points (in %) DBT length Sync propaga Phase Phase TSEG1 [3:0] TSEG2 [2:0] Segment...
Page 879 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-22. Bit rate combinations may be set (2/3) Valid bit rate settings C0BTR register setting Sampling value points (in %) DBT length Sync propaga Phase Phase TSEG1 [3:0] TSEG2 [2:0] Segment...
Page 880 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-22. Bit rate combinations may be set (3/3) Valid bit rate settings C0BTR register setting Sampling value points (in %) DBT length Sync propaga Phase Phase TSEG1 [3:0] TSEG2 [2:0] Segment...
Page 881 BAT32G137 user manual | Chapter 21 CAN Controller 21.15.2 Representative example of baud rate setting Tables 21-23 and 21-24 show representative examples of baud rate settings. Table 21-23. Representative example of baud rate setting ( MHz) (1/2) fCANMOD Set the...
Page 882 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-23. Representative example of baud rate setting ( = 8 MHz) (2/2) fCANMOD Set the C0BRP Valid Bit Rate Settings (in kbps) C0 BTR register Sampling baud rate register set value...
Page 883 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-24. Representative example of baud rate setting ( = 16 MHz) (1/2) fCANMOD Set the C0BRP Valid Bit Rate Settings (in kbps) C0 BTR register Sampling baud rate register set value...
Page 884 BAT32G137 user manual | Chapter 21 CAN Controller Table 21-24. Representative example of baud rate setting ( = 16 MHz) (2/2) fCANMOD Set the C0BRP Valid Bit Rate Settings (in kbps) C0 BTR register Sampling baud rate register set value...
Page 885 BAT32G137 user manual | Chapter 21 CAN Controller 21.16 Operation of CAN controller This chapter's operation flow is the CAN controller's operation flow. Development Refer to the process flow in this chapter. Notes m = 0 to 15 Figure 21-63. Initialization...
Page 886 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-64. Reinitialization Starte Clear OPMODE INIT mode C0BRP register, C0BTR register Set C0 IE register Setting C0MASK Registers Initialize message buffer C0ERC and C0INFO Register clearing? Set CCERC bit Set C0CTRL register (set OPMODE) Note: After you set the CAN module to initialization mode, do not immediately set to another mode of operation.
Page 887 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-65. Message cache initialization Starte RDY= 1? Clear RDY bit RDY= 0? C0MCONFm register C0MIDHm register, C0MIDLm register Send message cache? C0MDLCm register Clear C0MDBm Register C0MCTRLm register Set RDY bit Note: 1.
Page 888 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-66 shows the received message cache processing (C0MCONFm register MT[2:0] bits =001B to 101B). Figure 21-66. Message Cache Redefinition Started Note2 Wait 4 CAN Data Bits message cache Set RDY bit Notes 1.
Page 889 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-67 shows the processing of the transmitted message buffer during transmission (C0MCONFm register MT[2:0] bit=000B). Figure 21-67. Redefinition of message cache during transmission Starte Send abort process Clear RDY bits RDY= 0?
Page 890 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-68 shows the transmit message cache processing (C0MCONFm register MT[2:0] bit=000B). Figure 21-68. Message sending processing Starte TRQ = 0? Clear RDY bits RDY= 0? data frame remote frame Data frames or remote frames?
Page 891 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-69 shows the transmit message cache processing (C0MCONFm register MT[2:0] bit=000B). Figure 21-69. ABT Message Delivery Processing Starte ABTTRG =0? Clear RDY bits RDY= 0? setting C0MDATAxm registers setting C0MDLCm registers...
Page 892 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-70. Transmit Through Interrupt (using C0LOPT register) Starte Send complete interrupt handling Read C0LOPT register Clear RDY bits RDY= 0? data frame remote frame Data or remote frames? Setting C0MDATAxm Setting C0MDLCm Registers...
Page 893 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-71. Send by interrupt (using C0TGPT register) Note 1. The TRQ bit is set after the RDY bit is set. 2. RDY bit and TRQ bit cannot be set simultaneously. Note 1. Check the MBON flag at the beginning and end of the interrupt to check access to the message buffer and the TX history list register to prevent pending sleep patterns.
Page 894 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-72. Polling transmission over software Note 1. The TRQ bit is set after the RDY bit is set. 2. RDY bit and TRQ bit cannot be set simultaneously. Note 1. Check the MBON flag at the beginning and end of the interrupt to check access to the message buffer and the TX history list register to prevent pending sleep patterns.
Page 895 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-73. Transmission abort process (except for normal operation mode with ABT) Starte Clear TRQ bits Waiting for Note 11CAN data bits TSTAT=0? Read C0LOPT register Is the message cache matching the C0 LOPT...
Page 896 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-74. Send abort handling (except for ABT transmission) (normal operation companion ABT) Starte Clear ABTTRG Bit ABTTRG =0? Clear TRQ bit Note Waiting for 11CAN data bits TSTAT=0? Read register C0LOPT...
Page 897 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-75 show that when transmission ABT message cache is aborted, send message stops without skipping the processing of recovery Figure 21-75. ABT send abort process (normal operation mode with ABT) Note: 1. Do not set any transmission requests while ABT transmission abort processing is in progress.
Page 898 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-76 show that when transmission ABT message cache abort, send message stops skipping recovery processing. . Figure 21-76. ABT send request abort process (normal mode of operation with ABT) Clear ABTTRG Bit Note: 1.
Page 899 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-77. Receiving by interrupt (using register C0LIPT) Note checks MUC and DN bits using read Note: Check the MBON flag at the beginning and end of the interrupt to check access to the message buffer and the receive history list register to prevent execution of the suspended sleep mode.
Page 900 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-78. Receiving by interrupt (using register C0RGPT) Starte Generate receive completion interrupt Read register C0RGPT ROVF= 1? Clear ROVF Bit RHPM=1? Clear DN bit Read C0MDATAxm, C0MDLCm, C0MIDLm, C0MIDHm register DN = 0...
Page 901 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-79. Receive by software polling Note Note checks the MUC and DN bits using reading. Remarks1. Check the MBON flags for polling start and end to check access to message buffers and receive history list registers to prevent pending sleep patterns from being executed.
Page 902 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-80. Setting CAN Sleep/Stop Mode Start (when PSMODE[1:0]= 00B) Set PSMODE0 bit PSMODE0= 1? CAN sleep mode Set PSMODE1 bit PSMODE1= 1? Reapply for CAN sleep mode? CAN Stop Mode Clear OPMODE...
Page 903 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-81. Clear CAN sleep/stop mode Start Can Stop mode clear PSMODE1 bit when CAN clock is activated, when CAN clock disabled, activate release CAN sleep mode CAN Sleep mode activate release CAN sleep mode...
Page 904 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-82. Bus Shutdown Recovery (Normal Operation Mode with ABT) Starte BOFF= 1? Note Clear all TRQ bits Set register C0CTRL (ClearOPTION) Access registers other than C0CTRL and C0GMCTRL Force recovery from bus...
Page 905 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-83. Bus Shutdown Recovery (Normal Operation Mode with ABT) Starte BOFF= 1? Clear ABTTRG Bit Note Clear all TRQ bits Set register C0CTRL (ClearOPMODE) Access Registers and register C0GMCTRL other than C0CTRL...
Page 906 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-84. Normal shutdown handling Figure 21-85. Forced shutdown processing Must be followed by write Note: Do not read or write any registers through software between setting the EFSD bit and clearing the GOM bit.
Page 907 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-86. Error Handling Starte error interrupt CINTS2 =1? Check CAN module status (read register C0INFO) Clear CINTS2 bit CINTS3 =1? Check CAN protocol error status (read register C0LEC) Clear CINTS3 bit...
Page 908 BAT32G137 user manual | Chapter 21 CAN Controller Note: Before the CPU is set to enter CPU standby mode, check whether the CAN is in sleep mode. When the CAN sleep mode is detected, until the CPU is set to a standby mode, the CAN sleep mode may be canceled by the wake-up of the CAN bus.
Page 909 BAT32G137 user manual | Chapter 21 CAN Controller Figure 21-88. Setting CPU Standby (from CAN Stop Mode) Note in interrupt wake-up Note: CAN stop mode can only be released by writing 01B to the PSMODE[1:0] bit of the C0CTRL register, not by changing the CAN bus state. .
Page 910 BAT32G137 user manual | Chapter 22 IrDA Chapter 22 IrDA The IrDA implements the transmission and reception of IrDA communication waveforms in accordance with IrDA (InfraredDataAssociation) 1.0 by cooperating with SCI. 22.1 Features of IrDA If the IrDA function is set to be valid by the IRE bit of the IRCR register, TxD2 and RxD2 signals of the SCI can encode or decode the IrDA1.0 protocol waveform (IrTxD/IrRxD pin).
Page 911 BAT32G137 user manual | Chapter 22 IrDA 22.2 Register controlling IrDA Control the IrDA functionality through the following registers. • Peripheral Enable Register 0 (PER0s). • IrDA control register (IRCR) 22.2.1 Peripheral Enable Register 0 (PER0s). The PER0 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware.
Page 912 BAT32G137 user manual | Chapter 22 IrDA 22.2.2 IrDA control register (IRCR) This is the register that controls the IrDA function. Polarity switching between the received and transmitted data, clock selection for IrDA, and serial input/output Output pin functionality (usual serial and IrDA functionality) switching selection. The IRCR register is set by an 8- bit memory operation instruction.
Page 913 BAT32G137 user manual | Chapter 22 IrDA 22.3 Running of IrDA 22.3.1 Procedures for IrDA Communication Initial set-up process for IrDA communications Follow these steps to initially set up IrDA. Position "1" for IRDAEN of PER0 register. Sets the IRCR register.
Page 914 BAT32G137 user manual | Chapter 22 IrDA 22.3.2 Send At transmission, the output signal (UART frames) from the SCI is converted to IR frames via IrDA (reference FIGS. 22-4). When the IRTXINV bit is "0" and the serial data is "0", the output bit period (1 bit width period) x3/16 high level pulse (initial value).
Page 915 BAT32G137 user manual | Chapter 22 IrDA 22.3.4 Selection of high level pulse width If the pulse width at transmission is less than 3/16, the suitable setting (minimum pulse width) of IRCKS2~IRCKS0 bit and the setting high level pulse width are shown in Table 22-2.
Page 916 BAT32G137 user manual | Chapter 23 Enhanced DMA Chapter 23 Enhanced DMA 23.1 The Function of DMA The DMA is a function of transferring data between memories without using a CPU. Starting DMA for data transfer is interrupted by peripheral functions. When DMA and CPU access the same unit in FLASH, SRAM0, SRAM1 or peripheral module simultaneously, their bus use rights are higher.
Page 917 BAT32G137 user manual | Chapter 23 Enhanced DMA Table 23-1 Specifications for DMA (2/2) Project Specifications interrupt normal mode When the DMACTj register is transferred from "1" to "0", the CPU is requested to start the request source interrupt and interrupts.
Page 918 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.2 Structure of DMA The block diagram for DMA is shown in Figure 23-1 Figure 23-1 Block diagram for DMA peripherial interrupt signal interrupt source/ transmit start data transmission source selection control...
Page 919 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3 Register for controlling DMA The registers that control the DMA are shown in Table 23-2. Table 23-2 Register for controlling DMA register name symbol Peripheral Enable Register 1 PER1 DMA Boot Enable Register 0...
Page 920 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.1 DMA controls the allocation of data areas and DMA vector table areas A 704-byte region of the control data and the vector table assigned to the DMA is set to the RAM region through the DMABAR register.
Page 921 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.2 Controlling Data Allocation Starting from the starting address, control data is allocated in the order of DMACRj, DMBLSj, DMACTj, DMRLDj, DMSARj, DMDARj registers. The starting address is set by the DMABAR register, and the lower 10 bits are set by the vector tables assigned by each starting source.
Page 922 BAT32G137 user manual | Chapter 23 Enhanced DMA Table 23-4 The starting address of the control data Address Address Remark baseaddr: Setting value for the DMABAR register www.mcu.com.cn 922 / 1052 V2.1.1...
Page 923 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.3 vector table Once the DMA is started, control data assigned to the DMA control data area is read by data read from a vector table assigned to each start source. The DMA boot source and vector addresses are shown in Table 23-5. The vector table of each starting source has 1 byte, which stores the data of "00H"~27H, and selects 10 sets of data from the 40 sets.
Page 924 BAT32G137 user manual | Chapter 23 Enhanced DMA Table 23-5 DMA boot source and vector addresses Source vector address priority DMA boot source (interrupt request Number generation source) Retention High DMABAR REGISTER SETTING ADDRESS+00H INTP0 DMABAR REGISTER SETTING ADDRESS+01H INTP1...
Page 925 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.4 Peripheral Enable Register 1 (PER1) The PER1 register is a register that sets a clock that is allowed or prohibited to supply to each peripheral hardware. Reduce power consumption and noise by stopping clock supply to unused hardware.
Page 926 BAT32G137 user manual | Chapter 23 Enhanced DMA Figure 23-6 Format of DMA control register j(DMACRj) Address Refer to 23.3.2 Control Data Allocation.. After reset: indefinite value Symbol: DMACRj RPTINT CHEN DAMOD SUMMER RPTSEL MODE Selection of the length of the transmitted data...
Page 927 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.6 DMA block size register j(DMBLSj) (j=0~39). This register sets the block size of the transfer data started 1 time. Figure 23-7 Format of DMA block size register j(DMBLSj) Address Refer to 23.3.2 Control Data Allocation..
Page 928 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.7 DMA transfer times register j(DMACTj) (j=0~39). This register sets the number of data transfers for DMA. Each time you initiate a DMA transfer, you reduce 1. Figure 23-8 Format of DMA transfer number register j(DMACTj)
Page 929 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.8 DMA transfer times reload register j (DMRLDj) (j=0~39) This register sets the initial value of the transfer number register in repeat mode. In repeat mode, the value of this register must be the same as the initial value of the DMACT register because it is reloaded into the DMACT register.
Page 930 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.9 DMA source address register j(DMSARj) (j=0~39). This register specifies the transmission source address when the data is transferred. When the SZ bit of the DMACRj register is '01' (16-bit transfer), the lowest bit is ignored and processed as an even address.
Page 931 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.11 DMA Boot Enable Register i (DMAENi) (i=0~4) This is an 8-bit register that controls whether or not starting DMA through each interrupt source. The correspondence of that interrupt source and the DMAENi0~DMAENi7 bit is shown in Table 23-6.
Page 932 BAT32G137 user manual | Chapter 23 Enhanced DMA DMAENi2 Allow i2 for DMA start-up Disable start-up. Allow start-up. The DMAENi2 bit changes to "0" depending on the condition of the end of the delivery interrupt. DMAENi1 Allow i1 for DMA start-up Disable start-up.
Page 933 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.3.12 DMA base address register (DMABAR) This is a 32-bit register that sets the vector address that holds the starting address of the DMA control data area and the address of the DMA control data area.
Page 934 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.4 Operation of DMA Once the DMA is started, the control data is read from the DMA control data area, data transfer is performed based on the control data, and the control data transferred is written back. It is possible to store 40 sets of control data to a DMA control data area and to perform transfer of 40 sets of data.
Page 935 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.4.2 normal mode At 8-bit transmission, the transmission data of 1 start-up is 1~65535 bytes. In 16-bit transmission, the transmission data of 1 start-up is 2~131070 bytes; At 32-bit delivery, the 1-initiated delivery data is 4-262140 bytes.
Page 936 BAT32G137 user manual | Chapter 23 Enhanced DMA Example of normal mode use 1: Continuous reading A/D conversion results The DMA is started by an A/D conversion end interrupt, and the value of the A/D conversion result register is transferred to the RAM.
Page 937 BAT32G137 user manual | Chapter 23 Enhanced DMA Example of Normal Mode Usage 2: UART0 Continuous Transmit The DMA is initiated over the transmission buffer of the UART0 and the value of the RAM is transferred to the transmission buffer of the UART0.
Page 938 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.4.3 repetition mode The 1-time-initiated transfer data is 1-65535 bytes. The transmission source or the transmission target is designated as a repeat region, and the number of transmissions is 1-65535 times. Once the specified number of transfers is over, the DMACTj (j=0~39) register and the address specified as the repeat region are initialized and then repeatedly transferred.
Page 939 BAT32G137 user manual | Chapter 23 Enhanced DMA Figure 23-18 Repeat mode data transfer DMACTj register ≠1 FFFFFFFFFFFFFH 1 Boot To Transfer Block size (N bytes) DMBLSj register=N DMACTj register ≠1 DMSARj register=SRC DMDARj register=DST j=0~39 0000000H Settings for the DMACR register...
Page 940 BAT32G137 user manual | Chapter 23 Enhanced DMA Example of Using repetition Mode 1: Controlling Pulse Output Using a Port Stepping Motor A channel 0 interval timer function of Timer4 is used to start DMA and transfer the mode of the motor control pulse saved in the code flash memory to the universal port.
Page 941 BAT32G137 user manual | Chapter 23 Enhanced DMA Example of Using Repeating Patterns 2: Sine Wave Output Using 8-bit D/A Converter Using the channel 0 interval timer function using Timer4 and by interrupting starting DMA, the sine wave table saved in the data flash memory is transferred to 8-bit D/A conversion value setting register 0 (40044734H).
Page 942 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.4.4 chain transmission When the CHNE bit of DMACRj (j=0~38) register is '1 (Allow chain transmission), the transmission of multiple data can be carried out continuously through 1 start sources. Once the DMA is started, control data assigned to the DMA control data area is read by selecting control data from data read from a vector address corresponding to the start source.
Page 943 BAT32G137 user manual | Chapter 23 Enhanced DMA Examples of the use of chain transmission: Continuously taking A/D conversion result for UART0 transmission The DMA is started by an A/D conversion end interrupt and the A/D conversion result is transmitted to RAM for UART0 transmission.
Page 944 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.5 Precautionswhen using DMA 23.5.1 DMA control data and vector table settings · The DMA base address register (DMABAR) must be changed in a state where all DMA boot sources are set to disable boot.
Page 945 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.5.3 The number of execution clocks for DMA The execution of the DMA at start-up and the number of clocks required are shown in Table 23-9. Table 23-9 Performance and Required Number of Clocks at DMA Start-up...
Page 946 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.5.4 Response time for DMA The DMA response time is shown in Table 23-12. The DMA response time is the time from the detection of the DMA boot source to the start of the DMA transfer, excluding the number of DMA execution clocks.
Page 947 BAT32G137 user manual | Chapter 23 Enhanced DMA 23.5.6 Operation in standby mode Status DMA Operation sleep mode Capable of operation (not allowed in low power RTC mode). deep sleep mode Able to accept DMA boot source and perform DMA transfer note 1 Note 1.
Page 948 BAT32G137 user manual | Chapter 24 Coordination Controller(EVENTC) Chapter 24 Coordination Controller(EVENTC) 24.1 Features of EVENTC EVENTC links events output by each peripheral function to each other by the peripheral function. The event link allows for collaborative operation between peripheral functions without passing through the CPU.
Page 949 BAT32G137 user manual | Chapter 24 Coordination Controller(EVENTC) 24.3 control register The controller register is shown in Table 24-1. Table 24-1 Register controlling EVENTC register name symbol Event Output Target Selection Register 00 ELSEL00 Event Output Target Selection Register 01...
Page 950 BAT32G137 user manual | Chapter 24 Coordination Controller(EVENTC) 24.3.1 Output target selection register n(ELSELRn) (n=00~21). The ELSELRn register links each event signal to an event recipient peripheral function (link target peripheral function) when the event is accepted. Multiple event inputs cannot be linked to the same event output target (event recipient).
Page 951 BAT32G137 user manual | Chapter 24 Coordination Controller(EVENTC) Table 24-2 ELSELRn register (n=00~21) and correspondence of peripheral function register Event Occurrence Source (output source for event Event Content name input n) ELSEL00 External Interrupt Edge Detection 0 INTP0 External Interrupt Edge Detection 1...
Page 952 BAT32G137 user manual | Chapter 24 Coordination Controller(EVENTC) Table 24-3 The setting value of the ELSELRn register (n=00~21) and the corresponding of the run when the link target peripheral function accepts the event Link Target ELSELRn register's Link Target Run when event is accepted...
Page 953 BAT32G137 user manual | Chapter 24 Coordination Controller(EVENTC) 24.4 Operation of EVENTC The path used for the interrupt request of the interrupt control circuit and the path used for the EVENTC event are independent of each other. Therefore, each event signal is independent of interrupt control and can be used as an event signal for peripheral function operation of the event receiver.
Page 954 BAT32G137 user manual | Chapter 24 Coordination Controller(EVENTC) The response of the peripheral function accepting the event is shown in Table 24-4. Table 24-4 Accept the response of the event's peripheral function Event Acceptanc Function of Event Run after event...
Page 955 BAT32G137 user manual | Chapter 25 Interrupt function Chapter 25 Interrupt function The Cortex-M0+ processor has a built-in nested vector interrupt controller (NVIC) that supports up to 32 interrupt request (IRQ) inputs and 1 unmaskable interrupt (NMI) input, plus multiple internal exceptions.
Page 956 BAT32G137 user manual | Chapter 25 Interrupt function Table 25-1 List of interrupt sources (1/4) interrupt source Name trigger Inter note 2 INTLVI ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ Voltage detection Detection of Pin Input Edges INTP0 ⚪...
Page 957 BAT32G137 user manual | Chapter 25 Interrupt function Table 25-1 List of interrupt sources (2/4) interrupt source Name trigger End of transmission of INTST1/I UART1 transmission or end NTSSPI1 of transmission of buffer ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ ⚪...
Page 958 BAT32G137 user manual | Chapter 25 Interrupt function Table 2 5-1 List of interrupt sources (3/4) interrupt source Name trigger Retention INTP6 ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ INTP7 ⚪ ⚪ INTP8 ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ ⚪ ⚪...
Page 959 BAT32G137 user manual | Chapter 25 Interrupt function Table 25-1 List of interrupt sources (4/4) interrupt source interrupt interrupt source Internal/External Note 1 Basic Structure Type handling number Name trigger watchdog timer interval — unmaskable INTWDT Internal note 2 interrupt Note: 1.
Page 960 BAT32G137 user manual | Chapter 25 Interrupt function Figure 25-1 Basic structure of interrupt functionality (A) Internally masked interrupt internal bus CPU.IRQ standby release signal (B) Externally Masked Interrupt (INTPn) internal bus external interrupt edge edge CPU.IRQ detection circuit standby...
Page 961 BAT32G137 user manual | Chapter 25 Interrupt function (C) Externally Masked Interrupt (INTKR) internal key return pattern register (KRM) CPU.IRQ standby break release signal NOTE: 40 Pin: n=0, 2~5 48 Pin: n=0~5 52,64 pins: n=0~7 (D) Unmaskable interrupt internal CPU.NMI...
Page 962 BAT32G137 user manual | Chapter 25 Interrupt function 25.3 Register for controlling interrupt function Interrupt functionality is controlled through the following 4 registers. · Interrupt request flag register (IF00~IF31) · interrupt mask register (MK00~MK31) · External interrupt rising edge allow registers (EGP0, EGP1) ·...
Page 963 BAT32G137 user manual | Chapter 25 Interrupt function 25.3.2 interrupt mask register (MK00~MK31) The interrupt mask setting allows or disables the corresponding masked interrupt handling. The MK00L~MK31L, MK00H~MK31H register, or the MK00~MK31 register are set by the 8-bit memory operation instruction.
Page 964 BAT32G137 user manual | Chapter 25 Interrupt function Table 25-2 The Corresponding Relation of Interrupt Source and Flag Register interrupt interrupt interrupt interrupt interrupt request interrupt mask request flag mask Number Number source source flag register register register register IF00.IFL MK00.MKL...
Page 965 BAT32G137 user manual | Chapter 25 Interrupt function Figure 25-4 Relationship of Flag Registers to CPU.IRQ internal bus MKnL IFnL CPU.IRQn IFnH MKnH internal bus www.mcu.com.cn 965 / 1052 V2.1.1...
Page 966 BAT32G137 user manual | Chapter 25 Interrupt function 25.1.1 external interrupt rising edge permit register (EGP0, EGP1), external interrupt falling edge permit register (EGN0, EGN1) These registers set the effective edge of INTP0~INTP11. The EGP0, EGP1, EGN0, EGN1 registers are set by 8-bit memory operation instructions. After the reset signal is generated, the values of these registers change to '00H'.
Page 967 BAT32G137 user manual | Chapter 25 Interrupt function Table 25-3 Interrupt request signal corresponding to EGPn and EGNn bits Detect allowed bits interrupt 64 pins 52,48,40 pins 36 Pin 32 Pin request signal ○ ○ ○ ○ EGP0 EGN0 INTP0 ○...
Page 968 BAT32G137 user manual | Chapter 25 Interrupt function 25.4 Operation of interrupt handling 25.4.1 Acceptance of maskable interrupt requests If the interrupt request flag is set to '1' and the masking (MK) flag of the interrupt request is cleared to '0', the interrupt request can be passed to NVIC.
Page 969 BAT32G137 user manual | Chapter 26 key interrupt function Chapter 26 key interrupt function The number of input channels for the key interrupts is different based on the product. Function of key interrupt 26.1 A key interrupt (INTKR) can be generated by inputting a descending edge to key interrupt input pins (KR0 to KR7).
Page 970 BAT32G137 user manual | Chapter 26 key interrupt function Figure 2 6-1 Box for key break INTKR KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register www.mcu.com.cn 970 / 1052 V2.1.1...
Page 971 BAT32G137 user manual | Chapter 26 key interrupt function Register for controlling key interrupt 26.3 The key interrupt function is controlled through the following registers. · Key Return Mode Register (KRM) · Port Mode Register (PMx) 26.3.1 Key Return Mode Register (KRM) The KRM0~KRM7 bit controls the KR0~KR7 signal.
Page 972 BAT32G137 user manual | Chapter 26 key interrupt function 26.3.2 Port Mode Register (PMx) When used as key interrupt input pin (KR0~KR7), the PMxn bits must be set 1. In this case, the output latch for Pxn may be "0" or "1".
Page 973 BAT32G137 user manual | Chapter 27 standby function Chapter 27 standby function standby function 27.1 The standby function is the function of further reducing the working current of the system, there are two modes below. sleep mode The sleep mode is a mode that stops the CPU running the clock. If a high speed system clock oscillation circuit, a high speed internal oscillator or a sub-system clock oscillation circuit are oscillating before setting a sleep mode, each clock continues to oscillate.
Page 974 BAT32G137 user manual | Chapter 27 standby function sleep mode 27.2 27.2.1 Sleep mode configuration When the SLEEPDEEP bit of the SCR register is 0, the WFI instruction is executed and the sleep mode is started. In sleep mode, that CPU stop acting, but the value of the internal register is still maintain, and the peripheral module remain in the state before entering sleep mode.
Page 975 BAT32G137 user manual | Chapter 27 standby function Table 27-1 Health in Sleep Mode (1/2) A case where a WFI instruction is executed while the CPU is running at the main system clock Sleep mode settings CPU External Main System...
Page 976 BAT32G137 user manual | Chapter 27 standby function power-on reset function voltage detection function It works. external interrupt key interrupt function high speed operation Features universal CRC When DMA is performed in the operation of the RAM area, it can run.
Page 977 BAT32G137 user manual | Chapter 27 standby function Table 27-1 Health in Sleep Mode (2/2) A case where a WFI instruction is executed while the CPU is running at a sub-system clock Sleep mode settings CPU runs with external secondary...
Page 978 BAT32G137 user manual | Chapter 27 standby function Remark Stop Running: Automatically stops running when transferred to sleep mode. Disable Run: Stop running before transferring to sleep mode. : high speed internal oscillator clock : low-speed internal oscillator clock : X1 clock...
Page 979 BAT32G137 user manual | Chapter 27 standby function 27.2.2 Exit from Sleep Mode The sleep mode can be arbitrarily interrupted and the external reset terminal, the POR reset, the low voltage detection reset, the RAM parity error reset, the WDT reset and the software reset is released.
Page 980 BAT32G137 user manual | Chapter 27 standby function Table 2 7-2 Running State in Deep Sleep Mode A case where a WFI instruction is executed while the CPU is running at the main system clock Settings for deep sleep mode...
Page 981 BAT32G137 user manual | Chapter 27 standby function high speed operation Features universal CRC Stop running. RAM Parity SFR Protection Features Note 1. Stop running: Automatically stops running when transferred to deep sleep mode. Disable Run: Stop running before transferring to deep sleep mode.
Page 982 BAT32G137 user manual | Chapter 28 reset function 27.3.2 Exist form Deep sleep mode You can exit from Deep sleep mode by two methods. Exit via unmaskable interrupt request If an unmaskable interrupt request occurs, deep sleep mode is exited. After the oscillation stabilization time, if the state is allowed to accept the interrupt, the vector interrupt is processed.
Page 983 BAT32G137 user manual | Chapter 28 reset function The following 7 methods generate a reset signal. (1) External reset via the RESETB pin. (2) The inner reset is generated by the program runaway detection of the watchdog timer. (3) Internal reset is generated by comparing the power supply voltage and the detection voltage of the POR circuit.
Page 984 BAT32G137 user manual | Chapter 28 reset function Figure 28-1 Block diagram for reset function internal bus reset control flag register （RESF） SYSRF WDTRF RPERF IAWRF LVIRF reset reset reset reset reset watchdog timer reset signal erase erase erase erase...
Page 985 BAT32G137 user manual | Chapter 28 reset function Figure 28-3 Reset timing generated by overflowing of the watchdog timer, setting of the system reset request bit, detection of RAM parity errors or detection of illegal memory accesses wait till osc precision stablized...
Page 986 BAT32G137 user manual | Chapter 28 reset function Table 28-1 Operational status during reset Project reset period system clock Stop providing clock to CPU. main system Stop running. clock Stop running (X1 and X2 pins in input port mode). Invalid clock input (pin in input port mode).
Page 987 28.1.1 Reset control flag register (RESF) The BAT32G137 microcontroller has a variety of internal reset generation sources. The reset control flag register (RESF) holds the reset source where the reset request occurs. The RESF register can be read by an 8-bit memory operation instruction.
Page 988 BAT32G137 user manual | Chapter 28 reset function The RESF register status at the time of the reset request is shown in Table 28-2. Table 2 8-2 RESF register state when reset request occurs System Access to reset Reset Reset of...
Page 989 BAT32G137 user manual | Chapter 28 reset function Figure 28-5 Confirmation step for reset source after reset accepted read RESF register, save RESF value to any RAM location read RESF register (clear RESF register) SYSRF of RESF register = 1?
Page 990 When the power-on reset circuit generates an internal reset signal, the reset control flag register (RESF) is cleared '00H'. Note 1. BAT32G137 has multiple built-in hardware that generates internal reset signals. When the internal reset signal is generated by the access of the watchdog timer (WDT), the voltage detection (LVD) circuit, the system reset request position bit, RAM parity error or illegal memory;...
Page 991 BAT32G137 user manual | Chapter 29 Power-on reset circuit Structure of power-on reset circuit 29.2 A block diagram of the power-on reset circuit is shown in Figure 29-1. Figure 29-1 Block diagram of power-on reset circuit internal reset signal basic...
Page 992 BAT32G137 user manual | Chapter 29 Power-on reset circuit Figure 29-2 Generation sequence of internal reset signal of power-on reset circuit and voltage detection circuit (1/3) Cases of External Reset Input Using the RESETB Pin power supply voltage(V note 5...
Page 993 BAT32G137 user manual | Chapter 29 Power-on reset circuit Figure 29-2 Generation sequence of internal reset signal of power-on reset circuit and voltage detection circuit (2/3) Cases where LVD is Break & Reset mode (LVIMDS1, LVIMDS0=1, 0 of option bytes 000C1H)
Page 994 BAT32G137 user manual | Chapter 29 Power-on reset circuit Figure 29-2 Generation sequence of internal reset signal of power-on reset circuit and voltage detection circuit (3/3) (3) The case of LVD reset mode (LVIMDS1, LVIMDS0=1, 1 for option bytes 000C1H). The LVD...
Page 995 BAT32G137 user manual | Chapter 30 voltage detection circuit Chapter 30 voltage detection circuit 30.1 Function of Voltage Detection Circuit The voltage detection circuit sets an operation mode and a detection voltage ( , VLVDL, VLVD) VLVDH through an option byte (000C1H). The voltage detection (LVD) circuit has the following functions.
Page 996 BAT32G137 user manual | Chapter 30 voltage detection circuit 30.2 Structure of voltage detection circuit The block diagram of the voltage detection circuit is shown in Figure 30-1. Figure 30-1 Block diagram of voltage detection circuit internal reset N-ch signal...
Page 997 BAT32G137 user manual | Chapter 30 voltage detection circuit 30.3 Register for controlling voltage detection circuit The voltage detection circuit is controlled by the following registers. · Voltage detection register (LVIM) · Voltage detection level register (LVIS) 30.1.1 Voltage detection register (LVIM) This register setting allows or disables the rewrite of the voltage detection level register (LVIS) and confirms the masking status of the LVD output.
Page 998 BAT32G137 user manual | Chapter 30 voltage detection circuit 30.3.1 Voltage detection level register (LVIS) This is a register that sets the voltage detection level. The LVIS register is set by an 8-bit memory operation instruction. After the reset signal is generated, the...
Page 999 BAT32G137 user manual | Chapter 30 voltage detection circuit Table 30-1 Format of user option bytes (000C1H/010C1H) (1/2) H Note Address: 000C1H/010C1 VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 · Settings for LVD (Interrupt & Reset Mode) detection Setting value for option bytes...
Page 1000 BAT32G137 user manual | Chapter 30 voltage detection circuit Table 30-1 Format of user option bytes (000C1H) (2/2) Address: 000C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 · Settings for LVD (interrupt mode) detection Setting value for option bytes voltage...

Cmsemicon BAT32G137 User Manual

Chapter 1 CPU

Chapter 2 Pin Function

Chapter 3 System Structure

Chapter 4 Clock Generator

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