1. Manuals
  2. Brands
  3. Cmsemicon Manuals
  4. Microcontrollers
  5. CMS80F761 Series
  6. Reference manual

Cmsemicon CMS80F761 Series Reference Manual

Enhanced flash 8-bit 1t 8051 microcontroller
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
CMS80F761x Reference Manual

CMS80F761x Series

Reference Manual
Enhanced flash 8-bit 1T 8051 microcontroller
Rev. 1.0.4
Please note the following CMS IP policy
＊China Micro Semicon Co., Ltd. (hereinafter referred to as the Company) has applied for patents and holds absolute legal
rights and interests. The patent rights associated with the Company's MCUs or other products have not been authorized for use,
and any company, organization, or individual who infringes the Company's patent rights through improper means will be subject
to all possible legal actions taken by the Company to curb the infringement and to recover any damages suffered by the
Company as a result of the infringement or any illegal benefits obtained by the infringer.
＊The name and logo of Cmsemicon are registered trademarks of the Company.
＊The Company reserves the right to further explain the reliability, functionality and design improvements of the products in the
data sheet. However, the Company is not responsible for the use of the Specification Contents. The applications mentioned
herein are for illustrative purposes only and the Company does not warrant and does not represent that these applications can
be applied without further modification, nor does it recommend that its products be used in places that may cause harm to
persons due to malfunction or other reasons. The Company's products are not authorized for use as critical components in
lifesaving, life-sustaining devices or systems. The Company reserves the right to modify the products without prior notice. For
the latest information, please visit the official website at www.mcu.com.cn.
www.mcu.com.cn
/
Rev. 1.0.4
1
270

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the CMS80F761 Series and is the answer not in the manual?

Questions and answers

Related Manuals for Cmsemicon CMS80F761 Series

Summary of Contents for Cmsemicon CMS80F761 Series

  • Page 1: Cms80F761X Series

    Company as a result of the infringement or any illegal benefits obtained by the infringer. ＊The name and logo of Cmsemicon are registered trademarks of the Company. ＊The Company reserves the right to further explain the reliability, functionality and design improvements of the products in the data sheet.

  • Page 2: Table Of Contents

    CMS80F761x Reference Manual Table of contents CMS80F761x Series ........................1 Table of contents ........................2 1. Central Processing Unit (CPU) ..................12 Reset vector (0000H) ..............................12 Accumulator (ACC) ..............................13 B Register(B) ................................13 Stack Pointer Register (SP)............................13 Data Pointer Register (DPTR0/DPTR1) ........................
  • Page 3 CMS80F761x Reference Manual 5.4.5 Sleep Power Consumption in Debug Mode......................50 5.4.6 Example of a Sleep Mode Application ........................50 6. Interrupt ..........................51 Interrupt Overview ............................... 51 External Interrupts ............................... 52 6.2.1 INT0/INT1 Interrupt ..............................52 6.2.2 GPIO Interrupt ................................52 Interrupt With Sleep Wake-up ............................. 52 Interrupt Register .................................
  • Page 4 CMS80F761x Reference Manual 7.2.1 Port Multiplexing Feature Table ..........................71 7.2.2 Port Multiplexing Feature Configuration Register .....................74 7.2.3 The port input function allocation registers .......................75 7.2.4 Communication input function allocation registers ....................77 7.2.5 Port External Interrupt Control Registers .........................78 7.2.6 Multiplexing Features Application Notes ........................79 8.
  • Page 5 CMS80F761x Reference Manual 11.2.1 Timer2 Control Register T2CON ..........................102 11.2.2 Timer2 Data Register Low Bit TL2 .........................102 11.2.3 Timer2 Data Register High TH2 ..........................103 11.2.4 Timer2 Compare/Capture/Auto Reload Register Low Bit RLDL ................103 11.2.5 Timer2 Compare/Capture/Auto Reload Register High Bit RLDH ................103 11.2.6 Timer2 Compares/Captures Channel 1 Registers Low CCL1 ................103 11.2.7 Timer2 Compares/Captures Channel 1 Register High Bit CCH1 ................103 11.2.8 Timer2 Compares/Captures Channel 2 Registers Low CCL2 ................104...
  • Page 6 CMS80F761x Reference Manual 12.5.2 T4 - Mode 1 (16-bit Timing Mode) ..........................123 12.5.3 T4- Mode 2 (8-bit Auto Reload Timing Mode)......................124 12.5.4 T4 - Mode 3 (Stop Count)............................124 13. LSE Timer(LSE_Timer) ....................125 13.1 Overview ................................... 125 13.2 Related Registers ..............................125 13.2.1 LSE Timer Data Register Low 8 Bit LSECRL ......................125 13.2.2 LSE Timer Data Registers are 8 Bits High LSECRH ....................125 13.2.3 LSE Timer Control Register LSECON ........................126...
  • Page 7 CMS80F761x Reference Manual 18.5.3 PWM0/1 Clock Prescale Control Register PWM01PSC ..................143 18.5.4 PWM2/3 clock prescale control register PWM23PSC ....................143 18.5.5 PWM4/5 clock prescale control register PWM45PSC ....................143 18.5.6 PWM Clock Divide Control Register PWMnDIV (n=0-5) ..................144 18.5.7 PWM Data Loading Enable Control Register PWMLOADEN .................144 18.5.8 PWM Output Polarity Control Register PWMPINV ....................144 18.5.9 PWM Counter Mode Control Register PWMCNTM ....................145 18.5.10 PWM Counter Enable Control Register PWMCNTE ....................145...
  • Page 8 CMS80F761x Reference Manual 20.3.4 LED clock prescale data register high 8 bit LEDCLKH ...................163 20.3.5 COM port valid time selection register LEDCOMTIME ...................163 20.3.6 COM port enable control register LEDCOMEN ......................163 20.3.7 SEG port enable control register LEDSEGEN0......................163 20.3.8 SEG port enable control register LEDSEGEN1......................164 20.3.9 SEG port enable control register LEDSEGEN2......................164 20.3.10 SEG port enable control register LEDSEGEN3......................164 20.3.11 COM0 corresponding SEG data register LEDC0DATAn (n=0/1/2/3).
  • Page 9 CMS80F761x Reference Manual 22.1 Overview ................................... 196 22.2 SPI port configuration ..............................197 22.3 SPI hardware description ............................198 22.4 SPI-related Registers ..............................199 22.4.1 SPI Control Register SPCR............................199 22.4.2 SPI data register SPDR ............................199 22.4.3 SPI Device Select Control Register SSCR ......................200 22.4.4 SPI Status Register SPSR .............................200 22.5 SPI Master Mode ...............................
  • Page 10 CMS80F761x Reference Manual 24.2 UARTn Port Configuration ............................228 24.3 UARTn Baud Rate ..............................229 24.3.1 Baud Rate Clock Source ............................229 24.3.2 Baud Rate Calculation ............................229 24.3.3 Baud Rate Error ..............................230 24.4 UARTn Register ................................ 232 24.4.1 UART0/1 Baud Rate Selection Register FUNCCR ....................232 24.4.2 UART2 Baud Rate Selection Register FUNCCR1 ....................232 24.4.3 UARTn Buffer Register SBUFn ..........................233 24.4.4 UART Control Register SCONn ..........................233...
  • Page 11 CMS80F761x Reference Manual 25.6.11 AD Comparator Data Register ADCCMPH......................250 25.6.12 AD Comparator Data rRegister ADCOP .........................250 25.7 ADC Interrupt ................................251 25.7.1 Interrupt Mask Register EIE2 ..........................251 25.7.2 Interrupt Priority Control Register EIP2 ........................252 25.7.3 Peripheral Interrupt Flag Bit Register EIF2......................253 26.

  • Page 12: Central Processing Unit (Cpu)

    CMS80F761x Reference Manual 1. Central Processing Unit (CPU) This series is a microcontroller with 8-bit 8051 frame structure. The CPU is the core component of the microcontroller, which is composed of arithmetic units, controllers, and special register groups. The arithmetic unit module mainly implements data arithmetic and logic operations, bit variable processing and data transfer operations;...

  • Page 13: Accumulator (Acc)

    CMS80F761x Reference Manual Accumulator (ACC) The ALU is an 8Bit wide arithmetic logic unit through which all mathematical and logical operations of the MCU are completed. It can add, subtract, shift and logical operations on data; The ALU also controls the status bits (in the PSW status register) that represent the state of the result of the operation.

  • Page 14: Data Pointer Selection Register (Dps)

    CMS80F761x Reference Manual Data Pointer Selection Register (DPS) The data pointer selects register DPS 0x86 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SALT Reset value Bit7~Bit6 ID<1:0>: Subtract/add function selection. DPTR0 plus 1 or DPTR1 plus 1; DPTR0 minus 1 or DPTR1 plus 1; DPTR0 plus 1 or DPTR1 minus 1;...

  • Page 15: Program Counter (Pc)

    CMS80F761x Reference Manual Program Counter (PC) The program counter (PC) controls the order of instruction execution in the program memory FLASH, it can address the entire flash range, after obtaining the instruction code, the program counter (PC) will automatically add one, pointing to the address of the next instruction code.

  • Page 16: Memory And Register Mapping

    CMS80F761x Reference Manual 2. Memory and Register Mapping This series of Microcontrollers has the following types of memory: ◆ Up to 64 KB of FLASH program memory (APROM). ◆ Non-volatile data memory (Data FLASH) up to 1 KB. ◆ Up to 256B of general-purpose internal data memory (RAM). ◆...

  • Page 17: Non-Volatile Data Memory Data Flash

    CMS80F761x Reference Manual Non-volatile Data Memory Data FLASH The non-volatile data memory Data FLASH can be used to store important data such as constant data, calibration data, protection safety-related information, etc. The data stored in this area has the characteristic that the data is not lost in the event of a chip power outage or a sudden or unexpected power outage.
  • Page 18 CMS80F761x Reference Manual The high 128 Bytes shown above and SFR occupy the same area (80H to FFH), but they are independent. Storage spaces with direct addressing above 7FH (SFR) and indirect addressing above 7FH (128 Bytes high) go into different storage spaces. The low 128Bytes spatial register allocation shown in the figure above is shown in the figure below.

  • Page 19: General External Data Register Xram

    CMS80F761x Reference Manual General External Data Register XRAM There is a maximum 4KB XRAM area inside the chip, this area is not connected to FLASH/RAM, XRAM space allocation block diagram as shown in the following figure: 0FFFH XRAM (Indirect Addressing Mode) 0000H XRAM/XSFR spatial access operates through DPTR data pointers, which consist of two sets of pointers: DPTR0, DPTR1,...

  • Page 20: Special Function Register Sfr

    CMS80F761x Reference Manual Special Function Register SFR Special function registers refer to a set of registers with special purposes, essentially some on-chip RAM units with special functions, discretely distributed in the address range of 80H to FFH. Users can byte access them through direct addressing instructions, and addresses four bits lower than 0000 or 1000 can be addressed bitwise, such as P0, TCON, P1.
  • Page 21 CMS80F761x Reference Manual The BANK1 register table is as follows: BANK1 0xF8 PCRCDL PCRCDH MLOCK MADRL MADRH MDATA MCTRL 0xF0 0xE8 FUNCCR1 PCON1 0xE0 SCON2 SBUF2 0xD8 0xD0 0xC8 T2CON T2IF RLDL RLDH CCEN T2IE 0xC0 CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 0xB8...

  • Page 22: External Special Function Register Xsfr

    CMS80F761x Reference Manual External Special Function Register XSFR XSFR is a special register shared by the addressing space and XRAM, mainly including: port control registers, other function control registers. Its addressing range is shown in the following figure: FFFFH XSFR region: 4K F000H EFFFH Reserved space...
  • Page 23 CMS80F761x Reference Manual address register Register description F01DH P1SR P1 port slope control register F01EH P1DS Port P1 data input select register F020H P20CFG P20 port configuration register F021H P21CFG P21 port configuration register F022H P22CFG P22 port configuration register F023H P23CFG P23 port configuration register...
  • Page 24 CMS80F761x Reference Manual address register Register description F050H P50CFG P50 port configuration register F051H P51CFG P51 port configuration register F052H P52CFG P52 port configuration register F053H P53CFG P53 port configuration register F054H P54CFG P54 port configuration register F055H P55CFG P55 port configuration register F056H F057H F059H...
  • Page 25 CMS80F761x Reference Manual address register Register description F09FH P37EICFG P37 port interrupt control register F0A0H P40EICFG P40 port interrupt control register F0A1H P41EICFG P41 interrupt control register F0A2H P42EICFG P42 port interrupt control register F0A3H P43EICFG P43 port interrupt control register F0A4H P44EICFG P44 port interrupt control register...
  • Page 26 CMS80F761x Reference Manual address register Register description F12EH PWM4DIV PWM4 clock divider control register F12FH PWM5DIV PWM5 clock divider control register F130H PWMP0L The PWM0 cycle data register is 8 bits lower F131H PWMP0H The PWM0 periodic data register is 8 bits high F132H PWMP1L The PWM1 cycle data register is 8 bits lower...
  • Page 27 CMS80F761x Reference Manual address register Register description F5E0H UID0 UID<7:0> F5E1H UID1 UID<15:8> F5E2H UID2 UID<23:16> F5E3H UID3 UID<31:24> F5E4H UID4 UID<39:32> F5E5H UID5 UID<47:40> F5E6H UID6 UID<55:48> F5E7H UID7 UID<63:56> F5E8H UID8 UID<71:64> F5E9H UID9 UID<79:72> F5EAH UID10 UID<87:80> F5EBH UID11 UID<95:88>...
  • Page 28 CMS80F761x Reference Manual address register Register description F672H LCDSEG34 LCD SEG34 register F673H LCDSEG35 LCD SEG35 register F680H LCDCON0 LCD control register 0 F681H LCDCON1 LCD control register 1 F682H LCDCON2 LCD control register 2 F683H LCDCON3 LCD control register 3 F684H LCDCOMEN LCD COM port enable register...
  • Page 29 CMS80F761x Reference Manual address register Register description F6E2H F6E3H F6E4H F6E5H F708H CRCIN CRC module data input registers F709H CRCDL CRC operation results in a low 8-bit data register F70AH CRCDH The CRC operation results in a high 8-bit data register F710H LEDSDRP0L The P00-P03 drive current control register...
  • Page 30 CMS80F761x Reference Manual address register Register description drive). LED COM3 corresponds to the SEG15-SEG8 data register LEDC3DATA1 (matrix driver). F74DH LED0 dot matrix drive displays data registers (dot matrix LED7DATA drive). The LED COM3 corresponds to the SEG23-SEG16 data F74EH LEDC3DATA2 register (matrix driver).
  • Page 31 CMS80F761x Reference Manual address register Register description LED SEG23-SEG16 enable register 2 (matrix drive). LEDSEGEN2 F763H dot matrix drives the second stage of the cycle SCAN2WH configuration register 8 bits high LED SEG27-SEG24 enable register 3 (matrix driver). LEDSEGEN3 F764H dot matrix drives the second stage of the cycle SCAN2WL configuration register 8 bits high...

  • Page 32: Reset

    CMS80F761x Reference Manual 3. Reset Reset Time refers to the time from the time the chip resets to the time when the chip starts executing instructions, and its default design value is about 16ms. This time includes oscillator start time, configuration time. This reset time will exist whether the chip is powered on reset or otherwise caused by a reset.
  • Page 33 CMS80F761x Reference Manual = 1.8 V POR TIME = 16ms nPOR (Internal Signal) configuration effective CPU WORK RESETB (Internal Signal) Oscillation (CLK) Whether the system is power-on reset can be determined by the PORF (WDCON.6) flag bit. The types of resets that can be placed with a PORF flag of 1 are: power-on reset, LVR reset, power on monitoring reset, CONFIG protected reset, external reset, window watchdog reset.
  • Page 34 CMS80F761x Reference Manual Bit3 WDTIF: WDT overflow interrupt flag bit; WDT overflow (write 0 cleared); WDT does not overflow. Bit2 WDTRF: WDT reset marker bit; The system is reset by WDT (write 0 cleared); The system is not reset by WDT. Bit1 WDTRE: WDT reset enable bit;...

  • Page 35: External Reset

    CMS80F761x Reference Manual External Reset External reset refers to a reset signal from an external port (NRST) that resets the chip after being input by a Schmitt trigger. If the NRST pin remains low above about 16us (internal LSI clock sampled with 3 rising edges) during operating voltage range and stable oscillation, a reset is requested.

  • Page 36: Watchdog Reset

    CMS80F761x Reference Manual Watchdog Reset Watchdog reset is a protective setting of the system. In normal condition, the watchdog timer is cleared to zero by the program. If an error occurs, the system is in an unknown state, the watchdog timer overflows, and the system resets. After the watchdog is reset, the system reboots into a normal state.

  • Page 37: Config Status Protection Reset

    CMS80F761x Reference Manual CONFIG Status Protection Reset CONFIG state protection reset is an enhanced protection mechanism of the system. During power-on reset, there is an internal set of 16-bit CONFIG registers that load the fixed code set in flash (A569H) and do not operate during normal operation. If, in the case of a particular non-program operation, the value of the register changes and is not equal to the original fixed code, and after several clock samples, the register continues to remain in a state that is not fixed code, the system will reset.

  • Page 38: Clock Structure

    CMS80F761x Reference Manual 4. Clock Structure There are four types of clock sources for system clocks, and clock source and clock divider can be selected by setting the system configuration register or user register. The system clock sources are as follows: ◆...

  • Page 39: Related Registers

    CMS80F761x Reference Manual Related Registers 4.2.1 Oscillator Control Register CLKDIV 0x8F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLKDIV CLKDIV7 CLKDIV6 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0 Reset value Bit7~Bit0 System clock Fsys divider; CLKDIV<7:0>: 00H= Fsys=Fsys_pre; Other = Fsys=Fsys_pre/（2*CLKDIV）（2,4...

  • Page 40: System Clock Status Register Sckstau

    CMS80F761x Reference Manual 4.2.3 System clock status register SCKSTAU 0xD7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCKSTAU LSI_F LSE_F HSE_F HSI_F Reset value Bit7 LSI_F: Low-speed internal steady-state bit; Stability; Not stable. Bit6 LSE_F: Steady state bit of low-speed external crystal; Stability;...

  • Page 41: System Clock Monitor Register Scm

    CMS80F761x Reference Manual 4.2.4 System clock monitor register SCM Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 F697H XT_SCM SCMEN SCMIE SCMIF SCMSTA Reset value Bit7 SCMEN: Oscillation stop detection module enable; Enable; Disable. Bit6 Stop detection interrupt enable bit (this interrupt and LSE timer interrupt share a single SCMIE: interrupt entry);...

  • Page 42: Function Clock Control Registers

    CMS80F761x Reference Manual 4.2.5 Function clock control registers Watchdog overflow time/timer clock source selection register CKCON 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON WTS2 WTS1 WTS0 Reset value Bit7~Bit5 WTS<2:0>: WDT overflow time selection bits; 000= *Tsys; 001= *Tsys;...
  • Page 43 CMS80F761x Reference Manual UART2 baud rate selection register FUNCCR1 0xE2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FUNCCR1 UART2_CKS2 UART2_CKS1 UART2_CKS0 Reset value Registers in BANK1 Bit7~Bit3 Reserved, must be 0. Bit2~Bit0 UART2_CKS<2:0>: Timer clock source selection for UART2; 000= Overflow clock for Timer1;...

  • Page 44: System Clock Switching

    CMS80F761x Reference Manual System clock switching A set of crystal ports on the chip can only have one set of crystal ports valid at the same time, so it is forbidden to use the switching function of HSE/LSE. When the current chip selects an external HSE clock, the use of LSE-related functions is Disable.

  • Page 45: System Clock Monitoring

    CMS80F761x Reference Manual System Clock Monitoring System Clock Monitoring (SCM) is a monitoring and protection circuit designed to prevent the system from not working due to crystal oscillation suspension. When using HSE/LSE as the system clock, once the HSE/LSE clock stops, the system will force the HSI clock source to start, and the system will run at 8MHz after the HSI is stabilized, and then if the HSE/LSE clock is restored and stable, the system clock will automatically switch back from the HSI back to HSE/LSE.

  • Page 46: Power Management

    CMS80F761x Reference Manual 5. power Management Low-power modes fall into 2 categories: ◆ IDLE: Idle mode ◆ STOP: Sleep mode When users use C language for program development, it is strongly recommended to use IDLE and STOP macros to control the system mode, and do not directly set THE IDLE and STOP bits. The macros are as follows: Enter idle mode: IDLE();...

  • Page 47: Power Supply Monitor Register Lvdcon

    CMS80F761x Reference Manual Power Supply Monitor Register LVDCON The MCU comes with a power supply detection function. If the LVD module enable (LVDEN=1) is set and the voltage monitoring point LVDSEL is set, when the power supply voltage drops below the LVD setpoint, an interrupt will be generated to alert the user.

  • Page 48: Stop Sleep Mode

    CMS80F761x Reference Manual STOP Sleep Mode In this mode, all circuits except the LVD module and LSE module are shut down (the LVD/LSE module must be closed by software), the system is in a low-power mode, and the digital circuits are not working. 5.4.1 Sleep Wakes up After entering the sleep mode, you can turn on the sleep wake function (SWE=1...

  • Page 49: Sleep Wake-Up Time

    CMS80F761x Reference Manual 5.4.3 Sleep Wake-up Time The total wake-up time of the system with an external interrupt wake-up system is: Power Manager Settling Time (200us) + Wake-up Wait Time The total wake-up time of the system with timed wake-up is: Power Manager Settling Time (200us) + Timing of wake-up timer + Wake-up wait time (The above given time condition is Fsys>1MHz) www.mcu.com.cn...

  • Page 50: Reset Operation Under Sleep

    CMS80F761x Reference Manual 5.4.4 Reset Operation under Sleep In sleep mode, the system can also be restarted by power-down reset or external reset or WWDT reset, independent of the value of SWE, even if SWE=0 can also restart the system by the above reset operation. Power-down reset: No other conditions are required, VDD is reduced to 0V and then powered back on to the working voltage and enters the power-on reset state.

  • Page 51: Interrupt

    CMS80F761x Reference Manual 6. Interrupt Interrupt Overview The chip has 26 interrupt sources and interrupt vectors: Interrupt source Interrupt description Interrupt vector Sibling priority sequence INT0 External interrupt 0 0-0x0003 Timer0 Timer 0 interrupt 1-0x000B INT1 External interrupt 1 2-0x0013 Timer1 Timer 1 interrupt 3-0x001B...

  • Page 52: External Interrupts

    CMS80F761x Reference Manual External Interrupts 6.2.1 INT0/INT1 Interrupt The chip supports the 8051 native INT0, INT1 external interrupt, INT0/INT1 can choose to falling edge or low level trigger interrupt, the relevant control register is TCON. INT0 and INT1 occupy two interrupt vectors. 6.2.2 GPIO Interrupt Each GPIO pin of the chip supports an external interrupt and can support falling/rising/dual edge interrupts, with the edge...

  • Page 53: Interrupt Register

    CMS80F761x Reference Manual Interrupt Register 6.4.1 Interrupt Mask Registers 6.4.1.1 Interrupt Mask Register IE Interrupt mask register IE is a read-write register that can be operated bitwise. When an interrupt condition arises, the interrupt flag bit will be set to 1 regardless of the state of the corresponding interrupt enable bit or the global enable bit EA. The user software should ensure that the corresponding interrupt flag bits are cleared to zero before enabling an interrupt.

  • Page 54: Interrupt Mask Register Eie2

    CMS80F761x Reference Manual 6.4.1.2 Interrupt Mask Register EIE2 0xAA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIE2 SPIIE I2CIE WDTIE ADCIE PWMIE Reset value Bit7 SPIIE: SPI interrupt enable bit; Allow SPI interrupts; Disable SPI Interrupt. Bit6 I2CIE: I2C interrupt enable bit; Allow I2C interrupts;...

  • Page 55: Timer2 Interrupt Mask Register T2Ie

    CMS80F761x Reference Manual 6.4.1.4 Timer2 Interrupt Mask Register T2IE 0xCF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IE T2OVIE T2EXIE T2C3IE T2C2IE T2C1IE T2C0IE Reset value Bit7 T2OVIE: Timer2 overflow interrupt enable bits; Interrupts enabled; Disable Interrupt. Bit6 T2EXIE: Timer2 external loading interrupt enable bits;...

  • Page 56: P2 Interrupt Control Register P2Extie

    CMS80F761x Reference Manual 6.4.1.7 P2 Interrupt Control Register P2EXTIE 0xAE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P27IE P26IE P25IE P24IE P2EXTIE P23IE P22IE P21IE P20IE Reset value Bit7~Bit0 P2iIE: P2i port interrupt enable bits (i=0-7); Interrupts enabled; Disable Interrupt. 6.4.1.8 P3 Port Interrupt Control Register P3EXTIE 0xAF...

  • Page 57: Interrupt Priority Controls The Register

    CMS80F761x Reference Manual 6.4.2 Interrupt Priority Controls the Register 6.4.2.1 Interrupt priority controls register IP Interrupt priority control register IP is a read-write register that can be operated bitwise. 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0.

  • Page 58: Interrupt Priority Control Register Eip1

    CMS80F761x Reference Manual 6.4.2.2 Interrupt Priority Control Register EIP1 0xB9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP1 Reset value Bit7 Reserved, must be 0. Bit6 Reserved, must be 0. Bit5 PP5: P5 port interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt.

  • Page 59: Interrupt Priority Control Register Eip3

    CMS80F761x Reference Manual Bit2 PLED: LED dot matrix scan/LCD interrupt priority control bit Set to High-level Interrupt; Set to low-level interrupt. Bit1 PT4: TIMER4 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit0 PT3: TIMER3 interrupt priority control bit; Set to High-level Interrupt;...

  • Page 60: Interrupt Flag Bit Register

    CMS80F761x Reference Manual 6.4.3 Interrupt Flag Bit Register 6.4.3.1 Timer0/1, INT0/1 Interrupt Flag Bit Register TCON 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; Timer1 counter overflow, when entering the interrupt service program, the hardware is automatically cleared, and the software can also be cleared;...

  • Page 61: Timer2 Interrupt Flag Bit Register T2If

    CMS80F761x Reference Manual 6.4.3.2 Timer2 interrupt flag bit register T2IF 0xC9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IF T2EXIF T2C3IF T2C2IF T2C1IF T2C0IF Reset value Bit7 TF2: Timer2 counter overflow interrupt flag bit; Timer2 counter overflow, software zeroing is required; The Timer2 counter has no overflow.

  • Page 62: Spi Interrupt Flag Bit Register Spsr

    CMS80F761x Reference Manual cleared); The PWM did not produce an interrupt. Bit2 Reserved, must be 0. Bit1 TF4: Timer4 timer overflow interrupt flag bit; Timer4 timer overflow, the hardware is automatically cleared when entering the interrupt service program, and the software can also be cleared; The Timer4 timer has no overflow.

  • Page 63: I2C Slave Mode Status Register I2Cssr

    CMS80F761x Reference Manual 6.4.3.6 I2C slave mode status register I2CSSR 0xF2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I2CSSR SENDFIN TREQ RREQ Reset value Bit7~Bit3 Reserved, must be 0. Bit2 SENDFIN: I2C slave mode send operation completion flag bit, read-only; The data is no longer required by the master device, the TREQ is no longer set to 1, and the data transfer has been completed.

  • Page 64: P0 Port Interrupt Flag Register P0Extif

    CMS80F761x Reference Manual 6.4.3.8 P0 port interrupt flag register P0EXTIF 0xB4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P0EXTIF P07IF P06IF P05IF P04IF P03IF P02IF P01IF P00IF Reset value Bit7~Bit0 P0iIF: P0i interrupt flag bit (i=0-7); P0i port produces an interrupt, which requires software clearance; There is no interrupt in the P0i port.

  • Page 65: P4 Port Interrupt Flag Bit Register P4Extif

    CMS80F761x Reference Manual 6.4.3.12 P4 port interrupt flag bit register P4EXTIF 0xA6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P4EXTIF P47IF P46IF P45IF P44IF P43IF P42IF P41IF P40IF Reset value Bit7~Bit0 P4iIF: P4i interrupt flag bit (i=0-7); P4i port produces an interrupt, which requires software clearance; There is no interrupt in the P4i port.

  • Page 66: The Clear Operation For The Interrupt Flag Bit

    CMS80F761x Reference Manual 6.4.4 The clear operation for the interrupt flag bit The clear operation of the interrupt flag is divided into the following categories: ◆ Automatic hardware cleanup (requires entry into interrupt service) ◆ Software cleanup ◆ Read/write operations are cleare The hardware automatically clears the flag bits The bits that support hardware auto-clearing are the interrupt flag bits generated by IN0, INT1, T0, T1, T3, and T4.

  • Page 67: Special Interrupt Flag Bits In Debug Mode

    CMS80F761x Reference Manual 6.4.5 Special Interrupt Flag Bits in Debug Mode The flag bit in the system is not written to zero to the flag bit, but requires reading/writing other registers to clear the flag bit. In debug mode, after breakpoint execution, step-through, or stop operation, the emulator reads out all register values from the system to the emulation software, and the emulator reads/writes exactly the same as in normal mode.

  • Page 68: I/O Port

    CMS80F761x Reference Manual 7. I/O Port GPIO Function The chip has six sets of I/O ports: PORT0, PORT1, PORT2, PORT3, PORT4, PORT5. PORTx is a bidirectional port. Its corresponding data direction register is PxTRIS. A position 1 (=1) of the PxTRIS allows the corresponding pin to be configured as an output.

  • Page 69: Portx Open-Drain Control Register Pxod

    CMS80F761x Reference Manual 7.1.3 PORTx open-drain Control Register PxOD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxOD PxOD7 PxOD6 PxOD5 PxOD4 PxOD3 PxOD2 PxOD1 PxOD0 Reset value Register P0OD Address: F009H; Register P1OD Address: F019H; Register P2OD Address: F029H; Register P3OD Address: F039H;...

  • Page 70: Portx Slope Control Register Pxsr

    CMS80F761x Reference Manual 7.1.6 PORTx Slope Control Register PxSR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxSR PxSR7 PxSR6 PxSR5 PxSR4 PxSR3 PxSR2 PxSR1 PxSR0 Reset value Register P0SR Address: F00DH; Register P1SR Address: F01DH; Register P2SR Address: F02DH; Register P3SR Address: F03DH;...

  • Page 71: Multiplexed Functions

    CMS80F761x Reference Manual Multiplexed Functions 7.2.1 Port Multiplexing Feature Table Pins are shared in a variety of functions, and each I/O port can be flexibly configured with digital functions or specified analog functions. The digital function of the external input is selected by the port input function allocation register (PS_XX); The multiplexing function is selected by the port multiplexing function configuration register (PxnCFG), where the communication input function is also specified by the communication input function assignment register (PS_XX).
  • Page 72 CMS80F761x Reference Manual GPIO TXD0 MOSI TXD1 RXD1 T0G/T1G/T2EX GPIO MISO TXD1 RXD1 T0/T1/T2 GPIO NSS(NSSO0) TXD1 RXD1 GPIO NSS(NSSO1) TXD1 RXD1 GPIO NSS(NSSO2) TXD1 RXD1 MOQ/INT0 GPIO NSS(NSSO3) BUZZ TXD1 RXD1 INT0/INT1 GPIO TXD1 RXD1 GPIO RXD0 SCLK TXD1 RXD1 GPIO TXD0...
  • Page 73 CMS80F761x Reference Manual AN26 TK26 LCDSEG22 AN27 TK27 LCDSEG23 AN28 TK28 LCDSEG24 AN29 TK29 LCDSEG25 AN30 TK30 LCDSEG26 AN31 TK31 LCDSEG27 LEDSEG20 AN32 TK32 LCDSEG28 LEDSEG21 AN33 TK33 LCDSEG29 LEDSEG22 AN34 TK34 LCDSEG30 LEDSEG23 AN35 TK35 LCDSEG31 LEDSEG24 AN36 TK36 LCDSEG32 LEDSEG25 AN37...

  • Page 74: Port Multiplexing Feature Configuration Register

    CMS80F761x Reference Manual 7.2.2 Port Multiplexing Feature Configuration Register The PORTx function configuration register PxnCFG Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PxnCFG PxnCFG2 PxnCFG1 PxnCFG0 Reset value Bit7~Bit3 Reserved, must be 0. PxnCFG< 2:0>: Bit2~Bit0 Feature configuration bit, the default simulation is a function. For details, see port function configuration instructions;...

  • Page 75: The Port Input Function Allocation Registers

    CMS80F761x Reference Manual 7.2.3 The port input function allocation registers Inside the chip there are digital functions with only the input state, such as INT0/INT1... etc., this type of digital input function is independent of the port multiplexing state. As long as the assigned port supports digital input (such as RXD0 as a digital input and GPIO as an input function), the port supports this function.
  • Page 76 CMS80F761x Reference Manual The input function assignment structure allows multiple input functions to be assigned to the same port. For example, T0 and T1 can be assigned to port P03 at the same time, and the configuration is as follows: P03CFG = 0x00;...

  • Page 77: Communication Input Function Allocation Registers

    CMS80F761x Reference Manual 7.2.4 Communication input function allocation registers When the port is used as a communication port (UART0/UART1/SPI/IIC), it has multiple input ports to select, and different port inputs can be selected by setting the following registers. The communication input function port assignment registers are as follows: register address...

  • Page 78: Port External Interrupt Control Registers

    CMS80F761x Reference Manual 7.2.5 Port External Interrupt Control Registers When using an external interrupt, the port needs to be configured as GPIO function and the direction is set to the input port. Alternatively, the multiplexing function is the input port (e.g. RXD0, RXD1), each port can be configured as a GPIO interrupt function.

  • Page 79: Multiplexing Features Application Notes

    CMS80F761x Reference Manual 7.2.6 Multiplexing Features Application Notes The multiplexing function configuration register defaults to an analog function (0x01), and if you use the digital function, you need to set the value of the register to 0x00. The input of the multiplexing function is relatively independent of the structure of the port's external interrupt (GPIO interrupt) and port input function.

  • Page 80: Watchdog Timer (Wdt)

    CMS80F761x Reference Manual 8. Watchdog Timer (WDT) Overview The Watch Dog Timer is an on-chip timer with configurable overflow time and clock source provided by the system clock Fsys. When the watchdog timer counts to the configured overflow value, a watchdog overflow interrupt flag bit (WDTIF=1) is generated.
  • Page 81 CMS80F761x Reference Manual Note: If the WDT in CONFIG is configured as: ENABLE, the WDT is always enabled, regardless of the state of the WDTRE control bit. And the overflow reset function of WDT is forced on. If WDT in CONFIG is configured as : SOFTWARE CONTROL , WDTRE can be enabled or disabled using the WDTRE control bit.

  • Page 82: Watchdog Overflow Control Register Ckcon

    CMS80F761x Reference Manual 8.2.2 Watchdog overflow control register CKCON 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON WTS2 WTS1 WTS0 Reset value Bit7~Bit5 WTS<2:0>: WDT overflow time selection bits; 000= *Tsys; 001= *Tsys; 010= *Tsys; 011= *Tsys; 100= *Tsys 101= *Tsys;...

  • Page 83: Wdt Interrupt

    CMS80F761x Reference Manual WDT interrupt The watchdog timer can enable or disable interrupts via the EIE2 register, and the high/low priority is set via the EIP2 register, where the relevant bits are described as following. 8.3.1 Interrupt mask register EIE2 0xAA Bit7 Bit6...

  • Page 84: Interrupt Priority Control Register Eip2

    CMS80F761x Reference Manual 8.3.2 Interrupt priority control register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...

  • Page 85: Window Watchdog Timer (Wwdt)

    CMS80F761x Reference Manual 9. Window Watchdog Timer (WWDT) Overview The Window Watchdog Timer is an on-chip timer with window comparison time selectable and clock source provided by LSI. Window watchdogs have two mode options: Window feeding dog mode: the window watchdog 5-bit count value starts from 0x1F and counts down, if the window watchdog is cleared before the count value reaches the comparison value or the count value is 0, the window watchdog reset will be generated under the condition of window watchdog reset enable (WWDTRE=1).

  • Page 86: Related Registers

    CMS80F761x Reference Manual Related Registers 9.2.1 WWDT Control Register WWDTCON 0xE5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WWDTCON WWDTPSC3 WWDTPSC2 WWDTPSC1 WWDTPSC0 WWDTEN WWDTRE WWDTCLR WWDTRF Reset value Bit7:4 WWDTPSC<3:0>: Window watchdog prescaler 0000= Flsi/2 1000= Flsi/2 0001= Flsi/2 1001= Flsi/2...

  • Page 87: Wwdt Comparison Value Register Cmpdat

    CMS80F761x Reference Manual 9.2.2 WWDT comparison value register CMPDAT 0xE6 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CMPDAT CMPDAT4 CMPDAT3 CMPDAT2 CMPDAT1 CMPDAT0 Reset value Bit7:5 invalid Bit4:0 CMPDAT<4:0>: Window watchdog comparison values Modify the sequence of instructions required by CMPDAT (no other instructions can be inserted in the middle): TA,#0AAH TA,#055H CMPDAT,#01H...

  • Page 88: Wwdt Interrupt

    CMS80F761x Reference Manual WWDT Interrupt The window watchdog timer can enable or disable interrupts via the WWDTCON2 register, and set high/low priority via the EIP3 register, where the off correlation bits are as follows. 9.3.1 WWDT Control Register 2 WWDTCON2 0xE7 Bit7 Bit6...

  • Page 89: Timer Counter 0/1 (Timer0/1)

    CMS80F761x Reference Manual 10. Timer Counter 0/1 (Timer0/1) Timer 0 is similar in type and structure to Timer 1 and is two 16-bit timers. Timer 1 has three modes of operation and Timer 0 has four modes of operation. They provide basic timing and event counting operations. In "timer mode", the timing register is incremented every 12 or 4 system cycles when the timer clock is enabled.

  • Page 90: Related Registers

    CMS80F761x Reference Manual 10.2 Related Registers 10.2.1 Timer0/1 Mode Register TMOD 0x89 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMOD GATE1 T1M1 T1M0 GATE0 T0M1 T0M0 Reset value Bit7 GATE1: Timer 1 gate control bit; Enable; Disable. Bit6 CT1: Timer 1 timing/count select bits;...

  • Page 91: Timer0/1 Control Register Tcon

    CMS80F761x Reference Manual 10.2.2 Timer0/1 Control Register TCON 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; The Timer1 counter overflows and enters the interrupt service program hardware to automatically zero;...

  • Page 92: Timer0 Data Register Low Bit Tl0

    CMS80F761x Reference Manual 10.2.3 Timer0 Data Register Low Bit TL0 0x8A Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL07 TL06 TL05 TL04 TL03 TL02 TL01 TL00 Reset value Bit7~ Bit0 TL0<7:0>: Timer 0 low data register (also as counter low). 10.2.4 Timer0 Data Register High Bit TH0 0x8C...

  • Page 93: Function Clock Control Register Ckcon

    CMS80F761x Reference Manual 10.2.7 Function Clock Control Register CKCON 0x8E Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CKCON WTS2 WTS1 WTS0 Reset value Bit7~Bit5 WTS<2:0>: WDT overflow time selection bits; 000= *Tsys; 001= *Tsys; 010= *Tsys; 011= *Tsys; 100= *Tsys 101= *Tsys;...

  • Page 94: Timer0/1 Interrupt

    CMS80F761x Reference Manual 10.3 Timer0/1 Interrupt Timer0/1 can enable or disable interrupts via the IE register, and can also set high/low priority via the IP register, where the relevant bits are described as following: 10.3.1 Interrupt Mask Register IE 0xA8 Bit7 Bit6 Bit5...

  • Page 95: Interrupt Priority Controls Register Ip

    CMS80F761x Reference Manual 10.3.2 Interrupt Priority Controls Register IP 0xB8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value Bit7 Reserved, must be 0. Bit6 PS1: UART1 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit5 PT2: TIMER2 interrupt priority control bit;...

  • Page 96: Timer0/1, Int0/1 Interrupt Flag Bit Register Tcon

    CMS80F761x Reference Manual 10.3.3 Timer0/1, INT0/1 Interrupt Flag Bit Register TCON 0x88 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCON Reset value Bit7 TF1: Timer1 counter overflow interrupt flag bit; Timer1 counter overflow, when entering the interrupt service program, the hardware is automatically cleared, and the software can also be cleared;...

  • Page 97: Timer0 Working Mode

    CMS80F761x Reference Manual 10.4 Timer0 Working Mode 10.4.1 T0 - Mode 0 (13-bit Timing/Counting Mode) In this mode, timer 0 is a 13-bit register. When all the bits of the counter are flipped from 1 to 0, the timer 0 interrupt flag TF0 is set to 1.

  • Page 98: T0 - Mode 2 (8-Bit Auto-Reload Timing/Counting Mode)

    CMS80F761x Reference Manual 10.4.3 T0 - Mode 2 (8-bit Auto-reload Timing/Counting Mode) The mode 2 timer register is an 8-bit counter (TL0) with auto reload mode, as shown in the figure below. The overflow from TL0 not only sets TF0 to 1, but also Reloads the contents of TH0 from software to TL0. The value of TH0 remains unchanged during Reloading.

  • Page 99: Timer1 Working Mode

    CMS80F761x Reference Manual 10.5 Timer1 Working Mode 10.5.1 T1 - Mode 0 (13-bit Timing/Counting Mode) In this mode, timer 1 is a 13-bit register. When all the bits of the counter are flipped from 1 to 0, the timer 1 interrupt flag TF1 is set to 1.

  • Page 100: T1 - Mode 2 (8-Bit Auto Reload Timing/Counting Mode)

    CMS80F761x Reference Manual 10.5.3 T1 - Mode 2 (8-bit Auto Reload Timing/Counting Mode) The timer 1 register in mode 2 is an 8-bit counter (TL1) with auto-reload mode, as shown in the figure below. The overflow from TL1 not only makes TF1 1, but also Reloads the contents of TH1 from software to TL1. The value of TH1 remains unchanged during Reloading.

  • Page 101: Timer Counter 2 (Timer2)

    CMS80F761x Reference Manual 11. Timer Counter 2 (Timer2) Timer 2 with additional compare/capture/reload functionality is one of the core peripheral units. It can be used for the generation of various digital signals and event capture, such as pulse generation, pulse width modulation, pulse width measurement, etc.

  • Page 102: Related Registers

    CMS80F761x Reference Manual 11.2 Related Registers 11.2.1 Timer2 Control Register T2CON 0xC8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2CON T2PS I3FR CAPES T2R1 T2R0 T2CM T2I1 T2I0 Reset value Bit7 T2PS: Timer2 clock prescaler selection bit; Fsys/24; Fsys/12. Bit6 I3FR: Capture channel 0 input one-edge selection with comparison interrupt moment selection...

  • Page 103: Timer2 Data Register High Th2

    CMS80F761x Reference Manual 11.2.3 Timer2 Data Register High TH2 0xCD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TH27 TH26 TH25 TH24 TH23 TH22 TH21 TH20 Reset value Bit7~Bit0 TH2<7:0>: Timer 2 high-bit data register (also as counter low). 11.2.4 Timer2 Compare/Capture/Auto Reload Register Low Bit RLDL 0xCA Bit7...

  • Page 104: Timer2 Compares/Captures Channel 2 Registers Low Ccl2

    CMS80F761x Reference Manual 11.2.8 Timer2 Compares/Captures Channel 2 Registers Low CCL2 0xC4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CCL2 CCL27 CCL26 CCL25 CCL24 CCL23 CCL22 CCL21 CCL20 Reset value Bit7~Bit0 CCL2<7:0>: Timer 2 compares/captures channel 2 registers low. 11.2.9 Timer2 Compares/Captures Channel 2 Registers High-bit CCH2 0xC5...

  • Page 105: Timer2 Compares The Capture Control Register Ccen

    CMS80F761x Reference Manual 11.2.12 Timer2 Compares the Capture Control Register CCEN 0xCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CCEN CMH3 CML3 CMH2 CML2 CMH1 CML1 CMH0 CML0 Reset value Bit7~Bit6 CMH3-CML3: Capture/Compare Mode Control Bits; Capture/Compare Disable; The capture operation is triggered on the rising or falling edge of channel 3 (CAPES selection);...

  • Page 106: Timer2 Interrupts

    CMS80F761x Reference Manual 11.3 Timer2 Interrupts Timer 2 can be enabled or disabled by register IE, and high/low priority can also be set via IP registers. Timer2 has 4 interrupt types: ◆ A timed overflow interrupt. ◆ The external pin T2EX drops along the interrupt. ◆...

  • Page 107: Timer2 Interrupt Mask Register T2Ie

    CMS80F761x Reference Manual 11.3.1.2 Timer2 Interrupt Mask Register T2IE 0xCF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T2IE T2OVIE T2EXIE T2C3IE T2C2IE T2C1IE T2C0IE Reset value Bit7 T2OVIE: Timer2 overflow interrupt enable bits; Interrupts enabled; Disable Interrupt. Bit6 T2EXIE: Timer2 external loading interrupt enable bits;...

  • Page 108: Timer2 Interrupt Flag Bit Register T2If

    CMS80F761x Reference Manual Set to low-level interrupt. Bit1 PT0: TIMER0 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit0 PX0: External interrupt 0 interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. 11.3.1.4 Timer2 Interrupt Flag Bit Register T2IF 0xC9 Bit7...

  • Page 109: Timer Interrupts

    CMS80F761x Reference Manual 11.3.2 Timer Interrupts The timer interrupt enable bit is set by register T2IE[7], and the interrupt flag bit is viewed by register T2IF[7]. When the Timer2 timer overflows, the timer overflow interrupt flag bit TF2 will be set to 1. 11.3.3 Externally Triggered Interrupts The external pin T2EX descending edge trigger interrupt enable bit is set by register T2IE[6], and the interrupt flag bit is...

  • Page 110: Timer2 Feature Description

    CMS80F761x Reference Manual 11.4 Timer2 Feature Description Timer 2 is a 16-bit up counting timer with a clock source from the system clock. Timer2 can be configured with the following functional modes: ◆ Timing mode. ◆ Reload mode. ◆ Gating timing mode. ◆...

  • Page 111: Gated Timing Mode

    CMS80F761x Reference Manual 11.4.3 Gated Timing Mode When Timer2 is used as a gated timer function, an external input pin, T2, serves as the gated input to timer 2. If the T2 pin is high, the internal clock input is gated to the timer. A low T2 pin terminates the counting. This function is often used to measure pulse width.

  • Page 112: Compare Mode 0

    CMS80F761x Reference Manual 11.4.5.1 Compare Mode 0 In mode 0, when the timer's count value and the comparison register are equal, the comparison output signal changes from low to high. When the timer count value overflows, the comparison output signal goes low. The comparison output channel is directly controlled by two events: the timer overflow and the comparison operation.

  • Page 113: Comparison Mode 1

    CMS80F761x Reference Manual 11.4.5.2 Comparison Mode 1 In comparison mode 1, it is typically used where the output signal is independent of a constant signal cycle, where the software adaptively determines the output signal transition. If mode 1 is enabled, the software writes to the corresponding output register of the CCx port, and the new value does not appear on the output pin until the next comparison match occurs.

  • Page 114: Capture Mode 0

    CMS80F761x Reference Manual 11.4.6 Capture mode Each of the four 16-bit registers {RLDH,RLDL}, {CCH1,CCL1}, {CCH2,CCL2}, {CCH3,CCL3} can be used to latch the current 16-bit value of {TH2,TL2}. This feature provides two different capture modes. In mode 0, an external event can latch the contents of timer 2 into the capture register. In mode 1, the capture operation occurs when a low-bit byte (RLDL/CCL1/CCL2/CCL3) is written to the 16-bit capture register.

  • Page 115: Capture Mode 1

    CMS80F761x Reference Manual 11.4.6.2 Capture mode 1 In capture mode 1, the capture operation event is the execution of a write byte instruction to the capture register. A write register signal, such as a write RLDL, initiates a capture operation, and the value written is independent of this function. After the write instruction is executed, the contents of timer 2 are latched into the corresponding capture register.

  • Page 116: Timer 3/4 (Timer3/4)

    CMS80F761x Reference Manual 12. Timer 3/4 (Timer3/4) Timer 3/4 is similar to timer 0/1 in that it is two 16-bit timers. Timer 3 has four modes of operation and Timer 4 has three modes of operation. In contrast to Timer0/1, Timer3/4 only provides timer operations. With the timer activated, the value of the register is incremented every 12 or 4 system cycles.

  • Page 117: Timer3 Data Register Low Bit Tl3

    CMS80F761x Reference Manual 12.2.2 Timer3 Data Register Low Bit TL3 0xDA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TL37 TL36 TL35 TL34 TL33 TL32 TL31 TL30 Reset value Bit7~Bit0 TL3<7:0>: Timer 3 low bit data register (while acting as timer low bit). 12.2.3 Timer3 Data Register High Bit TH3 0xDB...

  • Page 118: Timer3/4 Interrupt

    CMS80F761x Reference Manual 12.3 Timer3/4 Interrupt Timer 3/4 can enable or disable interrupts via the EIE2 registers, and high/low prioritization can also be set via the EIP2 registers, where the relevant bits are described as following: 12.3.1 Interrupt Mask Register EIE2 0xAA Bit7 Bit6...

  • Page 119: Interrupt Priority Control Register Eip2

    CMS80F761x Reference Manual 12.3.2 Interrupt priority control register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...

  • Page 120: Peripheral Interrupt Flag Bit Register Eif2

    CMS80F761x Reference Manual 12.3.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...

  • Page 121: Timer3 Working Mode

    CMS80F761x Reference Manual 12.4 Timer3 Working Mode 12.4.1 T3 - Mode 0 (13-bit Timing Mode) In this mode, timer 3 is a 13-bit register. When all the bits of the timer are flipped from 1 to 0, the timer 3 interrupt flag TF3 is set to 1.

  • Page 122: T3 - Mode 2 (8-Bit Auto Reload Timing Mode)

    CMS80F761x Reference Manual 12.4.3 T3 - Mode 2 (8-bit Auto Reload Timing Mode) The timer 3 register in mode 2 is an 8-bit timer (TL3) with auto reload mode, as shown in the figure below. The overflow from TL3 not only puts TF3 at 1, but also Reloads the contents of TH3 from software to TL3. The value of TH3 remains unchanged during Reloading.

  • Page 123: Timer4 Working Mode

    CMS80F761x Reference Manual 12.5 Timer4 Working Mode 12.5.1 T4 - Mode 0 (13-bit Timing Mode) In this mode, timer 4 is a 13-bit register. When all the bits of the timer are flipped from 1 to 0, the timer 4 interrupt flag TF4 is set to 1.

  • Page 124: T4- Mode 2 (8-Bit Auto Reload Timing Mode)

    CMS80F761x Reference Manual 12.5.3 T4- Mode 2 (8-bit Auto Reload Timing Mode) The timer 4 register in mode 2 is an 8-bit timer (TL4) with an auto-reload mode, as shown in the figure below. The overflow from TL4 not only makes TF4 1, but also Reloads the contents of TH4 from software to TL4. The value of TH4 remains unchanged during Reloading.

  • Page 125: Lse Timer(Lse_Timer)

    CMS80F761x Reference Manual 13. LSE Timer(LSE_Timer) 13.1 Overview The LSE timer is a clock source from an external low-speed clock LSE, a 16-bit up-counting timer. When using the LSE timer function, you should first set the LSE module to enable, wait for the LSE clock to stabilize (about 1.5s), and then set the LSE count enable.

  • Page 126: Lse Timer Control Register Lsecon

    CMS80F761x Reference Manual 13.2.3 LSE Timer Control Register LSECON F696H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LSECON LSEEN LSEWUEN LSECNTEN LSESTA LSEIE LSEIF Reset value Bit7 LSEEN: LSE module enable control; Enable; Disable. Bit6 LSEWUEN: LSE timer wake-up enable control; Enable;...

  • Page 127: Interrupt With Sleep Wake-Up

    CMS80F761x Reference Manual 13.3 Interrupt With Sleep Wake-up The LSE timer can enable or disable interrupts via LSECON registers, setting high/low priority via EIP3 registers, where the relevant bits are described as following. 0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP3...

  • Page 128: Feature Description

    CMS80F761x Reference Manual 13.4 Feature Description To use the LSE timer function, you need to set LSEEN=1 to enable the LSE timer function module, and then wait for the LSE clock steady state bit LSESTA=1, then configure the LSE timing value {LSECRH[7:0], LSECRL[7:0]}, and finally set LSECNTEN=1, enable LSE count, and turn on the LSE count function.

  • Page 129: Wake-Up Timer (Wut)

    CMS80F761x Reference Manual 14. Wake-up Timer (WUT) 14.1 Overview Wake Up Timer is a clock source from the internal low-speed clock LSI, a 12-bit, up-count timer for sleep wake-ups that can be used to time-wake systems in sleep mode. Configure the timed wake-up time before the system goes to sleep and enable the timed wake-up function.

  • Page 130: Feature Description

    CMS80F761x Reference Manual 14.3 Feature Description The internal wake-up timer works on the principle that after the system enters sleep mode, the CPU stops working with all ≈ 8us). peripheral circuitry, and the internal low-power oscillator LSI begins to operate, and its oscillation clock is 125KHz (T Provides a clock for the WUT counter.

  • Page 131: Baud Rate Timer (Brt)

    CMS80F761x Reference Manual 15. Baud Rate Timer (BRT) 15.1 Overview The chip has a 16-bit baud rate timer BRT, which mainly provides a clock for the UART module. 15.2 Related Registers 15.2.1 BRT Module Control Register BRTCon F5C0H Bit7 Bit6 Bit5 Bit4 Bit3...

  • Page 132: Feature Description

    CMS80F761x Reference Manual 15.3 Feature Description The BRT has a 16-bit increment counter, the clock is derived from the pre-division circuit, the pre-division clock is determined by the timer pre-division select bit BRTCKDIV, and the initial value of the counter is loaded by {BRTDH, BRTDL}. When the timer enable bit BRTEN=1 is turned on, the counter starts working.

  • Page 133: Cyclic Redundancy Check Unit (Crc)

    CMS80F761x Reference Manual 16. Cyclic Redundancy Check Unit (CRC) 16.1 Overview In order to ensure safety during operation, the IEC61508 standard requires that data be confirmed even during CPU operation. This universal CRC module performs CRC operations as a peripheral function during CPU operation. The universal CRC module performs CRC checks by specifying the data to be confirmed by the program, and is not limited to the code flash memory area but can be used for multi-purpose checks.

  • Page 134: Feature Description

    CMS80F761x Reference Manual 16.3 Feature Description After writing the CRCIN register, a system clock is passed to save the CRC operation result to the CRCDL/CRCDH register. If necessary, the data of the previous operation must be read before writing, otherwise it will be overwritten by the new operation result.

  • Page 135: Buzzer Driver (Buzzer)

    CMS80F761x Reference Manual 17. Buzzer Driver (BUZZER) 17.1 Overview The buzzer drive module consists of an 8-bit counter, a clock driver, and a control register. The buzzer drives a 50% duty-square wave with a frequency set by registers BUZCON and BUZDIV, and its frequency output covers a wide range. 17.2 Related Registers 17.2.1 BUZZER Control Register BUZCON...

  • Page 136: Feature Description

    CMS80F761x Reference Manual 17.3 Feature Description When using a buzzer, you need to configure the corresponding port as a buzzer-driven output. For example, configure the P16 as a buzzer drive output port, the configuration is as follows: P16CFG = 0x04; The P16 is configured as a buzzer drive output By configuring the Related Registers of the buzzer drive module, it is possible to set the different frequencies at which the buzzer drive outputs.

  • Page 137: Pwm Module

    CMS80F761x Reference Manual 18. PWM Module 18.1 Overview The PWM module supports six PWM generators, which can be configured as 6 independent PWM outputs (PG0-PG5), or as 3 sets of synchronous PWM outputs, or 3 pairs of complementary PWM outputs with programmable dead-zone generators, where PG0-PG1, PG2-PG3, and PG4-PG5 are paired.

  • Page 138: Feature Description

    CMS80F761x Reference Manual 18.4 Feature Description 18.4.1 Functional Block Diagram PWM consists of a clock control module, a PWM counter module, an output comparison unit, a waveform generator, and an output controller, and its block diagram is shown in the following figure: PWMPnH &...

  • Page 139: Edge Alignment

    CMS80F761x Reference Manual 18.4.2 Edge alignment In edge alignment mode, the 16-bit PWM counter CNTn starts counting down at the beginning of each cycle and compares to the value CMPn locked in the PWMDnH/PWMDnL register, when CNTn= CMPn PGn outputs high, PWMnDIF is set to 1. CNTn continues to count down to 0, at which point PGn will output low and PWMnZIF will be set to 1.

  • Page 140: Complementary Model

    CMS80F761x Reference Manual 18.4.3 Complementary model 6 PWM can be set up as 3 sets of complementary PWM pairs. In the complementary mode, the cycle, duty cycle and clock divider control of PG1, PG3, and PG5 are determined by the PG0, PG2, and PG4 related registers, respectively, that is, in addition to the corresponding output enable control bits (PWMnOE), the PG1, PG3, and PG5 output waveforms are no longer controlled by their own registers.

  • Page 141: Synchronous Mode

    CMS80F761x Reference Manual 18.4.4 Synchronous Mode 6-channel PWM can be set to 3 sets of synchronous PWM pairs. In synchronous mode, the period, duty cycle and clock divider control of PG1, PG3, PG5 are determined by the PG0, PG2, PG4 related registers respectively, that is, in addition to the corresponding output enable control bit (PWMnOE), the PG1, PG3, PG5 output waveforms are no longer controlled by their own registers, PG1 output waveforms are similar to PG0, PG3 output waveforms are PG2, and PG5 output waveforms are similar to PG4.

  • Page 142: Pwm-Related Registers

    CMS80F761x Reference Manual 18.5 PWM-related Registers 18.5.1 PWM Control Register PWMCON F120H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCON PWMRUN PWMMODE1 PWMMODE0 GROUPEN Reset value Bit7 Reserved, must be 0. Bit6 PWMRUN: PWM clock pre-division, clock division enable bit; Prohibition (PWMmnPSC, PWMmnDIV are cleared 0);...

  • Page 143: Pwm0/1 Clock Prescale Control Register Pwm01Psc

    CMS80F761x Reference Manual 18.5.3 PWM0/1 Clock Prescale Control Register PWM01PSC F123H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM01PSC PWM01PSC7 PWM01PSC6 PWM01PSC5 PWM01PSC4 PWM01PSC3 PWM01PSC2 PWM01PSC1 PWM01PSC0 Reset value Bit7~Bit0 PWM01PSC<7:0>: PWM channel 0/1 prescale control bit; The prescaler clock stops, the counter of PWM0/1 stops; Other = The system clock is divided (PWM01PSC+1).

  • Page 144: Pwm Clock Divide Control Register Pwmndiv (N=0-5)

    CMS80F761x Reference Manual 18.5.6 PWM Clock Divide Control Register PWMnDIV (n=0-5) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMnDIV PWMnDIV2 PWMnDIV1 PWMnDIV0 Reset value Registers PWMnDIV (n=0-5) Address: F12AH, F12BH, F12CH, F12DH, F12EH, F12FH. Bit7~Bit3 Reserved, must be 0. Bit2~Bit0 PWMnDIV<2:0>: PWM channel n clock divider control bit;...

  • Page 145: Pwm Counter Mode Control Register Pwmcntm

    CMS80F761x Reference Manual 18.5.9 PWM Counter Mode Control Register PWMCNTM F127H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMCNTM PWM5CNTM PWM4CNTM PWM3CNTM PWM2CNTM PWM1CNTM PWM0CNTM Reset value Bit7~Bit6 Reserved, must be 0. Bit5~Bit0 PWMnCNTM: PWM channel n counter mode control bit (n=0-5); Auto loading mode;...

  • Page 146: Pwm Cycle Data Register High 8 Bits Pwmpnh (N=0-5)

    CMS80F761x Reference Manual 18.5.13 PWM Cycle Data Register High 8 Bits PWMPnH (n=0-5) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMPnH PWMPnH7 PWMPnH6 PWMPnH5 PWMPnH4 PWMPnH3 PWMPnH2 PWMPnH1 PWMPnH0 Reset value Registers PWMPnH (n=0-5) Address: F131H, F133H, F135H, F137H, F139H, F13BH. Bit7~Bit0 PWMPnH<7:0>: The PWM channel n-period data register is 8 bits high.

  • Page 147: Pwm0/1 Dead Zone Delay Data Register Pwm01Dt

    CMS80F761x Reference Manual 18.5.17 PWM0/1 Dead Zone Delay Data Register PWM01DT F161H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM01DT PWM01DT7 PWM01DT6 PWM01DT5 PWM01DT4 PWM01DT3 PWM01DT2 PWM01DT1 PWM01DT0 Reset value Bit7~Bit0 PWM01DT<7:0>: PWM channel 0/1 dead-zone delay data register. 18.5.18 PWM2/3 dead-zone delay data register PWM23DT F162H Bit7...

  • Page 148: Pwm Interrupt

    CMS80F761x Reference Manual 18.6 PWM Interrupt PWM has a total of 12 interrupt flags, of which 6 zero interrupt flags, 6 downward comparison interrupt flags, the generation of interrupt flag bits and the corresponding interrupt enable bit is not related to whether the corresponding interrupt enable bit is turned on.

  • Page 149: Interrupt Priority Control Register Eip2

    CMS80F761x Reference Manual 18.6.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...

  • Page 150: Pwm Down Compare Interrupt Mask Register Pwmdie

    CMS80F761x Reference Manual 18.6.4 PWM Down Compare Interrupt Mask Register PWMDIE F16BH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMDIE PWM5DIE PWM4DIE PWM3DIE PWM2DIE PWM1DIE PWM0DIE Reset value Bit7~Bit6 Reserved, must be 0. Bit5~Bit0 PWMnDIE: PWM channel n down compared interrupt shield bits (n=0-5); Enable interrupts;...

  • Page 151: Hardware Lcd Drive

    CMS80F761x Reference Manual 19. Hardware LCD Drive 19.1 Overview The hardware LCD drive contains a controller, a duty cycle generator, and COM and SEG output ports. The hardware LCD drive supports both traditional resistance and fast charging modes, and the bias resistor is selectable from 60KΩ, 225KΩ, and 900KΩ.

  • Page 152: Related Registers

    CMS80F761x Reference Manual 19.3 Related Registers 19.3.1 LCD Control Register LCDCON0 F680H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDCON0 LCDEN LCDDM1 LCDDM0 DUTY1 DUTY0 Reset value Bit7 LCDEN: LCD enable control bit; LCD enable; LCD Disable. Bit6 Reserved, must be 0. Bit5~Bit4 LCDDM<1:0>: LCD display mode;...

  • Page 153: Lcd Control Register Lcdcon1

    CMS80F761x Reference Manual 19.3.2 LCD Control Register LCDCON1 F681H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDCON1 LCDTEN BIAS1 BIAS0 LCDTVS3 LCDTVS2 LCDTVS1 LCDTVS0 Reset value Bit7 LCDTEN: LCD power supply voltage selection; The LCD voltage is provided by the internal power supply VLCD The LCD voltage is provided by VDD.

  • Page 154: Lcd Control Register Lcdcon 3

    CMS80F761x Reference Manual 19.3.4 LCD Control Register LCDCON 3 F683H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDCON3 LCDIE LCDIF LCDRM1 LCDRM0 FCMODE FCCTLM1 FCCTLM0 Reset value Bit7 LCDIE: LCD interrupt enable; LCD interrupt enable; LCD interrupt Disable. Bit6 LCDIF: LCD interrupt flag bit;...

  • Page 155: Seg Port Enable Control Register Lcdsegen1

    CMS80F761x Reference Manual 19.3.7 SEG Port Enable Control Register LCDSEGEN1 F686H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDSEGEN1 BLESSING15 BLESSING14 BLESSING13 BLESSING12 BLESSING11 BLESSING10 BLESSING9 BLESSING8 Reset value Bit7~Bit0 BLESSING<15:8>: LCD_S15-LCD_S8 port enable control bit; Enable; Disable. 19.3.8 SEG Port Enable Control Register LCDSEGEN2 F687H Bit7...

  • Page 156: Seg Data Register Lcdsegn (N=0-35)

    CMS80F761x Reference Manual 19.3.11 SEG Data Register LCDSEGn (n=0-35). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LCDSEGn ICOM7 ICOM6 ICOM5 ICOM4 ICOM3 ICOM2 ICOM1 ICOM0 Reset value THE ADDRESS OF LCDSEG0~LCDSEG35 IS: F650H~F677H. Bit7~Bit0 ICOM<7:0>: LCD_Sn port data output; High level;...

  • Page 157: Com-Seg Datasheet

    CMS80F761x Reference Manual 19.4 COM-SEG Datasheet Hardware LCD drives with different DUTY correspond to the following datasheet. 19.4.1 1/4DUTY Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICOM3 ICOM2 ICOM1 ICOM0 LCDSEG0 F650H SEG0 SEG0 SEG0 SEG0 LCDSEG1 F651H SEG1 SEG1 SEG1 SEG1...

  • Page 158: 1/5Duty

    CMS80F761x Reference Manual 19.4.2 1/5DUTY Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICOM4 ICOM3 ICOM2 ICOM1 ICOM0 LCDSEG1 F651H SEG1 SEG1 SEG1 SEG1 SEG1 LCDSEG2 F652H SEG2 SEG2 SEG2 SEG2 SEG2 LCDSEG3 F653H SEG3 SEG3 SEG3 SEG3 SEG3 LCDSEG4 F654H SEG4 SEG4...

  • Page 159: 1/6Duty

    CMS80F761x Reference Manual 19.4.3 1/6DUTY Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICOM5 ICOM4 ICOM3 ICOM2 ICOM1 ICOM0 LCDSEG2 F652H SEG2 SEG2 SEG2 SEG2 SEG2 SEG2 LCDSEG3 F653H SEG3 SEG3 SEG3 SEG3 SEG3 SEG3 LCDSEG4 F654H SEG4 SEG4 SEG4 SEG4 SEG4 SEG4...

  • Page 160: 1/8Duty

    CMS80F761x Reference Manual 19.4.4 1/8DUTY Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICOM7 ICOM6 ICOM5 ICOM4 ICOM3 ICOM2 ICOM1 ICOM0 LCDSEG4 F654H SEG4 SEG4 SEG4 SEG4 SEG4 SEG4 SEG4 SEG4 LCDSEG5 F655H SEG5 SEG5 SEG5 SEG5 SEG5 SEG5 SEG5 SEG5 LCDSEG6 F656H...

  • Page 161: Hardware Led Matrix Driver

    CMS80F761x Reference Manual 20. Hardware LED Matrix Driver 20.1 Overview The chip integrates a hardware LED matrix display driver circuit, which can facilitate the user to realize the display driver of the LED. 20.2 Characteristic Hardware LED matrix drivers have the following characteristics: ◆...

  • Page 162: Led Control Register Ledcon

    CMS80F761x Reference Manual 20.3.2 LED Control Register LEDCON F765H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCON LED_EN DUTY1 DUTY0 CC_CA CLKSEL1 CLKSEL0 Reset value Bit7 LED_EN: LED enable control bit; LED enable; LEDs are Disable. Bit6~Bit5 DUTY<1:0>: Duty cycle selection bit of the LED; 1/4DUTY;...

  • Page 163: Led Clock Prescale Data Register High 8 Bit Ledclkh

    CMS80F761x Reference Manual 20.3.4 LED clock prescale data register high 8 bit LEDCLKH F767H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCLKH CLK15 CLK14 CLK13 CLK12 CLK11 CLK10 CLK9 CLK8 Reset value Bit7~Bit0 CLK<15:8>: The LED clock divider is 8 bits high. Clock frequency of the LED driver: F / (CLK<15:0>+1).

  • Page 164: Seg Port Enable Control Register Ledsegen1

    CMS80F761x Reference Manual 20.3.8 SEG port enable control register LEDSEGEN1 F762H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSEGEN1 SEGEN15 SEGEN14 SEGEN13 SEGEN12 SEGEN11 SEGEN10 SEGEN9 SEGEN8 Reset value Bit7~Bit0 BLESSING<15:8>: LED_S15-LED_S8 port enable control bit; Enable; Disable. 20.3.9 SEG port enable control register LEDSEGEN2 F763H Bit7...

  • Page 165: Com0 Corresponding Seg Data Register Ledc0Datan (N=0/1/2/3)

    CMS80F761x Reference Manual 20.3.11 COM0 corresponding SEG data register LEDC0DATAn (n=0/1/2/3). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC0DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset value LEDC0DATA0 Address: F740H; LEDC0DATA1 Address: F741H; LEDC0DATA2 Address: F742H; LEDC0DATA3 Address: F743H. when n=0/1/2 Bit7~Bit0 SEG<8n+7:8n>:...

  • Page 166: Com2 Corresponding Seg Data Register Ledc2Datan (N=0/1/2/3)

    CMS80F761x Reference Manual 20.3.13 COM2 Corresponding SEG Data Register LEDC2DATAn (n=0/1/2/3). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC2DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset value LEDC2DATA0 Address: F748H; LEDC2DATA1 Address: F749H; LEDC2DATA2 Address: F74AH; LEDC2DATA3 Address: F74BH; when n=0/1/2 Bit7~Bit0 SEG<8n+7:8n>:...

  • Page 167: Com4 Corresponding Seg Data Register Ledc4Datan (N=0/1/2/3)

    CMS80F761x Reference Manual 20.3.15 COM4 corresponding SEG data register LEDC4DATAn (n=0/1/2/3). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC4DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset value LEDC4DATA0 Address: F750H; LEDC4DATA1 Address: F751H; LEDC4DATA2 Address: F752H; LEDC4DATA3 address: F753H. when n=0/1/2 Bit7~Bit0 SEG<8n+7:8n>:...

  • Page 168: Com6 Corresponding Seg Data Register Ledc6Datan (N=0/1/2/3)

    CMS80F761x Reference Manual 20.3.17 COM6 Corresponding SEG Data Register LEDC6DATAn (n=0/1/2/3). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDC6DATAn SEG[8n+7] SEG[8n+6] SEG[8n+5] SEG[8n+4] SEG[8n+3] SEG[8n+2] SEG[8n+1] SEG[8n] Reset value LEDC6DATA0 Address: F758H; LEDC6DATA1 Address: F759H; LEDC6DATA2 Address: F75AH; LEDC6DATA3 address: F75BH. when n=0/1/2 Bit7~Bit0 SEG<8n+7:8n>:...

  • Page 169: P04-P07 Drive Current Control Register Ledsdrp0H

    CMS80F761x Reference Manual 20.3.19 P04-P07 Drive Current Control Register LEDSDRP0H F711H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP0H DRC3 DRC2 DRC1 DRC0 Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 DRC<3:0>: Pull current drive selection control position (control P04/P05/P06/P07 four ports); 0000= 0mA;...

  • Page 170: P14-P17 Drive Current Control Register Ledsdrp1H

    CMS80F761x Reference Manual 20.3.21 P14-P17 Drive Current Control Register LEDSDRP1H F713H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP1H DRC3 DRC2 DRC1 DRC0 Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 DRC<3:0>: Pull current drive select control position (control P14/P15/P16/P17 four ports); 0000= 0mA;...

  • Page 171: P24-P27 Drive Current Control Register Ledsdrp2H

    CMS80F761x Reference Manual 20.3.23 P24-P27 Drive Current Control Register LEDSDRP2H F715H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP2H DRC3 DRC2 DRC1 DRC0 Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 DRC<3:0>: Pull current drive select control position (control P24/P25/P26/P27 four ports); 0000= 0mA;...

  • Page 172: P44-P47 Drive Current Control Register Ledsdrp4H

    CMS80F761x Reference Manual 20.3.25 P44-P47 Drive Current Control Register LEDSDRP4H F719H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP4H DRC3 DRC2 DRC1 DRC0 Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 DRC<3:0>: Pull current drive selection control position (control P44/P45/P46/P47 four ports); 0000= 0mA;...
  • Page 173 CMS80F761x Reference Manual The pull current drive at the LED5 pins is configured by the LEDSDRP0H register. The dot matrix drive function of the LED5 pins is Disable as a GPIO function; The current drive of the LED5 pin is the default. (LEDMODE!=0xAA) Matrix drive mode SEG5 (P11) / software drive P11 pin current drive enable bit;...

  • Page 174: Led Pin Drive Enable Register Leden1

    CMS80F761x Reference Manual Bit0 LEDEN0_0: (LEDMODE==0xAA) dot matrix drive mode LED0 (P00) pin function and current drive enable bit; LED0 pins enabled by dot matrix drive function; The pull current drive of the LED0 pins is configured by the LEDSDRP0L register. The dot matrix drive function of the LED0 pin is Disable as a GPIO function;...
  • Page 175 CMS80F761x Reference Manual Bit3 LEDEN1_3: (LEDMODE==0xAA); Invalid; Invalid. (LEDMODE!=0xAA) Matrix drive mode SEG11 (P17) / software drive P17 pin current drive enable bit; The pull current drive of the P17 pin is configured by the LEDSDRP1H register; The pull current drive of the P17 pin is the default value. Bit2 LEDEN1_2: (LEDMODE==0xAA);...

  • Page 176: Led Pin Drive Enable Register Leden2

    CMS80F761x Reference Manual 20.3.28 LED Pin Drive Enable Register LEDEN2 F772H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDEN2 LEDEN2_7 LEDEN2_6 LEDEN2_5 LEDEN2_4 LEDEN2_3 LEDEN2_2 LEDEN2_1 LEDEN2_0 Reset value Bit7 LEDEN2_7: (LEDMODE==0xAA); Invalid; Invalid. (LEDMODE!=0xAA) Matrix drive mode SEG23 (P43) / software drive P43 pin current drive enable bit;...

  • Page 177: Led Pin Drive Enable Register Leden3

    CMS80F761x Reference Manual (LEDMODE!=0xAA) Matrix drive mode SEG18 (P26) / software drive P26 pin current drive enable bit; P26-pin pull current drive is configured by LEDSDRP2H registers; The P 2 6 pin pull current drive is the default value. Bit1 LEDEN2_1: (LEDMODE==0xAA);...

  • Page 178: Com Port Sink Current Selection Register P0Dr

    CMS80F761x Reference Manual The pull current drive of the P45 pin is configured by the LEDSDRP4H register; The pull current drive of the P45 pin is the default. Bit0 LEDEN3_0: (LEDMODE==0xAA); Invalid; Invalid. (LEDMODE!=0xAA) Matrix drive mode SEG24 (P44) / software drive P44 pin current drive enable bit;...

  • Page 179: Led Driver Output Waveform

    CMS80F761x Reference Manual 20.4 LED Driver Output Waveform According to the relevant configuration registers of the LED driver, the corresponding LED driver output waveform can be set. The LED is configured with 1/4DUTY, co-negative drive mode, and the waveform is shown in the following figure: COM0 Valid COM0 Valid COM0...

  • Page 180: Hardware Led Dot Matrix Driver

    CMS80F761x Reference Manual 21. Hardware LED Dot Matrix Driver 21.1 Overview LED dot matrix drive is to configure LED0 ~ LED8 port, so as to drive multiple LED lights, convenient for users to drive LED dot matrix. 21.2 Characteristic LED dot matrix drive mode features: ◆...

  • Page 181: Feature Description

    CMS80F761x Reference Manual 21.3 Feature Description LED dot matrix is scanned by 8 * 8 dot matrix dual lamp mode, that is, two lights at a time (common cathode), corresponding to LED0 ~ LED8 port, up to 8x8 = 64 lights can be configured to drive. Configure the lighting situation of the corresponding address (1 means light, 0 means no light), the hardware will resolve the light address and the current scan address, and automatically complete the output control of the corresponding IO port.
  • Page 182 CMS80F761x Reference Manual The 7*8 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED 7*8 dot plot The 7*7 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7...
  • Page 183 CMS80F761x Reference Manual The 6*7 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED 6*7 dot plot The 6*6 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED 6*6 dot plot www.mcu.com.cn...
  • Page 184 CMS80F761x Reference Manual The 5*5 dot matrix is shown in the following figure: LED0 LED1 LED2 LED3 LED4 LED5 LED 5*5 dot plot The 4*4 dot matrix is shown in the following figure: LED 4*4 dot plot Taking the light 0, 1, and 2 as an example, the detailed digital output interface control timing is shown in the following figure: LED0 LED1...
  • Page 185 CMS80F761x Reference Manual Clock LED0_dout 0.016~4.096ms LED0_tris LED1_dout LED1_tris LED2_dout LED2_tris LED0 LED1 LED2 LED light 0 Scan procedure LED light 1 Scan procedure Digital output timing chart www.mcu.com.cn Rev. 1.0.4...

  • Page 186: Related Registers

    CMS80F761x Reference Manual 21.4 Related Registers 21.4.1 LED drive Mode Select Register LEDMODE F769O'CLOCK Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDMODE LEDMODE7 LEDMODE6 LEDMODE5 LEDMODE4 LEDMODE3 LEDMODE2 LEDMODE1 LEDMODE0 Reset value Bit7~Bit0 LEDMODE<7:0>: LED drive mode selection register; 0x55= The LED matrix drive mode is valid, and the relevant registers are effective;...

  • Page 187: Led Dot Matrix Drive Clock Prescale Register Low 8 Bit Ledclkl1

    CMS80F761x Reference Manual 21.4.3 LED Dot Matrix Drive Clock Prescale Register Low 8 Bit LEDCLKL1 F766H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDCLKL1 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 CLK0 Reset value Bit7~Bit0 CLK<7:0>: The LED dot matrix drive clock lower 8 bits. 21.4.4 LED Dot Matrix Drive Clock Prescale Register High 8 Bits LEDCLKH1 F767H...

  • Page 188: Led Dot Matrix Drive Second Stage Configuration Register High 8 Bits Scan2Wh

    CMS80F761x Reference Manual 21.4.7 Dot Matrix Drive Second Stage Configuration Register High 8 Bits SCAN2WH F763H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCAN2WH SCAN2WH7 SCAN2WH6 SCAN2WH5 SCAN2WH4 SCAN2WH3 SCAN2WH2 SCAN2WH1 SCAN2WH0 Reset value Bit7~Bit0 SCAN2WH<7:0>: LED dot matrix drive mode, the second stage of the light lighting cycle configuration register high 8 bits.

  • Page 189: Led Dot Matrix Drive Cycle Select Register Lednsel (N=0-7)

    CMS80F761x Reference Manual 21.4.10 LED Dot Matrix Drive Cycle Select Register LEDnSEL (n=0-7). Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDnSEL LEDnSEL7 LEDnSEL6 LEDnSEL5 LEDnSEL4 LEDnSEL3 LEDnSEL2 LEDnSEL1 LEDnSEL0 Reset value LED0SEL Address:F750H; LED1SEL Address:F751H; LED2SEL Address:F754H; LED3SEL Address:F755H; LED4SEL Address:F758H;...

  • Page 190: P04-P07 Drive Current Control Register Ledsdrp0H

    CMS80F761x Reference Manual 21.4.12 P04-P07 Drive Current Control Register LEDSDRP0H F711H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSDRP0H DRC3 DRC2 DRC1 DRC0 Reset value Bit7~Bit4 Reserved, must be 0. Bit3~Bit0 DRC<3:0>: Pull current drive select control position (control P04/P05/P06/P07 four ports); 0000= 0mA;...
  • Page 191 CMS80F761x Reference Manual The dot matrix drive function of the LED5 pins is Disable as a GPIO function; The current drive of the LED5 pin is the default. (LEDMODE!=0xAA) Matrix drive mode SEG5 (P11) / software drive P11 pin current drive enable bit;...
  • Page 192 CMS80F761x Reference Manual (LEDMODE==0xAA) dot matrix drive mode LED0 (P00) pin function and current drive enable bit; LED0 pins enabled by dot matrix drive function; The pull current drive of the LED0 pins is configured by the LEDSDRP0L register. The dot matrix drive function of the LED0 pin is Disable as a GPIO function;...

  • Page 193: Led Pin Drive Enable Higher 8 Bits Leden1

    CMS80F761x Reference Manual 21.4.14 LED Pin Drive Enable Higher 8 Bits LEDEN1 F771H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDEN1 LEDEN1_7 LEDEN1_6 LEDEN1_5 LEDEN1_4 LEDEN1_3 LEDEN1_2 LEDEN1_1 LEDEN1_0 Reset value Bit7 LEDEN1_7: (LEDMODE==0xAA); Invalid; Invalid. (LEDMODE!=0xAA) Matrix drive mode SEG15(P23)/software drive P23 pin current drive enable bit;...
  • Page 194 CMS80F761x Reference Manual (LEDMODE!=0xAA) Matrix drive mode SEG10(P16)/software drive P16 pin current drive enable bit; The pull current drive of the P16 pin is configured by the LEDSDRP1H register; The pull current drive of the P16 pin is the default value. Bit1 LEDEN1_1: (LEDMODE==0xAA);...

  • Page 195: Led Dot Matrix Drive Interrupt

    CMS80F761x Reference Manual 21.5 LED Dot Matrix Drive Interrupt 21.5.1 LED Dot Matrix Drive Status Register LEDSTATUS F76AH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LEDSTATUS LEDIE LEDIF Reset value Bit7~Bit2 Reserved, must be 0. Bit1 LEDIE: LED dot matrix drive mode interrupt enable bit; LED dot matrix drive mode interrupt enable;...

  • Page 196: Spi Module

    CMS80F761x Reference Manual 22. SPI Module 22.1 Overview This SPI is a fully configurable SPI master/slave device that allows the user to configure the polarity and phase of the serial clock signal SCLK. The serial clock line (SCLK) is synchronized with the shifting and sampling of information on two independent serial data lines, and the SPI data is sent and received simultaneously.

  • Page 197: Spi Port Configuration

    CMS80F761x Reference Manual 22.2 SPI port configuration Using the SPI function requires configuring the relevant port as an SPI channel and selecting the corresponding port input through the communication input port registers. For example, configure P00, P01, P02, and P03 as SPI communication ports. The configuration code is as follows: PS_SCLK = 0x00;...

  • Page 198: Spi Hardware Description

    CMS80F761x Reference Manual 22.3 SPI hardware description When an SPI transfer occurs, when one data pin moves out of one 8-bit character, the other data pin moves in the other 8-bit character. The 8-bit shift register in the master device and another 8-bit shift register in the slave device are connected as a cyclic 16-bit shift register, and when the transfer occurs, the distributed shift register is shifted by 8 bits, thus effectively swapping the characters of the master slave.

  • Page 199: Spi-Related Registers

    CMS80F761x Reference Manual 22.4 SPI-related Registers 22.4.1 SPI Control Register SPCR 0xEC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCR SPEN SPR2 MSTR CPOL CPHA SPR1 SPR0 Reset value Bit7 Reserved, must be 0. Bit6 SPEN: SPI module enable bit; Enable;...

  • Page 200: Spi Device Select Control Register Sscr

    CMS80F761x Reference Manual 22.4.3 SPI Device Select Control Register SSCR The slave device selection control register SSCR can be read or written at any time and is used to configure which slave selection output should be driven when confirming an SPI host transfer. When the SPI host transfer starts, the contents of the SSCR register are automatically assigned to the NSS pin.

  • Page 201: Spi Master Mode

    CMS80F761x Reference Manual 22.5 SPI Master Mode When SPI is configured for host mode, the transfer is initiated by writing to the SPDR registers. When new bytes are written to the SPDR register, the SPI starts transferring. The serial clock SCLK is generated by the SPI, enabled by the SPI in host mode, and output.

  • Page 202: Write Conflict Error

    CMS80F761x Reference Manual 22.5.1 Write Conflict Error If the SPI data registers are written during the transfer, a write violation occurs. The transfer continues uninterrupted, and the write data that causes the error is not written to the shifter. Write conflicts are indicated by the WCOL flag in the SPSR register.

  • Page 203: Spi Slave Mode

    CMS80F761x Reference Manual 22.6 SPI Slave Mode When configured as an SPI slave device, SPI transmission is initiated by an external SPI host module by using the SPI slave selection input and generates an SCLK serial clock. Before the transfer begins, it is necessary to determine which SPI slave will be used to exchange data. The NSS is used (clear = 0), and the clock signal connected to the SCLK line will transfer the SPI from the slave device to the receiving shift register contents of the MOSI line and drive the MISO line with the contents of the transmitter shift registers.
  • Page 204 CMS80F761x Reference Manual In case the CPHA is cleared, WCOL generation can also be caused by SPDR register writes when either NSS line is cleared, at which point the SPI host can also complete without generating a serial clock SCLK. This is because the transfer start is not explicitly specified, and the NSS is driven low after a full-byte transfer may indicate the start of the next byte transfer.

  • Page 205: Spi Clock Control Logic

    CMS80F761x Reference Manual 22.7 SPI Clock Control Logic 22.7.1 SPI Clock Phase and Polarity Control The software can choose to use either of the four combinations of two control bits (phase and polarity of the serial clock SCLK) in the SPI control register (SPCR). Clock polarity is specified by the CPOL control bit, and the CPOL control bit selection high or low level when the transmission is idle has no significant effect on the transmission format.

  • Page 206: Cpha=1 Transfer Format

    CMS80F761x Reference Manual 22.7.4 CPHA=1 Transfer Format The following figure is a timing diagram of the SPI transmission with CPHA = 1. SCLK shows two waveforms: one for CPOL=0 and one for CPOL=1. Since the SCLK, MISO, and MOSI pins are directly connected between the master and slave, this diagram can be interpreted as a master or slave timing diagram.

  • Page 207: Spi Data Transfer

    CMS80F761x Reference Manual 22.8 SPI Data Transfer 22.8.1 SPI Transfer Starts All SPI transfers are initiated and controlled by the master SPI device. As a slave device, the SPI will consider the transmission starting at the first SCLK edge or the falling edge of the NSS, depending on the CPHA format chosen. When CPHA = 0, the falling edge of the NSS indicates the start of the transmission.

  • Page 208: Spi Timing Diagram

    CMS80F761x Reference Manual 22.9 SPI Timing Diagram 22.9.1 Master Mode Transmission When the clock polarity of the SPI is CPOL=0 and the clock phase CPHA=1, the NSS in SPI master mode is the clK of the system clock after the low level, the MOSI starts to output, and the DATA of the MOSI is output on the rising edge of the SCLK clock.

  • Page 209: Spi Interrupt

    CMS80F761x Reference Manual 22.10 SPI Interrupt The interrupt number of the SPI is 22, where the interrupt vector is 0x00B3. To enable an SPI interrupt, it must set its enable bit SPIIE to 1 and the global interrupt enable bit EA to 1. If the SPI-related interrupt enables are all turned on, the CPU will enter the interrupt service program when the SPI global interrupt indicator bit SPIIF=1.

  • Page 210: Interrupt Priority Control Register Eip2

    CMS80F761x Reference Manual 22.10.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...

  • Page 211: Peripheral Interrupt Flag Bit Register Eif2

    CMS80F761x Reference Manual 22.10.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...

  • Page 212: I2C Module

    CMS80F761x Reference Manual 23. I2C Module 23.1 Overview The module provides an interface between the microcontroller and the I2C bus, as shown in the connection diagram below, and supports arbitration and clock synchronization to allow operation in multi-host systems. I2C supports normal, fast mode. The I2C module has the following characteristics: ◆...

  • Page 213: C Port Configuration

    CMS80F761x Reference Manual 23.2 I C Port Configuration If you use the I2C function, you should first configure the corresponding port as an SCL, SDA channel. For example, configure P00, P01 port as I2C function: PS_SCL = 0x04; Select the P04 port as the SCL pin PS_SDA = 0x05;...

  • Page 214: I 2 C Master Mode Timing Cycle Register

    CMS80F761x Reference Manual 23.3.1 C Master Mode Timing Cycle Register To generate a wide range of SCL frequencies, the module has a built-in 8-bit timer. For standard and fast transfers. TIMER_PRD ≠ 0, the clock period of the SCL: 2* (1+TIMER_PRD)*10* Tsys TIMER_PRD = 0, the clock period of the SCL: 3* 10* Tsys Refer to IIC Application Manual for specific calculation formula of SCL.

  • Page 215: I2C Master Mode Control And Status Registers

    CMS80F761x Reference Manual 23.3.2 I2C Master Mode Control and Status Registers The control registers include 4 bits: RUN, START, STOP, ACK bits. The START bit will produce the START or RESTART START condition. The STOP bit determines whether the data transfer stops at the end of the cycle, or continues. To generate a single transmission cycle, the slave address register writes to the desired address, the R/S bit is set to 0, and the control register writes to ACK=x, STOP=1, START=1, RUN=1 (I2CMCR=xxx0_x111x) to perform the operation and stop.
  • Page 216 CMS80F761x Reference Manual Combination of control bits (IDLE state) STOP START OPERATION START followed by SEND (master remains in send mode) START is followed by SEND and STOP Non response is adopted for receiving after START (master remains in receiver mode) START is followed by REVIVE and STOP START followed by RECOVER (master remains in receiver mode) Combinations are Disable...

  • Page 217: I2C Slave Address Register

    CMS80F761x Reference Manual Master mode status register I2CMSR 0xF5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I2CMSR I2CMIF BUS_BUSY IDLE ARB_LOST DATA_ACK ADD_ACK ERROR BUSY Reset value Bit7 I2CMIF: I2C Master mode interrupt flag bit; In master mode, send/receive completes, or a transmission error occurs. (Software zero, write 0 to clear);...

  • Page 218: I2C Master Mode Transmit And Receive Data Registers

    CMS80F761x Reference Manual 23.3.4 I2C Master Mode Transmit and Receive Data Registers The transmit data register consists of eight data bits that will be sent on the bus on the next send or burst send operation, the first of which is MD7 (MSB). Master mode data cache register I2CMBUF 0xF6 Bit7...

  • Page 219: I2C Slave Mode

    CMS80F761x Reference Manual 23.4 I2C Slave Mode There are five registers for connecting to the target device: self address, control, status, send data, and receive data registers. register address write Read Self address register I2CSADR Self address register I2CSADR 0xF1 Control register I2CSCR Status register I2CSSR 0xF2...

  • Page 220: I2C Slave Mode Transmit And Receive Buffer Registers I2Csbuf

    CMS80F761x Reference Manual The status register consists of three bits: sendfin bit, RREQ bit, TREQ bit. The SENDFIN bit of Send Complete indicates that the MasterI2C controller has completed the receipt of data during a single or continuous I2CS transmit operation. The Receive Request RREQ bit indicates that the I2CS device has receiveda data byte from the I2C master, and the I2CS device should read a data byte from the receiving data register I2CSBUF.

  • Page 221: I2C Interrupt

    CMS80F761x Reference Manual 23.5 I2C Interrupt The interrupt number for I2C is 21, where the interrupt vector is 0x00AB. The Enable I2C interrupt must set its enable bit I2CIE to 1 and the global interrupt enable bit EA to 1. If the I2C-related interrupt enables are turned on,the CPU will enter the interrupt service program when the I2C global interrupt indicator bit I2CIF=1 is turned on.

  • Page 222: Interrupt Priority Control Register Eip2

    CMS80F761x Reference Manual 23.5.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...

  • Page 223: Peripheral Interrupt Flag Bit Register Eif2

    CMS80F761x Reference Manual 23.5.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...

  • Page 224: I2C Slave Mode Transmission Mode

    CMS80F761x Reference Manual 23.6 I2C Slave Mode Transmission Mode All rendered waveforms in this section default I2C to have their own address 0x39 ("00111001"). 23.6.1 Single Receive The following figure shows the sequence of signals received by I2C during a single data session.

  • Page 225: Single Send

    CMS80F761x Reference Manual 23.6.2 Single Send The following figure shows the sequence of signals sent by I2C during a single data session. Single send sequence: Starting conditions; I2C is addressed by the I2C Master as a transmitter; The address is confirmed by I2C; Datais transmitted by I2C;...

  • Page 226: Continuous Reception

    CMS80F761x Reference Manual 23.6.3 Continuous reception The following figure shows the sequence of signals received by I2C during continuous data reception. Continuous receive sequence: Start conditions. I2C is addressed by the I2C Master as a receiver. The address is confirmed by I2C. Data is received by I2C.

  • Page 227: Continuous Sending

    CMS80F761x Reference Manual 23.6.4 Continuous Sending The following figure shows the sequence of signals sent by I2C during continuous data transmission. Consecutive send sequences: Send conditions. I2C is addressed by the I2C Master as a transmitter. The address is confirmed by I2C. The data is sent by I2C.

  • Page 228: Uartn Module

    CMS80F761x Reference Manual 24. UARTn Module 24.1 Overview Universal synchronous asynchronous transceivers (UART0 / UART1 / UART2) provide a flexible method for full-duplex data exchange with external devices. UARTn has two physically separate receive and transmit buffers, SBUFn, which distinguish between operations on a receive buffer or a transmit buffer by reading and writing instructions to SBUFn.

  • Page 229: Uartn Baud Rate

    CMS80F761x Reference Manual 24.3 UARTn Baud Rate UARTn In mode 0, the baud rate is fixed to the twelfth-way frequency of the system clock (Fsys/12); In mode 2, the baud rate is fixed to the system clock's division 32 or 64 (Fsys/32, Fsys/64); In modes 1 and 3, the baud rate is generated by the timer Timer1 or Timer4 or Timer2 or BRT module, and the chip chooses which timer to use as the baud rate clock source is determined by the registers FUNCCR / FUNCCR1.

  • Page 230: Baud Rate Error

    CMS80F761x Reference Manual 3) When BRT is used as a baud rate generator, the baud rate formula: SMODn Fsys×2 BaudRate= BRTCKDIV 32× 65536-{BRTDH,BRTDL} ×2 BRTCKDIV is a BRT timer prescale selection bit, set by the register BRTCON. That is, the value of the BRT at the corresponding baud rate should be set to: {BRTDH,BRTDL} SMODn Fsys×2...
  • Page 231 CMS80F761x Reference Manual 3）SMODn=0，BRTCKDIV=0 baud Fsys=8MHz Fsys=16MHz Fsys=24MHz Fsys=48MHz rate {BRTH, Current {BRTH, Current {BRTH, Current {BRTH, Current BRTL} Rate Error BRTL} Rate Error BRTL} Rate Error BRTL} Rate Error 4800 65484 4808 -0.16 65432 4808 -0.16 65380 4808 -0.16 65224 4808 -0.16...

  • Page 232: Uartn Register

    CMS80F761x Reference Manual 24.4 UARTn Register UARTn has the same functionality as the standard 8051 UART. Its Related Registers are: FUNCCR, FUNCCR1, SBUFn, SCONn, PCON, PCON1, IE, EIE3, IP, EIP3. The UARTn Data Buffer (SBUFn) consists of 2 independent registers: the transmit and receive registers.

  • Page 233: Uartn Buffer Register Sbufn

    CMS80F761x Reference Manual 24.4.3 UARTn Buffer Register SBUFn Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUFn BUFFERn7 BUFFERn6 BUFFERn5 BUFFERn4 BUFFERn3 BUFFERn2 BUFFERn1 BUFFERn0 Reset value BANK0: Register SBUF0 address 0x99; Register SBUF1 address 0xEB. BANK1 : Register SBUF2 address 0xE5. Bit7~Bit0 BUFFERn<7:0>: Buffered data registers.

  • Page 234: Pcon Registers

    CMS80F761x Reference Manual The UARTn schema is as follows: SMn0 SMn1 mode description baud rate Shift register Fsys/12 8-Bit UART Controlled by Timer4/Timer1/Timer2/BRT 9-Bit UART SMODn=0: Fsys/64; SMODn=1: Fsys/32 9-Bit UART Controlled by Timer4/Timer1/Timer2/BRT 24.4.5 PCON Registers 0x87 Bit7 Bit6 Bit5 Bit4 Bit3...

  • Page 235: Uartn Interrupt

    CMS80F761x Reference Manual 24.5 UARTn Interrupt The interrupt number of UART0 is 4, where the interrupt vector is 0x0023. The interrupt number of UART1 is 6, where the interrupt vector is 0x0033. UART2 has an interrupt number of 23, where the interrupt vector is 0x00BB. To enable a UARTn interrupt, it must set its enable bit ESn to 1 and the global interrupt enable bit EA to 1.

  • Page 236: Interrupt Mask Register Eie3

    CMS80F761x Reference Manual 24.5.2 Interrupt Mask Register EIE3 0xAB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIE3 Reset value Bit7~Bit1 Reserved, must be 0. Bit0 ES2: UART2 interrupt enable bits; Allow UART2 interrupts; Disable UART2 interrupt. 24.5.3 Interrupt Priority Controls Register IP 0xB8 Bit7 Bit6...

  • Page 237: Interrupt Priority Control Register Eip3

    CMS80F761x Reference Manual 24.5.4 Interrupt Priority Control Register EIP3 0xBB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP3 PWWDT PTOUCH PLVD PLSE PUART2 Reset value Bit7~Bit6 Reserved, must be 0. Bit5 PWWDT WWDT interrupt priority control bit Set to High-level Interrupt Set to low-level interrupt Bit4 PTOUCH...

  • Page 238: Uartn Mode

    CMS80F761x Reference Manual 24.6 UARTn Mode 24.6.1 Mode 0 - Synchronous Mode Pin RXDn is the input or output and TXDn is the clock output. The TXDn output is a shift clock. The baud rate is fixed at 1/12 of the system clock frequency. 8 bits are transmitted preferentially with LSB. Initialize the receive by setting the flag in SCONN, set to: RIn = 0 and RENn = 1.

  • Page 239: Mode 3-9 Bit Asynchronous Mode (Variable Baud Rate)

    CMS80F761x Reference Manual 24.6.4 Mode 3-9 Bit Asynchronous Mode (Variable Baud Rate) The only difference between mode 2 and mode 3 is that the baud rate in mode 3 is variable. When REN0=1, data reception is enabled. The baud rate is variable and depends on the TIMER1/TIMER2/TIMER4/BRT mode. The Mode 4 timing diagram is shown in the following figure: RXDn TXDn...

  • Page 240: Analog-To-Digital Converter (Adc)

    CMS80F761x Reference Manual 25. Analog-to-digital Converter (ADC) 25.1 Overview An analog-to-digital converter (ADC) converts an analog input signal into a 12-bit binary number representing the signal, as shown in the ADC block diagram below. The port analog input signal and the internal analog signal are connected to the input of the analog-to-digital converter after being multiplexed.

  • Page 241: Adc Configuration

    CMS80F761x Reference Manual 25.2 ADC Configuration When configuring and using an ADC, the following factors must be considered: ⚫ Port configuration. ⚫ Channel selection. ⚫ ADC converts the clock source. ⚫ Interrupt control. ⚫ The format in which the results are stored. 25.2.1 Port Configuration ADC can convert both analog and digital signals.

  • Page 242: Convert The Clock

    CMS80F761x Reference Manual 25.2.4 Convert the Clock The software can set the ADCKS bit of the ADCON1 register to select the clock source for conversion. The time to complete a bit conversion is defined as T ADCK ADC conversion completes 1 update conversion result: 1 full 12-bit conversion requires 32/28 T cycles;...

  • Page 243: The Adc Hardware Trigger Start

    CMS80F761x Reference Manual 25.3 The ADC Hardware Trigger Start In addition to software-triggered ADC conversion, the ADC module provides a way for hardware to trigger start. One is the external port edge triggering method, and the other is the edge or periodic triggering mode of the PWM. Using a hardware trigger ADC requires setting ADCX to 1, even if the ADC function can be triggered externally.

  • Page 244: Adc Results Comparison

    CMS80F761x Reference Manual 25.4 ADC Results Comparison The ADC module provides a set of digital comparators for comparing the results of an ADC with the value size of preloaded {ADCMPH, ADCMPL}. The result of each ADC conversion is compared to the preset value ADCMP, and the result of the comparison is stored in the ADCPO flag bit, which is automatically updated after the conversion is completed.

  • Page 245: A/D Conversion Steps

    CMS80F761x Reference Manual 25.5.4 A/D Conversion Steps The configuration steps for analog-to-digital conversion using an ADC are as follows: Port configuration: ⚫ Disable pin output drivers (see PxTRIS registers); ⚫ Configure the pins as analog input pins. Configure the ADC interrupt (optional): ⚫...

  • Page 246: Related Registers

    CMS80F761x Reference Manual 25.6 Related Registers There are 10 main registers associated with AD conversion, namely: ⚫ AD control registers ADCON0, ADCON1, ADCON2, ADCCHS; ⚫ Comparator control register ADCPC; ⚫ Delay data register ADDLYL; ⚫ AD result data register ADRSH/L; ⚫...

  • Page 247: Ad Control Register Adcon1

    CMS80F761x Reference Manual 25.6.2 AD Control Register ADCON1 0xDE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCON1 ADEN ADCTIMES1 ADCTIMES0 ADCKS3 ADCKS2 ADCKS1 ADCKS0 Reset value Bit7 ADEN: ADC enable bit; Enable ADC; ADC is Disable and does not consume operating current. Bit6 Reserved, must be 0.

  • Page 248: Ad Channel Selection Register Adcchs

    CMS80F761x Reference Manual 25.6.4 AD Channel Selection Register ADCCHS 0xD9 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCCHS CHS5 CHS4 CHS3 CHS2 CHS1 CHS0 Reset value Bit7 Reserved, must be 0. Bit5~Bit0 CHS<5:0>: Analog channel selection bits; 000000= AIN0; 010000= AIN16;...

  • Page 249: Ad Hardware Trigger Delay Data Register Addlyl

    CMS80F761x Reference Manual 25.6.6 AD Hardware Trigger Delay Data Register ADDLYL 0xD3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADDLYL ADDLY7 ADDLY6 ADDLY5 ADDLY4 ADDLY3 ADDLY2 ADDLY1 ADDLY0 Reset value Bit7~Bit0 ADDLY<7:0>: ADC hardware trigger delay data is 8 bits lower. 25.6.7 AD Data Register High ADRESH, ADFM=0 (Left Aligned) 0xDD...

  • Page 250: Ad Comparator Data Register Adccmph

    CMS80F761x Reference Manual 25.6.11 AD Comparator Data Register ADCCMPH 0xD5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCMPH Reset value Bit7~Bit0 ADCMP<11:4>: The ADC comparator data is 8 bits high. 25.6.12 AD Comparator Data rRegister ADCOP 0xD4 Bit7 Bit6 Bit5 Bit4 Bit3...

  • Page 251: Adc Interrupt

    CMS80F761x Reference Manual 25.7 ADC Interrupt The ADC module allows an interrupt to be generated after the analog-to-digital conversion is complete. The ADC interrupt enable bit is the ADCIE bit in the EIE2 register, and the ADC interrupt flag bit is the ADCIF bit in the EIF2 register. The ADCIF bit must be cleared with software, and the ADCIF bit is set to 1 after each conversion, regardless of whether the ADC interrupt is enabled.

  • Page 252: Interrupt Priority Control Register Eip2

    CMS80F761x Reference Manual 25.7.2 Interrupt Priority Control Register EIP2 0xBA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIP2 PSPI PI2C PWDT PADC PPWM PLED Reset value Bit7 PSPI: SPI interrupt priority control bit; Set to High-level Interrupt; Set to low-level interrupt. Bit6 PI2C: I2C interrupt priority control bit;...

  • Page 253: Peripheral Interrupt Flag Bit Register Eif2

    CMS80F761x Reference Manual 25.7.3 Peripheral Interrupt Flag Bit Register EIF2 0xB2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EIF2 SPIIF I2CIF ADCIF PWMIF Reset value Bit7 SPIIF: SPI global interrupt indicator bit, read-only; SPI generates an interrupt, (this bit is automatically cleared after the specific interrupt flag is cleared);...

  • Page 254: Touch Module (Touch)

    CMS80F761x Reference Manual 26. Touch Module (TOUCH) The touch module is an integrated circuit designed to realize the human touch interface, which can replace the mechanical light touch button to achieve waterproof and dustproof, sealed isolation, strong and beautiful operation interface. Technical parameters: ◆...

  • Page 255: Flash Memory

    CMS80F761x Reference Manual 27. Flash Memory 27.1 Overview Flash memory contains program memory (APROM) and nonvolatile data memory (Data FLASH). The maximum memory space of the program is 64KB, divided into 128 sectors, each containing 512B. The maximum data memory space is 1KB, which is divided into 2 sectors, each containing 512B.

  • Page 256: Related Registers

    CMS80F761x Reference Manual 27.2 Related Registers 27.2.1 Flash Protect Lock Register MLOCK 0xFB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MLOCK MLOCK7 MOCK6 MLOCK5 MLOCK4 MLOCK3 MLOCK2 MLOCK1 MLOCK0 Reset value Bit7~Bit0 MLOCK<7:0>: Memory operation enable bit (this register only supports write operations, read is 00H); AAH= Allows memory-dependent R/W/E operation;...

  • Page 257: Program Crc Operation Result Data Register Lower 8-Bit Pcrcdl

    CMS80F761x Reference Manual 27.2.5 Program CRC Operation Result Data Register Lower 8-bit PCRCDL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xF9 PCRCDL PCRCD<7:0> Reset value Bit7~Bit0 PCRCD<7:0> The program CRC operation results 8 bits lower data 27.2.6 Program CRC Operation Result Data Register Higher 8 Bits PCRCDH 0xFA Bit7 Bit6...

  • Page 258: Feature Description

    CMS80F761x Reference Manual 27.3 Feature Description During flash memory read/write/erase operations, the CPU is in a paused state, and when the operation is complete, the CPU continues to run instructions. The operation memory instruction must be followed by 6 NOP instructions, for example: MOV MCTRL,#09H ;...

  • Page 259: Unique Id (Uid)

    CMS80F761x Reference Manual 28. .Unique ID (UID) 28.1 Overview Each chip has a different 96-bit unique identification number, or Unique identification. It has been set at the factory and cannot be modified by the user. 28.2 UID Register Description UID0 F5E0H Bit7 Bit6...
  • Page 260 CMS80F761x Reference Manual UID4 F5E4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID4 UID39 UID38 UID37 UID36 UID35 UID34 UID33 UID32 Reset value Bit7~Bit0 UID<39:32> UID5 F5E5H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID5 UID47 UID46 UID45 UID44 UID43 UID42...
  • Page 261 CMS80F761x Reference Manual UID9 F5E9H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID9 UID79 UID78 UID77 UID76 UID75 UID74 UID73 UID72 Reset value Bit7~Bit0 UID<79:72> UID10（0xF5EA） F5EAH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UID10 UID87 UID86 UID85 UID84 UID83 UID82...

  • Page 262: User Configuration

    CMS80F761x Reference Manual 29. User Configuration The System Configuration Register (CONFIG) is a FLASH option for the initial conditions of the MCU and cannot be accessed or operated by the program. It contains the following: WDT (Watchdog Working Method Selection) ⚫...
  • Page 263 CMS80F761x Reference Manual ⚫ (default). 8MHz 10. EXT_RESET (external reset configuration) ⚫ DISABLE (default) External reset prohibits ⚫ ENABLE External reset enable An external reset is enabled and the internal pull-up resistor ⚫ ENABLE(OPEN PULLUP) of the reset port is turned on 11.

  • Page 264: In-Circuit Programming And Debugging

    CMS80F761x Reference Manual 30. In-circuit Programming and Debugging 30.1 Online Programming Mode The chip can be programmed serially in the end application circuit. Programming can be done simply by the following 4 wires: ⚫ Power cord ⚫ Ground wire ⚫ Data cable ⚫...

  • Page 265: Online Debug Mode

    CMS80F761x Reference Manual 30.2 Online Debug Mode The chip supports 2-wire (DSCK, DSDA) in-circuit debugging. If you use the in-circuit debugging function, you need to set DEBUG in the system configuration register to ENABLE. When using debug mode, you need to be aware of the following points: ◆...

  • Page 266: Instruction Description

    CMS80F761x Reference Manual 31. Instruction Description Assembly instructions consist of a total of 5 categories: arithmetic operations, logical operations, data transfer operations, Boolean operations, and program branch instructions, all of which are compatible with standard 8051. 31.1 Symbol Description Description Symbol Working registers R0-R 7 The cell address (00H-FFH) of the internal data memory RAM or the address in the special function...

  • Page 267: List Of Instructions

    CMS80F761x Reference Manual 31.2 List of Instructions Mnemonics description Operation class A,R n Accumulator plus register A,direct Accumulator plus direct addressing unit A,@Rto Accumulator plus indirectly addressed RAM A,#data The accumulator adds the immediate number ADDC A,Rn Accumulator plus registers and carry flags ADDC A,direct Accumulator plus direct addressing unit and carry signs...
  • Page 268 CMS80F761x Reference Manual Mnemonics description The accumulator is shifted in the left loop The accumulator is even the carry flag for a left loop shift The accumulator is shifted in the right loop RR RC A The accumulator is connected to the carry mark right loop shift SWAP The accumulator is swapped 4 bits high and 4 bits low Data transfer class...
  • Page 269 CMS80F761x Reference Manual Mnemonics description ACALL add r11 Absolute invocation within the 2K address range LCALL addr16 Long calls within 64K address range RAND Subroutine returns RETI Interrupt returns AJMP addr11 Absolute transfer within 2K address range LJMP add r16 Long transfer within 64K address range SJMP randl...

  • Page 270: Version Revision Notes

    CMS80F761x Reference Manual 32. Version Revision Notes Revision Date Modify content V1.00 Aug 2020 Initial release V1.0.1 Feb 2023 Modified the description of software clearing operations in 6.4.4 Added some remarks to section 27.2.7 V1.0.2 July 2023 Added the step "Clear the CRC end address select bit" to the function description in section 27.3 V1.0.3 Dec 2023...

Table of Contents