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Cmsemicon SC8F577 Series User Manual

Enhanced 8-bit cmos microcontroller with flash memory
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SC8F577x User Manual
Enhanced 8-bit CMOS Microcontroller with Flash Memory
Rev. 1.8
Please be reminded about following CMS's policies on intellectual property
＊Cmsemicron Limited (denoted as 'our company' for later use) has already applied for relative patents and entitled legal rights.
Any patents related to CMS's MCU or other products is not authorized to use. Any individual, organization or company which
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＊ The name of Cmsemicron Limited and logo are both trademarks of our company
* Our company preserve the rights to further elaborate on the improvements about product functions, reliability and design in
this manual. However, our company is not responsible for any usage about this manual. The applications and their purposes in
this manual are just for clarification, our company does not guarantee that these applications are feasible without further
improvements and changes, and does not recommend any usage of the products in areas where people's safety is endangered
during accident. Our company's products are not authorized to be used for life-saving or life support devices and systems. our
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  • Page 1 SC8F577x User Manual Enhanced 8-bit CMOS Microcontroller with Flash Memory Rev. 1.8 Please be reminded about following CMS’s policies on intellectual property ＊Cmsemicron Limited (denoted as ‘our company’ for later use) has already applied for relative patents and entitled legal rights. Any patents related to CMS’s MCU or other products is not authorized to use.
  • Page 2 SC8F577x Manual 1. PRODUCT DESCRIPTION ....................8 ..................................8 EATURES ............................9 YSTEM TRUCTURE IAGRAM ................................10 LLOCATION 1.3.1 SC8F5771 ................................10 1.3.2 SC8F5773 ................................10 1.3.3 SC8F5775 ................................11 1.3.4 SC8F5776 ................................12 ..........................14 YSTEM ONFIGURATION EGISTER ............................. 16 NLINE ERIAL ROGRAMMING...
  • Page 3 SC8F577x ............................40 WAKEN FROM LEEP ..............................41 NTERRUPT WAKENING ............................41 LEEP PPLICATION ............................42 LEEP WAKEN 6. I/O PORT ........................... 43 I/O S ................................43 UMMARY PORTA ..................................46 6.2.1 PORTA Data and Direction Control ........................46 6.2.2 PORTA Analog Control Selection ..........................
  • Page 4 SC8F577x TIMER2 ............................73 RELATED REGISTER 10. ANALOG TO DIGITAL CONVERSION (ADC) ..............74 10.1 ................................74 GENERAL 10.2 ..............................75 CONFIGURATION 10.2.1 Port configuration ..............................75 10.2.2 Channel selection ..............................75 10.2.3 ADC internal base voltage ............................ 75 10.2.4 ADC reference voltage ............................75 10.2.5 Converter clock ..............................
  • Page 5 SC8F577x 15.1 PGA ............................. 100 HE BLOCK DIAGRAM OF 15.2 PGA ..........................101 ELATED EGISTER OF 15.3 PGA ........................... 101 PERATION FLOW OF 16. UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS TRANSMITTER (USART) ..... 102 16.1 USART A ..........................104 SYNCHRONOUS 16.1.1 USART Asynchronous Generator ........................104 Enable Transmit .............................
  • Page 6 SC8F577x 18. IIC MODE ........................128 18.1 IIC M ..............................128 ENERAL 18.2 IIC R .............................. 129 ELATED EGISTER 18.3 ............................132 ASTER ONTROL 18.3.1 I C Master Control Mode Support ........................132 18.3.1.1 C Master Control Mode Operation......................133 18.3.2 Baud Rate Generator ............................
  • Page 7 SC8F577x 21.6 ........................157 ONSTANT URRENT OURCE EATURE 21.7 LVR F ................................157 EATURE 21.8 AC F ................................157 EATURE 22. INSTRUCTIONS ......................158 22.1 ..............................158 NSTRUCTIONS ABLE 22.2 ............................160 NSTRUCTIONS LLUSTRATION 23. PACKAGING ........................175 23.1 MSOP10 .................................. 175 23.2 DFN10 ..................................

  • Page 8: Product Description

    SC8F577x 1. Product Description Features ◆ Memory ◆ Working voltage: 1.8V~4.5V@16MHz ROM: 4Kx16bit Working temperature: -20℃~75℃ ◆ Internal RC: design frequency of 8MHz/16MHz Universal RAM: 256x8bit ◆ 8 level stack buffer ◆ Built-in 128-byte EEPROM ◆ Clean instructions (66 instructions) ◆...
  • Page 9 SC8F577x System Structure Diagram AD Converter 4096×16 256×8 Program Memory Data Memory TIMER0 Stack1 TIMER2 I/O PORT Addr Mux Stack8 PWM0-4 Instruction Reg Fsr Reg Pro EE Pro EE Instruction Decode USART Device Reset Timer and Control Power-on Reset Watch Dog Timer Timing Generation COMP VDD,GND...

  • Page 10: Pin Allocation

    SC8F577x Pin Allocation 1.3.1 SC8F5771 SDA/OSCIN/ICSPDAT/PWMD0/AN15/RB0 RA0/AN0/PGA/PWMA0/[INT]/PWMB0/SDA/CCO SC8F5771 SCL/OSCOUT/ICSPCLK/PWMB4/PWMD1/AN14/RB1 RA1/AN1/PWMA1/PWMB1/SCL MSOP10 DFN10 PWMB3/PWMD4/AN13/RB2 RA2/AN2/PWMA2/PWMB2 T0CKI/PWMD2/AN12/RB3 RA3/AN3/PWMA3 1.3.2 SC8F5773 SDA/OSCIN/ICSPDAT/PWMD0/AN15/RB0 RA0/AN0/TK0/PGA/PWMA0/[INT]/PWMB0/SDA/CCO SCL/OSCOUT/ICSPCLK/PWMB4/PWMD1/AN14/RB1 RA1/AN1/TK1/PWMA1/PWMB1/SCL MISO/PWMB3/PWMD4/AN13/RB2 RA2/AN2/TK2/PWMA2/PWMB2 SC8F5773 T0CKI/MOSI/TX/CK/PWMD2/AN12/RB3 RA3/AN3/TK3/PWMA3 TSSOP20 SCK/RX/DT/PWMD3/PWMC4/AN11/RB4 RA4/AN4/TK4/PWMA4 SS/PWMC3/AN10/RB5 RA5/AN5/TK5/PWMC0/[INT]/TX/CK CAP/PWMC2/AN9/RB6 RA6/AN6/TK6/PWMC1/RX/DT AN8/RB7 RA7/AN7/TK7 AN16/RC0 RC1/AN17 www.mcu.com.cn 10 / 181 V1.8...
  • Page 11 SC8F577x 1.3.3 SC8F5775 20 19 18 17 16 RA1/AN1/PWMA1/PWMB1/SCL SDA/OSCIN/ICSPDAT/PWMD0/AN15/RB0 RA2/AN2/PWMA2/PWMB2 SC8F5775 RA3/AN3/PWMA3 SCL/OSCOUT/ICSPCLK/PWMB4/PWMD1/AN14/RB1 QFN20 3*3 MISO/PWMB3/PWMD4/AN13/RB2 RA4/AN4/PWMA4 T0CKI/MOSI/TX/CK/PWMD2/AN12/RB3 RA5/AN5/PWMC0/[INT]/TX/CK 9 10 www.mcu.com.cn 11 / 181 V1.8...
  • Page 12 SC8F577x 1.3.4 SC8F5776 24 23 22 21 20 RA1/AN1/PWMA1/PWMB1/SCL RA2/AN2/PWMA2/PWMB2 SDA/OSCIN/ICSPDAT/PWMD0/AN15/RB0 SC8F5776 RA3/AN3/PWMA3 SCL/OSCOUT/ICSPCLK/PWMB4/PWMD1/AN14/RB1 QFN24 4*4 MISO/PWMB3/PWMD4/AN13/RB2 RA4/AN4/PWMA4 T0CKI/MOSI/TX/CK/PWMD2/AN12/RB3 RA5/AN5/PWMC0/[INT]/TX/CK SCK/RX/DT/PWMD3/PWMC4/AN11/RB4 RA6/AN6/PWMC1/RX/DT 10 11 SDA/OSCIN/ICSPDAT/PWMD0/AN15/RB0 RC3/RST SCL/OSCOUT/ICSPCLK/PWMB4/PWMD1/AN14/RB1 MISO/PWMB3/PWMD4/AN13/RB2 T0CKI/MOSI/TX/CK/PWMD2/AN12/RB3 RA0/AN0/TK0/PGA/PWMA0/[INT]/PWMB0/SDA/CCO SCK/RX/DT/PWMD3/PWMC4/AN11/RB4 SC8F5776 PGA_GND SSOP24 SS/PWMC3/AN10/RB5 RA1/AN1/TK1/PWMA1/PWMB1/SCL CAP/PWMC2/AN9/RB6 RA2/AN2/TK2/PWMA2/PWMB2 AN8/RB7 RA3/AN3/TK3/PWMA3 AN16/RC0 RA4/AN4/TK4/PWMA4 AN17/RC1...
  • Page 13 SC8F577x Pin description: Pin name IO type description VDD, GND Voltage input pin and ground OSCIN/OSCOUT 32.768KHz crystal oscillator input/output pin Programmable in/push-pull out pin, with pull-up resistance, pull-down resistance, RA0-RA7 electrical level interrupt function Programmable in/push-pull out pin, with pull-up resistance, pull-down resistance, RB0-RB7 electrical level interrupt function Programmable in/push-pull out pin, with pull-up resistance, pull-down resistance,...

  • Page 14: System Configuration Register

    SC8F577x System Configuration Register System configuration register (CONFIG)is the initial ROM choice of the MCU. It can only be burned by SC burner. User cannot visit. It includes the following: OSC (choice of oscillation) ◆ INTRC8M choose internal 8MHz RC oscillation ◆...
  • Page 15 SC8F577x ◆ 9pF ◆ 12pF 13. ICSPPORT _SEL (simulation port selection) ◆ ICSP ICSPCLK, DAT port keep as simulation port, all functions disabled ◆ NORMAL ICSPCLK, DAT port as normal port www.mcu.com.cn 15 / 181 V1.8...
  • Page 16 SC8F577x Online Serial Programming Can perform serial programming on MCU the final application circuit. Programming is done through the following: Power wire ⚫ ⚫ Ground wire ⚫ Data wire ⚫ Clock wire This ensures users to use un-programmed devices to make circuit and only program the MCU just before the product being delivered.

  • Page 17: Central Processing Unit (Cpu)

    SC8F577x 2. Central Processing Unit (CPU) Memory Program Memory 2.1.1 program memory space FLASH:4K Reset Vector 000H Program start, jump to user program 001H 002H 003H Interrupt vector 004H Interrupt entry, user interrupt program User program area FFDH FFEH FFFH Jump to Reset Vector 000H End of program Reset Vector (0000H)
  • Page 18 SC8F577x Interrupt Vector 2.1.1.2 The address for interrupt vector is 0004H. Once the interrupt responds, the current value for program counter PC will be saved to stack buffer and jump to 0004H to execute interrupt service program. All interrupt will enter 0004H. User will determine which interrupt to execute according to the bit of register of interrupt flag bit.
  • Page 19 SC8F577x Jump Table 2.1.1.3 Jump table can achieve multi-address jump feature. Since the addition of PCL and ACC is the new value of PCL, multi-address jump is then achieved through adding different value of ACC to PCL. If the value of ACC is n, then PCL+ACC represent the current address plus n.

  • Page 20: Data Memory

    SC8F577x 2.1.2 Data Memory List of data memory address address address address INDF INDF INDF 100H INDF 180H TMR0 OPTION_REG ---- 101H ---- 181H 102H 182H STATUS STATUS STATUS 103H STATUS 183H 104H 184H PORTA TRISA ---- 105H ---- 185H PORTB TRISB ----...
  • Page 21 SC8F577x Summary of special registers in Bank0 Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value INDF Look-up for this unit will use FSR, not physical register. xxxxxxxx TMR0 TIMER0 data register xxxxxxxx Lower bit of program counter 00000000 STATUS 00011xxx...
  • Page 22 SC8F577x Summary of special registers in Bank1 Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value INDF Look-up for this unit will use FSR, not physical register. xxxxxxxx OPTION_REG ---- INTEDG T0CS T0SE -1111011 Lower bit of program counter 00000000 STATUS 00011xxx...
  • Page 23 SC8F577x Summary of special registers in Bank2 address name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value 100H INDF Look-up for this unit will use FSR , not physical register. xxxxxxxx 102H Lower bit of program counter (PC) 00000000 103H STATUS...
  • Page 24 SC8F577x Summary of special registers in Bank3 Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset value 180H INDF Look-up for this unit will use FSR , not physical register. xxxxxxxx 182H Lower bit of program counter (PC) 00000000 183H STATUS...

  • Page 25: Immediate Addressing

    SC8F577x Addressing Mode 2.2.1 Direct Addressing Operate on RAM through accumulator (ACC) Example: pass the value in ACC to 30H register 30H, A Example: pass the value in 30H register to ACC A, 30H 2.2.2 Immediate Addressing Pass the immediate value to accumulator (ACC). Example: pass immediate value 12H to ACC LDIA 2.2.3 Indirect Addressing...
  • Page 26 SC8F577x Stack Stack buffer of the chip has 8 levels. Stack buffer is not part of data memory nor program memory. It cannot be written nor read. Operation on stack buffer is through stack pointers, which also cannot be written nor read.

  • Page 27: Accumulator (Acc)

    SC8F577x Accumulator (ACC) 2.4.1 General ALU is the 8-bit arithmetic-logic unit. All math and logic related calculations in MCU are done by ALU. It can perform addition, subtraction, shift and logical calculation on data; ALU can also control STATUS to represent the status of the product of the calculation.

  • Page 28: Reset Status

    SC8F577x Program Status Register (STATUS) STATUS register includes: ◆ status of ALU. ◆ Reset status. ◆ Selection bit of Data memory (GPR and SFR) Just like other registers, STATUS register can be the target register of any other instruction. If an instruction that affects Z, DC or C bit that use STATUS as target register, then it cannot write on these 3 status bits.
  • Page 29 SC8F577x TO and PD bit can reflect the reason for reset of chip. The following is the events which affects the TO and PD and the status of TO and PD after these events. events Reset reason Power on WDT overflow awaken MCU WDT overflow WDT overflow non-sleep status STOP instructions...
  • Page 30 SC8F577x Pre-scaler (OPTION_REG) OPTION_REG register can be read or written. Each control bit for configuration is as follow: ◆ TIMER0/WDT pre-scaler ◆ TIMER0 pre-scaler OPTION_REG (81H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 OPTION_REG INTEDG T0CS T0SE Read/write Reset value Bit7 Not used Bit6...
  • Page 31 SC8F577x Whether TIMER0 or WDT uses pre-scaler is full controlled by software. This can be changed dynamically. To avoid unintended chip reset, when switch from TIMER0 to WDT, the following instructions should be executed. ; Disable enable bit for interrupt to avoid CLRB INTCON, GIE entering interrupt during the following time...

  • Page 32: Program Counter (Pc)

    SC8F577x Program Counter (PC) program counter (PC)controls the instruction sequence in program memory FLASH, it can address in the whole range of FLASH. After obtaining instruction code, PC will increase by 1 and point to the address of the next instruction code. When executing jump, passing value to PCL, sub-program, initializing reset, interrupt, interrupt return, sub-program returns and other actions, PC will load the address which is related to the instruction, rather than the address of the next instruction.

  • Page 33: Watchdog Timer (Wdt)

    SC8F577x Watchdog Timer (WDT) Watchdog timer is a self-oscillated RC oscillation timer. There is no need for any external devices. Even the main clock of the chip stops working, WDT can still function/ WDT overflow will cause reset. 2.8.1 WDT Period WDT and TIMER0 share 8-bit pre-scaler.

  • Page 34: System Clock

    SC8F577x 3. System Clock General When clock signals input from OSCIN pin (or generated by internal oscillation), 4 non-overlapping orthogonal clock signals called Q1、Q2、Q3、Q4 are produced. Inside IC , each Q1 makes program counter (PC)increase 1, Q4 obtain this instruction from program memory unit and lock it inside instructions register. Compile and execute the instruction obtained between next Q1 and Q4, which means that 4 clock period for 1 executed instruction.
  • Page 35 SC8F577x Following is the relationship between working frequency of system and the speed of instructions: Double instruction period Single instruction period System frequency ( 1MHz 8μs 4μs 2MHz 4μs 2μs 4MHz 2μs 1μs 8MHz 1μs 500ns www.mcu.com.cn 35 / 181 V1.8...

  • Page 36: Reset Time

    SC8F577x System Oscillator Chip integrated with 8MHz/16MHz internal RC oscillation. 3.2.1 Internal RC Oscillation Default oscillation is internal RC oscillation. Its frequency is 8MHz or 16MHz, which is set by OSCCON register. Reset Time Reset Time is the time for chip to change from reset to stable oscillation. The value is about 18ms. Note: Reset time exists for both power on reset and other resets.

  • Page 37: Power-On Reset

    SC8F577x 4. Reset Chip has 3 ways of reset: ◆ Power on reset; ◆ Low voltage reset; ◆ Watchdog overflow reset under normal working condition. When any reset happens, all system registers reset to default condition, program stops executing and PC is cleared.
  • Page 38 SC8F577x Power off Reset 4.3.1 General Power off reset is used for voltage drop caused by external factors (such as interference or change in external load). Voltage drop may enter system dead zone. System dead zone means power source cannot satisfy the minimal working voltage of the system.

  • Page 39: Watchdog Timer

    SC8F577x 4.3.2 Improvements for Power off Reset Suggestions to improve the power off reset: ◆ Choose higher LVR voltage; ◆ Turn on watchdog timer; ◆ Lower working frequency of the system; ◆ Increase the gradient of the voltage drop. Watchdog timer Watchdog timer is used to make sure the program is run normally.

  • Page 40: Enter Sleep Mode

    SC8F577x 5. Sleep Mode Enter Sleep Mode System can enter sleep mode when executing STOP instructions. If WDT enabled, then: ◆ WDT is cleared and continue to run. ◆ PD bit in STATUS register is cleared. ◆ TO bit set to 1. ◆...
  • Page 41 SC8F577x Interrupt Awakening When forbidden overall interrupt ( GIE clear), and there exist 1 interrupt source with its interrupt enable bit and indication bit set to 1, one event from the following will happen: If interrupt happens before STOP instructions, then STOP instruction is executed as NOP instructions. Hence, WDT and its pre-scaler and post-scaler will not be cleared, and TO bit will not be set to 1, PD will not be cleared to 0.
  • Page 42 SC8F577x Sleep Mode Awaken Time When MCU is awaken from sleep mode, oscillation reset time is needed. This time is 1032* T clock period under internal high speed oscillation mode, 15 * T clock period under low speed oscillation mode. System main clock source System clock frequency (IRCF<2:0>) WAIT...
  • Page 43 SC8F577x 6. I/O Port I/O Summary Chip has 3 I/O port: PORTA、PORTB、PORTC (max. of 18 I/O).read/write port data register can directly read/write these ports. Port Pin Description Schmitt trigger input, push-pull output, AN0, PWM, PGA positive input, SDA Schmitt trigger input, push-pull output, AN1, PWM, SCL Schmitt trigger input, push-pull output, AN2, PWM Schmitt trigger input, push-pull output, AN3, PWM PORTA...
  • Page 44 SC8F577x （1） Analog Data Bus input mode Weak Write pull-up WPUA Read WPUA Write PORTA I/O pin Write TRISA （1） Analog input mode Read TRISA Read PORTA Write IOCA Read IOCA Interrupt- on-change Read PORTA Write WPDA To A/D converter Fig 6-1: I/O port structure (1) www.mcu.com.cn 44 / 181...
  • Page 45 SC8F577x （1） Analog Data Bus input mode Weak Write pull-up WPUB Read WPUB Write PORTB I/O pin Write TRISB （1） Analog input mode Read TRISB Read PORTB Write IOCB Read IOCB Interrupt- on-change Read PORTB Write WPDB To A/D converter Fig 6-2: I/O port structure (2) www.mcu.com.cn 45 / 181...
  • Page 46 SC8F577x PORTA 6.2.1 PORTA Data and Direction Control PORTA is 8 Bit bi-directional port. Its corresponding data direction register is TRISA. Setting 1 bit of TRISA to be 1 can configure the corresponding pin to be input. Setting 1 bit of TRISA to be 0 can configure the corresponding pin to be output.
  • Page 47 SC8F577x PORTA Analog Control Selection 6.2.2 The ANSEL0 register is used to configure the input mode of I/O pin to analog mode. Setting the appropriate bit in ANSEL0 to 1 will cause all digital read operations of the corresponding pin to return to 0 and make the analog function of the pin work normally.
  • Page 48 SC8F577x 6.2.4 PORTA Pull Down Resistance Each PORTA pin has an internal weak pull down that can be individually configured. The control bits WPDA<7:0> enable or disable each weak pull down. PORTA pull down resistance register WPDA (97H) Bit7 Bit6 Bit5 Bit4 Bit3...
  • Page 49 SC8F577x PORTA 电平变化中断寄存器 IOCA(95H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IOCA IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 Reset value Bit7~Bit0 IOCA<7:0> Control bit of level change interrupt of PORTA enable level change interrupt disable level change interrupt www.mcu.com.cn 49 / 181 V1.8...
  • Page 50 SC8F577x PORTB 6.3.1 PORTB Data and Direction PORTB is an 8Bit wide bi-directional port. The corresponding data direction register is TRISB. Set a bit in TRISB to 1 (=1) to make the corresponding PORTB pin as the input pin. Clearing a bit in TRISB (=0) will make the corresponding PORTB pin as the output pin.
  • Page 51 SC8F577x 6.3.2 PORTB Analog Selection Control The ANSEL1 register is used to configure the input mode of I/O pin to analog mode. Setting the appropriate bit in ANSEL1 to 1 will cause all digital read operations of the corresponding pin to return to 0 and make the analog function of the pin work normally.
  • Page 52 SC8F577x 6.3.4 PORTB Pull up Resistance Each PORTB pin has an internal weak pull up that can be individually configured. The control bits WPUB<7:0> enable or disable each weak pull up. PORTB pull up resistance register WPUB (08H) Bit7 Bit6 Bit5 Bit4 Bit3...
  • Page 53 SC8F577x PORTB level change interrupt register IOCB (09H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 Reset value Bit7~Bit0 IOCB<7:0> Control bit of level change interrupt of PORTB enable level change interrupt disable level change interrupt www.mcu.com.cn 53 / 181...
  • Page 54 SC8F577x PORTC 6.4.1 PORTC Data and Direction PORTC is a 2-bit wide bidirectional port. The corresponding data direction register is TRISC. Set a certain position in TRISC to 1 (=1) to make the corresponding PORTC pin as the input pin. Clearing a bit in TRISC (=0) will make the corresponding PORTC pin as the output pin.
  • Page 55 SC8F577x 6.4.2 PORTC Analog Control Selection The ANSEL2 register is used to configure the input mode of I/O pin to analog mode. Setting the appropriate bit in ANSEL2 to 1 will cause all digital read operations of the corresponding pin to return to 0 and make the analog function of the pin work normally.
  • Page 56 SC8F577x 6.4.4 PORTC Pull up Resistance Each PORTC pin has an internal weak pull up that can be individually configured. The control bits WPUC<3:0> enable or disable each weak pull up. PORTC pull up resistance register WPUC (99H) Bit7 Bit6 Bit5 Bit4 Bit3...
  • Page 57 SC8F577x PORTC level change interrupt register IOCC (94H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ---- ---- ---- ---- IOCC IOCB3 IOCB2 IOCC1 IOCC0 ---- ---- ---- ---- Reset ---- ---- ---- ---- value Bit7~Bi4 Not used Bit3~Bit0 IOCC<3:0> Control bit of level change interrupt of PORTC enable level change interrupt disable level change interrupt...
  • Page 58 SC8F577x I/O Usage 6.5.1 Write I/O Port The chip's I/O port register, like the general universal register, can be written through data transmission instructions, bit manipulation instructions, etc. Example: write I/O port program PORTA, A ;pass value of ACC to PORTA CLRB PORTB, 1 ;clear PORTB.1...
  • Page 59 SC8F577x Precautions for I/O Port Usage When operating the I/O port, pay attention to the following aspects: When I/O is converted from output to input, it is necessary to wait for several instruction periods for the I/O port to stabilize. If the internal pull up resistor is used, when the I/O is converted from output to input, the stable time of the internal level is related to the capacitance connected to the I/O port.
  • Page 60 SC8F577x 7. Interrupt Interrupt General The chip has the following interrupt source: ◆ ◆ A/D interrupt TIMER0 overflow interrupt ◆ ◆ PWM interrupt TIMER2 match interrupt ◆ ◆ INT interrupt PORTA level change interrupt ◆ ◆ USART receive/transmit interrupt PORTB level change interrupt ◆...

  • Page 61: Interrupt Control Register

    SC8F577x Interrupt control Register 7.2.1 Interrupt Control Register The interrupt control register INTCON is a readable and writable register, including the allowable and flag bits for TMR0 register overflow and PORTB port level change interrupt. When an interrupt condition occurs, regardless of the state of the corresponding interrupt enable bit or the global enable bit GIE (in the INTCON register), the interrupt flag bit will be set to 1.
  • Page 62 SC8F577x 7.2.2 Peripherals Interrupt Enable Register The peripherals interrupt enable register has PIE1 and PIE2. Before allowing any peripherals interrupt, the PEIE bit of the INTCON register must be set to 1. Peripherals interrupt enable register PIE1 (0DH) Bit7 Bit6 Bit5 Bit4 Bit3...
  • Page 63 SC8F577x Peripherals interrupt enable registerPIE2 (108H) 108H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIE2 TKIE COMPIE IICIE BCLIE RCCIE RACIE LVDIE Reset value Not used. Bit7 TKIE: Touch button detection over interrupt enable bit Bit6 enable touch button detection over interrupt disable touch button detection over interrupt COMPIE:.
  • Page 64 SC8F577x 7.2.3 Peripherals Interrupt Request Register The peripherals interrupt request register is PIR1 and PIR2. When an interrupt condition occurs, regardless of the state of the corresponding interrupt enable bit or the global enable bit GIE, the interrupt flag bit will be set to 1. The user software should ensure that the interrupt is set before allowing an interrupt. The corresponding interrupt flag bit is cleared.
  • Page 65 SC8F577x Peripherals interrupt request registerPIR2 (107H) 107H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIR2 TKIF COMPIF IICIF BCLIF RCCIF RACIF LVDIF Reset value Not used. Bit7 TKIF: Touch button detection over interrupt flag bit Bit6 Touch button detection over interrupt happens (must clear through software)； Touch button detection over interrupt not happen.
  • Page 66 SC8F577x Protection Methods for Interrupt After an interrupt request occurs and is responded, the program goes to 0004H to execute the interrupt sub-routine. Before responding to the interrupt, the contents of ACC and STATUS must be saved. The chip does not provide dedicated stack saving and unstack recovery instructions, and the user needs to protect ACC and STATUS by himself to avoid possible program operation errors after the interrupt ends.
  • Page 67 SC8F577x 8. TIMER0 TIMER0 General TIMER0 is composed of the following functions: ▪ 8-bit timer/counter register (TMR0); ▪ 8-bit pre-scaler (shared with watchdog timer); ▪ Programmable internal or external clock source; ▪ Programmable external clock edge selection; overflow interrupt. ▪ Fsys/4 Data Bus Synchron...

  • Page 68: 8-Bit Timer Mode

    SC8F577x Working Principle for TIMER0 The TIMER0 mod can be used as an 8-bit timer or an 8-bit counter. 8.2.1 8-bit Timer Mode When used as a timer, the TIMER0 mod will be incremented every instruction period (without pre-scaler). The timer mode can be selected by clearing the T0CS bit of the OPTION_REG register to 0. If a write operation is performed to the TMR0 register, the next two Each instruction period will be prohibited from incrementing.
  • Page 69 SC8F577x 8.2.4 Switch Prescaler Between TIMER0 and WDT Module After assigning the pre-scaler to TIMER0 or WDT, an unintentional device reset may occur when switching the prescaler. To change the pre-scaler from TIMER0 to WDT mod, the following instructions must be executed sequence.
  • Page 70 SC8F577x TIMER0 Related Register There are two registers related to TIMER0, 8-bit timer/counter (TMR0), and 8-bit programmable control register (OPTION_REG). TMR0 is an 8-bit readable and writable timer/counter, OPTION_REG is an 8-bit write-only register, the user can change the value of OPTION_REG to change the working mode of TIMER0, etc. Please refer to the application of 0 prescaler register (OPTION_REG).
  • Page 71 SC8F577x 9. TIMER2 TIMER2 General TIMER2 mod is an 8-bit timer/counter with the following characteristics: ◆ 8-bit timer register (TMR2); ◆ 8-bit period register (PR2); ◆ Interrupt when TMR2 matches PR2; ◆ Software programmable prescaler ratio (1:1, 1:4 and 1:16); ◆...
  • Page 72 SC8F577x Working Principle of TIMER2 The input clock of the TIMER2 mod is the system instruction clock (F ) or the external oscillator (32.768kHz). The clock is input to the TIMER2 pre-scaler. There are several division ratios to choose from: 1:1, 1:4 or 1:16.
  • Page 73 SC8F577x TIMER2 related register There are 2 registers related to TIMER2, namely data memory TMR2 and control register T2CON. TIMER2 data register TMR2 (11H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR2 Reset value TIMER2 control register T2CON (12H) Bit7 Bit6 Bit5...
  • Page 74 SC8F577x 10. Analog to Digital Conversion (ADC) 10.1 ADC general The analog-to-digital converter (ADC) can convert the analog input signal into a 12-bit binary number that represents the signal. The analog input channels used by the device share a sample and hold circuit. The output of the sample and hold circuit is connected to the input of the analog to digital converter.

  • Page 75: Adc Configuration

    SC8F577x 10.2 ADC configuration When configuring and using ADC, the following factors must be considered: ◆ Port configuration; ◆ Reference voltage selection; ◆ Channel selection; ◆ ADC conversion clock source; ◆ Interrupt control; ◆ The storage format of the result. 10.2.1 Port configuration ADC can convert both analog signal and digital signal.
  • Page 76 SC8F577x 10.2.5 Converter clock The ADCS bit of the ADCON0 and ADCON1 register can be set by software to select the clock source for conversion. There are 7 possible clock frequencies to choose from: ◆ F ◆ F ◆ F ◆...

  • Page 77: Adc Interrupt

    SC8F577x 10.2.6 ADC Interrupt ADC mod allows an interrupt to be generated after the completion of the analog-to-digital conversion. The ADC interrupt flag bit is the ADIF bit in PIR1 register. The ADC interrupt enable bit is the ADIE bit in PIE1 register.
  • Page 78 SC8F577x 10.3 ADC working principle 10.3.1 Start conversion To enable ADC mod, you must set the ADON bit of the ADCON0 register to 1, and set the GO/ DONE ̅̅̅̅̅̅̅̅̅ bit of the ADCON0 register to 1 to start analog-to-digital conversion. ̅̅̅̅̅̅̅̅̅...

  • Page 79: A/D Conversion Procedure

    SC8F577x 10.3.5 A/D conversion procedure The following steps give an example of using ADC for analog-to-digital conversion: 1. port configuration: ⚫ Disable pin output driver (see TRIS register); ⚫ Configure pin as analog input pin. 2. configuration ADC mod: ⚫ Select ADC reference voltage (AD conversion must be wait for up to 100us if the reference voltage switches from VDD to internal LDO);...
  • Page 80 SC8F577x 10.4 ADC Related Register There are mainly 4 registers related to AD conversion, namely control register ADCON0 and ADCON1, data register ADRESH and ADRESL. AD control register ADCON0 (9DH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ̅̅̅̅̅̅̅̅̅ ADCON0 ADCS1 ADCS0 CHS3...
  • Page 81 SC8F577x AD data register high bit ADCON1 (9CH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LDO_SEL LDO_SEL ADCON1 ADFM CHS4 ADCS2 LDO_EN Read/write Reset value Bit7 ADFM: A/D conversion result format selection bit Right alignment left alignment Bit6 CHS4: Combine with CHS<3:0>...
  • Page 82 SC8F577x AD data register high bit ADRESH (9EH), ADFM=1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRESH ---- ---- ---- ---- ---- ---- ADRES11 ADRES10 read/write ---- ---- ---- ---- ---- ---- Reset ---- ---- ---- ---- ---- ---- value Bit7~Bit2 Not used.

  • Page 83: Pin Configuration

    SC8F577x 11. PWM Mod A programmable PWM module with 10-bit width in chip, which can be configured as 4 channels of common period, independent duty cycle output and 1 channel of independent output, or 2 pairs of complementary outputs and 1 channel of independent output. The PWM output can be selected as RA1-RA5 or RA5-RA7、RB5、RB4 or RB0-RB4 through config.
  • Page 84 SC8F577x PWM control register PWMCON1 (14H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMIO_SEL[1:0] PWM2DTEN PWM0DTEN DT_DIV[1:0] PWMCON1 Reset value Bit7~6 PWMIO_SEL[1:0]: PWM IO selection PWM assigned to group A, PWM0-RA0, PWM1-RA1, PWM2-RA2, PWM3-RA3, PWM4- PWM assigned to group B, PWM0-RA0, PWM1-RA1, PWM2-RA2, PWM3-RB2, PWM4- PWM assigned to group C, PWM0-RA5, PWM1-RA6, PWM2-RB6, PWM3-RB5, PWM4- PWM assigned to group D, PWM0-RB0, PWM1-RB1, PWM2-RB3, PWM3-RB4, PWM4- Bit5...
  • Page 85 SC8F577x PWM4 lower bit of period register PWM4TL (1EH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM4T[7:0] PWMTL Reset value Bit7~Bit0 PWM4T[7:0]: Lower 8 bits of PWM4 period register PWM higher bit of period register PWMTH (16H) Bit7 Bit6 Bit5 Bit4 Bit3...
  • Page 86 SC8F577x PWM3 lower bit of duty register PWMD3L (1AH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWMD3L PWMD3[7:0] Reset value PWMD3[7:0]: PWM3 lower bit of duty register. Bit7~Bit0 PWM4 lower bit of duty register PWMD4L (1BH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2...
  • Page 87 SC8F577x PWM0/PWM1 dead-time register PWM01DT (0FH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM01DT PWM01DT[5:0] Reset value Not used. Bit7~Bit6 PWM01DT[5:0]: PWM0/PWM1 dead-time register. Bit5~Bit0 PWM2/PWM3 dead-time register PWM23DT (10H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM23DT PWM23DT[5:0] Reset value Not used.

  • Page 88: Pwm Duty Cycle

    SC8F577x 11.3 Sequence of PWM register write operation Since the 10-bit PWM duty cycle value is allocated in two registers, when modifying the duty cycle, the program always modifies these two registers one after the other. In order to ensure the correctness of the duty cycle value, a cache loading function is designed inside the chip.
  • Page 89 SC8F577x 11.7 Programmable dead-time delay mode Complementary output mode can be enabled by configured PWMxDT_EN, and the dead-time delay function is enabled automatically after enable complementary output mode. Cycle Cycle Pluse Width PWM0 PWM0_B td = dead-time delay Fig 11-1: Sample of PWM dead-time delay output Dead-time calculation formula: td=( PWMxxDT [5:0]+1)*T * ( DT_DIV prescaler value )
  • Page 90 SC8F577x 12. Program EEPROM and Program Memory Control 12.1 General The devices in this series have 4K words of program memory, the address range is from 0000h to 0FFFh, which is read-only in all address ranges; the device has a 128-byte program EEPROM, and the address range is 0000h to 007Fh, which is available in all address ranges.
  • Page 91 SC8F577x 12.2 Related Register EEADR and EEADRH Register 12.2.1 The EEADR and EEADRH registers can address up to 128 bytes of program EEPROM or up to 4K bytes of program memory. When the program memory address value is selected, the high byte of the address is written into the EEADRH register and the low byte is written into the EEADR register.
  • Page 92 SC8F577x EEPROM data register EEDATH (8FH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EEDATH EEDATH7 EEDATH6 EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 read/write Reset value Bit7~Bit0 EEDATH<7:0>: The upper 8 bits of data read from the program EEPROM/program memory. EEPROM address register EEADRH (96H) Bit7 Bit6...
  • Page 93 SC8F577x 12.3 Read Program EEPROM To read the program EEPROM cell, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register, and then set the control bit RD to 1. Once the read control bit is set, the program EEPROM controller will use the second instruction period to read data.
  • Page 94 SC8F577x 12.4 Write Program EEPROM To write a program EEPROM storage unit, the user should first write the unit's address to the EEADR register and write data to the EEDAT register. Then the user must start writing each byte in a specific order. If you do not follow the following instructions exactly (that is, first write 55h to EECON2, then write AAh to EECON2, and finally set the WR bit to 1) to write each byte, the write operation will not be started.
  • Page 95 SC8F577x F_GIE_ON ;restore interrupt enabled status SETB INTCON, GIE SNZB EECON1, WRERR ;check EEPROM write EEPDATA_WRITE_BACK SZDECR WERR_C ; Exit when the count expires, user-defined EEPDATA_WRITE ;rewrite when EEPROM write error EEPDATA_WRITE_BACK: www.mcu.com.cn 95 / 181 V1.8...
  • Page 96 SC8F577x 12.5 Read Program Memory To read the program memory unit, the user must write the high and low bits of the address to the EEADR and EEADRH registers respectively, set the EEPGD bit of EECON1register to 1, and then set the control bit RD to 1.
  • Page 97 SC8F577x 12.7 Precautions on Program EEPROM Programming Time for Program EEPROM 12.7.1 The program EEPROM programming time is not fixed. The time required to program different data is different, ranging from 100us to 5ms(10ms). The CPU stops working during the programming period, and the program needs to be well dealt with accordingly.
  • Page 98 SC8F577x 13. Constant Current Output The chip has a built-in pin for output 50mA constant drain current. 13.1 The Related Register of constant current output The control register of constant current output ECIGCON (9BH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ECIGCON...

  • Page 99: Comparator (Comp)

    SC8F577x 14. Comparator (COMP) A set of comparator is built into the chip, and the voltage of the input port can be higher than the chip power supply(VDD). Note: The input impedance of the comparator is 150kΩ, so more attention should be paid to the driving power when in use.
  • Page 100 SC8F577x 15. Programmable Gain Amplifier (PGA) A set of differential input PGA is built into the chip, it can get the gain with x4、x8 or x16 times, and the output of PGA can be connected to the input channel of the ADC. Note：...
  • Page 101 SC8F577x 15.2 The Related Register of PGA There are three registers associated with the PAG, PGACON、ADCON0 and ADCON1。 The control register of PGA PGACON (9AH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PGACON PGAEN PGACH ---- ---- ---- ---- GAIN[1:0] ---- ----...
  • Page 102 SC8F577x 16. Universal Synchronous/Asynchronous Transmitter (USART) The universal synchronous/asynchronous transmitter (USART) mod is a serial I/O communication peripheral. This mod includes all the clock generators, shift registers and data buffers necessary to perform input or output serial data transmissions that are not related to device program execution. USART It can also be called a serial communication interface (Serial Communications Interface, SCI), it can be configured as a duplex asynchronous system that can communicate with peripherals such as CRT terminals and personal computers;...
  • Page 103 SC8F577x CREN OERR RCIDL SPEN RSR register RX/DT pin Pin buffering Data Stop bit （8） 7 Start bit and control Recovery RX9EN Baud rate generator Fosc ÷ n Frequency SPBRG multiplier SYNC FIFO FERR RX9D RCREG register Data Bus RCIF Interrupt RCIE Fig 16-2: USART receive block diagram...
  • Page 104 SC8F577x 16.1 USART Asynchronous Mode USART uses the standard non-return-to-zero (NRZ) format for transmit and receive data. Two levels are used to implement NRZ: It represents the VOH mark state (mark state) of 1data bit, and the VOL space state (space state) of 0 data bit.
  • Page 105 SC8F577x 16.1.1.2 Transmit Data Write a character to the TXREG register to start transmit. If this is the first character, or the previous character has been completely removed from the TSR, the data in TXREG will be immediately transmitted to the TSR register.
  • Page 106 SC8F577x 16.1.1.6 Configure Asynchronous Transmit Initialize the SPBRG register to obtain the required baud rate (see "USART baud rate generator (BRG)" Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit to 1. If 9-bit transmit is required, set the TX9EN control bit to 1. When the receiver is set for address detection, set the 9th bit of the data bit to 1, indicating that the 8 lowest data bits are address.
  • Page 107 SC8F577x 16.1.2 USART Asynchronous Receiver Asynchronous mode is usually used in RS-232 system. Figure 16-2 shows the block diagram of the receiver. Receive data and driver data recovery circuit on RX/DT pin. The data recovery circuit is actually a 16 times baud rate as the operating frequency High-speed shifter, while the serial receives shift register (Receive Shift Register, RSR) works at the bit rate.
  • Page 108 SC8F577x 16.1.2.3 Receive Interrupt As long as the USART receiver is enabled and there is no unread data in the receive FIFO, the RCIF interrupt flag bit in the PIR1 register will be set to 1. The RCIF interrupt flag bit is read-only and cannot be set or cleared by software.
  • Page 109 SC8F577x 16.1.2.7 Asynchronous Receive Configuration Initialize the SPBRG register to obtain the required baud rate. (Please refer to the "USART baud rate generator (BRG)" chapter. Set the SPEN bit to 1 to enable the serial port. The SYNC bit must be cleared to perform asynchronous operations.
  • Page 110 SC8F577x 16.2 Clock Precision for Asynchronous Operations The output of the internal oscillation circuit (INTOSC) is calibrated by the manufacturer. But when VDD or temperature changes, INTOSC will have a frequency shift, which will directly affect the asynchronous baud rate. The baud rate clock can be adjusted by the following methods, but some type of reference is required clock source.
  • Page 111 SC8F577x RCSTA：receive status and control register (118H) 118H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RCSTA SPEN RX9EN SREN CREN RCIDL FERR OERR RX9D read/write Reset value Bit7 SPEN: Serial port enable bit; Enable serial port (RX/DT and TX/CK pin configured as serial port pin); Disable serial port (hold on reset).

  • Page 112: Usart Synchronous Mode

    SC8F577x 16.4 USART Baud Rate Generator (BRG) The baud rate generator (BRG) is an 8-bit, dedicated to supporting the asynchronous and synchronous working modes of USART. The SPBRG register determines the period of the free-running baud rate timer. Table 16-1 contains the formula for calculating baud rate. Formula 1 is an example of calculating baud rate and baud rate error.
  • Page 113 SC8F577x Synchronous serial communication is usually used in a system with a master control device and one or more slave devices. The master control device contains the necessary circuits to generate the baud rate clock and provides clock for all devices in the system. The slave device can use master control clock, so no internal clock generation circuit is needed.
  • Page 114 SC8F577x 16.5.1.3 Synchronous Master Control Transmit The RX/DT pin output data of the device. When the USART configuration is synchronous master control transmit operation, the RX/DT and TX/CK output pins of the device are automatically enabled. Write a character to the TXREG register to start the transmit. If all or part of the previous character is still stored in the TSR, the new character data is stored in TXREG until the stop bit of the previous character is transmitted.
  • Page 115 SC8F577x RX/DT pin Bit0 Bit1 Bit2 Bit6 Bit7 TX/CK pin Write to TXREG register TXIF bit TRMT bit TXEN bit Fig 16-7: synchronous transmit (through TXEN) 16.5.1.5 Synchronous Master Control Receive RX/DT pin receive data. When the USART configuration is synchronous master control receive, the output driver of the RX/DT pin of the device is automatically disabled.
  • Page 116 SC8F577x 16.5.1.7 Receive Overflow Error The receive FIFO buffer can store 2 characters. Before reading the RCREG to access the FIFO, if the third character is received completely, an overflow error will occur. At this time, the OERR bit of the RCSTA register will be set to 1.
  • Page 117 SC8F577x 16.5.2 Synchronous Slave Mode The following bits are used to configure USART for synchronous slave operation: ⚫ SYNC=1 ⚫ CSRC=0 ⚫ SREN=0 (to transmit); SREN=1 (to receive) ⚫ CREN=0 (to transmit); CREN=1 (to receive) ⚫ SPEN=1 Set the SYNC bit of the TXSTA register to 1 to configure the device for synchronous operation. Set the CSRC bit of the TXSTA register to 1 to configure the device as a slave device.
  • Page 118 SC8F577x 16.5.2.4 Synchronous Slave Receive Configuration Set the SYNC and SPEN bits and clear the CSRC bit. If interrupt is used, set the GIE and PEIE bits of the INTCON register to 1, and also set the RCIE bit of the PIE1 register. If you need to receive a 9-bit character, set the RX9EN bit to 1.

  • Page 119: Spi Mode

    SC8F577x 17. SPI Mode 17.1 SPI Mode General SPI mode allows simultaneous transmit and receive 8-bit data at the same time. Support 4 master modes and 2 slave modes for SPI. In addition, SPI supports 3-wire mode and 4-wire mode communication. The following three pins are used under 4-wire mod：...
  • Page 120 SC8F577x 17.2 SPI Related Registers SPICON2: SPI control register (9BH) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPICON2 MODE SPIBF read/write Reset value Bit7 Save, write 0 Bit 6 CKE: SPI clock edge selection bit. (Note: In slave mode, CKE must be set to 0) CKP= 0= Transmit data on the rising edge of SCK pin；...
  • Page 121 SC8F577x SPICON：SPI control register (99H) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPICON SPIWCOL SPIOV SPIEN SPICKP SPIM3 SPIM2 SPIM1 SPIM0 read/write Reset value Bit7 SPIWCOL: Write conflict detection bit. In the process of transmit/receive data, try to write to the SPIBUF register. No conflict.
  • Page 122 SC8F577x 17.3 SPI Working Principle When initializing the SPI, several options need to be specified. They can be specified by programming the corresponding control bits (SPICON<5:0> and SPICON2<7:6>). These control bits are used to specify the following options: ◆ ◆ master control mode (SCK as clock output) Slave mode (SCK as clock input) ◆...
  • Page 123 SC8F577x SPI mod consists of a transmit/receive shift register (SPISR) and a buffer register (SPIBUF). SPISR moves data in and out of the device, with the most significant bit first. SPIBUF saves the data written to the SPISR last time until the new receive. The data is ready. Once the 8-bit data receive is completed, the byte is moved into the SPIBUF register.
  • Page 124 SC8F577x 17.4 Enable SPI I/O To enable the serial port, the SPI enable bit SPIEN of the SPICON register must be set to 1. To reset or reconfigure the SPI mode, first clear the SPIEN bit, reinitialize the SPICON register, and then set the SPIEN bit to 1.
  • Page 125 SC8F577x Figure 17-2 shows the waveform of the master control mode. When the CKE bit of the SPICON2 register is 1, the SDO data is valid before the clock edge appears on the SCK. The figure indicates the time to load the received data into the SPIBUF.

  • Page 126: Slave Mode

    SC8F577x 17.6 Slave Mode In slave mode, when an external clock pulse appears on the SCK pin, transmit and receive data. When the last bit of data is latched, the SPIIF interrupt flag bit of PIR1register is set to 1. In slave mode, the clock is provided by the external clock source on the SCK pin.

  • Page 127: Sleep Operation

    SC8F577x SS Optional SCK(CKP=0 CKE=0) SCK(CKP=1 CKE=0) 写入SPIBUF Bit7 Bit5 Bit6 Bit4 Bit3 Bit1 Bit2 Bit0 Bit0 Bit7 Input sampling SPIIF Q4 cycle after Q2 SPISR to SPIBUF Fig 17-4: SPI mode waveform (slave mode, CKE=0) 17.8 Sleep Operation In sleep mode, all mod clocks will stop, and before the device is awakened, transmit/receive will remain in this stagnant state.

  • Page 128: Iic Mode

    SC8F577x 18. IIC Mode 18.1 IIC Mode General The IIC module can realize all master control and slave functions (including broadcast call support), and use hardware to provide interrupts of the start and stop bits to determine when the bus is idle (multi-master function).
  • Page 129 SC8F577x If the SCL and SDA pins have been programmed as input pins (set the corresponding TRIS bit to 1), selecting any I C mode and IICEN bit as 1 will force the SCL and SDA pins to be open drain. 18.2 IIC Related Register IICSTAT: IIC status register (10FH) 10FH...
  • Page 130 SC8F577x IICCON: IIC control register (10CH) 10CH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IICCON IICWCOL IICOV IICEN IICCKP ---- ---- IICM1 IICM0 read/write ---- ---- Reset ---- ---- value Bit7 IICWCOL: Write conflict detection bit. master control mode: 1= Trying to write to the IICBUF register when I C does not meet the condition of starting transmit data.
  • Page 131 SC8F577x IICCON2: IIC control register2 (10DH) 10DH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IICCON2 GCEN ACKSTAT ACKDT ACKEN RCEN RSEN read/write Reset value Bit7 GCEN: Broadcast call enable bit (only in I C slave mode). It is allowed to generate interrupt when receiving to the general call address (0000h) in IICSR.
  • Page 132 SC8F577x 18.3 Master Control Mode The master control mode works by generating interrupt when the start and stop conditions are detected. The stop (P) bit and the start (S) bit are cleared when reset or disable IIC mod. When the P bit is set to 1, the control of I2C bus can be obtained;...
  • Page 133 SC8F577x Note: When configured as I C master mode, IIC module does not allow event queuing. For example, before the end of the start condition, the user is not allowed to issue another start condition and write to the IICBUF register immediately to initiate the transfer. In this case, IICBUF will not be written and the WCOL bit will be set to 1, which indicates that no write operation to IICBUF has occurred.

  • Page 134: Baud Rate Generator

    SC8F577x Baud Rate Generator 18.3.2 In I C master control mode, the baud rate generator reloaded value is located in the lower 7 bits of the IICADD register (Figure 18-3). When the value is loaded, the baud rate generator will automatically start counting and decrement to 0, and then stop until the next reload.
  • Page 135 SC8F577x C Master Control Mode Transmit 18.3.3 Transmit a data byte and a 7-bit address can be achieved directly by writing a value to the IICBUF register. This operation will set the buffer full flag bit BF to 1, and the baud rate generator will start counting, and at the same time start the next transmit.
  • Page 136 SC8F577x C Master Control Mode Receive 18.3.4 By programming receive enable bit RCEN (IICCON2 register) to enable master control mode receive. The baud rate generator starts counting, and each time the count returns, the state of the SCL pin changes (from high to low or from low to high), and data is shifted into IICSR.
  • Page 137 SC8F577x Set ACKEN to 1, start the Write IICCON2<4> to start the Configure the master device as Write IICCON2<0> (SEN=1) response sequence, response sequence a receiver by programming Start condition start SDA=ACKDT=1 SDA=ACKDT(IICCON2<5>)=0 RCEN is IICCON2<3> (RCEN=1) ACK from slave device, automatically Here let the PEN bit=1 SEN=0...
  • Page 138 SC8F577x C Master Control Mode Start Condition Time Series 18.3.5 To initiate a start condition, the user should set the start condition enable bit SEN of the IICCON2 register to 1. When both SDA and SCL pins are sampled as high, the baud rate generator reloads the contents of IICADD<6:0>...
  • Page 139 SC8F577x C Master Control Mode Repeat Condition Time Series 18.3.6 When the RSEN bit (IICCON2 register) is programmed to be high and the I2C logic mod is in an idle state, a repeated start condition will occur. When the RSEN bit is 1, the SCL pin is pulled low. When the SCL pin is sampled low, baud rate generator loads the contents of IICADD<6:0>...
  • Page 140 SC8F577x ACK Time Series 18.3.7 Set the ACK enable bit ACKEN (IICCON2 register) to 1 to enable the acknowledgement. When this bit is set to 1, the SCL pin is pulled low, and the content of the ACK data bit appears on the SDA pin. If the user wants to generate a response, it should clear the ACKDT bit to zero;...

  • Page 141: Stop Condition

    SC8F577x Stop Condition 18.3.8 At the end of receive/transmit, by setting the enable bit of the stop sequence, PEN (IICCON2 register), the SDA pin will generate a stop bit. At the end of receive/transmit, the SCL pin will remain low after the falling edge of the 9th clock Level.

  • Page 142: Clock Arbitration

    SC8F577x Clock Arbitration 18.3.9 If during any receive, transmit, or repeated start/stop conditions, the master device pulls up the SCL pin (allowing the SCL pin to float high), clock arbitration will occur. If the SCL pin is allowed to float high, the baud rate generator (BRG) will pause counting until the SC L pin is actually sampled high.
  • Page 143 SC8F577x Multi Master Communication, Bus Conflict and Bus Arbitration 18.3.11 Multi-master mode is supported by bus arbitration. When the master device outputs the address/data bit to the SDA pin, if one master device outputs 1 on SDA by floating the SDA pin to high level, and the other master device outputs 0, bus arbitration will occur.
  • Page 144 SC8F577x Addressing 18.4.1 Once IIC mod is enabled, it will wait for the start condition to be generated. After the start condition occurs, 8 bits of data are shifted into the IICSR register. All input bits are sampled on the rising edge of the clock (SCL) line.
  • Page 145 SC8F577x Transmit 18.4.3 When the R/W bit of the received address byte is 1 and an address match occurs, the R/W bit of the IICSTAT register is 1. The received address is loaded into the IICBUF register. The ACK pulse is transmitted on the 9th bit while the SDA pin remains low.
  • Page 146 SC8F577x I2C Masking Register 18.4.4 In I C slave mode, the IIC mask (IICMSK) register is used to mask the value in the IICSR register under the address compare operation. A bit of 0 in the IICMSK register will make the corresponding bit in the IICSR register a "don't care".

  • Page 147: Touch Button

    SC8F577x 19. Touch Button 19.1 Touch Button Mod General The touch detection mod is an integrated circuit designed to realize a human touch interface. It can replace mechanical touch buttons to achieve a waterproof and dustproof, sealed and isolated, sturdy and beautiful operation interface.
  • Page 148 SC8F577x 19.2 Touch Button Related Register There are mainly 5 registers related touch button, namely control register KEYCON0、KEYCON1 and KEYCON2, result register KEYDATL and KEYDATH. Touch button result register lower bit KEYDATL(190H) 190H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 KEYDATL Reset value...
  • Page 149 SC8F577x Touch button control register KEYCON1(18DH) 18DH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 KEYCON1 KVREF[1:0] KCLK[1:0] KCHS[3:0] Reset value Bit7~Bit6 KVREF: Selection of negative voltage of touch button internal comparator; 0.4*V ； 0.5* V ； 0.6 *V ； 0.7 *V 。...
  • Page 150 SC8F577x Touch button control register KEYCON2(18EH) 18EH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 KEYCON2 CAP_LVBO[2:0] ---- LDOEN ---- ---- TKEN ---- ---- ---- Reset value ---- ---- ---- Bit7~Bit5 CAP_LVBO[2:0] Digital filtering time selection of end flag bit (T =1/ F TKDIV TKDIV...
  • Page 151 SC8F577x 19.3 Application for Touch Button Mod The process of reading “data of touch button” in query mode 19.3.1 Enable input of the corresponding IO (including key port and the sensitivity adjustment capacitor port); Set the TKEN bit in KEYCON2 as 1; Set the touch button control register KEYCON1 (including channel selection, touch button detected clock configuration, negative voltage of comparator configuration;...
  • Page 152 SC8F577x Judge method of key press 19.3.2 Base of judgment: no press down---large “data”; press down---small “data”; The current value is smaller than previous value in a certain extent, which can be considered as the key have been “pressed down”; Within a certain period of time, “data”...
  • Page 153 SC8F577x 19.4 Precautions for Touch Button Mod ◆ The ground wire of the detection part of the touch button should be separately connected to an independent ground, and another point is connected to the common ground of the whole machine. ◆...

  • Page 154: Low Voltage Detection (Lvd)

    SC8F577x 20. Low Voltage detection (LVD) 20.1 LVD Mod General SC8F577x series of MCU have a low-voltage detection function, which can be used to monitor the power supply voltage. If the power supply voltage is lower than the set value, an interrupt signal can be generated; the program can read the LVD output flag bit in real time.

  • Page 155: Electrical Parameter

    SC8F577x 21. Electrical Parameter 21.1 Limit Parameter Supplying voltage…………………………………………..………………….….……….. GND-0.3V~GND+5V Storage temperature……………………………………………………….….……………………. -50℃~125℃ Working temperature…………………………………………………...………..…………………… -20℃~75℃ Port input voltage.……………….…………………………………..………………… GND-0.3V~VDD+0.3V Maximum source current for all ports………………………………...………………………………….. 200mA Maximum sink current for all ports………………….……………………………………………………- 150mA Note: If the device operating conditions exceed the above "limit parameters", it may cause permanent damage to the device.
  • Page 156 SC8F577x 21.3 ADC Feature （T = 25℃, unless otherwise indicated） Symbol Parameter Test condition Unit Working voltage Accuracy GND≤VAIN≤VDD or ADVREF Input voltage range VREF VDD=3V, reference voltage =VDD, ADC current Differential nonlinearity VDD=3V, reference voltage =VDD, DNL1 ±2 error 1 AD_CLK=4MHz Integral nonlinearity VDD=3V, reference voltage =VDD,...
  • Page 157 SC8F577x 21.5 PGA Feature （T = 25℃, unless otherwise indicated） Symbol Parameter Test condition Unit Working voltage range Working current VDD=3.3V Input common mode VDD=3.3V voltage range VOUT Output voltage range VDD=3.3V 0.04 Input impedance VDD=3.3V KΩ Gain PGACH=1 and 0, take the GN_ERR Gain error 1.6%...
  • Page 158 SC8F577x 22. Instructions 22.1 Instructions Table Instructions mnemonic operation symbol period control-3 Empty operation None STOP Enter sleep mode TO, PD CLRWDT Clear watchdog timer TO, PD Data transfer-4 [R], A Transfer content to ACC to R NONE A, [R] Transfer content to R to ACC TESTZ Transfer the content of data memory data memory...
  • Page 159 SC8F577x Instructions mnemonic operation symbol period INCR Increment data memory R, result stored in R DECA Decrement data memory R, result stored in ACC DECR Decrement data memory R, result stored in R Bit operation-2 CLRB [R], b Clear some bit in data memory R NONE SETB [R], b...
  • Page 160 SC8F577x 22.2 Instructions Illustration ADDA operation: Add ACC to R, save the result to ACC period: Affected flag bit: C, DC, Z, OV example: LDIA ;load 09H to ACC R01, A ;load ACC (09H) to R01 LDIA 077H ;load 77H to ACC ADDA ;execute：ACC=09H + 77H =80H ADDR...
  • Page 161 SC8F577x ADDIA operation: Add i to ACC, save the result to ACC period: affected flag bit: C, DC, Z, OV example: LDIA ; load 09H to ACC ADDIA 077H ;execute：ACC = ACC (09H) + i (77H)=80H ANDA Perform ‘AND’ on register R and ACC, save the result to ACC operation: period: affected flag bit:...
  • Page 162 SC8F577x CLRA operation: ACC clear period: affected flag bit: example: CLRA ;execute：ACC=0 operation: Register R clear period: affected flag bit: example: ;execute：R01=0 CLRB [R], b operation: Clear b bit on register R period: affected flag bit: none example: CLRB R01, 3 ;execute：3 bit of R01 is 0 CLRWDT...
  • Page 163 SC8F577x COMR operation: Reverse register R, save the result to R period: affected flag bit: example: LDIA ; load 0AH to ACC R01, A ; load ACC (0AH) to R01 COMR ;execute：R01=0F5H DECA operation: Decrement value in register , save the result to ACC period: affected flag bit: example:...
  • Page 164 SC8F577x HSUBR operation: ACC subtract R, save the result to R period: affected flag bit: C, DC, Z, OV example: LDIA 077H ; load 077H to ACC R01, A ; load ACC (077H) to R01 LDIA 080H ; load 080H to ACC HSUBR ;execute：R01= (80H-77H)=09H HSUBCA...
  • Page 165 SC8F577x INCR operation: Register R increment 1, save the result to R period: affected flag bit: example: LDIA ; load 0AH to ACC R01, A ; load ACC (0AH) to R01 INCR ;execute：R01= (0AH+1)=0BH operation: Jump to add address period: affected flag bit: none example:...
  • Page 166 SC8F577x operation: Empty instructions period: affected flag bit: none example: ORIA operation: Perform ‘OR’ on I and ACC, save the result to ACC period: affected flag bit: example: LDIA ; load 0AH to ACC ORIA 030H ;execute：ACC = (0AH or 30H)=3AH operation: Perform ‘OR’...
  • Page 167 SC8F577x operation: Return from subroutine period: affected flag bit: none example: CALL LOOP ; Call subroutine LOOP ; This statement will be executed after RET instructions return … ; others LOOP: … ;subroutine ;return operation: Return with parameter from the subroutine, and put the parameter in ACC period: affected flag bit: none...
  • Page 168 SC8F577x RLCR operation: Register R rotates one bit to the left with C, and save the result into R period: affected flag bit: example: LDIA ; load 03H to ACC R01, A ; load ACC to R01, R01=03H RLCR ;operation result：R01=06H (C=0); R01=07H (C=1);...
  • Page 169 SC8F577x RRCR operation: Register R rotates one bit to the right with C, and save the result into R period: affected flag bit: example: LDIA ; load 03H to ACC R01, A ; load ACC to R01, R01=03H RRCR ;operation result：R01=01H (C=0); R01=81H (C=1);...
  • Page 170 SC8F577x STOP operation: Enter sleep period: affected flag bit: TO, PD example: ; The chip enters the power saving mode, the CPU and oscillator STOP stop working, and the IO port keeps the original state SUBIA operation: ACC minus I, save the result to ACC period: affected flag bit: C, DC, Z, OV...
  • Page 171 SC8F577x SUBCA operation: Register R minus ACC minus C, save the result to ACC period: affected flag bit: C, DC, Z, OV example: LDIA 080H ; load 80H to ACC R01, A ; load ACC to R01, R01=80H LDIA ; load 77H to ACC SUBCA ;operation result：ACC=80H-77H-C=09H (C=0);...
  • Page 172 SC8F577x [R], b operation: Determine the bit b of register R, if it is 0 then jump, otherwise execute in sequence period: 1 or 2 affected flag bit: none example: R01, 3 ;determine 3 bit of R01 LOOP ;if is 1, execute, jump to LOOP LOOP1 ;...
  • Page 173 SC8F577x SZINCA operation: Increment register by 1, save the result to ACC, if it is 0 then jump, otherwise execute in sequence period: 1 or 2 affected flag bit: none example: SZINCA ;R01+1→ACC LOOP ; if ACC is not 0, execute, jump to LOOP LOOP1 ;...
  • Page 174 SC8F577x TESTZ operation: Pass the R to R, as affected Z flag bit period: affected flag bit: example: TESTZ STATUS, Z ;check Z flag bit, if it is 0 then jump Add1 ;if R0 is 0, jump to address Add1 Add2 ;if R0 is not 0, jump to address Add2 XORIA...
  • Page 175 SC8F577x 23. Packaging 23.1 MSOP10 Millimeter Symbol 1.10 0.05 0.15 0.75 0.85 0.95 0.30 0.35 0.40 0.18 0.26 0.17 0.20 0.23 0.15 0.19 0.14 0.15 0.16 2.90 3.00 3.10 4.70 4.90 5.10 2.90 3.00 3.10 0.50BSC 0.40 0.70 0.95REF θ 8°...
  • Page 176 SC8F577x 23.2 DFN10 Millimeter Symbol 0.70 0.75 0.80 0.05 0.203REF 0.18 0.23 0.28 2.90 3.00 3.10 2.90 3.00 3.10 1.60 1.70 1.80 2.30 2.40 2.50 0.50TYP 0.35 0.40 0.45 www.mcu.com.cn 176 / 181 V1.8...
  • Page 177 SC8F577x 23.3 TSSOP20 Millimeter Symbol 1.20 0.05 0.15 0.80 1.00 1.05 0.19 0.30 0.19 0.22 0.25 0.09 0.20 0.09 0.16 6.40 6.50 6.60 4.30 4.40 4.50 6.20 6.40 6.60 0.65BSC 0.45 0.60 0.75 1.00REF 0.20 Φ1 Φ0.8×0.05~0.10DP Φ2 Φ1.50×0.05~0.15DP θ 8°...
  • Page 178 SC8F577x 23.4 QFN20 Millimeter Symbol 0.70 0.75 0.80 0.02 0.05 0.15 0.20 0.25 0.18 0.20 0.25 2.90 3.00 3.10 1.55 1.65 1.75 0.4BSC 1.6BSC 1.6BSC 3.00 3.10 1.55 1.65 1.75 0.35 0.40 0.45 0.20 0.25 0.30 www.mcu.com.cn 178 / 181 V1.8...
  • Page 179 SC8F577x 23.5 QFN24 Millimeter Symbol 0.70 0.75 0.80 0.02 0.05 0.20 0.25 0.30 0.203REF 3.90 4.00 4.10 2.60 2.70 2.80 0.5BSC 2.5BSC 2.5BSC 3.90 4.00 4.10 2.60 2.70 2.80 0.35 0.40 0.45 0.25 0.30 0.35 0.25REF 0.075REF www.mcu.com.cn 179 / 181 V1.8...
  • Page 180 SC8F577x 23.6 SSOP24 Millimeter Symbol 1.75 0.10 0.15 0.25 1.30 1.40 1.50 0.60 0.65 0.70 0.23 0.31 0.22 0.25 0.28 0.20 0.24 0.19 0.20 0.21 8.55 8.65 8.75 5.80 6.00 6.20 3.80 3.90 4.00 0.635BSC 0.30 0.50 0.50 0.80 1.05REF θ...
  • Page 181 SC8F577x 24. Version Revision Version number Time Revised content V1.0 Aug, 2019 Original version 1. Add ADC conversion clock frequency division selection instructions; V1.1 Feb, 2020 2. The SPI mode adds instructions that CKE must be cleared in slave mode; Add touch button chapter descriptions.

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