Cmsemicon CMS32M65 Series User Manual

Ultra-low power 32-bit microcontrollers based on arm cortex-m0+

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CMS32M65xx User Manual

Ultra-low power 32-bit microcontrollers based on ARM

Cortex

-M0+

V1.0.1

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Summary of Contents for Cmsemicon CMS32M65 Series

Page 1 ＊The name and logo of Cmsemicon are registered trademarks of the Company. ＊The Company reserves the right to further explain the reliability, functionality and design improvements of the products in the data sheet.
Page 2: Documentation Instructions
CMS32M65xx User Manual | Document Instructions Documentation Instructions This manual is a technical reference manual for the CMS32M65xx microcontroller product. The technical reference manual is the application instruction material on how to use this series of products, including the structure, function description, working mode and register configuration of each functional module. The technical reference manual is a description of all functional modules of this series of products.
Page 3: Table Of Contents
CMS32M65xx User Manual | Table of Contents Table of Contents Documentation Instructions ........................... 2 Chapter 1 CPU ........................14 Overview ............................... 14 Cortex-M0+ core features ........................14 Chapter 2 Debugging Features ................... 15 SWD interface pins ..........................16 ARM reference documents ........................17 Chapter 3 Pin Function ......................
Page 4 CMS32M65xx User Manual | Table of Contents System clock oscillation circuit ......................57 5.5.1 High-speed on-chip oscillator ....................... 57 5.5.2 Low-speed on-chip oscillator ......................57 Operation of clock generation circuit..................... 58 Clock control ............................59 5.7.1 Example of setting up a high-speed on-chip oscillator ..............59 5.7.2 CPU clock status transition diagram ....................
Page 5 CMS32M65xx User Manual | Table of Contents 6.6.1 Structure of TImn pin input circuit ....................124 6.6.2 Noise filter ........................... 124 6.6.3 Cautions on channel input operation ..................125 Independent channel operation function of general-purpose timer unit ..........126 6.7.1 Operation as interval timer/square wave output ................
Page 6 CMS32M65xx User Manual | Table of Contents Chapter 10 DIVSQRT Unit ....................189 10.1 Overview ............................. 189 10.2 Features .............................. 189 10.3 Functional description ......................... 189 10.4 Register mapping ..........................190 10.5 Register description ..........................191 10.5.1 DIVSQRT control register (DIVSQRTCON) ................191 10.5.2 DIVSQRT data A register (DIVSQRTALUA) ................
Page 7 CMS32M65xx User Manual | Table of Contents 12.5.6 CCP interrupt source status register (CCPRIS) ................. 208 12.5.7 CCP enabled interrupt status register (CCPMIS) ..............209 12.5.8 CCP interrupt clear register (CCPICLR) ..................210 12.5.9 CCP operation register (CCPRUN) .................... 210 12.5.10 CCP write enable control register (LOCK) .................
Page 8 CMS32M65xx User Manual | Table of Contents 13.5.15 EPWM interrupt enable register (IMSC)..................258 13.5.16 EPWM interrupt source status register (RIS) ................259 13.5.17 EPWM enabled interrupt status register (MIS) ................260 13.5.18 EPWM interrupt clear control register (ICLR) ................261 13.5.19 EPWM interrupt accumulation control register (IFA) ..............
Page 9 CMS32M65xx User Manual | Table of Contents 16.4.3 SSP data register (DAT) ......................279 16.4.4 SSP clock controller (CLK) ......................279 16.4.5 SSP interrupt enable register (IMSC) ..................280 16.4.6 SSP interrupt source status register (RIS) ................. 280 16.4.7 SSP enabled interrupt status register (MIS) ................280 16.4.8 SSP interrupt clear register (ICLR) ....................
Page 10 CMS32M65xx User Manual | Table of Contents 18.5.5 PGA2 control register 0 ......................306 18.5.6 PGA12 control register 0 ......................306 18.5.7 PGA1/PGA2 access register enable ..................306 Chapter 19 Analog Comparator (ACMP0/1) ................ 307 19.1 Overview ............................. 307 19.2 Block diagram of structure ........................307 19.3 Features ..............................
Page 11 CMS32M65xx User Manual | Table of Contents 22.5.5 IRQ0~IRQ3 Interrupt priority register (IPR0)................326 22.5.6 IRQ4~IRQ7 Interrupt priority register (IPR1)................326 22.5.7 IRQ8~IRQ11 Interrupt priority register (IPR2) ................327 22.5.8 IRQ12~IRQ15 Interrupt priority register (IPR3) ................. 328 22.5.9 IRQ16~IRQ19 Interrupt priority register (IPR4) ................. 328 22.5.10 IRQ20~IRQ23 Interrupt priority register (IPR5) .................
Page 12 CMS32M65xx User Manual | Table of Contents 27.3.1 Flash CRC operation function (high-speed CRC) ..............377 27.3.1.1 Flash memory CRC operation result register L (PGCRCL) ............378 27.3.1.2 CRC operation function (general-purpose CRC) ............... 380 27.3.1.3 CRC input register (CRCIN) ....................... 381 27.3.1.4 CRC data register (CRCD) ......................
Page 13 CMS32M65xx User Manual | Table of Contents 30.5.2 Chip erase ..........................404 30.5.3 Word program ..........................404 30.6 Flash memory read ..........................405 30.7 Cautions for FLASH operation ......................405 Appendix Revision History ....................406 www.mcu.com.cn 13 / 407 Rev.1.0.1...
Page 14: Chapter 1 Cpu
CMS32M65xx User Manual | Chapter 1 CPU Chapter 1 CPU 1.1 Overview This chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+ core. For details, please refer to the ARM related documentation. 1.2 Cortex-M0+ core features ⚫...
Page 15: Chapter 2 Debugging Features
CMS32M65xx User Manual | Chapter 2 Debugging Features Chapter 2 Debugging Features ⚫ 2-wire SWD debug interface ⚫ Support for suspending, resuming and single-step execution of programs ⚫ Access to the processor’s core registers and special function registers ⚫ 4 hardware breakpoints (BPU) ⚫...
Page 16: Swd Interface Pins
CMS32M65xx User Manual | Chapter 2 Debugging Features 2.1 SWD interface pins The 2 GPIOs of this product can be used as SWD interface pins, which exist in all packages. Table 2-1: SWD debug port pins SWD port name Debugging function Pin assignment Serial clock SWDCLK...
Page 17: Arm Reference Documents
CMS32M65xx User Manual | Chapter 2 Debugging Features 2.2 ARM reference documents The built-in debugging feature in the Cortex®-M0+ core is part of the ARM® CoreSight design suite. For documentation, refer to: ® Cortex -M0+ Technical Reference Manual (TRM) ⚫ ®...
Page 18: Chapter 3 Pin Function
CMS32M65xx User Manual | Chapter 3 Pin Function Chapter 3 Pin Function 3.1 Port function Refer to the datasheet of the corresponding product series for specific port functions. 3.2 Port multiplexing function The specific port multiplexing functions are described in the datasheets for each product family. See the table below for details of the port multiplexing functions.
Page 19 CMS32M65xx User Manual | Chapter 3 Pin Function Table 3-2: Analog function and special function pins Analog Special function pin ACMP C1P3 A0GND AN10 RESINB AN11 AN12 A12O AN13 SWDCLK SWDIO AN18 C0P0 C0P1 C0P2 AN14 C1P0 AN15 A1GND C1P1 AN16 C1P2 AN17...
Page 20: Register Mapping
CMS32M65xx User Manual | Chapter 3 Pin Function 3.3 Register mapping Control function register mapping 3.3.1 (Base address of the port control register=0x40040000) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value 0x000 Set the register for configuring the 0x00 output latch value in 1-bit units;...
Page 21 CMS32M65xx User Manual | Chapter 3 Pin Function PCLR1 0x081 bit units. 0x00 PCLR2 0x082 0x00 www.mcu.com.cn 21 / 407 Rev.1.0.1...
Page 22: Output-Input Multiplexing Function Register Mapping
CMS32M65xx User Manual | Chapter 3 Pin Function Output-input multiplexing function register mapping 3.3.2 (Base address of the output-input multiplexing function registers =0x40040800) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value P00CFG 0x00 0x00 P01CFG 0x02 0x00...
Page 23 CMS32M65xx User Manual | Chapter 3 Pin Function UART rxd signal input port multiplexing register, which can be mapped to a _CFG 0x68 0x07 uart0rxd specific port. For specific mappings, please refer to Table 3-1. EPWM external brake input port multiplexing register, which can be _CFG 0x69...
Page 24: Special Function Port Resinb Control Register Mapping
CMS32M65xx User Manual | Chapter 3 Pin Function Special function port RESINB control register mapping 3.3.3 (Register base address =0x40020400) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value Select the RESINB (P02) port as the RSTM 0x0B 0x00...
Page 25: Register Description
CMS32M65xx User Manual | Chapter 3 Pin Function 3.4 Register description The port is controlled via the following registers. (1) Port register (Px) (2) Port mode register (PMx) (3) Pull-up resistor selection register (PUx) (4) Pull-down resistor selection register (PDx) (5) Port output mode register (POMx) (6) Port mode control register (PMCx) (7) Port set control register (PSETx)
Page 26: Port Register (Px)
CMS32M65xx User Manual | Chapter 3 Pin Function Port register (Px) 3.4.1 This is register Px (x=0 to 2) which sets the value of the port's output latch in 1-bit units. Reading this register in input mode gives the pin level, and reading it in output mode gives the value of the port's output latch.
Page 27: Port Mode Register (Pmx)
CMS32M65xx User Manual | Chapter 3 Pin Function Port mode register (PMx) 3.4.2 When the port is used as a digital channel, this is the register PMx (x=0~2) that sets its input/output in bits. After a reset signal is generated, all ports default to the input state. The register is described as follows: Symbol Description...
Page 28: Pull-Up Resistor Selection Register (Pux)
CMS32M65xx User Manual | Chapter 3 Pin Function Pull-up resistor selection register (PUx) 3.4.3 On-chip pull-up resistor selection register PUx (x=0 to 2). The pull-up resistor can only be set when the corresponding PMCx bit is equal to 0. After a reset signal is generated, the pull-up function of the P02 port is turned on automatically, and the pull-up function of the other ports will not be turned on by default.
Page 29: Pull-Down Resistor Selection Register (Pdx)
CMS32M65xx User Manual | Chapter 3 Pin Function Pull-down resistor selection register (PDx) 3.4.4 On-chip pull-down resistor selection register PDx (x=0 to 2). The pull-down resistor can only be set when the corresponding PMCx bit is equal to 0; RESINB (P02) port has no pull-down function. After a reset signal is generated, the pull-down function of P06 and P07 ports will be turned on automatically, and the pull-down function of other ports will not be turned on by default.
Page 30: Port Output Mode Register (Pomx)
CMS32M65xx User Manual | Chapter 3 Pin Function Port output mode register (POMx) 3.4.5 Port Output Mode Register POMx (x=0~2), will only be enabled if configured to output mode N-channel open drain. When P03CFG=0x05 or P04CFG=0x05, it will force the N-channel open drain mode of P03 or P04 to be turned on.
Page 31: Port Mode Control Register (Pmcx)
CMS32M65xx User Manual | Chapter 3 Pin Function Port mode control register (PMCx) 3.4.6 Port Mode Register (PMCx (x=0~2)), sets the port as a digital (input/output) or analog (input) channel in 1-bit units. After a reset signal is generated, P00, P01, P02, P06, P07 are used as digital channels by default (PMC00, PMC01, PMC02, PMC06, PMC07 are reset to “0”), and the other ports are used as analog channels by default, i.e., the corresponding bit of PMCx is equal to 1.
Page 32: Port Set Control Register (Psetx)
CMS32M65xx User Manual | Chapter 3 Pin Function Port set control register (PSETx) 3.4.7 This is a register that sets the port output latch PSETx (x=0 to 2) in 1-bit units. After a reset signal is generated, the value of the register changes to “00H”. The register is described as follows: Symbol Description...
Page 33: Port Clear Control Register (Pclrx)
CMS32M65xx User Manual | Chapter 3 Pin Function Port clear control register (PCLRx) 3.4.8 This is a register that sets the port output latch PCLRx (x=0 to 2) in 1-bit units. After a reset signal is generated, the value of the register changes to “00H”. The register is described as follows: Symbol Description...
Page 34: Port Output Multiplexing Configuration Register (Pmncfg)
CMS32M65xx User Manual | Chapter 3 Pin Function Port output multiplexing configuration register (PmnCFG) 3.4.9 The port multiplexing configuration register can map the output function of some peripheral modules to any port, see Table 3-1. If the reset value of the Port Output Multiplexing Configuration Register is "00H", and the port is defaulted to multiplexing function and GPIO function.
Page 35: Port Input Multiplexing Configuration Register (Psxx_Cfg)
CMS32M65xx User Manual | Chapter 3 Pin Function Port input multiplexing configuration register (PSxx_CFG) 3.4.10 INTP0, INTP1, INTP2, INTP3, TI00, TI01, TI02, TI03 can be mapped to any GPIO inputs; RXD, BKIN, CCP0AIN, CCP0BIN, CCP1AIN, CCP1BIN can be mapped to the specified GPIO inputs, the specific mapping of the input functions, see Table 3-1;...
Page 36 CMS32M65xx User Manual | Chapter 3 Pin Function PSintp3_CFG is described as follows: Symbol Description Reset value Reserved INTP3 selects the GPIO input 0x00: Select P00 as INTP3 input 0x01: Select P01 as INTP3 input … … PSintp3_CFG[5:0] 0x3F 0x26: Select P26 as INTP3 input 0x27: Select P27 as INTP3 input Other: Input low level PStau0tin0_CFG is described as follows:...
Page 37 CMS32M65xx User Manual | Chapter 3 Pin Function PStau0tin3_CFG is described as follows: Symbol Description Reset value Reserved TI03 selects the GPIO input 0x00: Select P00 as TI03 input 0x01: Select P01 as TI03 input PStau0tin3_CFG … … 0x3F [5:0] 0x26: Select P26 as TI03 input 0x27: Select P27 as TI03 input Other: TI03 input low level...
Page 38 CMS32M65xx User Manual | Chapter 3 Pin Function PSccp0bin_CFG is described as follows: Symbol Description Reset value Reserved CCP0BIN selects the GPIO input 0x00: Select P02 as CCP0BIN input 0x01: Select P04 as CCP0BIN input PSccp0b_i_CFG [2:0] 0x02: Select P06 as CCP0BIN input 0x03: Select P07 as CCP0BIN input 0x04: Select P26 as CCP0BIN input Other: CCP0BIN input low level...
Page 39: Ttl And Schmitt Input Selection (Pxttlcfg,X=0 And 2)
CMS32M65xx User Manual | Chapter 3 Pin Function TTL and Schmitt input selection (PxTTLCFG,x=0 and 2) 3.4.11 The PxTTLCFG selection register is described as follows. Symbol Description Reset value Px7 input level selection PxTTL7 0: Schmitt input 1: TTL input Px6 input level selection PxTTL6 0: Schmitt input...
Page 40: Chapter 4 System Architecture
CMS32M65xx User Manual | Chapter 4 System Architecture Chapter 4 System Architecture 4.1 Overview This product system consists of the following components: ⚫ 1 AHB bus Master: Cortex-M0+ ⚫ 3 AHB buses Slaves: FLASH memory SRAM memory AHB to APB Bridge, contains all APB interface peripherals Figure 4-1: Block diagram of system architecture Flash memory...
Page 41: System Address Partitioning
CMS32M65xx User Manual | Chapter 4 System Architecture 4.2 System address partitioning Figure 4-2: Map of address area FFFF_FFFFH Reserved E00F_FFFFH Cortex-M0+ Dedicated Peripheral Resource Area E000_0000H Reserved 4006_FFFFH Peripheral Resource Area 4000_0000H Reserved 2000_1FFFH SRAM (up to 8KB) 2000_0000H Reserved 0050_05FFH Data Flash 1KB...
Page 42 CMS32M65xx User Manual | Chapter 4 System Architecture Peripheral Address Assignment Table 4-1: Start address of peripheral register group Start address Peripheral Remark 0x4000_0000 - 0x4000_4FFF Reserved 0x4000_5000 - 0x4000_5FFF Reserved 0x4000_6000 - 0x4000_6FFF Interrupt control 0x4000_7000 - 0x4001_8FFF Reserved 0x4001_9000 - 0x4001_9FFF Reserved 0x4001_A000 - 0x4001_FFFF...
Page 43 CMS32M65xx User Manual | Chapter 4 System Architecture 0x4006_4380 – 0x4006_43BF Reserved 0x4006_8000 – 0x4006_80FF 0x4006_8100 – 0x4006_81FF Reserved 0x4006_8200 – 0x4006_823F ACMP0 0x4006_8240 – 0x4006_827F Reserved Reserved 0x4006_8300 – 0x4006_831F PGA0 0x4006_8320 – 0x4006_833F PGA12 0x4006_8340 – 0x4006_835F ADCLDO 0x4006_8360 –...
Page 44: Chapter 5 Clock Generation Circuit
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Chapter 5 Clock Generation Circuit 5.1 Function of clock generation circuit The clock generation circuit is a circuit that generates a clock supplied to the CPU and peripheral hardware. There are the following 2 types of system clock and clock oscillation circuits (1) Main system clock high-speed on-chip oscillator (high-speed OCO) The frequency at which to oscillate can be selected from among F =64MHz, 48MHz, 32MHz,...
Page 45: Configuration Of Clock Generation Circuit
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit 5.2 Configuration of clock generation circuit The clock generation circuit includes the following hardware. Table 5-1: Configuration of clock generation circuit Item Configuration System clock control register (CKC) Clock operation status control register (CSC) Peripheral enable registers 0, 1 (PER0, PER11, PER12, PER13) Control registers Subsystem clock supply mode control register (OSMC)
Page 46 CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Figure 5-1: Block diagram of clock generation circuit Internal bus System Clock Control Register(CKC) Standby control circuit DEEPSLEEP mode SLEEP mode Buzzer Selector SLEEPDEEP output Normal operation signal mode Option byte CPU clock (00C2H) Main system...
Page 47: Register Mapping
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit 5.3 Register mapping (Base address of the following registers = 0x4002_0400) RO: Read Only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value Clock operation state control register 0x001 0xC0 System clock control register 0x004...
Page 48: Register Description
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit 5.4 Register description The clock generation circuit is controlled through the following registers. ⚫ System clock control register (CKC) ⚫ Clock operation status control register (CSC) ⚫ Peripheral enable registers 0, 1 (PER0, PER11, PER12, PER13) ⚫...
Page 49: Clock Operation Status Control Register (Csc)
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Clock operation status control register (CSC) 5.4.2 This is a register that controls the operation of the high-speed system clock The CSC register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “C0H”.
Page 50: Peripheral Enable Registers 0, 1 (Per0, Per11, Per12, Per13)
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Peripheral enable registers 0, 1 (PER0, PER11, PER12, 5.4.3 PER13) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. When using the following peripheral functions controlled by these registers, the corresponding bit must be set to “1”...
Page 51 CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Peripheral enable register 0 (PER0) Symbol Description Reset value Control of LSITIMER input clock supply (power-down sleep enabled) 0: Stops input clock supply • SFR used by the LSITIMER cannot be written. LSITIMEREN •...
Page 52 CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Peripheral enable register 1 (PER12) Symbol Description Reset value Reserved Control of IIC module input clock supply 0: Stops input clock supply • IIC cannot run IICEN 1: Enables input clock supply •...
Page 53 CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Peripheral enable register 1 (PER13) Symbol Description Reset value Reserved ADCLDOEN Control of ADCLDO module input clock supply 0: Stops input clock supply • ADCLDO cannot run 1: Enables input clock supply •...
Page 54: 12-Bit Interval Timer Operation Clock Select Register (Osmc)
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit 12-bit interval timer operation clock select register (OSMC) 5.4.4 Select the operation clock for the 12-bit interval timer LSITIMER via the OSMC register. The OSMC register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “00H”.
Page 55: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit High-speed on-chip oscillator frequency select register 5.4.5 (HOCODIV) This is a register that changes the frequency of the high-speed on-chip oscillator set by the option byte (000C2H). However, the frequency that can be selected varies depending on the values of the FRQSEL4 bit and FRQSEL3 bit of the option byte (000C2H).
Page 56: Low-Speed On-Chip Oscillator Clock Select Register (Subcksel)
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Low-speed on-chip oscillator clock select register 5.4.6 (SUBCKSEL) The SUBCKSEL register is a register that selects the subsystem clock FSUB and the low-speed on-chip oscillator clock F The SUBCKSEL register is set by an 8-bit memory manipulation instruction. After a reset signal is generated, the value of this register changes to “00H”.
Page 57: System Clock Oscillation Circuit
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit 5.5 System clock oscillation circuit High-speed on-chip oscillator 5.5.1 The CMS32M65xx has a built-in high-speed on-chip oscillator. The frequency can be selected from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, and 2MHz using the option byte (000C2H).
Page 58: Operation Of Clock Generation Circuit
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit 5.6 Operation of clock generation circuit The clock generation circuit generates various clocks as shown below and controls the CPU operation modes such as standby mode (refer to Figure 5-1). : Main system clock frequency MAIN : High-speed on-chip oscillator clock frequency : Low-speed on-chip oscillator clock frequency...
Page 59: Clock Control
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit 5.7 Clock control Example of setting up a high-speed on-chip oscillator 5.7.1 The CPU/peripheral hardware clock (F ) must run at the high-speed on-chip oscillator clock after the reset is released. The frequency of the high-speed on-chip oscillator can be selected from 64MHz, 48MHz, 32MHz, 24MHz, 16MHz, 12MHz, 8MHz, 6MHz, 4MHz, 3MHz, and 2MHz by using bits FRQSEL0 to FRQSEL4 of the option byte (000C2H).
Page 60 CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit [Setting of high-speed on-chip oscillator frequency select register (HOCODIV)] Symbol Description Reset value Reserved Selection of high-speed on-chip oscillator clock frequency FSQSEL4=0 FSQSEL3=0 FSQSEL3=1 =48MHZ =64MHZ =48MHZ =64MHZ HOCO HOCO =24MHZ =32MHZ Set value of =48MHZ...
Page 61: Cpu Clock Status Transition Diagram
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit CPU clock status transition diagram 5.7.2 Figure 5-3 shows the CPU clock status transition diagram of this product. Figure 5-3: CPU clock status transition diagram Power ON Lower limit of the operating voltage range (release from the reset state triggered by the LVD circuit or an external reset ) Release reset CPU: High-speed on-...
Page 62 CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Table 5-3: CPU clock transition and SFR register setting examples (2/3) (3) The CPU moves from high-speed on-chip clock operation (B) to low-speed on-chip clock operation (C). (SFR register setting order) SFR register setting flag SUBCKSEL register CKC register...
Page 63 CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Table 5-3: CPU clock transition and SFR register setting examples (3/3) (7) The CPU moves from high-speed on-chip clock operation (B) to deep sleep mode with partial power- down (F). The CPU moves from low-speed on-chip clock operation (C) to deep sleep mode with partial power- down (I).
Page 64: Conditions Before Cpu Clock Transfer And Post-Transfer Processing
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Conditions before CPU clock transfer and post-transfer 5.7.3 processing The conditions before the CPU clock transfer and the processing after the transfer are shown below. Table 5-4: Transfer of CPU clocks CPU clock Conditions before transfer Post-transfer processing...
Page 65: Time Required To Switch Cpu Clock And Main System Clock
CMS32M65xx User Manual | Chapter 5 Clock Generation Circuit Time required to switch CPU clock and main system 5.7.4 clock It can switch CPU clock (main system clock↔sub system clock) and main system clock (high speed on-chip oscillator clock↔high speed system clock) by setting bit6 (CSS) of system clock control register. The actual switchover does not occur immediately after the CKC register is overridden, but several clocks continue to run with the clock before the switchover after the CKC register is changed (see Table 5-5).
Page 66: Chapter 6 General-Purpose Timer Unit
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Chapter 6 General-Purpose Timer Unit 6.1 Function of general-purpose timer unit The general-purpose timer unit has the following functions: Independent channel operation function 6.1.1 The independent channel operation function is a function that enables independent use of any channel without being affected by other channel operation modes.
Page 67 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit timer input (TImn) capture operation channel N capture edge detection start (6) Measurement of the high-/low-level width of the input signal The high- and low-level width of the input signal is measured by starting the count on one edge of the input signal at the timer input pin (TImn) and capturing the count value on the other edge.
Page 68: Multi-Channel Linkage Operation Functions
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Multi-channel linkage operation functions 6.1.2 The multi-channel linked operation function is a combination of a master channel (the reference timer for the master control cycle) and a slave channel (a timer that operates in compliance with the master channel). The multi-channel linkage operation function can be used as the following modes.
Page 69 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit interrupt signal comparison operation (INTTmn) operation clock Channel n (master) comparison operation timer output (TOmp) Channel p (slave) duty cycle period comparison operation timer output (TOmq) duty cycle Channel p (slave) period Note 1: Please refer to “6.3.1 Basic rules of multi-channel linkage operation function”...
Page 70: 8-Bit Timer Operation Function (Channels 1 And 3 Of Unit 0 Only)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit 8-bit timer operation function (channels 1 and 3 of unit 0 6.1.3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels. This function can only be used for channels 1 and 3. Note: There are several rules for using 8-bit timer operation function.
Page 71: Structure Of General-Purpose Timer Unit
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit 6.2 Structure of general-purpose timer unit The general-purpose timer unit consists of the following hardware. Table 6-1: Structure of general-purpose timer unit Item Structure Counter Timer count register mn (TCRmn) Register Timer data register mn (TDRmn) Note1 TI00~TI03...
Page 72 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit The block diagram of the general-purpose timer unit is shown in Figure 6-1. Figure 6-1: Overall block diagram of general-purpose timer unit 0 Timer clock select register 0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Timer input select register 0 (TIOS0) TIS07 TIS06 TIS05 TIS04 TOS03 TIS02 TIS01 TIS00 TO02...
Page 73: Register Mapping
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Register mapping 6.2.1 (Base address of the following registers = 0x4004_1D80) RO: Read only, WO: Write Only, R/W: Read/Write Register name Offset address R/W Bit width Description Reset value Timer channel 0 count register TCR00 0x000 FFFFH...
Page 74: Timer Count Register Mn (Tcrmn)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer count register mn (TCRmn) 6.2.2 The TCRmn register is a 16-bit read-only register that counts the count clock. The count is incremented or decremented synchronously with the rising edge of the count clock. The operation mode is selected by the MDmn3 to MDmn0 bits of the Timer Mode Register mn (TMRmn) to switch between incremental and decremental counting (refer to “6.2.6: Timer Mode Register mn (TMRmn)”).
Page 75: Timer Data Register Mn (Tdrmn)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer data register mn (TDRmn) 6.2.3 This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).
Page 76: Peripheral Enable Register 0 (Per0)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Peripheral enable register 0 (PER0) 6.2.4 The PER0 register is a register that sets whether to enable or disable the supply of clocks to each peripheral hardware. Reduce power consumption and noise by stopping clocks to hardware that is not in use. To use general-purpose timer unit 4, bit0 (TM40EN) must be set to “1”.
Page 77: Timer Clock Select Register M (Tpsm)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer clock select register m (TPSm) 6.2.5 The TPSm register is a 16-bit register that selects the two or four common operating clocks (CKm0, CKm1, CKm2, CKm3) provided to each channel. CKm0 is selected via bits 3~0 of the TPSm register, and CKm1 is selected via bits 7~4 of the TPSm register.
Page 78 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit purpose timer unit needs to be stopped even when the operation clock (F ) is selected or when the active edge of the TImn pin input signal is used. Note 2: F : CPU/peripheral hardware clock frequency Note 3: The clock waveform selected by the TPSm register is high for only 1 F cycle from the rising...
Page 79: Timer Mode Register Mn (Tmrmn)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer mode register mn (TMRmn) 6.2.6 The TMRmn register is a register that sets the operation mode of channel n. It performs the selection of the operation clock (F ), the selection of the count clock, the selection of master/slave, the selection of the 16-bit/8-bit timer (limited to channel 1 and channel 3), the setting of the start trigger and the capture trigger, the selection of the effective edge of the timer input, and the operation modes (interval, capture, event counter, single count, capture &...
Page 80 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Must be set to 0 Start trigger and capture trigger settings for channel n STS002-STS000: 00H: Only software triggering is active at the start (no other trigger source is selected). 01H: Use the active edge of the TI00 pin input for start triggering and capture triggering.
Page 81 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit For a detailed description of MD003- MD000, see the following table Setting of channel n Count operation of Corresponding functions operation mode Interval timer/square wave output/ Interval timer mode Frequency divider function/PWM output Count down (master) Capture mode...
Page 82 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-12: Timer channel 0 mode register TMR01 Symbol Description Reset value 31:16 Reserved Selection of channel n operation clock (F CKS011- CKS010: 00H: The operation clock CKm0 set by the timer clock select register m (TPSm).
Page 83 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit width) Start trigger: falling edge, capture trigger: rising edge 03H: Double edge (when measuring high-level width) Start trigger: rising edge, capture trigger: falling edge Reserved Setting of channel n operation mode and interrupt MD013- MD010: Setting of channel n operation mode and interrupt MD013- MD010:...
Page 84 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit No timer interrupt is generated when counting starts (the output of • Interval timer mode (0, 0, 0) the timer does not change). • Capture mode (0, 1, 0) A timer interrupt is generated when counting starts (the output of the timer also changes).
Page 85 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit or multi-channel operation. 01H: Used as a master control channel for multi- channel operation. Channel 0 is fixed to “0” (since channel 0 is the highest bit channel, it is used as the master channel regardless of the setting of this bit).
Page 86 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit count operation is valid. No interruption at this time. 0CH: Capture & single count mode, no timer interrupt is generated when counting starts. For a detailed description of MD023- MD020, see the following table Setting of channel n Count operation of Corresponding functions...
Page 87 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation mode (Value set by the MD023 to MD021 Setting of starting counting and interrupt bits (see table above)) No timer interrupt is generated when counting starts (the output of • the timer does not change).
Page 88 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-14: Timer channel 3 mode register TMR03 Symbol Description Reset value 31:16 Reserved Selection of channel n operation clock (F CKS031- CKS030: 00H: The operation clock CKm0 set by the timer clock select register m (TPSm) 01H: The operation clock CKm2 set by the timer clock select register m (TPSm)
Page 89 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit rising edge 03H: Double edge (when measuring high level width) Start trigger: rising edge, capture trigger: falling edge Reserved Setting of channel n operation mode and interrupt MD033-MD030: 00H: Interval timer mode, no timer interrupt is generated at the start of counting.
Page 90 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit output of the timer does not change). The start trigger in the count operation is invalid. No interruption at this time. • Single count mode Note 1 (1, 0, 0) Note 2 The start trigger in the count operation is valid .
Page 91: Timer Status Register Mn (Tsrmn)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer status register mn (TSRmn) 6.2.7 The TSRmn register is a register that indicates the overflow status of the channel n counter. The TSRmn register is valid only in capture mode (MDmn3~MDmn1=010B) and capture & single count mode (MDmn3~MDmn1=110B).
Page 92: Timer Channel Enable Status Register M (Tem)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer channel enable status register m (TEm) 6.2.8 The TEm register is a register that indicates the enable or stop status of each channel timer operation. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and timer channel stop register m (TTm).
Page 93: Timer Channel Start Register M (Tsm)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer channel start register m (TSm) 6.2.9 The TSm register is a trigger register that initializes the timer counter register mn (TCRmn) and sets the start of counting operation for each channel. If each bit is set to “1”, the corresponding bit of the timer channel enable status register m (TEm) is set to “1”.
Page 94 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit until the TSmn bit is set to “1”: When the TImn pin noise filter is valid (TNFENmn=1): 4 operating clocks (F When the TImn pin noise filter is invalid (TNFENmn=0): 2 operating clocks (F Note 3: The TSm register always reads “0”.
Page 95: Timer Channel Stop Register M (Ttm)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer channel stop register m (TTm) 6.2.10 The TTm register is a trigger register to set the count stop of each channel. If each bit is set to “1”, the corresponding bit in the timer channel enable status register m (TEm) is cleared to “0”.
Page 96: Timer Input/Output Output Select Register (Tios0)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer input/output output select register (TIOS0) 6.2.11 The TIOS0 register is used to make selections for the inputs and outputs of unit 0. The timer inputs for channel 0 and channel 1 and the timer output for channel 2 of unit 0 are selected. The TIOS0 register is set by an 8-bit memory manipulation instruction.
Page 97: Timer Output Enable Register M (Toem)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer output enable register m (TOEm) 6.2.12 The TOEm register is a register that sets to enable or disable the timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
Page 98: Timer Output Register M (Tom)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer output register m (TOm) 6.2.13 The TOm register is a buffer register for each channel timer output. The bit value of this register is output from the output pin (TOmn) of each channel timer. The TOmn bit of this register can be rewritten by software only when timer output is disabled (TOEmn=0).
Page 99: Timer Output Level Register M (Tolm)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer output level register m (TOLm) 6.2.14 The TOLm register is a register that controls the output level of each channel timer. When timer output (TOEmn=1) is enabled and the multi-channel linkage operation function (TOMmn=1) is used, the set and reset timing of the timer output signal reflects the inverse setting of each channel n performed by this register.
Page 100: Timer Output Mode Register M (Tomm)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer output mode register m (TOMm) 6.2.15 The TOMm register is a register that controls the output mode of each channel timer. When used as an independent channel operation function, the corresponding bit of the using channel should be set to “0”. When used as a multi-channel linkage operation function (PWM output, single trigger pulse output and multiple PWM output), the corresponding bit of the master channel is "0"...
Page 101: Noise Filter Enable Register 1 (Nfen1)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Noise filter enable register 1 (NFEN1) 6.2.16 The NFEN1 register sets whether the noise filter is used for the input signals of the timer input pins of each channel of Unit 0. For pins that require noise removal, the corresponding bit must be set to “1” to make the noise filter effective.
Page 102: Registers Controlling Port Functions Of Timer Input/Output Pins
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Registers controlling port functions of timer input/output 6.2.17 pins When using the General-Purpose Timer Unit, the output pins of Timer0 are multiplexed to a fixed port, and the input pins of Timer0 can be configured to any port. For details, refer to “Chapter 3 Pin Function”. When multiplexing the output pin of Timer 0 to a port, the corresponding bit of the Port Mode Control Register (PMCxx), the bit of the Port Mode Register (PMxx), and the bit of the Port Register (Pxx) must be set to “0”.
Page 103: Basic Rules Of General-Purpose Timer Unit
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit 6.3 Basic rules of general-purpose timer unit Basic rules of multi-channel linkage operation function 6.3.1 The multi-channel linkage function is a function that combines a master channel (a reference timer that counts cycles) and a slave channel (a timer that operates in compliance with the master channel), and several rules need to be observed when using it.
Page 104 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Example 1 Timer4 Channel group 1 (Multi-channel linkage function) CK00 Channel 0: Master Channel 1: Slave Channel group 2 (Multi-channel linkage function) CK01 Channel 2: Master Channel 3: Slave Example 2 Timer4 Channel group 1 (Multi-channel linkage operation function)
Page 105: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Basic rules of 8-bit timer operation function (channels 1 6.3.2 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-bit timer channels. This function can only be used for channels 1 and 3, and there are several rules for using it.
Page 106: Count Clock (F Tclk )
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit 6.4 Operation of counter Count clock (F 6.4.1 TCLK The count clock of the general-purpose timer unit (F ) can be selected by the CCSmn bit of the timer TCLK mode register mn (TMRmn) for any of the following clocks: ①...
Page 107 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (F ) is a signal that detects an active edge of the TImn pin input signal and is TCLK synchronized with the next F rising edge.
Page 108: Start Timing Of Counter
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Start timing of counter 6.4.2 The timer count register mn (TCRmn) enters the operation enable state by setting TSmn bit of the timer channel start register m (TSm). Execution from the counting enable state to the start of the timer count register mn (TCRmn) is shown in Table 6-26.
Page 109: Operation Of Counter
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation of counter 6.4.3 The following describes the counter operation for each mode. (1) Operation of interval timer mode ① The operation enable state is entered by writing “1” to the TSmn bit (TEmn=1). The timer count register mn (TCRmn) remains at its initial value until a count clock is generated.
Page 110 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit (2) Operation of event counter mode ① The timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn=0). ② The operation enable state is enabled by writing "1" to the TSmn bit (TEmn=1). ③...
Page 111 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit (3) Operation of capture mode (interval measurement of input pulses) ① The operation enable state is entered by writing “1” to the TSmn bit (TEmn=1). ② The timer count register mn (TCRmn) remains at its initial value until a count clock is generated. ③...
Page 112 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit information about the start of the count timing, set MDmn0 to “1” so that an interrupt can be generated at the start of the count. Note 2: This is a timing without the noise filter. If the noise filter is used, the edge detection is delayed by 2 more F cycles (3~4 cycles in total) from the TImn input.
Page 113 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit (4) Operation of single count mode ① The operation enable state is entered by writing "1" to the TSmn bit (TEmn=1). ② The timer count register mn (TCRmn) remains the initial value until a start trigger signal is generated.
Page 114 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit (5) Operation of capture & single count mode (measurement of high-level width) ① The operation enable state is entered by writing "1" to the TSmn bit of the timer channel start register m (TSm)(TEmn=1).
Page 115: Channel Output (Tomn Pin) Control
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit 6.5 Channel output (TOmn pin) control TOmn pin output circuit configuration 6.5.1 Figure 6-9: Output circuit configuration TOmn register Interrupt signal of master channel （INTTMmn） Interrupt signal of slave Tomn pin channel （INTTMmp）...
Page 116: Tomn Pin Output Setting
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit TOmn pin output setting 6.5.2 The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-10: State change from setting timer output to start of operation TCRmn Random value (“FFFFH after reset ) (counter)
Page 117: Cautions On Channel Output Operation
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Cautions on channel output operation 6.5.3 (1) Change of setting values for TOm, TOEm, TOLm, TOMm registers in timer operation The operation of the timer (timer count register mn (TCRmn) and timer data register mn (TDRmn)) and the Tomn output circuit are independent.
Page 118 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit When operation starts with slave channel output mode (TOMmn = 1) setting (PWM output)) In slave channel output mode (TOMmn=1), the active level depends on the setting of timer output level register m (TOLmn).
Page 119 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition.
Page 120 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-14: Set/reset timing operation status (1) Basic operation timing TCLK INTTMmn Master channel Internal reset signal Tomn pin/TOmn Toggle Toggle Internal reset signal Delay 1 clock cycle INTTMmp Slave channel Internal reset signal Tomp Pin/TOmp Reset...
Page 121 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Note 2: Internal set signal: TOmn pin set signal Note 3: m: unit number (m=0) n: channel number n=0~3 (master channel: n=0, 2) p: slave channel number n=0: p=1, 2, 3 n=2: p=3 www.mcu.com.cn 121 / 407 Rev.1.0.1...
Page 122: One-Time Operation Of Tomn Bit
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit One-time operation of TOmn bit 6.5.4 Like the timer channel start register m (TSm), the timer output register m (TOm) has the set bits (TOmn) for all channels and can therefore operate the TOmn bits for all channels at once. Table 6-27: One-time operation example of TO0n bit Before writing TO03...
Page 123: Timer Interrupt And Tomn Pin Output When Counting Starts
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Timer interrupt and TOmn pin output when counting 6.5.5 starts In interval timer mode or capture mode, the MDmn0 bit of timer mode register mn (TMRmn) is the bit that sets whether to generate a timer interrupt when counting starts. When the MDmn0 bit is “1”, the start timing of the count can be known by generating a timer interrupt (INTTMmn).
Page 124: Control Of Timer Input (Timn)
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit 6.6 Control of timer input (TImn) Structure of TImn pin input circuit 6.6.1 The signal from the timer input pins is input to the timer control circuit via a noise filter and the edge detection circuit.
Page 125: Cautions On Channel Input Operation
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Cautions on channel input operation 6.6.3 When set to not use the timer input pin, no operating clock is provided to the noise filter circuit. Therefore, the following wait time is required from the time set to use the timer input pin to the time the channel corresponding to the timer input pin is set to operate the enable trigger.
Page 126: Independent Channel Operation Function Of General-Purpose Timer Unit
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit 6.7 Independent channel operation function of general-purpose timer unit Operation as interval timer/square wave output 6.7.1 (1) Interval timer It can be used as a reference timer to generate INTTMmn (timer interrupt) at fixed intervals. The interrupt generation period can be calculated using the following equation: INTTMmn (timer interrupt) generation period = count clock period ...
Page 127 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-19: Example of basic timing operating as an interval timer/square wave output (MDmn0=1) CKm1 Operation Output Note Timer counter register mn clock TOmn pin control (TCRmn) CKm0 circuit Interrupt Timer data register mn Interrupt signal control TSmn...
Page 128 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-21: Example of register setting contents for interval timer/square wave output (a) Timer mode register mn (TMRmn) Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn Operation mode of channel n 000B: Interval timer...
Page 129 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-28: Procedure for interval timer/square wave output function Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register) Set the TM4mEN bit of peripheral enable register 0(PER0) The input clock of timer unit m is in the providing state.
Page 130: Operation As External Event Counter
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation as external event counter 6.7.2 It can be used as an event counter to count the active edges (external events) detected on the TImn pin input and generate an interrupt if the specified count value is reached. The specified count value can be calculated using the following equation: Specified count value = TDRmn set value + 1 In the event counter mode, the timer count register mn (TCRmn) is used as a decrement counter.
Page 131 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-23: Example of register contents setting in external event counter mode (a) Timer mode register mn (TMRmn) Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn Operation mode of channel n...
Page 132 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-29: Procedure for external event counter function Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register) Timer4 Set the TM4mEN bit of peripheral enable register 0(PER0) The input clock of timer unit m is in the providing state and...
Page 133: Operation As Frequency Divider
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation as frequency divider 6.7.3 The clock input from the TI00 pin can be divided and used as a divider for the output of the TO00 pin. The divided clock frequency of the TO00 output can be calculated using the following equation: •...
Page 134 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit TE00: Bit 0 of timer channel enable status register (TE0) TI00: TI00 pin input signal TCR00: Timer count register 00 (TCR00) TDR00: Timer data register 00 (TDR00) TO00: TO00 pin output signal Figure 6-25: Example of register contents setting when operating as a frequency divider (a) Timer mode register 00 (TMR00) CKS001...
Page 135 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-30: Procedure for frequency divider function Software operation Hardware status The input clock of timer unit 0 is in the stop-providing state. (Stop providing clock, cannot write to each register) Timer4 Set the TM4mEN bit of peripheral enable register 0(PER0) The input clock of timer unit 0 is in the providing state and...
Page 136: Operation As Input Pulse Interval Measurement
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation as input pulse interval measurement 6.7.4 The count value can be captured at the active edge of TImn and the interval between TImn input pulses can be measured. The software operation (TSmn=1) can also be set to capture the count value during the period when the TEmn bit is “1”.
Page 137 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Note 2: TSmn: Bit n of timer channel start register m (TSm) TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal Note 3: TCRmn: Timer count register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) OVF: Bit0 of timer status register mn (TSRmn) www.mcu.com.cn...
Page 138 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-27: Example of register contents setting in measuring input pulse interval (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn 注 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn Operation mode of channel N 010B: capture mode...
Page 139 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-31: Procedure for input pulse interval measurement function Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register) Timer4 Set the TM4mEN bit of the peripheral enable register The input clock of timer unit m is in the providing state and...
Page 140: Operation As Input Signal High-/Low-Level Width Measurement
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation as input signal high-/low-level width 6.7.5 measurement Note: When used as a LIN-bus support function, bit1 (ISC1) of the Input Switching Control Register (ISC) must be set to “1” and RxD0 should be used instead of TImn in the following description. The signal width (high-/low-level width) of TImn can be measured by starting counting at one edge of the input to the TImn pin and capturing the count value at the other edge.
Page 141 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-28: Example of basic timing operating as high-/low-level width measurement of input signal TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn 0000H INTTMmn Note 1: m: unit number (m= 0) n: channel number (n=0~3) Note 2: TSmn: Bit n of timer channel start register m (TSm) TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal...
Page 142 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-29: Example of register contents setting in measuring high-/low-level width of input signal (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn Note STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn...
Page 143 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-32: Procedure for high-/low-level width measurement function of input signal Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register) Timer4 Set the TM4mEN bit of the peripheral enable register The input clock of timer unit m is in the providing state and...
Page 144: Operation As Delay Counter
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation as delay counter 6.7.6 The count can be decremented by the active edge detection (external event) of the TImn pin input and INTTTMmn (timer interrupt) is generated at any set interval. During the period when the TEmn bit is “1”, the TSmn bit can be set to “1”...
Page 145 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-31: Example of register contents setting for delay counter function (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn Note STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn0 MDmn3 MDmn2 MDmn1 TMRmn Operation mode of channel N 100B: Single counting mode Start trigger during operation...
Page 146 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-33: Procedure for delay counter function Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register) Timer4 Set the TM4mEN bit of the peripheral enable register The input clock of timer unit m is in the providing state and...
Page 147: Multi-Channel Linkage Operation Function For General Purpose Timer Unit
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit 6.8 Multi-channel linkage operation function for general purpose timer unit Operation as single trigger pulse output function 6.8.1 Using the 2 channels in pairs, a single trigger pulse with any delay pulse width can be generated from the input of the TImn pin.
Page 148 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-32: Block diagram of operation as single trigger pulse output function Master channel (Single count mode) CKm1 Operation Timer count register mn clock CKm0 (TCRmn) TNFENxx TSmn Interrupt signal Timer data register mn Interrupt control circuit (TDRmn)
Page 149 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-33: Example of basic timing operating as a single trigger pulse output function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp...
Page 150 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-34: Example of register contents setting for single trigger pulse output function (master channel) (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn...
Page 151 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-35: Example of register contents setting for single trigger pulse output function (slave channel) (a) Timer mode register mp (TMRmp) CKSmp1 CKSmp0 CCSmp Note STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0...
Page 152 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-34: Procedure for single trigger pulse output function (1/2) Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register) Timer4 Set the TM4mEN bit of the peripheral enable register The input clock of timer unit m is in the providing state and...
Page 153 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-34: Procedure for single trigger pulse output function (2/2) Software operation Hardware status Set the TOEmp bit (slave) to "1" (restart operation only). The TEmn and TEmp bits are set to 1 and the master Set the TSmn (master) and TSmp (slave) bits of the Timer channel enters the start trigger detection (the valid edge of Channel Start Register m (TSm) to "1"...
Page 154: Operation As Pwm Function
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation as PWM function 6.8.2 By using the 2 channels in pairs, pulses of any period and duty cycle can be generated. The period and duty cycle of the output pulses can be calculated using the following equations: Pulse period = {TDRmn (master) set value +1} ...
Page 155 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-36: Block diagram of operation as PWM function Master channel (Interval timer mode) CKm1 Operation clock Timer counter CKm0 register mn (TCRmn) interrupt Timer data Interrupt signal control TSmn register mn (TDRmn) (INTTMmn) circuit Slave channel...
Page 156 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-37: Example of basic timing operating as PWM function TSmn TEmn FFFFH TCRmn 0000H Master channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TOmp INTTMmp Note 1: m: unit number (m= 0) n: master channel number (n=0, 2) p: slave channel number (n=0: p=1, 2, 3, n=2: p=3) Note 2: TSmn, TSmp: Bit n of timer channel start register m (TSm), p TEmn, TEmp: Bit n of timer channel enable status register m (TEm), p...
Page 157 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-38: Example of basic timing operating as PWM function (a) Timer mode register mn (TMRmn) TSmn TEmn FFFFH TCRmn 0000H Master channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp...
Page 158 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit (e) Timer output mode register m (TOMm) bit n TOMm TOMmn 0: Sets master channel output mode. Note 1: m: unit number (m=0, 1) n: master channel number (n=0, 2) Note 2: TMRm2: MASTERmn=1 TMRm0: Fixed to “0”.
Page 159 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-39: Example of register contents setting for PWM function (slave channel) (a) Timer mode register mp (TMRmp) CKSmp1 CKSmp0 CCSmp Note STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0 TMRmp Operation mode of channel p 100B: Single counting mode...
Page 160 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-35: Procedure for the PWM function (1/2) Software operation Hardware status The input clock of timer unit m is in the stop-providing state. Timer4 (Stop providing clock, cannot write to each register) Set the TM4mEN bit of the peripheral enable register The input clock of timer unit m is in the providing state and 0(PER0) to "1”.
Page 161 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-35: Procedure for the PWM function (2/2) Software operation Hardware status Set the TOEmp bit to “1” (only limited to restart operation). Set both the TSmn bit (master) and TSmp bit (slave) of the timer channel start register m (TSm) to "1".
Page 162: Operation As Multiple Pwm Output Function
CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Operation as multiple PWM output function 6.8.3 This is a function that extends the PWM function and uses multiple slave channels for multiple PWM outputs with different duty cycles. For example, when using 2 slave channels in pairs, the period and duty cycle of the output pulse can be calculated by using the following equation: Pulse period = {TDRmn(master) set value +1} ...
Page 163 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-40: Block diagram of operation as multiple PWM output function (output two types of PWMs) Master channel (Interval timer mode) CKm1 Operation clock Timer count register mn CKm0 (TCRmn) Interrupt Timer data register mn Interrupt signal control...
Page 164 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-41: Example of basic timing operating as multiple PWM output function (output two types of PWMs) TSmn TEmn FFFFH TCRmn 0000H Master channel TDRmn TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel 1...
Page 165 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Note 2: TSmn, TSmp, TSmq : Bit n of timer channel start register m (TSm), p, q TEmn, TEmp, TEmq: Bit n of timer channel enable status register m (TEm), p, q TCRmn, TCRmp, TCRmq: Timer count registers mn, mp, mq (TCRmn, TCRmp, TCRmq) TDRmn, TDRmp, TDRmq: Timer data registers mn, mp, mq (TDRmn, TDRmp, TDRmq) TOmn, TOmp, TOmq: TOmn, TOmp, TOmq pin output signals...
Page 166 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-42: Example of register contents setting for multiple PWM output function (master channel) (a) Timer mode register mn (TMRmn) CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TMRmn Note...
Page 167 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Figure 6-43: Example of register contents setting for multiple PWM output function (slave channel) (output two types of PWMs) (a) Timer mode registers mp, mq (TMRmp, TMRmq) CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1...
Page 168 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-36: Procedure for the multiple PWM output function (output two types of PWMs) (1/2) Software operation Hardware status The input clock of timer unit m is in the stop-providing state. (Stop providing clock, cannot write to each register) Timer4 Set the TM4mEN bit of the peripheral enable register...
Page 169 CMS32M65xx User Manual | Chapter 6 General-Purpose Timer Unit Table 6-36: Procedure for the multiple PWM output function (output two types of PWMs) (2/2) Software operation Hardware status (Sets the TOEmp and TOEmq (slave) bits to 1 only when resuming operation.) The TSmn bit (master), and TSmp and TSmq (slave) bits TEmn = 1, TEmp, TEmq = 1 Start...
Page 170: Chapter 7 Lsitimer 12-Bit Interval Timer
CMS32M65xx User Manual | Chapter 7 LSITIMER 12-Bit Interval Timer Chapter 7 LSITIMER 12-Bit Interval Timer 7.1 Function of 12-bit interval timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from sleep mode, deep sleep mode and partial power-down mode.
Page 171: 12-Bit Interval Timer Control Register (Con0)
CMS32M65xx User Manual | Chapter 7 LSITIMER 12-Bit Interval Timer 7.4 12-bit interval timer control register (CON0) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The CON0 register can be set by a 12-bit memory manipulation instruction.
Page 172: 12-Bit Interval Timer Operation
CMS32M65xx User Manual | Chapter 7 LSITIMER 12-Bit Interval Timer 7.5 12-bit interval timer operation 12-bit interval timer operation timing 7.5.1 The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate a 12-bit interval timer that repeatedly generates interrupt requests (INTIT).
Page 173: Start Of Count Operation And Re-Enter To Sleep Mode After Returned From Sleep Mode
CMS32M65xx User Manual | Chapter 7 LSITIMER 12-Bit Interval Timer Start of count operation and re-enter to sleep mode after 7.5.2 returned from sleep mode When setting the RINTE bit after returned from sleep mode and entering sleep mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.
Page 174: Chapter 8 Clock Output/Buzzer Output Controller
CMS32M65xx User Manual | Chapter 8 Clock Output/Buzzer Output Controller Chapter 8 Clock Output/Buzzer Output Controller 8.1 Function of clock output/buzzer output controller Clock output is the function of outputting the clock provided to the peripheral IC, and buzzer output is the function of outputting the buzzer frequency square wave.
Page 175: Structure Of Clock Output/Buzzer Output Controller
CMS32M65xx User Manual | Chapter 8 Clock Output/Buzzer Output Controller 8.2 Structure of clock output/buzzer output controller The clock output/buzzer output controller consists of the following hardware. Table 8-1: Structure of clock output/buzzer output controlle Item Structure Clock output select registers n (CKSn) Control registers Port mode control register (PMCxx), Port mode register (PMxx), Port multiplexing control register (PxxCFG)
Page 176: Register Mapping
CMS32M65xx User Manual | Chapter 8 Clock Output/Buzzer Output Controller 8.3 Register mapping (CKS0/1 base address = 0x4004_0FA5) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value CKS0 0x000 Clock output select register 0 CKS1 0x001 Clock output select register 1 Clock output select register (CKS0)
Page 177: Clock Output Select Register (Cks1)
CMS32M65xx User Manual | Chapter 8 Clock Output/Buzzer Output Controller Clock output select register (CKS1) 8.3.2 The register sets output enable/disable for clock output or for the buzzer frequency output pin (CLKBUZ1), and sets the output clock. Select the clock to be output from the CLKBUZ1 pin by using the CKS1 register. The CKS1 register is set by a 32-bit memory manipulation instruction.
Page 178: Registers For Configuring Clock Output/Buzzer Output Port Functions
CMS32M65xx User Manual | Chapter 8 Clock Output/Buzzer Output Controller 8.4 Registers for configuring clock output/buzzer output port functions This product has two clock output/buzzer output pins, CLKBUZ0 can be used as clock output or buzzer output from P20, P25, P00, P06, P22, and CLKBUZ1 can be used as clock output or buzzer output from P21, P25, P06, P22.
Page 179: Operation Of Clock Output/Buzzer Output Controller
CMS32M65xx User Manual | Chapter 8 Clock Output/Buzzer Output Controller 8.5 Operation of clock output/buzzer output controller One pin can be used as clock output or buzzer output. The CLKBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0). The CLKBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1).
Page 180: Chapter 9 Watchdog Timer
CMS32M65xx User Manual | Chapter 9 Watchdog Timer Chapter 9 Watchdog Timer 9.1 Function of watchdog timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock (F The watchdog timer is used to detect an inadvertent program loop.
Page 181 CMS32M65xx User Manual | Chapter 9 Watchdog Timer Figure 9-1: Block diagram of watchdog timer WDTINT of option bytes Interval time controller Interval time (000C0H) (count value overflow time x3/4 +1/2F WDCS2~WDCS0 of option bytes (000C0H) Inter Overflow signal counter Clock input Selector (17-bit)
Page 182: Register Mapping
CMS32M65xx User Manual | Chapter 9 Watchdog Timer 9.3 Register mapping (WDTE base address = 0x4002_1001) Register Offset value Description Reset value WDTE 0x000 Watchdog timer enable register 0x1A/0x9A (LOCKCTL base address = 0x4002_0405) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description...
Page 183: Lockup Control Register (Lockctl)
CMS32M65xx User Manual | Chapter 9 Watchdog Timer LOCKUP control register (LOCKCTL) 9.3.2 The LOCKCTL register is a configuration register for controlling the Cortex-M0+ LockUp function to operate the watchdog timer, and PRCR is its write-protect register. The LOCKCTL register is set by an 8-bit memory manipulation instruction. After generating a reset signal, the value of the LOCKCTL register changes to “01H”.
Page 184: Watchdog Configuration Register (Wdtcfg0/1/2/3)
CMS32M65xx User Manual | Chapter 9 Watchdog Timer Watchdog configuration register (WDTCFG0/1/2/3) 9.3.4 The WDTCFGx configuration register is a register that forces the watchdog timer to operate or not. The WDTCFGx register is set by an 8-bit register manipulation instruction. After a reset signal is generated, the value of the WDTCFGx register changes to “00H”.
Page 185: Operation Of Watchdog Timer
CMS32M65xx User Manual | Chapter 9 Watchdog Timer 9.4 Operation of watchdog timer Operational control of watchdog timer 9.4.1 1. When using the watchdog timer, set the following items by option byte (000C0H): (1) The bit 4 (WDTON) of the option byte (000C0H) must be set to "1" to enable the watchdog timer count to operate (the counter starts operating after the reset is released) (refer to Chapter 29 Option Byte for details).
Page 186: Setting Overflow Time Of Watchdog Timer
CMS32M65xx User Manual | Chapter 9 Watchdog Timer Setting overflow time of watchdog timer 9.4.2 Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing “ACH”...
Page 187: Setting Window Open Period Of Watchdog Timer
CMS32M65xx User Manual | Chapter 9 Watchdog Timer Setting window open period of watchdog timer 9.4.3 Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows: •...
Page 188: Setting Watchdog Timer Interval Interrupt
CMS32M65xx User Manual | Chapter 9 Watchdog Timer Setting watchdog timer interval interrupt 9.4.4 Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be generated when 75%+1/2F of the overflow time is reached. Table 9-5: Setting of watchdog timer interval interrupt WDTINT Use of watchdog timer interval interrupt...
Page 189: Chapter 10 Divsqrt Unit
CMS32M65xx User Manual | Chapter 10 DIVSQRT Unit Chapter 10 DIVSQRT Unit 10.1 Overview The chip contains a 32-bit/32-bit hardware divider and a 32-bit hardware square root extractor. 10.2 Features ◆ Support signed/unsigned division and square root operations. ◆ Both quotient and remainder are 32 bits wide. ◆...
Page 190: Register Mapping
CMS32M65xx User Manual | Chapter 10 DIVSQRT Unit 10.4 Register mapping (DIVSQRT base address = 0x4006_4380) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value 0x000 Operation unit control register ALUA 0x004 Operation unit data A register ALUB 0x008 Operation unit data B register...
Page 191: Register Description
CMS32M65xx User Manual | Chapter 10 DIVSQRT Unit 10.5 Register description DIVSQRT control register (DIVSQRTCON) 10.5.1 Symbol Description Reset value 31:5 Reserved Operation mode select bit MODE 0: Division mode 1: Square root mode Operation completion indicator bit 0: Operation is ongoing READY Operation is completed or is in idle state...
Page 192: Chapter 11 Timer (Timer0/1)
CMS32M65xx User Manual | Chapter 11 Timer (TIMER0/1) Chapter 11 Timer (TIMER0/1) 11.1 Overview It contains two programmable 32-bit/16-bit counters, TIMER0/TIMER1, providing users with convenient timer counting functions. 11.2 Features ◆ Configurable 32-bit/16-bit count down counter. ◆ Each timer has an independent prescaler. ◆...
Page 193: Delayed Load Function
CMS32M65xx User Manual | Chapter 11 Timer (TIMER0/1) Delayed load function 11.3.4 When data is written to the load register, the counter does not continue to decrement but loads the initial value from the load register on the next TIMER_CLK rising edge and then starts decrementing. When data is written to the delayed load register, the data is written into the load register on the next TIMER_CLK rising edge.
Page 194: Register Mapping
CMS32M65xx User Manual | Chapter 11 Timer (TIMER0/1) 11.4 Register mapping (Timer0 base address= 0x4006_1000, Timer1 base address= 0x4006_1100) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value 0x000 Timer control register 0x20 LOAD 0x004 Timer load register 0x008 Timer current value register...
Page 195: Register Description
CMS32M65xx User Manual | Chapter 11 Timer (TIMER0/1) 11.5 Register description Timer control register (CON0/1) 11.5.1 Symbol Description Reset value 31:8 Reserved Timer enable bit TMREN 0: Disable 1: Enable Timer mode select bit TMRMS 0: Continuous counting mode 1: Periodic counting mode Timer interrupt enable bit TMRIE 0: Disable interrupts...
Page 196: Timer Interrupt Source Status Register (Ris0/1)
CMS32M65xx User Manual | Chapter 11 Timer (TIMER0/1) Timer interrupt source status register (RIS0/1) 11.5.4 Symbol Description Reset value 31:1 Reserved Timer interrupt source status TMRxRIS 1: An interrupt is generated 0: No interrupts generated Timer enabled interrupt status register (MIS0/1) 11.5.5 Symbol Description...
Page 197: Chapter 12 Capture/Compare/Pwm Module (Ccp0/1)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) Chapter 12 Capture/Compare/PWM Module (CCP0/1) 12.1 Overview It contains 2 sets of CCP modules (CCP0/CCP1), each set of CCP corresponds to two channels A and B. CCP0 corresponds to CCP0A/CCP0B, CCP1 corresponds to CCP1A/CCP1B. 12.2 Features ◆...
Page 198: Function Description
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) 12.3 Function description Pulse Width Modulation (PWM) 12.3.1 Each CCP can output two PWMs: PWMxA and PWMxB, which share one cycle, and the output duty cycle can be set independently by CCPDxA and CCPDxB. The polarity of PWMxA/PWMxB outputs can be set by PWMxAO/PWMxBO bits, and correspond to CCPxA/CCPxB channel outputs respectively.
Page 199: Capture Mode 0
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) Capture mode 0 12.3.3 This capture mode is an external capture mode. Each group of CCP can be set to use either channel A or channel B as the external capture signal pin. After setting CCPRUNx, the 16-bit counter counts down from 0xFFFF.
Page 200 CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) In capture mode 1, PWM output and external capture mode 0 are disabled for CCP0 and CCP1. This mode requires CCP1 to operate in counting mode, and the capture operation loads the value of CCP1’s counter into the corresponding registers.
Page 201: Capture Mode 2
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) Capture mode 2 12.3.5 This capture mode is external capture and is mainly used to capture PWM waveform information input from external sources. In capture mode 2, channels CAP2 and CAP3 are mapped to CAP1, meaning that CAP1-3 are the same capture channel, and CAP0 is disabled.
Page 202 CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) e: CAP1-3 share the same capture channel, and capture operations will simultaneously generate corresponding capture flags on CAP1-CAP3. Input(PWM) PWMLOADx(New) PWMLOADx(Old) 16-bit counter value load load CAP3/ CAP1 CAP2 CAP2 CAP3/ CAP1 CAP1 www.mcu.com.cn...
Page 203: Pwm Configuration Process
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) PWM configuration process 12.3.6 ⚫ Configure PWM control registers by setting the prescaler, selecting the PWM mode, and enabling PWM. ⚫ Configure the PWM period by writing to the CCPLOADx register. ⚫...
Page 204: Register Mapping
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) 12.4 Register mapping (CCP base address = 0x4006_4280) RO: read only; WO: write only; R/W: read/write. Register Offset value Description Reset value CCP0 Control Register CCPCON0 0x000 (P1B) CCP0 Reload Register CCPLOAD0 0x004 (P1A)
Page 205: Register Description
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) 12.5 Register description CCPx control register (CCPCONx) (x=0,1) 12.5.1 Symbol Decription Reset value 31:10 Reserved Square wave mode enable bit for channel B (valid for PWM mode) CCPxZBEN 0: Disable Enable, and duty cycle loaded value is LOADx/2 Square wave mode enable bit for channel A (valid for PWM mode)
Page 206: Ccp Reload Register (Ccploadx) (X=0,1)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) CCP reload register (CCPLOADx) (x=0,1) 12.5.2 Symbol Description Reset value 31:17 Reserved CCP0 module: PWM mode: Reload enable bit Counter reload value is 0xFFFF Counter reload value is CCP0LOAD Capture mode 0: Counter reload value is 0xFFFF Counter reload value is...
Page 207: Ccpxb Data Register (Ccpdxb) (X=0,1)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) CCPxB data register (CCPDxB) (x=0,1) 12.5.4 Symbol Description Reset value 31:17 Reserved PWMxB output polarity selection PWMxBOP 0: Normal output 1: Inverted output PWM mode: PWMxB duty cycle 15:0 CCPxBDATA Capture mode Capture result CCP interrupt enable register (CCPIMSC) 12.5.5...
Page 208: Ccp Interrupt Source Status Register (Ccpris)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) CCP interrupt source status register (CCPRIS) 12.5.6 Symbol Description Reset value 31:12 Reserved CAP3 capture interrupt status bit CAP3RIS 1: An interrupt is generated 0: No interrupt is generated CAP2 capture interrupt status bit CAP2RIS 1: An interrupt is generated 0: No interrupt is generated...
Page 209: Ccp Enabled Interrupt Status Register (Ccpmis)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) CCP enabled interrupt status register (CCPMIS) 12.5.7 Symbol Description Reset value 31:12 Reserved CAP3 enabled capture interrupt status bit Interrupt enable and an interrupt is CAP3MIS generated 0: No interrupt is generated CAP2 enabled capture interrupt status bit Interrupt enable and an interrupt is CAP2MIS...
Page 210: Ccp Interrupt Clear Register (Ccpiclr)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) CCP interrupt clear register (CCPICLR) 12.5.8 Symbol Description Reset value Reserved 31:12 Clear CAP3 capture interrupt status bit CAP3ICLR Write 1 to clear the CAP2 capture interrupt CAP2ICLR status bit Write 1 to clear the CAP1 capture interrupt CAP1ICLR status bit Write 1 to clear the CAP0 capture interrupt...
Page 211: Cap Control Register (Capcon)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) CAP control register (CAPCON) 12.5.11 Reset Symbol Description value 31:14 Reserved Capture mode 2 enable bit (only valid for CCP1) 0: -- CAPEN2 Capture Mode 2 enable bit, and disable Capture Mode 1 Capture mode 1 enable bit 0: CCP0/CCP1 in PWM mode or Capture Mode 0...
Page 212 CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) 0x3: Both Edges CAP1 capture mode selection 0x0: Disable CAP1ES 0x1: Rising edge capture 0x2: Falling edge capture 0x3: Both Edges CAP0 capture mode selection 0x0: Disable CAP0ES 0x1: Rising edge capture 0x2: Falling edge capture 0x3: Both Edges www.mcu.com.cn...
Page 213: Cap Channel Select Register (Capchs)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) CAP channel select register (CAPCHS) 12.5.12 Symbol Description Reset value 31:17 Reserved ECAP capture channel group selection ECAPS 0: Select ECAP00-ECAP02 1: Select ECAP10-ECAP13 CAP3 capture channel selection 0x0: ECAPx0 (x=0 or 1, determined by ECAPS) 0x1: ECAPx1 0x2: ECAPx2...
Page 214: Cap Data Register (Cap0Data)
CMS32M65xx User Manual | Chapter 12 Capture/Compare/PWM Module (CCP0/1) CAP data register (CAP0DATA) 12.5.13 Symbol Description Reset value Read: Capture mode 2: After capturing, store CAPXDATA = Capture value of CAP1 - Capture value of CAP3. Other: - 31:16 CAPXDATA Write: Capture mode 2: - Other: 0x55aa, generate a capture operation for CAPn.
Page 215: Chapter 13 Enhanced Pwm (Epwm)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Chapter 13 Enhanced PWM (EPWM) 13.1 Overview The EPWM supports six PWM generators which can be configured as six independent PWM outputs, (EPWM0-EPWM5), or as three complementary PWM pairs (EPWM0-EPWM1, EPWM2-EPWM3, EPWM4- EPWM5) with three programmable dead-time generators.
Page 216: Function Description
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) 13.3 Function description Explanation of related terms: Period Point: When the counter CNTn counts to be equal to the period PERIODn, it is called the period point. The interrupt generated is PIFn. Zero Point: When the counter CNTn counts to 0, it is called the zero point.
Page 217: Block Diagram
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Block diagram 13.3.1 Figure 13-1: The signal of IPGn is the signal of EPWMn before remapping Counting control Output control Channel LOADENn remapping PIFn/ZIFn PERIODn BufferPn EN_DTn.n+1 MODE Compare Compar PWMn CLRCNTn GROUPE 16bit...
Page 218: Complementary Output Mode
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Complementary output mode 13.3.4 In complementary output mode, the 6 PWM channels are divided into 3 pairs: 1 pair for EPWM0 and EPWM1, 1 pair for EPWM2 and EPWM3, and 1 pair for EPWM4 and EPWM5. EPWM0-EPWM1 operate according to the period/duty cycle data of EPWM0, EPWM0 and EPWM1 waveforms are inverted.
Page 219: Load Update Mode
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Load update mode 13.3.7 There are two types of counter loading modes: One-shot and Continuous (auto-loading mode). One-shot mode: Cycle duty cycle related data is loaded once at the beginning of the counter, and the output PWM cycle is related to the loading method.
Page 220 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) In the register EPWMCON3, LOADTYPn (0-5) can be set to determine the loading method and the interrupt generation method for the zero point/period point: LOADTYEn Center-aligned loading Edge-aligned loading Load and generate zero point and period Load and generate zero point and period point interrupt flags at each zero point or point interrupt flags at each zero point or...
Page 221 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Figure 13-2: Updated block diagram of PWM period/duty cycle loading Center-aligned Edge-Aligned Counter start Counter start Period point LOADTYP Zero point LOADTYP LOADTYP LOADTYP Initial loading www.mcu.com.cn 221 / 407 Rev.1.0.1...
Page 222: Edge-Aligned Counting Mode
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Edge-aligned counting mode 13.3.8 In edge-aligned mode, with counting down method, the 16-bit PWM counter CNTn starts counting down at the beginning of each cycle. It compares with the latched value CMPDATn, and when CNTn=CMPDATn, EPWMn outputs a high-level signal and sets CMPnDIF to 1.
Page 223: Center-Aligned Counting Mode
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Center-aligned counting mode 13.3.9 In center-aligned mode, the counting process starts by counting up and then counts down. Center-aligned mode can be further divided into two types: symmetric counting mode and asymmetric counting mode.
Page 224 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Figure 13-5: Center-aligned counter waveform (symmetric counting) Reload PERIODn with CMPDATn when CNTn counts to zero or center point Center poinit Zero point (Period point) EPWMn clock PERIODn(new) PERIODn(old) CMPDATn(new) CMPDATn(old) CNTn (0->PERIOD->0…) EPWMn...
Page 225 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Figure 13-6: Center-aligned mode asymmetric counting waveform Reload PERIODn/CMPDATn/CMPDDATn when CNTn counts to zero or period point (center point) PERIODn(7FF) CMPDDATn(500) CMPDATn(3FF) PIFn ZIFn UIFn DIFn PWMn PWM period PWM period www.mcu.com.cn 225 / 407 Rev.1.0.1...
Page 226: Independent Counter Compare Function
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Independent counter compare function 13.3.10 During the counting of the PWMn channel counter (CNTn), two digital comparators are provided to compare the counter value with pre-set values. If the counter value equals the pre-set value, an interrupt signal or ADC trigger can be generated.
Page 227 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Center-aligned mode, digital comparator operation method: Figure 13-9: Center-aligned mode, digital comparator operation method Reload PERIODn/CMPDATn/CMPDDATn/CMPTGD0/CMPTGD1 when when CNTn counts to zero or the cycle point (center point). PERIODn(7FF) CMPTGD0(5FF) CMPTGD1(480) CMPDATn(3FF) DC0IF DC1IF...
Page 228: Programmable Dead-Time Generator
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Programmable dead-time generator 13.3.11 The 6-channel PWM can be configured into 3 complementary pairs. In the complementary output mode, the period and duty cycle of PWM1, PWM3, and PWM5 are determined by the corresponding registers of PWM0, PWM2, and PWM4, respectively.
Page 229: Mask And Mask Preset Function
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Mask and mask preset function 13.3.12 EPWM supports the mask function. Each channel of EPWM0-EPWM5 has individual control, and the corresponding control bits for EPWMn are MASKENn and MASKDn (in the MASK register). When MASKENn=0, the EPWMn channel outputs the normal PWM waveform.
Page 230 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Each valid state of HALLST corresponds to a mask preset cache, and there are totally seven mask preset caches: HALLST(HALLEN=1) Corresponding mask preset cache: Mask preset cache 7 Mask preset cache 1 Mask preset cache 2 Mask preset cache 3 Mask preset cache 4...
Page 231 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Figure 13-11: Example of HALL detection timing (this does not represent the actual running waveform) www.mcu.com.cn 231 / 407 Rev.1.0.1...
Page 232: Fault Protection Function (Brake And Recovery Function)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Fault protection function (brake and recovery function) 13.3.14 EPWM supports fault protection function, and BKODn controls the brake threshold for 6 channels. The fault protection function is controlled by the BRKCTL register. The triggering sources for EPWM fault protection are as follows: Level-triggered sources: External BKIN level signal (high or low level)
Page 233 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Pause Mode: Generate fault protection and fault interrupt flags, but the counter continues to operate. To recover the output, revoke the brake signal, execute the fault state clearing operation (BRKCLR=1), and restore normal output at the most recent load update point.
Page 234: Output Status In Debug Mode
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Output status in debug mode 13.3.15 In debug mode, the CPU has two states: operation state and pause state. The operation state is the normal execution state, while the pause state occurs after executing a STOP instruction, reaching a breakpoint, or stepping.
Page 235: Interrupts
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Interrupts 13.3.18 The EPWM unit has eight interrupt sources: ⚫ ZIFn – An interrupt flag generated when the EPWM counter counts to zero. ⚫ UIFn - An interrupt flag generated when the EPWM counter counts up to CMPDATn. ⚫...
Page 236: Register Mapping
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) 13.4 Register mapping (EPWM base address = 0x4006_4200) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Descripton Reset value EPWM Prescaler Register CLKPSC 0x000 (P1B) EPWM Clock Select Register CLKDIV 0x004 (P1B)
Page 237 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) (P1A): When LOCK==55H or AAH, the marked registers allow writing; when it equals any other value, writing is prohibited. (P1B): When LOCK==55H, the marked registers allow writing; when it equals any other value, writing is prohibited.
Page 238: Register Description
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) 13.5 Register description EPWM prescaler register (CLKPSC) 13.5.1 Symbol Description Reset value 31:24 Reserved EPWM counter 4 and 5 clock prescaler CLK_PSC45 = PCLK/(CLKPSC45+1) 23:16 CLKPSC45 If CLKPSC45=0, the pre-scaler has no clock output.
Page 239: Epwm Clock Selection Register (Clkdiv)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM clock selection register (CLKDIV) 13.5.2 Symbol Description Reset value 31:23 Reserved Counter 5 clock division frequency selection 000: CLK_PSC45/2 001: CLK_PSC45/4 22:20 CLKDIV5 010: CLK_PSC45/8 011: CLK_PSC45/16 100: CLK_PSC45/1 Other value: PCLK Reserved Counter 4 clock division frequency selection 000: CLK_PSC45/2...
Page 240 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) 011: CLK_PSC01/16 100: CLK_PSC01/1 Other value: PCLK www.mcu.com.cn 240 / 407 Rev.1.0.1...
Page 241: Epwm Control Register (Con)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM control register (CON) 13.5.3 Symbol Description Reset value 31:27 Reserved EPWMn channel status control bit during HALT (debug pause) (If POENn=0, the output of EPWMn is in high resistance state) 0: All channels output normally (POENn=1) HALTMS...
Page 242 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM3 output polarity control bit PINV3 0: Normal output 1: Inverted output EPWM2 output polarity control bit PINV2 0: Normal output 1: Inverted output EPWM1 output polarity control bit PINV1 0: Normal output 1: Inverted output EPWM0 output polarity control bit PINV0...
Page 243: Epwm Control Register (Con2)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM control register (CON2) 13.5.4 Symbol Description Reset value 31:6 Reserved EPWM5 counter enable bit 0: Disable CNTEN5 1: Enable (The bit is cleared automatically after one-shot mode completion) EPWM4 counter enable bit 0: Disable CNTEN4 1: Enable...
Page 244: Epwm Control Register (Con3)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM control register (CON3) 13.5.5 Symbol Description Reset value EPWM load interrupt flag-related control bit Load control is not related to the interrupt flag Load control is related to the LOADNWINT interrupt flag When the load action is generated, whether the interrupt flag is generated with the load or not, if...
Page 245 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM3 load/interrupt mode selection bit 00: Interrupt flags are loaded and generated at each zero and period point. 01: Each zero point is loaded with a generated interrupt flag 23:22 LOADTYP3 The first zero point is loaded alternately with the next period point with the generation of...
Page 246 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) by hardware after loading) EPWM3 period/comparator load enable 0: Disable LOADEN3 Enable (Automatically cleared by hardware after loading) EPWM2 period/comparator load enable 0: Disable LOADEN2 Enable (Automatically cleared by hardware after loading) EPWM1 period/comparator load enable 0: Disable LOADEN1...
Page 247: Epwm Period Register 0-5 (Period0-5)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM period register 0-5 (PERIOD0-5) 13.5.6 Symbol Description Reset value 31:16 Reserved 15:0 PERIODn EPWMn counter period value EPWM compare register 0-5(CMPDAT0-5) 13.5.7 Symbol Description Reset value 31:16 CMPDDATn EPWMn counter down compare value 15:0 CMPDATn EPWMn counter compare value...
Page 248: Epwm Output Channel Remap Register (Poremap)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM output channel remap register (POREMAP) 13.5.9 Symbol Description Reset value EPWM channel remap function enable control AAH: Remap function enable Selection of EPWMn channel output by PWMnRM Other: Remap function disable The EPWMn fixed channel 31:24 PWMRMEN...
Page 249 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) 001: Map the output of IPG1 010: Map the output of IPG2 011: Map the output of IPG3 100: Map the output of IPG4 101: Map the output of IPG5 11x: Reserved Reserved EPWM channel 0 remap select bit...
Page 250: Epwm Fault Protection Control Register (Brkctl)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM fault protection control register (BRKCTL) 13.5.10 Symbol Description Reset value EPWM fault protection function general enable Disable (reset fault protection BRKEN circuit) 1: Enable EPWM fault signal flag bit (read-only) 0: No fault generated BRKAF Fault signal generated or...
Page 251 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) 0: Low level generates brake 1: High level generates brake Analog comparator 1 output event control brake enable bit 0: Disable 1: Enable ACMP1BKEN (Comparator output event refers to generating rising edge/falling edge/double edge, which can be selected in ACMP->CEVCON)
Page 252 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) 1: High level generates brake Must be set to 0 EPWMn brake output level selection bit 0: After fault brake, channel n BRKODn outputs low level 1: After fault brake, channel n outputs high level www.mcu.com.cn 252 / 407...
Page 253: Epwm Dead Time Control Register (Dtctl)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM dead time control register (DTCTL) 13.5.11 Symbol Description Reset value 31:30 Reserved Channel 4 and 5 dead time control register 29:20 DTI45 Dead time = PWM_CLK45 DTI45 Channel 2 and 3 dead time control register 19:10 DTI23 Dead time = PWM_CLK23...
Page 254: Epwm Mask Output Control Register (Mask)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM mask output control register (MASK) 13.5.12 Symbol Description Reset value 31:14 Reserved EPWM5 mask output enable bit MASKEN5 0: Disable 1: Enable EPWM4 mask output enable bit MASKEN4 0: Disable 1: Enable EPWM3 mask output enable bit MASKEN3...
Page 255: Epwm Mask Output Control Preset Register (Masknxt)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM mask output control preset register (MASKNXT) 13.5.13 Symbol Description Reset value 31:25 Reserved HALL detection mode enable bit HALLEN 0: Disable 1: Enable HALL error status clear bit 0: Writing 0 is invalid 1: Writing 1 clears the HALLST error status and resets it to the initial state 000.
Page 256 CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) Mask preset cache selection bit; 000: Select mask preset cache 0 001: Select mask preset cache 1 010: Select mask preset cache 2 011: Select mask preset cache 3 100: Select mask preset cache 4 101: Select mask preset cache 5 110: Select mask preset cache 6 111: Select mask preset cache 7...
Page 257: Epwm Trigger Compare Register (Cmptgd0-1)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM1 mask data preset bit PMASKD1 (This bit can be set to load into the MASK register at the loading point of EPWMn) EPWM0 mask data preset bit PMASKD0 (This bit can be set to load into the MASK register at the loading point of EPWMn) EPWM trigger compare register (CMPTGD0-1) 13.5.14...
Page 258: Epwm Interrupt Enable Register (Imsc)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM interrupt enable register (IMSC) 13.5.15 Symbol Description Reset value EPWM fault interrupt enable bit EN_BRKIF 0: Disable 1: Enable HALL status error interrupt enable bit EN_HALLIF 0: Disable 1: Enable EPWMn downward compare interrupt enable bit EN_DIFn 29:24...
Page 259: Epwm Interrupt Source Status Register (Ris)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM interrupt source status register (RIS) 13.5.16 Symbol Description Reset value EPWM fault interrupt source status bit RIS_BRKIF 0: No interrupt generated 1: Generated an interrupt HALL status error interrupt source status bit RIS_HALLIF 0: No interrupt generated 1: Generated an interrupt...
Page 260: Epwm Enabled Interrupt Status Register (Mis)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM enabled interrupt status register (MIS) 13.5.17 Symbol Description Reset value EPWM fault enabled interrupt status bit 0: No interrupt generated MIS_BRKIF An interrupt is enabled and generated HALL state error enabled interrupt status bit 0: No interrupt generated MIS_HALLIF An interrupt is enabled and...
Page 261: Epwm Interrupt Clear Control Register (Iclr)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM interrupt clear control register (ICLR) 13.5.18 Symbol Description Reset value EPWM fault interrupt clear control bit ICLR_BRKIF 0: No effect 1: Clear RIS_BRKIF flag bit HALL state error interrupt clear control bit 0: No effect ICLR_HALLIF 1: Clear RIS_HALLIF flag bit...
Page 262: Epwm Interrupt Accumulation Control Register (Ifa)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM interrupt accumulation control register (IFA) 13.5.19 Symbol Description Reset value 31:16 Reserved Accumulated compare value for fault protection interrupt 15:12 BRKIFCMP When the fault interrupt accumulates to (BRKIFCMP+1), set the BRKIF interrupt flag bit to 1. 11:9 Reserved Fault protection interrupt accumulation enable bit...
Page 263: Epwm Fault Protection Recovery Delay Register (Brkrdt)
CMS32M65xx User Manual | Chapter 13 Enhanced PWM (EPWM) EPWM fault protection recovery delay register (BRKRDT) 13.5.21 Symbol Description Reset value 31:20 Must be set to 0 Fault protection (brake) signal filter time selection 0000: (0~1)* TPCLK 0001: (1~2)* TPCLK 0010: (2~3)* TPCLK 0011: (4~5)* TPCLK 0100: (8~9)* TPCLK...
Page 264: Chapter 14 Universal Asynchronous Receiver Transmitter (Uart)
CMS32M65xx User Manual | Chapter 14 Universal Asynchronous Receiver Transmitter (UART) Chapter 14 Universal Asynchronous Receiver Transmitter (UART) 14.1 Overview It contains 1 universal asynchronous serial interface. 14.2 Features ◆ Full duplex, asynchronous communication. ◆ Programmable serial interface features. Data bit length can be set to 5-8 bits. Parity bit can be set to odd, even, no parity, or fixed parity generation and detection.
Page 265: Register Mapping
CMS32M65xx User Manual | Chapter 14 Universal Asynchronous Receiver Transmitter (UART) 14.4 Register mapping (UART0 base address = 0x4006_4000) RO: read only; WO: write only; R/W: read/write. Register Offset value Description Reset value Receive Buffer Register 0x000 Transmit Buffer Register 0x004 Baud Rate Divider Register 0x008...
Page 266: Register Description
CMS32M65xx User Manual | Chapter 14 Universal Asynchronous Receiver Transmitter (UART) 14.5 Register description Receive buffer register (RBR) 14.5.1 Symbol Description Reset value 31:8 Reserved Read operation, returns the data received from the receive buffer. Transmit buffer register (THR) 14.5.2 Symbol Description Reset value...
Page 267: Interrupt Status Register (Iir)
CMS32M65xx User Manual | Chapter 14 Universal Asynchronous Receiver Transmitter (UART) Interrupt status register (IIR) 14.5.5 Symbol Description Reset value 31:4 Reserved Interrupt status indication 0x0: Modem status has been changed. INTID 0x1: Transmit holding register is empty. 0x2: Receive data is valid. 0x3: Receive line status Interrupt status 0: At least one interrupt in the queue.
Page 268: Modem Control Register (Mcr)
CMS32M65xx User Manual | Chapter 14 Universal Asynchronous Receiver Transmitter (UART) Modem control register (MCR) 14.5.7 Symbol Description Reset value 31:5 Reserved Modem loopback mode MLBM 0: Disable Modem loopback mode 1: Enable Modem loopback mode Reserved Line status register (LSR) 14.5.8 Symbol Description...
Page 269: Uart Access End Register (End)
CMS32M65xx User Manual | Chapter 14 Universal Asynchronous Receiver Transmitter (UART) UART access end register (END) 14.5.9 Symbol Description Reset value UART access end register Enable access to registers outside of 31: 0 0x0: UART. Other: Write disabled. Note: 1. After accessing UART-related registers, before operating registers outside of UART, the END register must be written as 0.
Page 270: Chapter 15 I C Serial Interface Controller (I C)
CMS32M65xx User Manual | Chapter 15 I2C Serial Interface Controller (I2C) Chapter 15 C Serial Interface Controller (I 15.1 Overview C is a two-wire bi-directional serial bus that provides a simple and efficient connection for exchanging data between devices. I C is a true multi-host bus, incorporating conflict detection and arbitration mechanisms.
Page 271: Register Mapping
CMS32M65xx User Manual | Chapter 15 I2C Serial Interface Controller (I2C) 15.3 Register mapping (I2C0 base address = 0x4006_4300) RO: read only; WO: write only; R/W: read/write. Register Offset value Description Reser value C Control Set Register CONSET 0x000 C Control Clear Register CONCLR 0x004 C Status Register...
Page 272: Register Description
CMS32M65xx User Manual | Chapter 15 I2C Serial Interface Controller (I2C) 15.4 Register description C control set register (CONSET) 15.4.1 Symbol Description Reset value 31:9 Reserved C broadcast call flag bit Read-only 0: No broadcast call received 1: Broadcast call address matched This flag is cleared when a stop bit/restart bit/reset signal is received Interrupt enable flag bit...
Page 273: I 2 C Control Clear Register (Conclr)
CMS32M65xx User Manual | Chapter 15 I2C Serial Interface Controller (I2C) when receiving data in master or slave mode C 10-bit Sslave address flag bit Read-only 0: I C address does not match XADRF 1: 1 C 10-bit address matched This flag is cleared when a stop bit/reset signal is received C 7-bit slave address flag bit, read-only...
Page 274: C Status Register (Stat)
CMS32M65xx User Manual | Chapter 15 I2C Serial Interface Controller (I2C) C status register (STAT) 15.4.3 Symbol Description Reset value 31:8 Reserved C status code 00H: Bus error (master mode only) 08H: Start bit transmitted 10H: Restart bit transmitted 18H: Address + Write bit transmitted, ACK received Address + Write bit transmitted, no ACK 20H: received...
Page 275: I 2 C Data Register (Dat)
CMS32M65xx User Manual | Chapter 15 I2C Serial Interface Controller (I2C) F8H: Uncertain status Other: Reserved C data register (DAT) 15.4.4 Symbol Description Reset value 31:8 Reserved Received data or data to be transmitted (reading received data is required Data immediately after data reception is completed).
Page 276: C Extended Slave Address Register (Xadr0)
CMS32M65xx User Manual | Chapter 15 I2C Serial Interface Controller (I2C) C extended slave address register (XADR0) 15.4.8 Symbol Description Reset value 31:11 Reserved 10:1 Address 10-bit slave address Enable broadcast call address recognition Disable broadcast call address recognition C extended slave address mask register (XADM0) 15.4.9 Symbol Description...
Page 277: Chapter 16 Spi Controller (Ssp/Spi)
CMS32M65xx User Manual | Chapter 16 SPI Controller (SSP/SPI) Chapter 16 SPI Controller (SSP/SPI) 16.1 Overview Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that operates in full- duplex mode. Devices can operate in master/slave mode and communicate with each other using a 4-wire bidirectional interface.
Page 278: Register Description
CMS32M65xx User Manual | Chapter 16 SPI Controller (SSP/SPI) 16.4 Register description SSP control register (CON) 16.4.1 Symbol Description Reset value 31:12 Reserved Loopback mode enable bit 0: Normal operaton mode Loopback mode, connect serial input to serial output SSP enable bit SSPEN 0: Disable 1: Enable...
Page 279: Ssp Status Register (Stat)
CMS32M65xx User Manual | Chapter 16 SPI Controller (SSP/SPI) SSP status register (STAT) 16.4.2 Symbol Description Reset value 31:5 Reserved Busy flag bit, read-only 0: SSP is idle 1: SSP is transmitting/receiving data or Transmit Buffer has been written data Reserved SSP data register (DAT) 16.4.3...
Page 280: Ssp Interrupt Enable Register (Imsc)
CMS32M65xx User Manual | Chapter 16 SPI Controller (SSP/SPI) SSP interrupt enable register (IMSC) 16.4.5 Symbol Description Reset value 31:4 Reserved Transmit Buffer interrupt enable bit Disable interrupt for empty transmit TXIM buffer. Enable interrupt for empty transmit buffer. Receive Buffer interrupt enable bit Disable interrupt for received data RXIM in receive buffer.
Page 281: Ssp Interrupt Clear Register (Iclr)
CMS32M65xx User Manual | Chapter 16 SPI Controller (SSP/SPI) TXMIS = TXIM & TXRIS RXMIS = RXIM & RXRIS RTMIS = RTIM & RTRIS RORMIS = RORIM & RORRIS SSP interrupt clear register (ICLR) 16.4.8 Symbol Description Reset value 31:2 Reserved RTIC 1: Clear the RTRIS flag bit...
Page 282: Chapter 17 Analog-To-Digital Conversion (Adc)
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) Chapter 17 Analog-to-Digital Conversion (ADC) 17.1 Overview The chip contains a 12-bit, 23-channel fast successive approximation analog-to-digital converter (ADC). 17.2 Features ◆ Simulation input voltage range: VSS ~ AVDD. ◆ Maximum sampling rate: 1.2Msps. ◆...
Page 283: Functioal Description
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) 17.3 Functioal description ADC channels 17.3.1 ADC channel number (supports ADC channel ADC channel Description hardware trigger) priority PGA0 channel (see Chapter AN0 (PGA0O) Highest 18 for details) PGA0 channel (see Chapter AN1 (PGA0O) 18 for details) PGA1 channel (see Chapter...
Page 284: Block Diagram Of Adc Structure
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) Block diagram of ADC structure 17.3.2 VREF PGA0O PGA0O ADCST AN10 AN10 AN11 AN11 AN12 AN12 RSLT AN13 AN13 AN14 AN14 AN15 DCMP To PWM AN15 AN16 AN16 ADCCMPDATA AN17 AN17 AN18 AN18 Temp Sensor...
Page 285: Adc Power Consumption Modes
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC power consumption modes 17.3.3 There are two modes of ADC operation: high-speed mode and low current mode. High-speed mode: This mode has a faster conversion speed. Low current mode: This mode has a slightly slower conversion speed, and the operating current of the ADC is significantly reduced.
Page 286: Adc Channel Selection And Interrupt Generation
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC channel selection and interrupt generation 17.3.6 ADCCON ADCSCAN ADCCON Interrupt Channel description Result storage (ADCSWCHE) (ADEn) (ADCMS) generation Disable all channels Converts the highest- After the priority channel After conversion of a already enabled conversion...
Page 287: Adc Hardware Trigger Start
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC hardware trigger start 17.3.8 Trigger sources: In addition to software-triggered conversion, the ADC can also be triggered by hardware signals. There are several types of hardware trigger sources: Internal triggers EPWM output channel triggers EPWM count comparator 0 triggers EPWM count comparator 1 triggers...
Page 288 CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) EPWM Count Comparator Trigger: EPWM count comparator 0/1 triggers can be set to start ADC conversion at any time within the EPWM period, similar to EPWM channel triggers. It is also possible to choose to start ADC conversion after a certain delay.
Page 289 CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) Figure 17-2: EPWM trigger to initiate ADC setup EPWMn counter PTG0 trig PTG1 trig Zero point converted 3 Compare point channels 0/1 converted 1 channel Note 1: The channel that enables ADC conversion triggered at the zero point is determined by ADCCHPEM.
Page 290: Register Mapping
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) 17.4 Register mapping (ADC base address = 0x4006_8000) RO: Read only, WO: Write Only, R/W: Read/Write Offset Register Description Reset value value ADC Control Register 0x000 0xD0000 (P1B) ADC Control Register 2 CON2 0x004 (P1B)
Page 291 CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC Channel 15 Conversion Result DATA15 0x0BC Register ADC Channel 16 Conversion Result DATA16 0x0C0 Register ADC Channel 17 Conversion Result DATA17 0x0C4 Register ADC Channel 18 Conversion Result DATA18 0x0C8 Register ADC Channel 20 Conversion Result DATA20...
Page 292: Register Description
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) 17.5 Register description ADC control register (CON) 17.5.1 Symbol Description Reset value ADC module reset control bit ADCRST 0: --- 1: ADC module reset 30:26 Reserved, must be set to 0 ADC power mode select bit 00: High-speed mode 25:24...
Page 293 CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) 01: Select VREF 10: Reserved 11: Disable selection Reserved, must be set to 0 ADC enable control bit ADCEN 0: Disable 1: Enable ADC conversion mode delect bit 0: Single conversion 1: Continuous conversion (Convert all enabled ADC channels at one time, the order is...
Page 294: Adc Control Register 2 (Con2)
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC control register 2 (CON2) 17.5.2 Symbol Description Reset value 31:16 Reserved ADC internal channel (AN23) select bit 15:13 ADCICHES 100: Select internal channel 4 Other: Disable selection ADC conversion status flag bit 4 (read-only) ADCSF4 0: - 1: Single conversion completed...
Page 295: Adc Hardware Trigger Control Register (Hwtg)
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC hardware trigger control register (HWTG) 17.5.3 Symbol Description Reset value 31:16 Reserved ADC internal function trigger enable bit ADCINTTGEN 0: Disable 1: Enable ADC internal function trigger source channel select 000: Reserved 001: ADC conversion end signal 14:12...
Page 296: Adc Epwm Trigger Delay Register (Epwmtgdly)
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC EPWM trigger delay register (EPWMTGDLY) 17.5.4 Symbol Description Reset value 31:10 Reserved ADC EPWM trigger delay data EPWM (including output channel triggering and ADCEPWMTGDLY EPWM comparator 0/1 triggering) delay trigger ADC delay data (see section 17.3.8 EPWM trigger delay for details) Note: The EPWMTGDLY register bit12 needs to be written 1 after the chip is powered on.
Page 297: Adc Epwm Comparator 0 Trigger Conversion Channel Enable Register (Chptg0)
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC EPWM comparator 0 trigger conversion channel 17.5.7 enable register (CHPTG0) Symbol Description Reset value 31:24 Reserved ADC EPWM comparator 0 trigger conversion channel enable bit (n=23-0,n≠19) 23:0 ADCCHPTG0n 0: Disable 1: Enable Note: Bit19 is reserved and must be 0.
Page 298: Adc Compare Control Register 0 (Cmpx) X=0~1
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC compare control register 0 (CMPx) x=0~1 17.5.10 Symbol Description Reset value ADC comparator x enable bit ADCCMPxEN 0: - 1: Enable ADC comparator x result bit (read-only) (This bit is automatically updated after the selected channel is converted) ADCCMPxO The conditions for comparison are...
Page 299: Adc Interrupt Enable Register (Imsc)
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC interrupt enable register (IMSC) 17.5.11 Symbol Description Reset value ADC comparator 0 interrupt enable bit ADCIMSC31 0: Disable 1: Enable 30:24 Reserved ADC channel n interrupt enable bit (n=23-0,n≠ 23:0 ADCIMSCn 0: Disable 1: Enable...
Page 300: Adc Interrupt Clear Register (Iclr)
CMS32M65xx User Manual | Chapter 17 Analog-to-Digital Conversion (ADC) ADC interrupt clear register (ICLR) 17.5.14 Symbol Description Reset value ADC comparator 0 interrupt status Clear ADC Comparator 0 interrupt ADCICLR31 status 0: No effect 30:24 Reserved ADC channel n interrupt status (n=23-0,n≠19) 23:0 ADCICLRn 0: No effect...
Page 301: Chapter 18 Programmable Gain Amplifier (Pga0/1/2)
CMS32M65xx User Manual | Chapter 18 Programmable Gain Amplifier (PGA0/1/2) Chapter 18 Programmable Gain Amplifier (PGA0/1/2) 18.1 Overview The chip contains three basic operational amplifier modules and three programmable gain amplifiers. Basic signal amplification and signal processing functions can be achieved with a few external components. 18.2 Features PGA0 (Programmable Gain Amplifier 0) ◆...
Page 302: Block Diagram Of Structure
CMS32M65xx User Manual | Chapter 18 Programmable Gain Amplifier (PGA0/1/2) 18.3 Block diagram of structure Figure 18-1: PGA structure diagram VREF VREF/2 PGA0_VREF=0 Buffer PGA0_REF Bus current sampling PGA0 PGA0_VREF=1 To ADC/ACMP A0P/AN8 P00(A0P) PGA0O PGA0_MODE=1 P01(A0GND) PGA0 A0GND/AN9 P02(A0O) PGA0_MODE=0 PGA0_OT_SELR=0 PGA0_OTEN...
Page 303: Register Mapping
CMS32M65xx User Manual | Chapter 18 Programmable Gain Amplifier (PGA0/1/2) 18.4 Register mapping (PGA0 base address = 0x4006_8300) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value PGA0CON0 0x000 PGA0 Control Register 0 PGA0CON1 0x004 PGA0 Control Register 1 PGA0LOCK 0x008...
Page 304: Register Description
CMS32M65xx User Manual | Chapter 18 Programmable Gain Amplifier (PGA0/1/2) 18.5 Register description PGA0 control register 0 18.5.1 Symbol Description Reset value 31:8 Reserved PGA0 enable bit PGA0_EN 0: Disable 1: Enable Reserved - PG0 mode selection PGA0_MODE 0: Single-ended mode 1: Full differential mode PGA0 reference voltage selection bit PGA0S_VREF...
Page 305: Pga0 Access Enable Register
CMS32M65xx User Manual | Chapter 18 Programmable Gain Amplifier (PGA0/1/2) PGA0 access enable register 18.5.3 Symbol Description Reset value 31:8 Reserved PGA0 register access enable bit PGA0_LOCK 0x55: Access to PGA0 related registers Other: Disable access PGA1 control register 0 18.5.4 Symbol Description...
Page 306: Pga2 Control Register 0
CMS32M65xx User Manual | Chapter 18 Programmable Gain Amplifier (PGA0/1/2) PGA2 control register 0 18.5.5 Symbol Description Reset value 31:8 Reserved PGA2 enable bit PGA2_EN 0: Disable 1: Enable Reserved - PGA2 mode selection PGA2_MODE 0: Single-ended mode 1: Full differential mode PGA2 gain selection 000: 1X 001: 2X...
Page 307: Chapter 19 Analog Comparator (Acmp0/1)
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) Chapter 19 Analog Comparator (ACMP0/1) 19.1 Overview The chip contains two analog comparators. The comparators can be configured to suit different applications. The comparators output a logic 1 when the positive voltage is greater than the negative voltage and a 0 when the negative voltage is greater than the positive voltage, which can also be changed via the output polarity selection bit.
Page 308 CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) Figure 19-2: Block diagram of comparator hysteresis function The output waveform of the comparator with fixed The output waveform of the comparator with fixed voltage at the negative end and changing the voltage at voltage at the positive end and changing the voltage at the positive end the negative end...
Page 309: Features
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) 19.3 Features ◆ Analog input voltage range: (0~VDD)V. ◆ Supports single/bilateral hysteresis function. ◆ Supports hysteresis voltage selection (10mV/20mV/60mV – typical value). ◆ Each comparator’s positive side can be selected from multiple sources. ◆...
Page 310: Register Mapping
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) 19.5 Register mapping (ACMP base address = 0x4006_8200) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value Analog Comparator 0 Control Register 0 C0CON0 0x000 (P1B) Analog Comparator 0 Control Register 1 C0CON1 0x004...
Page 311: Register Description
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) 19.6 Register description Analog comparator 0 control register 0 (C0CON0) 19.6.1 Symbol Description Reset value 31:17 Reserved Analog comparator 0 center point select enable C0_ZXD 0: Disable 1: Enable Analog comparator 0 enable bit C0_EN 0: Disable 1: Enable...
Page 312: Analog Comparator 0 Control Register 1 (C0Con1)
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) Analog comparator 0 control register 1 (C0CON1) 19.6.2 Symbol Description Reset value 31:14 Reserved Analog comparator 0 hysteresis mode selection 00: No hysteresis 13:12 C0_HYSPN_S 01: Positive hysteresis 10: Negative hysteresis 11: Positive and negative hysteresis Analog comparator 0 hysteresis voltage selection 00: No hysteresis...
Page 313: Analog Comparator 1 Control Register 0 (C1Con0)
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) Analog comparator 1 control register 0 (C1CON0) 19.6.3 Symbol Description Reset value 31:16 Reserved Analog comparator 1 enable bit C1_EN 0: Disable 1: Enable Analog comparator 1 output enable bit C1_OEN 0: Disable 1: Enable 13:9...
Page 314: Analog Comparator 1 Control Register 1 (C1Con1)
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) Analog comparator 1 control register 1 (C1CON1) 19.6.4 Symbol Description Reset value 31:14 Reserved Analog comparator 1 hysteresis mode selection 00: No hysteresis 13:12 C1HYSPN_S 01: Positive hysteresis 10: Negative hysteresis 11: Positive and negative hysteresis Analog comparator 1 hysteresis voltage selection 00: No hysteresis...
Page 315: Analog Comparator Event Control Register (Cevcon)
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) Analog comparator event control register (CEVCON) 19.6.5 Symbol Description Reset value 31:6 Reserved Analog comparator 1 event output enable bit (does not affect interrupt generation) EVE1 0: Disable 1: Enable Analog comparator 0 event output enable bit (does not affect interrupt generation) EVE0 0: Disable...
Page 316: Analog Comparator Enabled Interrupt Source Status Register (Mis)
CMS32M65xx User Manual | Chapter 19 Analog Comparator (ACMP0/1) generation) Analog comparator 0 interrupt source status bit 0: No interrupt generated RIS_C0IF Interrupt has been generated (event generation) Analog comparator enabled interrupt source status 19.6.8 register (MIS) Symbol Description Reset value 31:2 Reserved Analog comparator 1 enabled interrupt status bit...
Page 317: Chapter 20 Dac
CMS32M65xx User Manual | Chapter 20 DAC Chapter 20 20.1 Overview The chip contains an internal digital-to-analog converter. 20.2 Block diagram of structure DAC_O VREF DAC_S<7:0> 20.3 Features ◆ The analog reference voltage input is the output of ADCLDO. ◆ Multiple levels of output voltage are available for selection. 20.4 Register mapping (DAC base address = 0x4006_8360) RO: Read only, WO: Write Only, R/W: Read/Write Register...
Page 318: Register Description
CMS32M65xx User Manual | Chapter 20 DAC 20.5 Register description DAC control register 0(CON0) 20.5.1 Symbol Description Reset value 31:9 Reserved DAC module enable DAC_EN 0: Disable 1: Enable DAC_S DAC digital signal input DAC write enable control register (LOCK) 20.5.2 Symbol Description...
Page 319: Chapter 21 Overview Of Adcldo
CMS32M65xx User Manual | Chapter 21 Overview of ADCLDO Chapter 21 Overview of ADCLDO It contains an internal LDO to provide reference voltage to some modules. 21.1 Features ◆ Analog input voltage range: VDD. ◆ Output voltage: can be selected from VDD, 4.2V, and 3.6V. 21.2 Block diagram of structure ADLDO_EN=0 ADLDO_V_SEL=0 (default)
Page 320: Register Description
CMS32M65xx User Manual | Chapter 21 Overview of ADCLDO 21.4 Register description ADCLDO control register 0(CON0) 21.4.1 Symbol Description Reset value 31:21 Reserved 20:16 ADCLDO_AJ[4:0] ADCLDO trim bit (read-only) 15:9 Reserved ADCLDO module enable ADCLDO_EN 0: Disable, ADLDO output VDD 1: Enable, ADLDO output LDO voltage ADCLDO output voltage selection ADCLDO_V_SEL...
Page 321: Chapter 22 Nested Vectored Interrupt Controller (Nvic)
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) Chapter 22 Nested Vectored Interrupt Controller (NVIC) Cortex®-M0+ CPU includes a Nested Vectored Interrupt Controller (NVIC) for interrupt handling. 22.1 Features ◆ Supports nested vectored interrupts. ◆ Automatically saves and restores processor state. ◆...
Page 322: Exception Mode And System Interrupt Mapping
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) 22.2 Exception mode and system interrupt mapping The table below lists the exception modes supported by this product. Like all interrupts, software can set 4 levels of priority for some of these exceptions. Users can configure the highest priority as 0 and the lowest priority as 3.
Page 323: Vector Table
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) 22.3 Vector table Exception Interrupt Vector Exception type Description number number address System exception 1-15 0x00-0x3c 0x40 INTLVI Voltage detection 0x44 INTP0 Edge detection of pin input 0x48 INTP1 Edge detection of pin input 0x4c INTP2...
Page 324: Register Mapping
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) 22.4 Register mapping (NVIC base address = 0xE000_E000) RO: Read only, WO: Write Only, R/W: Read/Write. Register Offset value Description Reset value ISER 0x100 Interrupt Enable Control Register Interrupt Clear Enable Control ICER 0x180 Register...
Page 325: Register Description
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) 22.5 Register description Interrupt set enable control register (ISER) 22.5.1 Symbol Description Reset value Interrupt enable bit Enables one or more interrupts. Each bit represents an interrupt from IRQ0 to IRQ31 (vector number from 16 to 47).
Page 326: Interrupt Clear Pending Control Register (Icpr)
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) pending state Note: Reading this register indicates that the current state is pending. Interrupt clear pending control register (ICPR) 22.5.4 Symbol Description Reset value Clear interrupt pending bit Write operation: 0: Invalid 1: Clear pending status.
Page 327: Irq8~Irq11 Interrupt Priority Register (Ipr2)
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) 0 represents the highest priority, and 3 represents the lowest priority. 21:16 Reserved IRQ5 priority 15:14 PRI_5 0 represents the highest priority, and 3 represents the lowest priority. 13:8 Reserved IRQ4 priority PRI_4...
Page 328: Irq12~Irq15 Interrupt Priority Register (Ipr3)
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) IRQ12~IRQ15 Interrupt priority register (IPR3) 22.5.8 Symbol Description Reset value IRQ15 priority 31:30 PRI_15 0 represents the highest priority, and 3 represents the lowest priority. 29:24 Reserved IRQ14 priority 23:22 PRI_14 0 represents the highest priority, and 3...
Page 329: Irq20~Irq23 Interrupt Priority Register (Ipr5)
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) IRQ20~IRQ23 Interrupt priority register (IPR5) 22.5.10 Symbol Description Reset value IRQ23 priority 31:30 PRI_23 0 represents the highest priority, and 3 represents the lowest priority. 29:24 Reserved IRQ22 priority 23:22 PRI_22 0 represents the highest priority, and 3...
Page 330: Irq28~Irq31 Interrupt Priority Register (Ipr7)
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) IRQ28~IRQ31 Interrupt priority register (IPR7) 22.5.12 Symbol Description Reset value IRQ31 priority 31:30 PRI_31 0 represents the highest priority, and 3 represents the lowest priority. 29:24 Reserved IRQ30 priority 23:22 PRI_30 0 represents the highest priority, and 3...
Page 331: External Interrupt Rising Edge Enable Register (Egp0)
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) External interrupt rising edge enable register (EGP0) 22.5.13 EGP0 and EGN0 registers are used to set the active edge of INTP0~INTP3. The EGP0 and EGN0 registers are set by 8-bit memory operation instructions. After a reset signal is generated, the values of these registers are changed to “00H”.
Page 332: External Interrupt Falling Edge Enable Register (Egn0)
CMS32M65xx User Manual | Chapter 22 Nested Vectored Interrupt Controller (NVIC) External interrupt falling edge enable register (EGN0) 22.5.14 Symbol Description Reset value Reserved INTP3 external interrupt falling edge enable register: EGN3 0: Disable external interrupt falling edge 1: Enable external interrupt falling edge INTP2 external interrupt falling edge enable register: 0: Disable external interrupt falling edge 1: Enable external interrupt falling edge...
Page 333: Chapter 23 Standby Function
CMS32M65xx User Manual | Chapter 23 Standby Function Chapter 23 Standby Function 23.1 Standby function The standby function is a function that further reduces the operating current of the system and has the following two modes. (1) Sleep mode Sleep mode is the mode in which the CPU is stopped from running the clock. If the high-speed on-chip oscillator or the low-speed on-chip oscillator is oscillating before the sleep mode is set, the clocks continue to oscillate.
Page 334 CMS32M65xx User Manual | Chapter 23 Standby Function Caution: When the interrupt request flag is “1” (an interrupt request signal is generated), the interrupt request signal is used to release the sleep mode. Therefore, even if the WFI instruction is executed in this case, it does not shift to the sleep mode.
Page 335: Sleep Mode Release
CMS32M65xx User Manual | Chapter 23 Standby Function Sleep mode release 23.2.2 The sleep mode can be released by any interrupt or external reset, POR reset, low voltage detection reset, or WDT reset. (1) Released by interrupts When a interrupt is generated and the interrupt is allowed to be accepted, sleep mode is released and the CPU begins processing interrupt services.
Page 336 CMS32M65xx User Manual | Chapter 23 Standby Function (2) Released by resets When a reset signal is generated, the CPU is in reset state and the sleep mode is released. As with a normal reset, the program is executed after shifting to the reset vector address. Figure 23-2: Release sleep mode by resets reset signal note1...
Page 337: Deep Sleep Mode
CMS32M65xx User Manual | Chapter 23 Standby Function 23.3 Deep sleep mode Setting of deep sleep mode 23.3.1 When the SLEEPDEEP bit of the SCR register is 1, the WFI instruction is executed and deep sleep mode is entered. In this mode, the CPU, most of the peripheral modules, and the oscillator operation stops. However, the values of the CPU internal registers, the RAM data, the peripheral modules, the state of the I/O are maintained.
Page 338 CMS32M65xx User Manual | Chapter 23 Standby Function External interrupt Operable High-speed CRC Operation stopped General-purpose CRC Operation stopped SFR guard function Operation stopped Note: Operation stopped: Operation is automatically stopped before switching to the deep sleep mode. Operation disabled: Operation is stopped before switching to the deep sleep mode. : High-speed on-chip oscillator : Low-speed on-chip oscillator clock...
Page 339: Deep Sleep Mode Release
CMS32M65xx User Manual | Chapter 23 Standby Function Deep sleep mode release 23.3.2 The deep sleep mode can be released by the following two methods. (a) Released by non-maskable interrupt requests If an LVD detection, INTP0-3, LSI timer or WDT interrupt request occurs, the deep sleep mode is released. After the oscillation stabilization time, if it is allowed to accept interrupt, it will process the vector interrupt.
Page 340: Deep Sleep Mode With Partial Power Down
CMS32M65xx User Manual | Chapter 23 Standby Function 23.4 Deep sleep mode with partial power down Setting of deep sleep mode with partial power down 23.4.1 The deep sleep mode with partial power loss is a deep sleep mode that further saves power consumption by turning off some peripheral power supplies on the basis of deep sleep mode.
Page 341 CMS32M65xx User Manual | Chapter 23 Standby Function Note: When the interrupt request flag is “1” (an interrupt request signal is generated), the interrupt request signal is used to release the deep sleep mode. Therefore, if the WFI instruction is executed in this case, it is released as soon as the deep sleep mode is entered, and the partial power-down mode is not entered in this case.
Page 342 CMS32M65xx User Manual | Chapter 23 Standby Function Table 23-3: Operation status in deep sleep mode with partial power down Item Deep sleep mode with partial power down Operation stopped System clock The operating state is set via the OSMC register and the SUBCKSEL register, and the set state is retained.
Page 343: Release Deep Sleep Mode With Partial Power Down
CMS32M65xx User Manual | Chapter 23 Standby Function Release deep sleep mode with partial power down 23.4.2 Release the deep sleep mode with partial power down by the following 2 methods. (a) Release deep sleep mode with partial power-down via interrupt requests If INTP0-3, LSITIMER timer interrupt, LVI interrupt and WDT interrupt are requested, it is possible to release the deep sleep mode with partial power down.
Page 344: Chapter 24 Reset Function
CMS32M65xx User Manual | Chapter 24 Reset Function Chapter 24 Reset Function The following six operations are available to generate a reset signal. (1) External reset input via RESETB pin. (2) Internal by watchdog timer program loop detection. (3) Internal reset by comparison of the supply voltage and detection voltage of power-on reset (POR) circuit.
Page 345 CMS32M65xx User Manual | Chapter 24 Reset Function Figure 24-1: Block diagram of reset function Internal bus Reset control flag register (RESF) SYSRF WDTRF IAWRF LVIRF Watchdog timer reset signal Clear Clear Clear Clear Reset signal generated by the system reset request setting Reset signal generated by LVIM/LVIS register reset accessing illegal memory...
Page 346 CMS32M65xx User Manual | Chapter 24 Reset Function Reset timing When the RESETB pin is input low, a reset is generated. The reset state is then released if the RESETB pin is input high and the program begins with a high-speed on-chip oscillator clock after the reset process is completed.
Page 347 CMS32M65xx User Manual | Chapter 24 Reset Function ⚫ During a power-on reset, P02 is at a high level, while P06 and P07 are at a low level. Note 2: The watchdog timer is also reset when an internal reset occurs. For resets generated by the POR circuit and LVD circuit voltage detection, if VDD≥VPOR or VDD≥VLVD after the reset, the reset state is released, and the program starts executing using the high-speed on-chip oscillator clock after the reset processing.
Page 348 CMS32M65xx User Manual | Chapter 24 Reset Function Table 24-1: Operation status during resetting Reset period External Write reset Illegal Item Watchdog Power-on reset LVD reset register memory reset reset RESINB reset access reset Operation Operation Operation Operation Operation Operation System stopped stopped...
Page 349 CMS32M65xx User Manual | Chapter 24 Reset Function Operation Operation Operation Operation Operation Operation stopped stopped stopped stopped stopped stopped Operation Operation Operation Operation Operation Operation ADCLDO stopped stopped stopped stopped stopped stopped Power-on reset Operable Operable Operable Operable Operable Operable function Voltage detection...
Page 350: Registers For Confirming The Reset Source
CMS32M65xx User Manual | Chapter 24 Reset Function 24.1 Registers for confirming the reset source Register mapping 24.1.1 (Reset control base address = 0x4002_0440) RO: Read only, WO: Write Only, R/W: Read/Write. Register Offset value Description Reset value RESF 0x000 Reset control flag register Reset control flag register (RESF) 24.1.2...
Page 351 CMS32M65xx User Manual | Chapter 24 Reset Function detection circuit (LVD) 0: No internal reset request is generated or the RESF register is cleared. 1: An internal reset request is generated. Note: The value after reset varies depending on the reset source. See Table 24-2. Table 24-2: RESF register status when a reset request occurs Reset Reset...
Page 352 CMS32M65xx User Manual | Chapter 24 Reset Function Figure 24-4 shows the procedure for checking a reset source. Figure 24-4: Example of procedure for checking reset source After reset acceptance Read the RESF register (clear the RESF Read RESF register register) and store the value of the RESF register in any RAM.
Page 353: Chapter 25 Power-On-Reset Circuit
CMS32M65xx User Manual | Chapter 25 Power-On-Reset Circuit Chapter 25 Power-On-Reset Circuit 25.1 Function of power-on-reset circuit The power-on-reset circuit (POR) has the following functions. ① Generates internal reset signal at power on. The reset signal is released when the supply voltage (V ) exceeds the detection voltage (V ).
Page 354: Structure Of Power-On Reset Circuit
CMS32M65xx User Manual | Chapter 25 Power-On-Reset Circuit 25.2 Structure of power-on reset circuit The block diagram of the power-on reset circuit is shown in Figure 25-1. Figure 25-1: Block diagram of power-on reset circuit Internal reset signal Basic voltage source www.mcu.com.cn 354 / 407...
Page 355: Operation Of Power-On Reset Circuit
CMS32M65xx User Manual | Chapter 25 Power-On-Reset Circuit 25.3 Operation of power-on reset circuit The timing of the internal reset signal generation for the power-on reset circuit and the voltage detection circuit is shown below. Figure 25-2: Timing of internal reset signal generation for power-on reset circuit and voltage detection circuit (1/3) (1) When the externally input reset signal on the RESETB pin is used Supply voltage(V...
Page 356 CMS32M65xx User Manual | Chapter 25 Power-On-Reset Circuit operating voltage range. Note 3: VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage Note 4: When LVD is OFF, the external reset of RESETB pin must be used. For details, please refer to “Chapter 26 Voltage Detection Circuit”.
Page 357 CMS32M65xx User Manual | Chapter 25 Power-On-Reset Circuit possibility that the power supply voltage may return to the high voltage detection voltage (V ) or LVDH ), follow the steps in “Figure 26- higher without falling below the low voltage detection voltage (V LVDL 5 Setting Procedure for Confirmation/Reset of Operating Voltage”...
Page 358 CMS32M65xx User Manual | Chapter 25 Power-On-Reset Circuit Figure 25-2: Timing of internal reset signal generation for power-on reset circuit and voltage detection circuit (3/3) (3) LVD reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1) Supply voltage(V Lower limit voltage for guaranteed operation =1.51V(TYP)
Page 359: Chapter 26 Voltage Detection Circuit
CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit Chapter 26 Voltage Detection Circuit 26.1 Function of voltage detection circuit The voltage detection circuit sets the operating mode and detection voltage (V ) by option LVDH LVDL byte (000C1H). The voltage detection circuit (LVD) has the following functions. The internal reset or internal interrupt signal is generated by comparing the supply voltage (V ) with the detection voltage (V...
Page 360 CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit If a reset occurs, bit 0 (LVIRF) of the reset control flag register (RESF) is set to “1”. For details of the RESF register, please refer to “Chapter 24 Reset Function”. www.mcu.com.cn 360 / 407 Rev.1.0.1...
Page 361: Structure Of Voltage Detection Circuit
CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit 26.2 Structure of voltage detection circuit The block diagram of the voltage detection circuit is shown in Figure 26-1. Figure 26-1: Block diagram of voltage detection circuit Internal reset N-ch signal Voltage LVDH detection...
Page 362: Registers For Controlling Voltage Detection Circuit
CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit 26.4 Registers for controlling voltage detection circuit The voltage detection circuit is controlled by the following registers. ⚫ Voltage detection register (LVIM) ⚫ Voltage detection level register (LVIS) Voltage detection register (LVIM) 26.4.1 This register is set to enable or disable overwriting of the voltage detection level register (LVIS), and to confirm the masking status of the LVD output.
Page 363: Voltage Detection Level Register (Lvis)
CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit Voltage detection level register (LVIS) 26.4.2 This is a register that sets the voltage detection level. The LVIS register is set by an 8-bit memory manipulation instruction. After generating a reset signal, the value of this register changes to “00H/01H/81H”...
Page 364: Operation Of Voltage Detection Circuit
CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit 26.5 Operation of voltage detection circuit When used as reset mode 26.5.1 The operation mode (reset mode (LVIMDS1, LVIMDS0=1, 1)) and the detection voltage (V ) are set via the option byte 000C1H. If the reset mode is set, operation starts with the following initial settings. ◼...
Page 365: When Used As Interrupt Mode
CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit 26.6 When used as interrupt mode The operation mode (interrupt mode (LVIMDS1, LVIMDS0=0, 1)) and the detection voltage (V ) are set via the option byte 000C1H. If the interrupt mode is set, operation starts with the following initial settings. ◼...
Page 366 CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit voltage returns to the operating voltage range. 3.VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage www.mcu.com.cn 366 / 407 Rev.1.0.1...
Page 367: When Used As Interrupt & Reset Mode
CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit 26.7 When used as interrupt & reset mode The operation mode (interrupt & reset mode (LVIMDS1, LVIMDS0=1, 0)) and the detection voltage (V LVDH ) are set via the option byte 000C1H. LVDL If the interrupt &...
Page 368 CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit Figure 26-4: Reset & interrupt signal generation timing (LVIMDS1, LVIMDS0=1, 0) (1/2) if after release mask no reset is generated, then it can be tell that V has recovered to value V .
Page 369 CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit Note 1. After the reset signal is generated, the LVIMK flag becomes “1”. 2. When using the interrupt & reset mode, you must follow “Figure 26-5: Setting procedure for confirmation /reset of operating voltage” after an interrupt occurs. 3.
Page 370 CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit Figure 26-4: Reset & interrupt signal generation timing (LVIMDS1, LVIMDS0=1, 0) (2/2) When a condition of V is V < after releasing the mask, a LVIH reset is generated because of LVIMD = 1 (reset mode).
Page 371 CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit 3. When using the interrupt&reset mode, you must follow the steps in “Figure 26-6: Initial setting procedure for interrupt & reset mode” after the reset is released. 4.VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage Figure 26-5: Setting procedure for confirmation/reset of operating voltage INTLVI generated...
Page 372 CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit resets or interrupts generated by LVD. The initial setting procedure for interrupt & reset mode is shown in Figure 26-6. Figure 26-6: Initial setting procedure for interrupt & reset mode Power supply voltage arise Refer to Figure 24-3 Confirmation Check reset source procedure for reset source...
Page 373: Cautions For Voltage Detection Circuit
CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit 26.8 Cautions for voltage detection circuit (1) Voltage fluctuation when power is supplied In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVD detection voltage, the system may be repeatedly reset and released from the reset status.
Page 374 CMS32M65xx User Manual | Chapter 26 Voltage Detection Circuit (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released A delay occurs from the time the supply voltage (V ) < LVD detection voltage (V ) is met to the time the ) ≤...
Page 375: Chapter 27 Safety Functions
CMS32M65xx User Manual | Chapter 27 Safety Functions Chapter 27 Safety Functions 27.1 Overview of safety functions The following safety functions are provided in the CMS32M65xx to comply with the IEC60730 and IEC61508 safety standards. These functions enable the microcontroller to self-diagnose abnormalities and stop operating if an abnormality is detected.
Page 376 CMS32M65xx User Manual | Chapter 27 Safety Functions (Flash memory CRC base address = 0x4002_1810) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value CRC0CTL 0x000 Flash memory CRC control register Flash memory CRC operation result PGCRCL 0x002 register L...
Page 377: Operation Of Safety Functions
CMS32M65xx User Manual | Chapter 27 Safety Functions 27.3 Operation of safety functions Flash CRC operation function (high-speed CRC) 27.3.1 The IEC60730 standard mandates the checking of data in the flash memory, and recommends using CRC to do it. The high-speed CRC can be used to check the entire code flash memory area during the initialization routine.
Page 378: Flash Memory Crc Operation Result Register L
CMS32M65xx User Manual | Chapter 27 Safety Functions 27.3.1.1 Flash memory CRC operation result register L (PGCRCL) This register is used to store the lowest 16-bit results of the high-speed CRC operation. The PGCRCL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H.
Page 379: Operation Flow
CMS32M65xx User Manual | Chapter 27 Safety Functions The flowchart of the flash memory CRC operation function (high-speed CRC) is shown in Figure 27-1. ＜Operation flow＞ Figure 27-1: Flow chart of flash CRC operation function (high-speed CRC) Start Store the expected CRC operation result value in the lowest 4 bytes.
Page 380: Crc Operation Function (General-Purpose Crc)
CMS32M65xx User Manual | Chapter 27 Safety Functions 27.3.1.2 CRC operation function (general-purpose CRC) In order to guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the CPU is operating. The general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area.
Page 381: Crc Input Register (Crcin)
CMS32M65xx User Manual | Chapter 27 Safety Functions 27.3.1.3 CRC input register (CRCIN) CRCIN register is an 8-bit register that is used to set the CRC operation data of general-purpose CRC. The possible setting range is 00H to FFH. The CRCIN register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 382: Crc Data Register (Crcd)
CMS32M65xx User Manual | Chapter 27 Safety Functions 27.3.1.4 CRC data register (CRCD) This register is used to store the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (F ) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register.
Page 383: Sfr Guard Function
CMS32M65xx User Manual | Chapter 27 Safety Functions SFR guard function 27.3.2 In order to ensure safety during operation, the IEC61508 standard requires that even if the CPU is out of control, it is necessary to protect important SFR from being rewritten. The SFR protection function is used to protect data from the control registers of the comparator function, port function, interrupt function, clock control function, and voltage detection circuitry.
Page 384: Frequency Detection Function
CMS32M65xx User Manual | Chapter 27 Safety Functions Frequency detection function 27.3.3 The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (F ) and measuring the pulse width of the input signal to channel 1 of the Timer40, whether the proportional relationship between the two clock frequencies is correct can be determined.
Page 385: A/D Test Function
CMS32M65xx User Manual | Chapter 27 Safety Functions A/D test function 27.3.4 The IEC60730 standard mandates testing the A/D converter. The A/D test function checks whether or not the A/D converter is operating normally by executing A/D conversions of the A/D converter’s positive and negative reference voltages, analog input channel (ANI), temperature sensor output voltage, and the internal reference voltage.
Page 386: Digital Output Signal Level Detection Function For Input/Output Pins
CMS32M65xx User Manual | Chapter 27 Safety Functions Digital output signal level detection function for 27.3.5 input/output pins The IEC60730 standard mandates confirming that the I/O functions are normal. Input/Output Pin Digital Output Signal Level Detection Function reads the digital output level of a pin when the pin is in output mode.
Page 387: Product Unique Id Register
CMS32M65xx User Manual | Chapter 27 Safety Functions Product unique ID register 27.3.6 The unique ID of the product is perfect for: (1) Used as a serial number (e.g. USB character serial number or other terminal applications). (2) Used as a password, this unique ID is used in conjunction with a software encryption and decryption algorithm when writing flash memory to improve the security of the code in the flash memory.
Page 388: Chapter 28 Temperature Sensor
CMS32M65xx User Manual | Chapter 28 Temperature Sensor Chapter 28 Temperature Sensor 28.1 Function of temperature sensor The on-chip temperature sensor measures and monitors the core temperature of the product, thus ensuring reliable operation of the product. The voltage output by the temperature sensor is proportional to the core temperature, and there is a linear relationship between the voltage and temperature.
Page 389: Instructions For Using Temperature Sensor
CMS32M65xx User Manual | Chapter 28 Temperature Sensor 28.4 Instructions for using temperature sensor The temperature (T) is proportional to the sensor voltage output (Vs), so the temperature is calculated as follows: T = (Vs - V1) / slope + 25 ℃...
Page 390: Chapter 29 Option Byte
CMS32M65xx User Manual | Chapter 29 Option Byte Chapter 29 Option Byte 29.1 Function of option byte Addresses 000C0H~000C3H, 500004H of the flash emory of the CMS32M65xx form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and Flash memory data protection option byte (000C3H, 500004H).
Page 391: Flash Memory Data Protection Option Bytes (000C3H, 500004H)
CMS32M65xx User Manual | Chapter 29 Option Byte 29.2 Flash memory data protection option bytes (000C3H, 500004H) ⚫ Control of flash memory data protection when debugging on-chip Level0: Read/write/erase operations on flash data are enabled via debugger. Level1: Chip erase operations on flash data via debugger are enabled, read/write operations are disabled.
Page 392: User Option Bytes
CMS32M65xx User Manual | Chapter 29 Option Byte 29.4 User option bytes User option byte (000C0H) 29.4.1 Symbol Description Reset value Interval interrupt of watchdog timer 0: Interval interrupt is not used. WDTINT When 75% of the overflow time + 1/2FIL is reached, an interval interrupt is generated.
Page 393: User Option Byte (000C1H)
CMS32M65xx User Manual | Chapter 29 Option Byte User option byte (000C1H) 29.4.2 Symbol Description Reset value VPOC[2:0] Detection voltage setting Reserved (Must be 1) LVIS[1:0] Detection voltage setting Mode selection 10: Interrupt & reset mode LVIMDS[1:0] 11: Reset mode 01: Interrupt mode LVD settings (interrupt &...
Page 394 CMS32M65xx User Manual | Chapter 29 Option Byte LVD setting (reset mode) Detect voltage Setting value of option byte VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Rising Falling LVIMDS1 LVIMDS0 1.67V 1.63V 1.77V 1.73V 1.88V 1.84V 1.98V 1.94V 2.09V 2.04V 2.50V 2.45V...
Page 395 CMS32M65xx User Manual | Chapter 29 Option Byte LVD setting (interrupt mode) Detect voltage Setting value of option byte VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Rising Falling LVIMDS1 LVIMDS0 1.67V 1.63V 1.77V 1.73V 1.88V 1.84V 1.98V 1.94V 2.09V 2.04V 2.50V 2.45V...
Page 396: User Option Byte (000C2H)
CMS32M65xx User Manual | Chapter 29 Option Byte User option byte (000C2H) 29.4.3 Symbol Description Reset value Reserved (Must be 1) High-speed on-chip oscillator clock frequency FRQSE[4:0] 0x0C selection High-speed on-chip oscillator clock frequency FRQSE4 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 HOCO 64MHz 64MHz 48MHz...
Page 397: Chapter 30 Flash Control
CMS32M65xx User Manual | Chapter 30 FLASH Control Chapter 30 FLASH Control 30.1 Overivew of FLASH control This product contains a 64KByte FLASH memory, which is divided into 128 Sectors, each with a capacity of 512 Bytes. It can be used as program memory and data memory. This module supports erase, program and read operations for this memory.
Page 398: Register Mapping
CMS32M65xx User Manual | Chapter 30 FLASH Control 30.3 Register mapping (FLASH control base address = 0x4002_0000) RO: Read only, WO: Write Only, R/W: Read/Write Register Offset value Description Reset value FLSTS 0x000 FLASH Status Register FLOPMD1 0x004 FLASH Operation Control Register 1 FLOPMD2 0x008 FLASH Operation Control Register 2...
Page 399: Register Description
CMS32M65xx User Manual | Chapter 30 FLASH Control 30.4 Register description Flash write protection register (FLPROT) 30.4.1 Flash protection register is a register used to protect the FLASH operation control register. Symbol Description Reset value 31:8 Reserved WRP write protection PRKEY 78h: Enable rewriting WRP Other: Disable rewriting WRP...
Page 400: Flash Erase Control Register (Flermd)
CMS32M65xx User Manual | Chapter 30 FLASH Control Flash erase control register (FLERMD) 30.4.4 Flash erase control register is used to set the type of FLASH erase operation. Symbol Description Reset value Reserved Erase operation control bit. Sector erase, no hardware check after erase Note ERMD...
Page 401: Flash Chip Erase Time Control Register (Flcercnt)
CMS32M65xx User Manual | Chapter 30 FLASH Control Flash chip erase time control register (FLCERCNT) 30.4.6 FLCERCNT register enables to set the FLASH chip erase time. Symbol Description Reset value Note Chip erase time setting selection 0: Erase time is set by hardware Load Erase time is set by software (FLCERCNT[9:0])
Page 402: Flash Write Time Control Register (Flprocnt)
CMS32M65xx User Manual | Chapter 30 FLASH Control Flash write time control register (FLPROCNT) 30.4.8 FLPROCNT register enables to set the FLASH WORD write time. Symbol Description Reset value Note 1 Write action setup time (T ) setting 0: Write action setup time by hardware Load1 Write action setup time by software FLPGSCNT[12:0]...
Page 403: How To Operate Flash
CMS32M65xx User Manual | Chapter 30 FLASH Control 30.5 How to operate FLASH Sector erase 30.5.1 The Sector erase time is realized by the hardware or can be configured by FLSERCNT. The operation flow is as follows. Set FLERMD.ERMD0 to 1'b0, select the sector erase mode, and set the value of ERMD1 according to whether or not hardware check is required.
Page 404: Chip Erase
CMS32M65xx User Manual | Chapter 30 FLASH Control Chip erase 30.5.2 Chip erase, and the erase time are implemented by hardware and can also be configured via FLCERCNT. The operation process is as follows 1) Set FLERMD. ERMD0 to 1'b1, and select chip erase mode; 2) Set FLPROT to 0xF1 to unprotect FLOPMD.
Page 405: Flash Memory Read
CMS32M65xx User Manual | Chapter 30 FLASH Control 30.6 Flash memory read The fastest fetch frequency supported by the built-in FLASH is 32 MHz. when the HCLK frequency exceeds 32 MHz, the hardware will insert 1 wait cycle when the CPU accesses the FLASH. 30.7 Cautions for FLASH operation Flash memory has strict time requirements for the control signal of erasing and programming operation, and the timing of the control signal is not qualified, which will cause the erase operation...
Page 406: Appendix Revision History
CMS32M65xx User Manual | Appendix Revision History Appendix Revision History Version Date Revision decription V0.1.0 February 2023 Initial version Updated formatting. Corrected the referenced links in the full text. Modified registers in section 3.4.9 and updated description in Table 3-2. Corrected symbol SELLOSC in sections 5.4.6 and 5.7.
Page 407 CMS32M65xx User Manual | Appendix Revision History Corrected the timing diagram for 12-bit interval timer in Figure 7-1. Updated NIVC to support discrete interrupt numbers. Revised LVIM register description. Modified some contents in section 6.2.11. Modified some contents in Chapter 27. Modified some contents in section 28.2.

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